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crypto: mv_cesa - Add sha1 and hmac(sha1) async hash drivers
[deliverable/linux.git] / drivers / crypto / mv_cesa.c
CommitLineData
85a7f0ac
SAS		 1/*
2 * Support for Marvell's crypto engine which can be found on some Orion5X
3 * boards.
4 *
5 * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
6 * License: GPLv2
7 *
8 */
9#include <crypto/aes.h>
10#include <crypto/algapi.h>
11#include <linux/crypto.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kthread.h>
15#include <linux/platform_device.h>
16#include <linux/scatterlist.h>
750052dd
US		 17#include <crypto/internal/hash.h>
18#include <crypto/sha.h>
85a7f0ac
SAS		 19
20#include "mv_cesa.h"
750052dd
US		 21
22#define MV_CESA "MV-CESA:"
23#define MAX_HW_HASH_SIZE 0xFFFF
24
85a7f0ac
SAS		 25/*
26 * STM:
27 * /---------------------------------------\
28 * | | request complete
29 * \./ |
30 * IDLE -> new request -> BUSY -> done -> DEQUEUE
31 * /°\ |
32 * | | more scatter entries
33 * \________________/
34 */
35enum engine_status {
36 ENGINE_IDLE,
37 ENGINE_BUSY,
38 ENGINE_W_DEQUEUE,
39};
40
41/**
42 * struct req_progress - used for every crypt request
43 * @src_sg_it: sg iterator for src
44 * @dst_sg_it: sg iterator for dst
45 * @sg_src_left: bytes left in src to process (scatter list)
46 * @src_start: offset to add to src start position (scatter list)
750052dd 47 * @crypt_len: length of current hw crypt/hash process
3b61a905 48 * @hw_nbytes: total bytes to process in hw for this request
f0d03dea 49 * @copy_back: whether to copy data back (crypt) or not (hash)
85a7f0ac
SAS		 50 * @sg_dst_left: bytes left dst to process in this scatter list
51 * @dst_start: offset to add to dst start position (scatter list)
7a5f691e 52 * @hw_processed_bytes: number of bytes processed by hw (request).
85a7f0ac
SAS		 53 *
54 * sg helper are used to iterate over the scatterlist. Since the size of the
55 * SRAM may be less than the scatter size, this struct struct is used to keep
56 * track of progress within current scatterlist.
57 */
58struct req_progress {
59 struct sg_mapping_iter src_sg_it;
60 struct sg_mapping_iter dst_sg_it;
a58094ac
US		 61 void (*complete) (void);
62 void (*process) (int is_first);
85a7f0ac
SAS		 63
64 /* src mostly */
65 int sg_src_left;
66 int src_start;
67 int crypt_len;
3b61a905 68 int hw_nbytes;
85a7f0ac 69 /* dst mostly */
f0d03dea 70 int copy_back;
85a7f0ac
SAS		 71 int sg_dst_left;
72 int dst_start;
7a5f691e 73 int hw_processed_bytes;
85a7f0ac
SAS		 74};
75
76struct crypto_priv {
77 void __iomem *reg;
78 void __iomem *sram;
79 int irq;
80 struct task_struct *queue_th;
81
82 /* the lock protects queue and eng_st */
83 spinlock_t lock;
84 struct crypto_queue queue;
85 enum engine_status eng_st;
3b61a905 86 struct crypto_async_request *cur_req;
85a7f0ac
SAS		 87 struct req_progress p;
88 int max_req_size;
89 int sram_size;
750052dd
US		 90 int has_sha1;
91 int has_hmac_sha1;
85a7f0ac
SAS		 92};
93
94static struct crypto_priv *cpg;
95
96struct mv_ctx {
97 u8 aes_enc_key[AES_KEY_LEN];
98 u32 aes_dec_key[8];
99 int key_len;
100 u32 need_calc_aes_dkey;
101};
102
103enum crypto_op {
104 COP_AES_ECB,
105 COP_AES_CBC,
106};
107
108struct mv_req_ctx {
109 enum crypto_op op;
110 int decrypt;
111};
112
750052dd
US		 113enum hash_op {
114 COP_SHA1,
115 COP_HMAC_SHA1
116};
117
118struct mv_tfm_hash_ctx {
119 struct crypto_shash *fallback;
120 struct crypto_shash *base_hash;
121 u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
122 int count_add;
123 enum hash_op op;
124};
125
126struct mv_req_hash_ctx {
127 u64 count;
128 u32 state[SHA1_DIGEST_SIZE / 4];
129 u8 buffer[SHA1_BLOCK_SIZE];
130 int first_hash; /* marks that we don't have previous state */
131 int last_chunk; /* marks that this is the 'final' request */
132 int extra_bytes; /* unprocessed bytes in buffer */
133 enum hash_op op;
134 int count_add;
135 struct scatterlist dummysg;
136};
137
85a7f0ac
SAS		 138static void compute_aes_dec_key(struct mv_ctx *ctx)
139{
140 struct crypto_aes_ctx gen_aes_key;
141 int key_pos;
142
143 if (!ctx->need_calc_aes_dkey)
144 return;
145
146 crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
147
148 key_pos = ctx->key_len + 24;
149 memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
150 switch (ctx->key_len) {
151 case AES_KEYSIZE_256:
152 key_pos -= 2;
153 /* fall */
154 case AES_KEYSIZE_192:
155 key_pos -= 2;
156 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
157 4 * 4);
158 break;
159 }
160 ctx->need_calc_aes_dkey = 0;
161}
162
163static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
164 unsigned int len)
165{
166 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
167 struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
168
169 switch (len) {
170 case AES_KEYSIZE_128:
171 case AES_KEYSIZE_192:
172 case AES_KEYSIZE_256:
173 break;
174 default:
175 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
176 return -EINVAL;
177 }
178 ctx->key_len = len;
179 ctx->need_calc_aes_dkey = 1;
180
181 memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
182 return 0;
183}
184
15d4dd35 185static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
85a7f0ac
SAS		 186{
187 int ret;
15d4dd35
US		 188 void *sbuf;
189 int copied = 0;
85a7f0ac 190
15d4dd35
US		 191 while (1) {
192 if (!p->sg_src_left) {
193 ret = sg_miter_next(&p->src_sg_it);
194 BUG_ON(!ret);
195 p->sg_src_left = p->src_sg_it.length;
196 p->src_start = 0;
197 }
85a7f0ac 198
15d4dd35
US		 199 sbuf = p->src_sg_it.addr + p->src_start;
200
201 if (p->sg_src_left <= len - copied) {
202 memcpy(dbuf + copied, sbuf, p->sg_src_left);
203 copied += p->sg_src_left;
204 p->sg_src_left = 0;
205 if (copied >= len)
206 break;
207 } else {
208 int copy_len = len - copied;
209 memcpy(dbuf + copied, sbuf, copy_len);
210 p->src_start += copy_len;
211 p->sg_src_left -= copy_len;
212 break;
213 }
214 }
215}
85a7f0ac 216
3b61a905 217static void setup_data_in(void)
15d4dd35
US		 218{
219 struct req_progress *p = &cpg->p;
0c5c6c4b 220 int data_in_sram =
7a5f691e 221 min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
0c5c6c4b
US		 222 copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
223 data_in_sram - p->crypt_len);
224 p->crypt_len = data_in_sram;
85a7f0ac
SAS		 225}
226
227static void mv_process_current_q(int first_block)
228{
3b61a905 229 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
85a7f0ac
SAS		 230 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
231 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
232 struct sec_accel_config op;
233
234 switch (req_ctx->op) {
235 case COP_AES_ECB:
236 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
237 break;
238 case COP_AES_CBC:
6bc6fcd6 239 default:
85a7f0ac
SAS		 240 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
241 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
242 ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
243 if (first_block)
244 memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
245 break;
246 }
247 if (req_ctx->decrypt) {
248 op.config |= CFG_DIR_DEC;
249 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
250 AES_KEY_LEN);
251 } else {
252 op.config |= CFG_DIR_ENC;
253 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
254 AES_KEY_LEN);
255 }
256
257 switch (ctx->key_len) {
258 case AES_KEYSIZE_128:
259 op.config |= CFG_AES_LEN_128;
260 break;
261 case AES_KEYSIZE_192:
262 op.config |= CFG_AES_LEN_192;
263 break;
264 case AES_KEYSIZE_256:
265 op.config |= CFG_AES_LEN_256;
266 break;
267 }
268 op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
269 ENC_P_DST(SRAM_DATA_OUT_START);
270 op.enc_key_p = SRAM_DATA_KEY_P;
271
3b61a905 272 setup_data_in();
85a7f0ac
SAS		 273 op.enc_len = cpg->p.crypt_len;
274 memcpy(cpg->sram + SRAM_CONFIG, &op,
275 sizeof(struct sec_accel_config));
276
277 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
278 /* GO */
279 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
280
281 /*
282 * XXX: add timer if the interrupt does not occur for some mystery
283 * reason
284 */
285}
286
287static void mv_crypto_algo_completion(void)
288{
3b61a905 289 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
85a7f0ac
SAS		 290 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
291
a58094ac
US		 292 sg_miter_stop(&cpg->p.src_sg_it);
293 sg_miter_stop(&cpg->p.dst_sg_it);
294
85a7f0ac
SAS		 295 if (req_ctx->op != COP_AES_CBC)
296 return ;
297
298 memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
299}
300
750052dd
US		 301static void mv_process_hash_current(int first_block)
302{
303 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
304 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
305 struct req_progress *p = &cpg->p;
306 struct sec_accel_config op = { 0 };
307 int is_last;
308
309 switch (req_ctx->op) {
310 case COP_SHA1:
311 default:
312 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
313 break;
314 case COP_HMAC_SHA1:
315 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
316 break;
317 }
318
319 op.mac_src_p =
320 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
321 req_ctx->
322 count);
323
324 setup_data_in();
325
326 op.mac_digest =
327 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
328 op.mac_iv =
329 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
330 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
331
332 is_last = req_ctx->last_chunk
333 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
334 && (req_ctx->count <= MAX_HW_HASH_SIZE);
335 if (req_ctx->first_hash) {
336 if (is_last)
337 op.config |= CFG_NOT_FRAG;
338 else
339 op.config |= CFG_FIRST_FRAG;
340
341 req_ctx->first_hash = 0;
342 } else {
343 if (is_last)
344 op.config |= CFG_LAST_FRAG;
345 else
346 op.config |= CFG_MID_FRAG;
347 }
348
349 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
350
351 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
352 /* GO */
353 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
354
355 /*
356 * XXX: add timer if the interrupt does not occur for some mystery
357 * reason
358 */
359}
360
361static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
362 struct shash_desc *desc)
363{
364 int i;
365 struct sha1_state shash_state;
366
367 shash_state.count = ctx->count + ctx->count_add;
368 for (i = 0; i < 5; i++)
369 shash_state.state[i] = ctx->state[i];
370 memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
371 return crypto_shash_import(desc, &shash_state);
372}
373
374static int mv_hash_final_fallback(struct ahash_request *req)
375{
376 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
377 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
378 struct {
379 struct shash_desc shash;
380 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
381 } desc;
382 int rc;
383
384 desc.shash.tfm = tfm_ctx->fallback;
385 desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
386 if (unlikely(req_ctx->first_hash)) {
387 crypto_shash_init(&desc.shash);
388 crypto_shash_update(&desc.shash, req_ctx->buffer,
389 req_ctx->extra_bytes);
390 } else {
391 /* only SHA1 for now....
392 */
393 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
394 if (rc)
395 goto out;
396 }
397 rc = crypto_shash_final(&desc.shash, req->result);
398out:
399 return rc;
400}
401
402static void mv_hash_algo_completion(void)
403{
404 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
405 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
406
407 if (ctx->extra_bytes)
408 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
409 sg_miter_stop(&cpg->p.src_sg_it);
410
411 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
412 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
413 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
414 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
415 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
416
417 if (likely(ctx->last_chunk)) {
418 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
419 memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
420 crypto_ahash_digestsize(crypto_ahash_reqtfm
421 (req)));
422 } else
423 mv_hash_final_fallback(req);
424 }
425}
426
85a7f0ac
SAS		 427static void dequeue_complete_req(void)
428{
3b61a905 429 struct crypto_async_request *req = cpg->cur_req;
85a7f0ac
SAS		 430 void *buf;
431 int ret;
7a5f691e 432 cpg->p.hw_processed_bytes += cpg->p.crypt_len;
f0d03dea
US		 433 if (cpg->p.copy_back) {
434 int need_copy_len = cpg->p.crypt_len;
435 int sram_offset = 0;
436 do {
437 int dst_copy;
438
439 if (!cpg->p.sg_dst_left) {
440 ret = sg_miter_next(&cpg->p.dst_sg_it);
441 BUG_ON(!ret);
442 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
443 cpg->p.dst_start = 0;
444 }
445
446 buf = cpg->p.dst_sg_it.addr;
447 buf += cpg->p.dst_start;
448
449 dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
450
451 memcpy(buf,
452 cpg->sram + SRAM_DATA_OUT_START + sram_offset,
453 dst_copy);
454 sram_offset += dst_copy;
455 cpg->p.sg_dst_left -= dst_copy;
456 need_copy_len -= dst_copy;
457 cpg->p.dst_start += dst_copy;
458 } while (need_copy_len > 0);
459 }
85a7f0ac 460
0c5c6c4b 461 cpg->p.crypt_len = 0;
85a7f0ac
SAS		 462
463 BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
7a5f691e 464 if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
85a7f0ac
SAS		 465 /* process next scatter list entry */
466 cpg->eng_st = ENGINE_BUSY;
a58094ac 467 cpg->p.process(0);
85a7f0ac 468 } else {
a58094ac 469 cpg->p.complete();
85a7f0ac 470 cpg->eng_st = ENGINE_IDLE;
0328ac26 471 local_bh_disable();
3b61a905 472 req->complete(req, 0);
0328ac26 473 local_bh_enable();
85a7f0ac
SAS		 474 }
475}
476
477static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
478{
479 int i = 0;
15d4dd35
US		 480 size_t cur_len;
481
482 while (1) {
483 cur_len = sl[i].length;
484 ++i;
485 if (total_bytes > cur_len)
486 total_bytes -= cur_len;
487 else
488 break;
489 }
85a7f0ac
SAS		 490
491 return i;
492}
493
750052dd 494static void mv_start_new_crypt_req(struct ablkcipher_request *req)
85a7f0ac 495{
3b61a905 496 struct req_progress *p = &cpg->p;
85a7f0ac
SAS		 497 int num_sgs;
498
3b61a905
US		 499 cpg->cur_req = &req->base;
500 memset(p, 0, sizeof(struct req_progress));
501 p->hw_nbytes = req->nbytes;
a58094ac
US		 502 p->complete = mv_crypto_algo_completion;
503 p->process = mv_process_current_q;
f0d03dea 504 p->copy_back = 1;
85a7f0ac
SAS		 505
506 num_sgs = count_sgs(req->src, req->nbytes);
3b61a905 507 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
85a7f0ac
SAS		 508
509 num_sgs = count_sgs(req->dst, req->nbytes);
3b61a905
US		 510 sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
511
85a7f0ac
SAS		 512 mv_process_current_q(1);
513}
514
750052dd
US		 515static void mv_start_new_hash_req(struct ahash_request *req)
516{
517 struct req_progress *p = &cpg->p;
518 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
519 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
520 int num_sgs, hw_bytes, old_extra_bytes, rc;
521 cpg->cur_req = &req->base;
522 memset(p, 0, sizeof(struct req_progress));
523 hw_bytes = req->nbytes + ctx->extra_bytes;
524 old_extra_bytes = ctx->extra_bytes;
525
526 if (unlikely(ctx->extra_bytes)) {
527 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
528 ctx->extra_bytes);
529 p->crypt_len = ctx->extra_bytes;
530 }
531
532 memcpy(cpg->sram + SRAM_HMAC_IV_IN, tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
533
534 if (unlikely(!ctx->first_hash)) {
535 writel(ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
536 writel(ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
537 writel(ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
538 writel(ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
539 writel(ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
540 }
541
542 ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
543 if (ctx->extra_bytes != 0
544 && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
545 hw_bytes -= ctx->extra_bytes;
546 else
547 ctx->extra_bytes = 0;
548
549 num_sgs = count_sgs(req->src, req->nbytes);
550 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
551
552 if (hw_bytes) {
553 p->hw_nbytes = hw_bytes;
554 p->complete = mv_hash_algo_completion;
555 p->process = mv_process_hash_current;
556
557 mv_process_hash_current(1);
558 } else {
559 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
560 ctx->extra_bytes - old_extra_bytes);
561 sg_miter_stop(&p->src_sg_it);
562 if (ctx->last_chunk)
563 rc = mv_hash_final_fallback(req);
564 else
565 rc = 0;
566 cpg->eng_st = ENGINE_IDLE;
567 local_bh_disable();
568 req->base.complete(&req->base, rc);
569 local_bh_enable();
570 }
571}
572
85a7f0ac
SAS		 573static int queue_manag(void *data)
574{
575 cpg->eng_st = ENGINE_IDLE;
576 do {
85a7f0ac
SAS		 577 struct crypto_async_request *async_req = NULL;
578 struct crypto_async_request *backlog;
579
580 __set_current_state(TASK_INTERRUPTIBLE);
581
582 if (cpg->eng_st == ENGINE_W_DEQUEUE)
583 dequeue_complete_req();
584
585 spin_lock_irq(&cpg->lock);
586 if (cpg->eng_st == ENGINE_IDLE) {
587 backlog = crypto_get_backlog(&cpg->queue);
588 async_req = crypto_dequeue_request(&cpg->queue);
589 if (async_req) {
590 BUG_ON(cpg->eng_st != ENGINE_IDLE);
591 cpg->eng_st = ENGINE_BUSY;
592 }
593 }
594 spin_unlock_irq(&cpg->lock);
595
596 if (backlog) {
597 backlog->complete(backlog, -EINPROGRESS);
598 backlog = NULL;
599 }
600
601 if (async_req) {
750052dd
US		 602 if (async_req->tfm->__crt_alg->cra_type !=
603 &crypto_ahash_type) {
604 struct ablkcipher_request *req =
605 container_of(async_req,
606 struct ablkcipher_request,
607 base);
608 mv_start_new_crypt_req(req);
609 } else {
610 struct ahash_request *req =
611 ahash_request_cast(async_req);
612 mv_start_new_hash_req(req);
613 }
85a7f0ac
SAS		 614 async_req = NULL;
615 }
616
617 schedule();
618
619 } while (!kthread_should_stop());
620 return 0;
621}
622
3b61a905 623static int mv_handle_req(struct crypto_async_request *req)
85a7f0ac
SAS		 624{
625 unsigned long flags;
626 int ret;
627
628 spin_lock_irqsave(&cpg->lock, flags);
3b61a905 629 ret = crypto_enqueue_request(&cpg->queue, req);
85a7f0ac
SAS		 630 spin_unlock_irqrestore(&cpg->lock, flags);
631 wake_up_process(cpg->queue_th);
632 return ret;
633}
634
635static int mv_enc_aes_ecb(struct ablkcipher_request *req)
636{
637 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
638
639 req_ctx->op = COP_AES_ECB;
640 req_ctx->decrypt = 0;
641
3b61a905 642 return mv_handle_req(&req->base);
85a7f0ac
SAS		 643}
644
645static int mv_dec_aes_ecb(struct ablkcipher_request *req)
646{
647 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
648 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
649
650 req_ctx->op = COP_AES_ECB;
651 req_ctx->decrypt = 1;
652
653 compute_aes_dec_key(ctx);
3b61a905 654 return mv_handle_req(&req->base);
85a7f0ac
SAS		 655}
656
657static int mv_enc_aes_cbc(struct ablkcipher_request *req)
658{
659 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
660
661 req_ctx->op = COP_AES_CBC;
662 req_ctx->decrypt = 0;
663
3b61a905 664 return mv_handle_req(&req->base);
85a7f0ac
SAS		 665}
666
667static int mv_dec_aes_cbc(struct ablkcipher_request *req)
668{
669 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
670 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
671
672 req_ctx->op = COP_AES_CBC;
673 req_ctx->decrypt = 1;
674
675 compute_aes_dec_key(ctx);
3b61a905 676 return mv_handle_req(&req->base);
85a7f0ac
SAS		 677}
678
679static int mv_cra_init(struct crypto_tfm *tfm)
680{
681 tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
682 return 0;
683}
684
750052dd
US		 685static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
686 int is_last, unsigned int req_len,
687 int count_add)
688{
689 memset(ctx, 0, sizeof(*ctx));
690 ctx->op = op;
691 ctx->count = req_len;
692 ctx->first_hash = 1;
693 ctx->last_chunk = is_last;
694 ctx->count_add = count_add;
695}
696
697static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
698 unsigned req_len)
699{
700 ctx->last_chunk = is_last;
701 ctx->count += req_len;
702}
703
704static int mv_hash_init(struct ahash_request *req)
705{
706 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
707 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
708 tfm_ctx->count_add);
709 return 0;
710}
711
712static int mv_hash_update(struct ahash_request *req)
713{
714 if (!req->nbytes)
715 return 0;
716
717 mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
718 return mv_handle_req(&req->base);
719}
720
721static int mv_hash_final(struct ahash_request *req)
722{
723 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
724 /* dummy buffer of 4 bytes */
725 sg_init_one(&ctx->dummysg, ctx->buffer, 4);
726 /* I think I'm allowed to do that... */
727 ahash_request_set_crypt(req, &ctx->dummysg, req->result, 0);
728 mv_update_hash_req_ctx(ctx, 1, 0);
729 return mv_handle_req(&req->base);
730}
731
732static int mv_hash_finup(struct ahash_request *req)
733{
734 if (!req->nbytes)
735 return mv_hash_final(req);
736
737 mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
738 return mv_handle_req(&req->base);
739}
740
741static int mv_hash_digest(struct ahash_request *req)
742{
743 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
744 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
745 req->nbytes, tfm_ctx->count_add);
746 return mv_handle_req(&req->base);
747}
748
749static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
750 const void *ostate)
751{
752 const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
753 int i;
754 for (i = 0; i < 5; i++) {
755 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
756 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
757 }
758}
759
760static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
761 unsigned int keylen)
762{
763 int rc;
764 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
765 int bs, ds, ss;
766
767 if (!ctx->base_hash)
768 return 0;
769
770 rc = crypto_shash_setkey(ctx->fallback, key, keylen);
771 if (rc)
772 return rc;
773
774 /* Can't see a way to extract the ipad/opad from the fallback tfm
775 so I'm basically copying code from the hmac module */
776 bs = crypto_shash_blocksize(ctx->base_hash);
777 ds = crypto_shash_digestsize(ctx->base_hash);
778 ss = crypto_shash_statesize(ctx->base_hash);
779
780 {
781 struct {
782 struct shash_desc shash;
783 char ctx[crypto_shash_descsize(ctx->base_hash)];
784 } desc;
785 unsigned int i;
786 char ipad[ss];
787 char opad[ss];
788
789 desc.shash.tfm = ctx->base_hash;
790 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
791 CRYPTO_TFM_REQ_MAY_SLEEP;
792
793 if (keylen > bs) {
794 int err;
795
796 err =
797 crypto_shash_digest(&desc.shash, key, keylen, ipad);
798 if (err)
799 return err;
800
801 keylen = ds;
802 } else
803 memcpy(ipad, key, keylen);
804
805 memset(ipad + keylen, 0, bs - keylen);
806 memcpy(opad, ipad, bs);
807
808 for (i = 0; i < bs; i++) {
809 ipad[i] ^= 0x36;
810 opad[i] ^= 0x5c;
811 }
812
813 rc = crypto_shash_init(&desc.shash) ? :
814 crypto_shash_update(&desc.shash, ipad, bs) ? :
815 crypto_shash_export(&desc.shash, ipad) ? :
816 crypto_shash_init(&desc.shash) ? :
817 crypto_shash_update(&desc.shash, opad, bs) ? :
818 crypto_shash_export(&desc.shash, opad);
819
820 if (rc == 0)
821 mv_hash_init_ivs(ctx, ipad, opad);
822
823 return rc;
824 }
825}
826
827static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
828 enum hash_op op, int count_add)
829{
830 const char *fallback_driver_name = tfm->__crt_alg->cra_name;
831 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
832 struct crypto_shash *fallback_tfm = NULL;
833 struct crypto_shash *base_hash = NULL;
834 int err = -ENOMEM;
835
836 ctx->op = op;
837 ctx->count_add = count_add;
838
839 /* Allocate a fallback and abort if it failed. */
840 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
841 CRYPTO_ALG_NEED_FALLBACK);
842 if (IS_ERR(fallback_tfm)) {
843 printk(KERN_WARNING MV_CESA
844 "Fallback driver '%s' could not be loaded!\n",
845 fallback_driver_name);
846 err = PTR_ERR(fallback_tfm);
847 goto out;
848 }
849 ctx->fallback = fallback_tfm;
850
851 if (base_hash_name) {
852 /* Allocate a hash to compute the ipad/opad of hmac. */
853 base_hash = crypto_alloc_shash(base_hash_name, 0,
854 CRYPTO_ALG_NEED_FALLBACK);
855 if (IS_ERR(base_hash)) {
856 printk(KERN_WARNING MV_CESA
857 "Base driver '%s' could not be loaded!\n",
858 base_hash_name);
859 err = PTR_ERR(fallback_tfm);
860 goto err_bad_base;
861 }
862 }
863 ctx->base_hash = base_hash;
864
865 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
866 sizeof(struct mv_req_hash_ctx) +
867 crypto_shash_descsize(ctx->fallback));
868 return 0;
869err_bad_base:
870 crypto_free_shash(fallback_tfm);
871out:
872 return err;
873}
874
875static void mv_cra_hash_exit(struct crypto_tfm *tfm)
876{
877 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
878
879 crypto_free_shash(ctx->fallback);
880 if (ctx->base_hash)
881 crypto_free_shash(ctx->base_hash);
882}
883
884static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
885{
886 return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
887}
888
889static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
890{
891 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
892}
893
85a7f0ac
SAS		 894irqreturn_t crypto_int(int irq, void *priv)
895{
896 u32 val;
897
898 val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
899 if (!(val & SEC_INT_ACCEL0_DONE))
900 return IRQ_NONE;
901
902 val &= ~SEC_INT_ACCEL0_DONE;
903 writel(val, cpg->reg + FPGA_INT_STATUS);
904 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
905 BUG_ON(cpg->eng_st != ENGINE_BUSY);
906 cpg->eng_st = ENGINE_W_DEQUEUE;
907 wake_up_process(cpg->queue_th);
908 return IRQ_HANDLED;
909}
910
911struct crypto_alg mv_aes_alg_ecb = {
912 .cra_name = "ecb(aes)",
913 .cra_driver_name = "mv-ecb-aes",
914 .cra_priority = 300,
915 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
916 .cra_blocksize = 16,
917 .cra_ctxsize = sizeof(struct mv_ctx),
918 .cra_alignmask = 0,
919 .cra_type = &crypto_ablkcipher_type,
920 .cra_module = THIS_MODULE,
921 .cra_init = mv_cra_init,
922 .cra_u = {
923 .ablkcipher = {
924 .min_keysize = AES_MIN_KEY_SIZE,
925 .max_keysize = AES_MAX_KEY_SIZE,
926 .setkey = mv_setkey_aes,
927 .encrypt = mv_enc_aes_ecb,
928 .decrypt = mv_dec_aes_ecb,
929 },
930 },
931};
932
933struct crypto_alg mv_aes_alg_cbc = {
934 .cra_name = "cbc(aes)",
935 .cra_driver_name = "mv-cbc-aes",
936 .cra_priority = 300,
937 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
938 .cra_blocksize = AES_BLOCK_SIZE,
939 .cra_ctxsize = sizeof(struct mv_ctx),
940 .cra_alignmask = 0,
941 .cra_type = &crypto_ablkcipher_type,
942 .cra_module = THIS_MODULE,
943 .cra_init = mv_cra_init,
944 .cra_u = {
945 .ablkcipher = {
946 .ivsize = AES_BLOCK_SIZE,
947 .min_keysize = AES_MIN_KEY_SIZE,
948 .max_keysize = AES_MAX_KEY_SIZE,
949 .setkey = mv_setkey_aes,
950 .encrypt = mv_enc_aes_cbc,
951 .decrypt = mv_dec_aes_cbc,
952 },
953 },
954};
955
750052dd
US		 956struct ahash_alg mv_sha1_alg = {
957 .init = mv_hash_init,
958 .update = mv_hash_update,
959 .final = mv_hash_final,
960 .finup = mv_hash_finup,
961 .digest = mv_hash_digest,
962 .halg = {
963 .digestsize = SHA1_DIGEST_SIZE,
964 .base = {
965 .cra_name = "sha1",
966 .cra_driver_name = "mv-sha1",
967 .cra_priority = 300,
968 .cra_flags =
969 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
970 .cra_blocksize = SHA1_BLOCK_SIZE,
971 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
972 .cra_init = mv_cra_hash_sha1_init,
973 .cra_exit = mv_cra_hash_exit,
974 .cra_module = THIS_MODULE,
975 }
976 }
977};
978
979struct ahash_alg mv_hmac_sha1_alg = {
980 .init = mv_hash_init,
981 .update = mv_hash_update,
982 .final = mv_hash_final,
983 .finup = mv_hash_finup,
984 .digest = mv_hash_digest,
985 .setkey = mv_hash_setkey,
986 .halg = {
987 .digestsize = SHA1_DIGEST_SIZE,
988 .base = {
989 .cra_name = "hmac(sha1)",
990 .cra_driver_name = "mv-hmac-sha1",
991 .cra_priority = 300,
992 .cra_flags =
993 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
994 .cra_blocksize = SHA1_BLOCK_SIZE,
995 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
996 .cra_init = mv_cra_hash_hmac_sha1_init,
997 .cra_exit = mv_cra_hash_exit,
998 .cra_module = THIS_MODULE,
999 }
1000 }
1001};
1002
85a7f0ac
SAS		 1003static int mv_probe(struct platform_device *pdev)
1004{
1005 struct crypto_priv *cp;
1006 struct resource *res;
1007 int irq;
1008 int ret;
1009
1010 if (cpg) {
750052dd 1011 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
85a7f0ac
SAS		 1012 return -EEXIST;
1013 }
1014
1015 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1016 if (!res)
1017 return -ENXIO;
1018
1019 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1020 if (!cp)
1021 return -ENOMEM;
1022
1023 spin_lock_init(&cp->lock);
1024 crypto_init_queue(&cp->queue, 50);
1025 cp->reg = ioremap(res->start, res->end - res->start + 1);
1026 if (!cp->reg) {
1027 ret = -ENOMEM;
1028 goto err;
1029 }
1030
1031 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1032 if (!res) {
1033 ret = -ENXIO;
1034 goto err_unmap_reg;
1035 }
1036 cp->sram_size = res->end - res->start + 1;
1037 cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1038 cp->sram = ioremap(res->start, cp->sram_size);
1039 if (!cp->sram) {
1040 ret = -ENOMEM;
1041 goto err_unmap_reg;
1042 }
1043
1044 irq = platform_get_irq(pdev, 0);
1045 if (irq < 0 || irq == NO_IRQ) {
1046 ret = irq;
1047 goto err_unmap_sram;
1048 }
1049 cp->irq = irq;
1050
1051 platform_set_drvdata(pdev, cp);
1052 cpg = cp;
1053
1054 cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1055 if (IS_ERR(cp->queue_th)) {
1056 ret = PTR_ERR(cp->queue_th);
1057 goto err_thread;
1058 }
1059
1060 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1061 cp);
1062 if (ret)
1063 goto err_unmap_sram;
1064
1065 writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1066 writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1067
1068 ret = crypto_register_alg(&mv_aes_alg_ecb);
1069 if (ret)
1070 goto err_reg;
1071
1072 ret = crypto_register_alg(&mv_aes_alg_cbc);
1073 if (ret)
1074 goto err_unreg_ecb;
750052dd
US		 1075
1076 ret = crypto_register_ahash(&mv_sha1_alg);
1077 if (ret == 0)
1078 cpg->has_sha1 = 1;
1079 else
1080 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1081
1082 ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1083 if (ret == 0) {
1084 cpg->has_hmac_sha1 = 1;
1085 } else {
1086 printk(KERN_WARNING MV_CESA
1087 "Could not register hmac-sha1 driver\n");
1088 }
1089
85a7f0ac
SAS		 1090 return 0;
1091err_unreg_ecb:
1092 crypto_unregister_alg(&mv_aes_alg_ecb);
1093err_thread:
1094 free_irq(irq, cp);
1095err_reg:
1096 kthread_stop(cp->queue_th);
1097err_unmap_sram:
1098 iounmap(cp->sram);
1099err_unmap_reg:
1100 iounmap(cp->reg);
1101err:
1102 kfree(cp);
1103 cpg = NULL;
1104 platform_set_drvdata(pdev, NULL);
1105 return ret;
1106}
1107
1108static int mv_remove(struct platform_device *pdev)
1109{
1110 struct crypto_priv *cp = platform_get_drvdata(pdev);
1111
1112 crypto_unregister_alg(&mv_aes_alg_ecb);
1113 crypto_unregister_alg(&mv_aes_alg_cbc);
750052dd
US		 1114 if (cp->has_sha1)
1115 crypto_unregister_ahash(&mv_sha1_alg);
1116 if (cp->has_hmac_sha1)
1117 crypto_unregister_ahash(&mv_hmac_sha1_alg);
85a7f0ac
SAS		 1118 kthread_stop(cp->queue_th);
1119 free_irq(cp->irq, cp);
1120 memset(cp->sram, 0, cp->sram_size);
1121 iounmap(cp->sram);
1122 iounmap(cp->reg);
1123 kfree(cp);
1124 cpg = NULL;
1125 return 0;
1126}
1127
1128static struct platform_driver marvell_crypto = {
1129 .probe = mv_probe,
1130 .remove = mv_remove,
1131 .driver = {
1132 .owner = THIS_MODULE,
1133 .name = "mv_crypto",
1134 },
1135};
1136MODULE_ALIAS("platform:mv_crypto");
1137
1138static int __init mv_crypto_init(void)
1139{
1140 return platform_driver_register(&marvell_crypto);
1141}
1142module_init(mv_crypto_init);
1143
1144static void __exit mv_crypto_exit(void)
1145{
1146 platform_driver_unregister(&marvell_crypto);
1147}
1148module_exit(mv_crypto_exit);
1149
1150MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1151MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1152MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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