Commit | Line | Data |
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15b59e7c MV |
1 | /* |
2 | * Freescale i.MX23/i.MX28 Data Co-Processor driver | |
3 | * | |
4 | * Copyright (C) 2013 Marek Vasut <marex@denx.de> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | #include <linux/crypto.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/stmp_device.h> | |
24 | ||
25 | #include <crypto/aes.h> | |
26 | #include <crypto/sha.h> | |
27 | #include <crypto/internal/hash.h> | |
28 | ||
29 | #define DCP_MAX_CHANS 4 | |
30 | #define DCP_BUF_SZ PAGE_SIZE | |
31 | ||
1a7c6856 MV |
32 | #define DCP_ALIGNMENT 64 |
33 | ||
15b59e7c MV |
34 | /* DCP DMA descriptor. */ |
35 | struct dcp_dma_desc { | |
36 | uint32_t next_cmd_addr; | |
37 | uint32_t control0; | |
38 | uint32_t control1; | |
39 | uint32_t source; | |
40 | uint32_t destination; | |
41 | uint32_t size; | |
42 | uint32_t payload; | |
43 | uint32_t status; | |
44 | }; | |
45 | ||
46 | /* Coherent aligned block for bounce buffering. */ | |
47 | struct dcp_coherent_block { | |
48 | uint8_t aes_in_buf[DCP_BUF_SZ]; | |
49 | uint8_t aes_out_buf[DCP_BUF_SZ]; | |
50 | uint8_t sha_in_buf[DCP_BUF_SZ]; | |
51 | ||
52 | uint8_t aes_key[2 * AES_KEYSIZE_128]; | |
53 | uint8_t sha_digest[SHA256_DIGEST_SIZE]; | |
54 | ||
55 | struct dcp_dma_desc desc[DCP_MAX_CHANS]; | |
56 | }; | |
57 | ||
58 | struct dcp { | |
59 | struct device *dev; | |
60 | void __iomem *base; | |
61 | ||
62 | uint32_t caps; | |
63 | ||
64 | struct dcp_coherent_block *coh; | |
65 | ||
66 | struct completion completion[DCP_MAX_CHANS]; | |
67 | struct mutex mutex[DCP_MAX_CHANS]; | |
68 | struct task_struct *thread[DCP_MAX_CHANS]; | |
69 | struct crypto_queue queue[DCP_MAX_CHANS]; | |
70 | }; | |
71 | ||
72 | enum dcp_chan { | |
73 | DCP_CHAN_HASH_SHA = 0, | |
74 | DCP_CHAN_CRYPTO = 2, | |
75 | }; | |
76 | ||
77 | struct dcp_async_ctx { | |
78 | /* Common context */ | |
79 | enum dcp_chan chan; | |
80 | uint32_t fill; | |
81 | ||
82 | /* SHA Hash-specific context */ | |
83 | struct mutex mutex; | |
84 | uint32_t alg; | |
85 | unsigned int hot:1; | |
86 | ||
87 | /* Crypto-specific context */ | |
15b59e7c MV |
88 | struct crypto_ablkcipher *fallback; |
89 | unsigned int key_len; | |
90 | uint8_t key[AES_KEYSIZE_128]; | |
91 | }; | |
92 | ||
2021abaa MV |
93 | struct dcp_aes_req_ctx { |
94 | unsigned int enc:1; | |
95 | unsigned int ecb:1; | |
96 | }; | |
97 | ||
15b59e7c MV |
98 | struct dcp_sha_req_ctx { |
99 | unsigned int init:1; | |
100 | unsigned int fini:1; | |
101 | }; | |
102 | ||
103 | /* | |
104 | * There can even be only one instance of the MXS DCP due to the | |
105 | * design of Linux Crypto API. | |
106 | */ | |
107 | static struct dcp *global_sdcp; | |
fe70be5c | 108 | static DEFINE_MUTEX(global_mutex); |
15b59e7c MV |
109 | |
110 | /* DCP register layout. */ | |
111 | #define MXS_DCP_CTRL 0x00 | |
112 | #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) | |
113 | #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22) | |
114 | ||
115 | #define MXS_DCP_STAT 0x10 | |
116 | #define MXS_DCP_STAT_CLR 0x18 | |
117 | #define MXS_DCP_STAT_IRQ_MASK 0xf | |
118 | ||
119 | #define MXS_DCP_CHANNELCTRL 0x20 | |
120 | #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff | |
121 | ||
122 | #define MXS_DCP_CAPABILITY1 0x40 | |
123 | #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16) | |
124 | #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16) | |
125 | #define MXS_DCP_CAPABILITY1_AES128 (1 << 0) | |
126 | ||
127 | #define MXS_DCP_CONTEXT 0x50 | |
128 | ||
129 | #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40)) | |
130 | ||
131 | #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40)) | |
132 | ||
133 | #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40)) | |
134 | #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40)) | |
135 | ||
136 | /* DMA descriptor bits. */ | |
137 | #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13) | |
138 | #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12) | |
139 | #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11) | |
140 | #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8) | |
141 | #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9) | |
142 | #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6) | |
143 | #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5) | |
144 | #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1) | |
145 | #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0) | |
146 | ||
147 | #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16) | |
148 | #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16) | |
149 | #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4) | |
150 | #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4) | |
151 | #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0) | |
152 | ||
153 | static int mxs_dcp_start_dma(struct dcp_async_ctx *actx) | |
154 | { | |
155 | struct dcp *sdcp = global_sdcp; | |
156 | const int chan = actx->chan; | |
157 | uint32_t stat; | |
158 | int ret; | |
159 | struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; | |
160 | ||
161 | dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc), | |
162 | DMA_TO_DEVICE); | |
163 | ||
164 | reinit_completion(&sdcp->completion[chan]); | |
165 | ||
166 | /* Clear status register. */ | |
167 | writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan)); | |
168 | ||
169 | /* Load the DMA descriptor. */ | |
170 | writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan)); | |
171 | ||
172 | /* Increment the semaphore to start the DMA transfer. */ | |
173 | writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan)); | |
174 | ||
175 | ret = wait_for_completion_timeout(&sdcp->completion[chan], | |
176 | msecs_to_jiffies(1000)); | |
177 | if (!ret) { | |
178 | dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n", | |
179 | chan, readl(sdcp->base + MXS_DCP_STAT)); | |
180 | return -ETIMEDOUT; | |
181 | } | |
182 | ||
183 | stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan)); | |
184 | if (stat & 0xff) { | |
185 | dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n", | |
186 | chan, stat); | |
187 | return -EINVAL; | |
188 | } | |
189 | ||
190 | dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | /* | |
196 | * Encryption (AES128) | |
197 | */ | |
2021abaa MV |
198 | static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, |
199 | struct ablkcipher_request *req, int init) | |
15b59e7c MV |
200 | { |
201 | struct dcp *sdcp = global_sdcp; | |
202 | struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; | |
2021abaa | 203 | struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); |
15b59e7c MV |
204 | int ret; |
205 | ||
206 | dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, | |
207 | 2 * AES_KEYSIZE_128, | |
208 | DMA_TO_DEVICE); | |
209 | dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf, | |
210 | DCP_BUF_SZ, DMA_TO_DEVICE); | |
211 | dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf, | |
212 | DCP_BUF_SZ, DMA_FROM_DEVICE); | |
213 | ||
214 | /* Fill in the DMA descriptor. */ | |
215 | desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | | |
216 | MXS_DCP_CONTROL0_INTERRUPT | | |
217 | MXS_DCP_CONTROL0_ENABLE_CIPHER; | |
218 | ||
219 | /* Payload contains the key. */ | |
220 | desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; | |
221 | ||
2021abaa | 222 | if (rctx->enc) |
15b59e7c MV |
223 | desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT; |
224 | if (init) | |
225 | desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT; | |
226 | ||
227 | desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128; | |
228 | ||
2021abaa | 229 | if (rctx->ecb) |
15b59e7c MV |
230 | desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB; |
231 | else | |
232 | desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; | |
233 | ||
234 | desc->next_cmd_addr = 0; | |
235 | desc->source = src_phys; | |
236 | desc->destination = dst_phys; | |
237 | desc->size = actx->fill; | |
238 | desc->payload = key_phys; | |
239 | desc->status = 0; | |
240 | ||
241 | ret = mxs_dcp_start_dma(actx); | |
242 | ||
243 | dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, | |
244 | DMA_TO_DEVICE); | |
245 | dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE); | |
246 | dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE); | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
251 | static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) | |
252 | { | |
253 | struct dcp *sdcp = global_sdcp; | |
254 | ||
255 | struct ablkcipher_request *req = ablkcipher_request_cast(arq); | |
256 | struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); | |
2021abaa | 257 | struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); |
15b59e7c MV |
258 | |
259 | struct scatterlist *dst = req->dst; | |
260 | struct scatterlist *src = req->src; | |
261 | const int nents = sg_nents(req->src); | |
262 | ||
263 | const int out_off = DCP_BUF_SZ; | |
264 | uint8_t *in_buf = sdcp->coh->aes_in_buf; | |
265 | uint8_t *out_buf = sdcp->coh->aes_out_buf; | |
266 | ||
267 | uint8_t *out_tmp, *src_buf, *dst_buf = NULL; | |
268 | uint32_t dst_off = 0; | |
269 | ||
270 | uint8_t *key = sdcp->coh->aes_key; | |
271 | ||
272 | int ret = 0; | |
273 | int split = 0; | |
274 | unsigned int i, len, clen, rem = 0; | |
275 | int init = 0; | |
276 | ||
277 | actx->fill = 0; | |
278 | ||
279 | /* Copy the key from the temporary location. */ | |
280 | memcpy(key, actx->key, actx->key_len); | |
281 | ||
2021abaa | 282 | if (!rctx->ecb) { |
15b59e7c MV |
283 | /* Copy the CBC IV just past the key. */ |
284 | memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128); | |
285 | /* CBC needs the INIT set. */ | |
286 | init = 1; | |
287 | } else { | |
288 | memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128); | |
289 | } | |
290 | ||
291 | for_each_sg(req->src, src, nents, i) { | |
292 | src_buf = sg_virt(src); | |
293 | len = sg_dma_len(src); | |
294 | ||
295 | do { | |
296 | if (actx->fill + len > out_off) | |
297 | clen = out_off - actx->fill; | |
298 | else | |
299 | clen = len; | |
300 | ||
301 | memcpy(in_buf + actx->fill, src_buf, clen); | |
302 | len -= clen; | |
303 | src_buf += clen; | |
304 | actx->fill += clen; | |
305 | ||
306 | /* | |
307 | * If we filled the buffer or this is the last SG, | |
308 | * submit the buffer. | |
309 | */ | |
310 | if (actx->fill == out_off || sg_is_last(src)) { | |
2021abaa | 311 | ret = mxs_dcp_run_aes(actx, req, init); |
15b59e7c MV |
312 | if (ret) |
313 | return ret; | |
314 | init = 0; | |
315 | ||
316 | out_tmp = out_buf; | |
317 | while (dst && actx->fill) { | |
318 | if (!split) { | |
319 | dst_buf = sg_virt(dst); | |
320 | dst_off = 0; | |
321 | } | |
322 | rem = min(sg_dma_len(dst) - dst_off, | |
323 | actx->fill); | |
324 | ||
325 | memcpy(dst_buf + dst_off, out_tmp, rem); | |
326 | out_tmp += rem; | |
327 | dst_off += rem; | |
328 | actx->fill -= rem; | |
329 | ||
330 | if (dst_off == sg_dma_len(dst)) { | |
331 | dst = sg_next(dst); | |
332 | split = 0; | |
333 | } else { | |
334 | split = 1; | |
335 | } | |
336 | } | |
337 | } | |
338 | } while (len); | |
339 | } | |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
344 | static int dcp_chan_thread_aes(void *data) | |
345 | { | |
346 | struct dcp *sdcp = global_sdcp; | |
347 | const int chan = DCP_CHAN_CRYPTO; | |
348 | ||
349 | struct crypto_async_request *backlog; | |
350 | struct crypto_async_request *arq; | |
351 | ||
352 | int ret; | |
353 | ||
354 | do { | |
355 | __set_current_state(TASK_INTERRUPTIBLE); | |
356 | ||
357 | mutex_lock(&sdcp->mutex[chan]); | |
358 | backlog = crypto_get_backlog(&sdcp->queue[chan]); | |
359 | arq = crypto_dequeue_request(&sdcp->queue[chan]); | |
360 | mutex_unlock(&sdcp->mutex[chan]); | |
361 | ||
362 | if (backlog) | |
363 | backlog->complete(backlog, -EINPROGRESS); | |
364 | ||
365 | if (arq) { | |
366 | ret = mxs_dcp_aes_block_crypt(arq); | |
367 | arq->complete(arq, ret); | |
368 | continue; | |
369 | } | |
370 | ||
371 | schedule(); | |
372 | } while (!kthread_should_stop()); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc) | |
378 | { | |
379 | struct crypto_tfm *tfm = | |
380 | crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); | |
381 | struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx( | |
382 | crypto_ablkcipher_reqtfm(req)); | |
383 | int ret; | |
384 | ||
385 | ablkcipher_request_set_tfm(req, ctx->fallback); | |
386 | ||
387 | if (enc) | |
388 | ret = crypto_ablkcipher_encrypt(req); | |
389 | else | |
390 | ret = crypto_ablkcipher_decrypt(req); | |
391 | ||
392 | ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm)); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
397 | static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb) | |
398 | { | |
399 | struct dcp *sdcp = global_sdcp; | |
400 | struct crypto_async_request *arq = &req->base; | |
401 | struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); | |
2021abaa | 402 | struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); |
15b59e7c MV |
403 | int ret; |
404 | ||
405 | if (unlikely(actx->key_len != AES_KEYSIZE_128)) | |
406 | return mxs_dcp_block_fallback(req, enc); | |
407 | ||
2021abaa MV |
408 | rctx->enc = enc; |
409 | rctx->ecb = ecb; | |
15b59e7c MV |
410 | actx->chan = DCP_CHAN_CRYPTO; |
411 | ||
412 | mutex_lock(&sdcp->mutex[actx->chan]); | |
413 | ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); | |
414 | mutex_unlock(&sdcp->mutex[actx->chan]); | |
415 | ||
416 | wake_up_process(sdcp->thread[actx->chan]); | |
417 | ||
418 | return -EINPROGRESS; | |
419 | } | |
420 | ||
421 | static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req) | |
422 | { | |
423 | return mxs_dcp_aes_enqueue(req, 0, 1); | |
424 | } | |
425 | ||
426 | static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req) | |
427 | { | |
428 | return mxs_dcp_aes_enqueue(req, 1, 1); | |
429 | } | |
430 | ||
431 | static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req) | |
432 | { | |
433 | return mxs_dcp_aes_enqueue(req, 0, 0); | |
434 | } | |
435 | ||
436 | static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req) | |
437 | { | |
438 | return mxs_dcp_aes_enqueue(req, 1, 0); | |
439 | } | |
440 | ||
441 | static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
442 | unsigned int len) | |
443 | { | |
444 | struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm); | |
445 | unsigned int ret; | |
446 | ||
447 | /* | |
448 | * AES 128 is supposed by the hardware, store key into temporary | |
449 | * buffer and exit. We must use the temporary buffer here, since | |
450 | * there can still be an operation in progress. | |
451 | */ | |
452 | actx->key_len = len; | |
453 | if (len == AES_KEYSIZE_128) { | |
454 | memcpy(actx->key, key, len); | |
455 | return 0; | |
456 | } | |
457 | ||
458 | /* Check if the key size is supported by kernel at all. */ | |
459 | if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) { | |
460 | tfm->base.crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | /* | |
465 | * If the requested AES key size is not supported by the hardware, | |
466 | * but is supported by in-kernel software implementation, we use | |
467 | * software fallback. | |
468 | */ | |
469 | actx->fallback->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; | |
470 | actx->fallback->base.crt_flags |= | |
471 | tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK; | |
472 | ||
473 | ret = crypto_ablkcipher_setkey(actx->fallback, key, len); | |
474 | if (!ret) | |
475 | return 0; | |
476 | ||
477 | tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK; | |
478 | tfm->base.crt_flags |= | |
479 | actx->fallback->base.crt_flags & CRYPTO_TFM_RES_MASK; | |
480 | ||
481 | return ret; | |
482 | } | |
483 | ||
484 | static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm) | |
485 | { | |
486 | const char *name = tfm->__crt_alg->cra_name; | |
487 | const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; | |
488 | struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm); | |
489 | struct crypto_ablkcipher *blk; | |
490 | ||
491 | blk = crypto_alloc_ablkcipher(name, 0, flags); | |
492 | if (IS_ERR(blk)) | |
493 | return PTR_ERR(blk); | |
494 | ||
495 | actx->fallback = blk; | |
2021abaa | 496 | tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx); |
15b59e7c MV |
497 | return 0; |
498 | } | |
499 | ||
500 | static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm) | |
501 | { | |
502 | struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm); | |
503 | ||
504 | crypto_free_ablkcipher(actx->fallback); | |
505 | actx->fallback = NULL; | |
506 | } | |
507 | ||
508 | /* | |
509 | * Hashing (SHA1/SHA256) | |
510 | */ | |
511 | static int mxs_dcp_run_sha(struct ahash_request *req) | |
512 | { | |
513 | struct dcp *sdcp = global_sdcp; | |
514 | int ret; | |
515 | ||
516 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
517 | struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); | |
518 | struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); | |
519 | ||
520 | struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; | |
521 | dma_addr_t digest_phys = dma_map_single(sdcp->dev, | |
522 | sdcp->coh->sha_digest, | |
523 | SHA256_DIGEST_SIZE, | |
524 | DMA_FROM_DEVICE); | |
525 | ||
526 | dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf, | |
527 | DCP_BUF_SZ, DMA_TO_DEVICE); | |
528 | ||
529 | /* Fill in the DMA descriptor. */ | |
530 | desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | | |
531 | MXS_DCP_CONTROL0_INTERRUPT | | |
532 | MXS_DCP_CONTROL0_ENABLE_HASH; | |
533 | if (rctx->init) | |
534 | desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT; | |
535 | ||
536 | desc->control1 = actx->alg; | |
537 | desc->next_cmd_addr = 0; | |
538 | desc->source = buf_phys; | |
539 | desc->destination = 0; | |
540 | desc->size = actx->fill; | |
541 | desc->payload = 0; | |
542 | desc->status = 0; | |
543 | ||
544 | /* Set HASH_TERM bit for last transfer block. */ | |
545 | if (rctx->fini) { | |
546 | desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM; | |
547 | desc->payload = digest_phys; | |
548 | } | |
549 | ||
550 | ret = mxs_dcp_start_dma(actx); | |
551 | ||
552 | dma_unmap_single(sdcp->dev, digest_phys, SHA256_DIGEST_SIZE, | |
553 | DMA_FROM_DEVICE); | |
554 | dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE); | |
555 | ||
556 | return ret; | |
557 | } | |
558 | ||
559 | static int dcp_sha_req_to_buf(struct crypto_async_request *arq) | |
560 | { | |
561 | struct dcp *sdcp = global_sdcp; | |
562 | ||
563 | struct ahash_request *req = ahash_request_cast(arq); | |
564 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
565 | struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); | |
566 | struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); | |
567 | struct hash_alg_common *halg = crypto_hash_alg_common(tfm); | |
568 | const int nents = sg_nents(req->src); | |
569 | ||
570 | uint8_t *digest = sdcp->coh->sha_digest; | |
571 | uint8_t *in_buf = sdcp->coh->sha_in_buf; | |
572 | ||
573 | uint8_t *src_buf; | |
574 | ||
575 | struct scatterlist *src; | |
576 | ||
577 | unsigned int i, len, clen; | |
578 | int ret; | |
579 | ||
580 | int fin = rctx->fini; | |
581 | if (fin) | |
582 | rctx->fini = 0; | |
583 | ||
584 | for_each_sg(req->src, src, nents, i) { | |
585 | src_buf = sg_virt(src); | |
586 | len = sg_dma_len(src); | |
587 | ||
588 | do { | |
589 | if (actx->fill + len > DCP_BUF_SZ) | |
590 | clen = DCP_BUF_SZ - actx->fill; | |
591 | else | |
592 | clen = len; | |
593 | ||
594 | memcpy(in_buf + actx->fill, src_buf, clen); | |
595 | len -= clen; | |
596 | src_buf += clen; | |
597 | actx->fill += clen; | |
598 | ||
599 | /* | |
600 | * If we filled the buffer and still have some | |
601 | * more data, submit the buffer. | |
602 | */ | |
603 | if (len && actx->fill == DCP_BUF_SZ) { | |
604 | ret = mxs_dcp_run_sha(req); | |
605 | if (ret) | |
606 | return ret; | |
607 | actx->fill = 0; | |
608 | rctx->init = 0; | |
609 | } | |
610 | } while (len); | |
611 | } | |
612 | ||
613 | if (fin) { | |
614 | rctx->fini = 1; | |
615 | ||
616 | /* Submit whatever is left. */ | |
617 | ret = mxs_dcp_run_sha(req); | |
618 | if (ret || !req->result) | |
619 | return ret; | |
620 | actx->fill = 0; | |
621 | ||
622 | /* For some reason, the result is flipped. */ | |
623 | for (i = 0; i < halg->digestsize; i++) | |
624 | req->result[i] = digest[halg->digestsize - i - 1]; | |
625 | } | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | static int dcp_chan_thread_sha(void *data) | |
631 | { | |
632 | struct dcp *sdcp = global_sdcp; | |
633 | const int chan = DCP_CHAN_HASH_SHA; | |
634 | ||
635 | struct crypto_async_request *backlog; | |
636 | struct crypto_async_request *arq; | |
637 | ||
638 | struct dcp_sha_req_ctx *rctx; | |
639 | ||
640 | struct ahash_request *req; | |
641 | int ret, fini; | |
642 | ||
643 | do { | |
644 | __set_current_state(TASK_INTERRUPTIBLE); | |
645 | ||
646 | mutex_lock(&sdcp->mutex[chan]); | |
647 | backlog = crypto_get_backlog(&sdcp->queue[chan]); | |
648 | arq = crypto_dequeue_request(&sdcp->queue[chan]); | |
649 | mutex_unlock(&sdcp->mutex[chan]); | |
650 | ||
651 | if (backlog) | |
652 | backlog->complete(backlog, -EINPROGRESS); | |
653 | ||
654 | if (arq) { | |
655 | req = ahash_request_cast(arq); | |
656 | rctx = ahash_request_ctx(req); | |
657 | ||
658 | ret = dcp_sha_req_to_buf(arq); | |
659 | fini = rctx->fini; | |
660 | arq->complete(arq, ret); | |
661 | if (!fini) | |
662 | continue; | |
663 | } | |
664 | ||
665 | schedule(); | |
666 | } while (!kthread_should_stop()); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static int dcp_sha_init(struct ahash_request *req) | |
672 | { | |
673 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
674 | struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); | |
675 | ||
676 | struct hash_alg_common *halg = crypto_hash_alg_common(tfm); | |
677 | ||
678 | /* | |
679 | * Start hashing session. The code below only inits the | |
680 | * hashing session context, nothing more. | |
681 | */ | |
682 | memset(actx, 0, sizeof(*actx)); | |
683 | ||
684 | if (strcmp(halg->base.cra_name, "sha1") == 0) | |
685 | actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1; | |
686 | else | |
687 | actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256; | |
688 | ||
689 | actx->fill = 0; | |
690 | actx->hot = 0; | |
691 | actx->chan = DCP_CHAN_HASH_SHA; | |
692 | ||
693 | mutex_init(&actx->mutex); | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
698 | static int dcp_sha_update_fx(struct ahash_request *req, int fini) | |
699 | { | |
700 | struct dcp *sdcp = global_sdcp; | |
701 | ||
702 | struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); | |
703 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
704 | struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); | |
705 | ||
706 | int ret; | |
707 | ||
708 | /* | |
709 | * Ignore requests that have no data in them and are not | |
710 | * the trailing requests in the stream of requests. | |
711 | */ | |
712 | if (!req->nbytes && !fini) | |
713 | return 0; | |
714 | ||
715 | mutex_lock(&actx->mutex); | |
716 | ||
717 | rctx->fini = fini; | |
718 | ||
719 | if (!actx->hot) { | |
720 | actx->hot = 1; | |
721 | rctx->init = 1; | |
722 | } | |
723 | ||
724 | mutex_lock(&sdcp->mutex[actx->chan]); | |
725 | ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); | |
726 | mutex_unlock(&sdcp->mutex[actx->chan]); | |
727 | ||
728 | wake_up_process(sdcp->thread[actx->chan]); | |
729 | mutex_unlock(&actx->mutex); | |
730 | ||
731 | return -EINPROGRESS; | |
732 | } | |
733 | ||
734 | static int dcp_sha_update(struct ahash_request *req) | |
735 | { | |
736 | return dcp_sha_update_fx(req, 0); | |
737 | } | |
738 | ||
739 | static int dcp_sha_final(struct ahash_request *req) | |
740 | { | |
741 | ahash_request_set_crypt(req, NULL, req->result, 0); | |
742 | req->nbytes = 0; | |
743 | return dcp_sha_update_fx(req, 1); | |
744 | } | |
745 | ||
746 | static int dcp_sha_finup(struct ahash_request *req) | |
747 | { | |
748 | return dcp_sha_update_fx(req, 1); | |
749 | } | |
750 | ||
751 | static int dcp_sha_digest(struct ahash_request *req) | |
752 | { | |
753 | int ret; | |
754 | ||
755 | ret = dcp_sha_init(req); | |
756 | if (ret) | |
757 | return ret; | |
758 | ||
759 | return dcp_sha_finup(req); | |
760 | } | |
761 | ||
762 | static int dcp_sha_cra_init(struct crypto_tfm *tfm) | |
763 | { | |
764 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
765 | sizeof(struct dcp_sha_req_ctx)); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | static void dcp_sha_cra_exit(struct crypto_tfm *tfm) | |
770 | { | |
771 | } | |
772 | ||
773 | /* AES 128 ECB and AES 128 CBC */ | |
774 | static struct crypto_alg dcp_aes_algs[] = { | |
775 | { | |
776 | .cra_name = "ecb(aes)", | |
777 | .cra_driver_name = "ecb-aes-dcp", | |
778 | .cra_priority = 400, | |
779 | .cra_alignmask = 15, | |
780 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
781 | CRYPTO_ALG_ASYNC | | |
782 | CRYPTO_ALG_NEED_FALLBACK, | |
783 | .cra_init = mxs_dcp_aes_fallback_init, | |
784 | .cra_exit = mxs_dcp_aes_fallback_exit, | |
785 | .cra_blocksize = AES_BLOCK_SIZE, | |
786 | .cra_ctxsize = sizeof(struct dcp_async_ctx), | |
787 | .cra_type = &crypto_ablkcipher_type, | |
788 | .cra_module = THIS_MODULE, | |
789 | .cra_u = { | |
790 | .ablkcipher = { | |
791 | .min_keysize = AES_MIN_KEY_SIZE, | |
792 | .max_keysize = AES_MAX_KEY_SIZE, | |
793 | .setkey = mxs_dcp_aes_setkey, | |
794 | .encrypt = mxs_dcp_aes_ecb_encrypt, | |
795 | .decrypt = mxs_dcp_aes_ecb_decrypt | |
796 | }, | |
797 | }, | |
798 | }, { | |
799 | .cra_name = "cbc(aes)", | |
800 | .cra_driver_name = "cbc-aes-dcp", | |
801 | .cra_priority = 400, | |
802 | .cra_alignmask = 15, | |
803 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
804 | CRYPTO_ALG_ASYNC | | |
805 | CRYPTO_ALG_NEED_FALLBACK, | |
806 | .cra_init = mxs_dcp_aes_fallback_init, | |
807 | .cra_exit = mxs_dcp_aes_fallback_exit, | |
808 | .cra_blocksize = AES_BLOCK_SIZE, | |
809 | .cra_ctxsize = sizeof(struct dcp_async_ctx), | |
810 | .cra_type = &crypto_ablkcipher_type, | |
811 | .cra_module = THIS_MODULE, | |
812 | .cra_u = { | |
813 | .ablkcipher = { | |
814 | .min_keysize = AES_MIN_KEY_SIZE, | |
815 | .max_keysize = AES_MAX_KEY_SIZE, | |
816 | .setkey = mxs_dcp_aes_setkey, | |
817 | .encrypt = mxs_dcp_aes_cbc_encrypt, | |
818 | .decrypt = mxs_dcp_aes_cbc_decrypt, | |
819 | .ivsize = AES_BLOCK_SIZE, | |
820 | }, | |
821 | }, | |
822 | }, | |
823 | }; | |
824 | ||
825 | /* SHA1 */ | |
826 | static struct ahash_alg dcp_sha1_alg = { | |
827 | .init = dcp_sha_init, | |
828 | .update = dcp_sha_update, | |
829 | .final = dcp_sha_final, | |
830 | .finup = dcp_sha_finup, | |
831 | .digest = dcp_sha_digest, | |
832 | .halg = { | |
833 | .digestsize = SHA1_DIGEST_SIZE, | |
834 | .base = { | |
835 | .cra_name = "sha1", | |
836 | .cra_driver_name = "sha1-dcp", | |
837 | .cra_priority = 400, | |
838 | .cra_alignmask = 63, | |
839 | .cra_flags = CRYPTO_ALG_ASYNC, | |
840 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
841 | .cra_ctxsize = sizeof(struct dcp_async_ctx), | |
842 | .cra_module = THIS_MODULE, | |
843 | .cra_init = dcp_sha_cra_init, | |
844 | .cra_exit = dcp_sha_cra_exit, | |
845 | }, | |
846 | }, | |
847 | }; | |
848 | ||
849 | /* SHA256 */ | |
850 | static struct ahash_alg dcp_sha256_alg = { | |
851 | .init = dcp_sha_init, | |
852 | .update = dcp_sha_update, | |
853 | .final = dcp_sha_final, | |
854 | .finup = dcp_sha_finup, | |
855 | .digest = dcp_sha_digest, | |
856 | .halg = { | |
857 | .digestsize = SHA256_DIGEST_SIZE, | |
858 | .base = { | |
859 | .cra_name = "sha256", | |
860 | .cra_driver_name = "sha256-dcp", | |
861 | .cra_priority = 400, | |
862 | .cra_alignmask = 63, | |
863 | .cra_flags = CRYPTO_ALG_ASYNC, | |
864 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
865 | .cra_ctxsize = sizeof(struct dcp_async_ctx), | |
866 | .cra_module = THIS_MODULE, | |
867 | .cra_init = dcp_sha_cra_init, | |
868 | .cra_exit = dcp_sha_cra_exit, | |
869 | }, | |
870 | }, | |
871 | }; | |
872 | ||
873 | static irqreturn_t mxs_dcp_irq(int irq, void *context) | |
874 | { | |
875 | struct dcp *sdcp = context; | |
876 | uint32_t stat; | |
877 | int i; | |
878 | ||
879 | stat = readl(sdcp->base + MXS_DCP_STAT); | |
880 | stat &= MXS_DCP_STAT_IRQ_MASK; | |
881 | if (!stat) | |
882 | return IRQ_NONE; | |
883 | ||
884 | /* Clear the interrupts. */ | |
885 | writel(stat, sdcp->base + MXS_DCP_STAT_CLR); | |
886 | ||
887 | /* Complete the DMA requests that finished. */ | |
888 | for (i = 0; i < DCP_MAX_CHANS; i++) | |
889 | if (stat & (1 << i)) | |
890 | complete(&sdcp->completion[i]); | |
891 | ||
892 | return IRQ_HANDLED; | |
893 | } | |
894 | ||
895 | static int mxs_dcp_probe(struct platform_device *pdev) | |
896 | { | |
897 | struct device *dev = &pdev->dev; | |
898 | struct dcp *sdcp = NULL; | |
899 | int i, ret; | |
900 | ||
901 | struct resource *iores; | |
902 | int dcp_vmi_irq, dcp_irq; | |
903 | ||
904 | mutex_lock(&global_mutex); | |
905 | if (global_sdcp) { | |
906 | dev_err(dev, "Only one DCP instance allowed!\n"); | |
907 | ret = -ENODEV; | |
908 | goto err_mutex; | |
909 | } | |
910 | ||
911 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
912 | dcp_vmi_irq = platform_get_irq(pdev, 0); | |
d9588f87 FE |
913 | if (dcp_vmi_irq < 0) { |
914 | ret = dcp_vmi_irq; | |
915 | goto err_mutex; | |
916 | } | |
917 | ||
15b59e7c | 918 | dcp_irq = platform_get_irq(pdev, 1); |
d9588f87 FE |
919 | if (dcp_irq < 0) { |
920 | ret = dcp_irq; | |
15b59e7c MV |
921 | goto err_mutex; |
922 | } | |
923 | ||
924 | sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); | |
925 | if (!sdcp) { | |
926 | ret = -ENOMEM; | |
927 | goto err_mutex; | |
928 | } | |
929 | ||
930 | sdcp->dev = dev; | |
931 | sdcp->base = devm_ioremap_resource(dev, iores); | |
932 | if (IS_ERR(sdcp->base)) { | |
933 | ret = PTR_ERR(sdcp->base); | |
934 | goto err_mutex; | |
935 | } | |
936 | ||
937 | ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0, | |
938 | "dcp-vmi-irq", sdcp); | |
939 | if (ret) { | |
940 | dev_err(dev, "Failed to claim DCP VMI IRQ!\n"); | |
941 | goto err_mutex; | |
942 | } | |
943 | ||
944 | ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0, | |
945 | "dcp-irq", sdcp); | |
946 | if (ret) { | |
947 | dev_err(dev, "Failed to claim DCP IRQ!\n"); | |
948 | goto err_mutex; | |
949 | } | |
950 | ||
951 | /* Allocate coherent helper block. */ | |
1a7c6856 MV |
952 | sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT, |
953 | GFP_KERNEL); | |
15b59e7c | 954 | if (!sdcp->coh) { |
15b59e7c MV |
955 | ret = -ENOMEM; |
956 | goto err_mutex; | |
957 | } | |
958 | ||
1a7c6856 MV |
959 | /* Re-align the structure so it fits the DCP constraints. */ |
960 | sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT); | |
961 | ||
15b59e7c | 962 | /* Restart the DCP block. */ |
fecfd7f7 FE |
963 | ret = stmp_reset_block(sdcp->base); |
964 | if (ret) | |
965 | goto err_mutex; | |
15b59e7c MV |
966 | |
967 | /* Initialize control register. */ | |
968 | writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES | | |
969 | MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf, | |
970 | sdcp->base + MXS_DCP_CTRL); | |
971 | ||
972 | /* Enable all DCP DMA channels. */ | |
973 | writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, | |
974 | sdcp->base + MXS_DCP_CHANNELCTRL); | |
975 | ||
976 | /* | |
977 | * We do not enable context switching. Give the context buffer a | |
978 | * pointer to an illegal address so if context switching is | |
979 | * inadvertantly enabled, the DCP will return an error instead of | |
980 | * trashing good memory. The DCP DMA cannot access ROM, so any ROM | |
981 | * address will do. | |
982 | */ | |
983 | writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT); | |
984 | for (i = 0; i < DCP_MAX_CHANS; i++) | |
985 | writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i)); | |
986 | writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR); | |
987 | ||
988 | global_sdcp = sdcp; | |
989 | ||
990 | platform_set_drvdata(pdev, sdcp); | |
991 | ||
992 | for (i = 0; i < DCP_MAX_CHANS; i++) { | |
993 | mutex_init(&sdcp->mutex[i]); | |
994 | init_completion(&sdcp->completion[i]); | |
995 | crypto_init_queue(&sdcp->queue[i], 50); | |
996 | } | |
997 | ||
998 | /* Create the SHA and AES handler threads. */ | |
999 | sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha, | |
1000 | NULL, "mxs_dcp_chan/sha"); | |
1001 | if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) { | |
1002 | dev_err(dev, "Error starting SHA thread!\n"); | |
1003 | ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]); | |
e921f030 | 1004 | goto err_mutex; |
15b59e7c MV |
1005 | } |
1006 | ||
1007 | sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes, | |
1008 | NULL, "mxs_dcp_chan/aes"); | |
1009 | if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) { | |
1010 | dev_err(dev, "Error starting SHA thread!\n"); | |
1011 | ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]); | |
1012 | goto err_destroy_sha_thread; | |
1013 | } | |
1014 | ||
1015 | /* Register the various crypto algorithms. */ | |
1016 | sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1); | |
1017 | ||
1018 | if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) { | |
1019 | ret = crypto_register_algs(dcp_aes_algs, | |
1020 | ARRAY_SIZE(dcp_aes_algs)); | |
1021 | if (ret) { | |
1022 | /* Failed to register algorithm. */ | |
1023 | dev_err(dev, "Failed to register AES crypto!\n"); | |
1024 | goto err_destroy_aes_thread; | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) { | |
1029 | ret = crypto_register_ahash(&dcp_sha1_alg); | |
1030 | if (ret) { | |
1031 | dev_err(dev, "Failed to register %s hash!\n", | |
1032 | dcp_sha1_alg.halg.base.cra_name); | |
1033 | goto err_unregister_aes; | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) { | |
1038 | ret = crypto_register_ahash(&dcp_sha256_alg); | |
1039 | if (ret) { | |
1040 | dev_err(dev, "Failed to register %s hash!\n", | |
1041 | dcp_sha256_alg.halg.base.cra_name); | |
1042 | goto err_unregister_sha1; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | ||
1048 | err_unregister_sha1: | |
1049 | if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) | |
1050 | crypto_unregister_ahash(&dcp_sha1_alg); | |
1051 | ||
1052 | err_unregister_aes: | |
1053 | if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) | |
1054 | crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); | |
1055 | ||
1056 | err_destroy_aes_thread: | |
1057 | kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); | |
1058 | ||
1059 | err_destroy_sha_thread: | |
1060 | kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); | |
1061 | ||
15b59e7c MV |
1062 | err_mutex: |
1063 | mutex_unlock(&global_mutex); | |
1064 | return ret; | |
1065 | } | |
1066 | ||
1067 | static int mxs_dcp_remove(struct platform_device *pdev) | |
1068 | { | |
1069 | struct dcp *sdcp = platform_get_drvdata(pdev); | |
1070 | ||
15b59e7c MV |
1071 | if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) |
1072 | crypto_unregister_ahash(&dcp_sha256_alg); | |
1073 | ||
1074 | if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) | |
1075 | crypto_unregister_ahash(&dcp_sha1_alg); | |
1076 | ||
1077 | if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) | |
1078 | crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); | |
1079 | ||
1080 | kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); | |
1081 | kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); | |
1082 | ||
1083 | platform_set_drvdata(pdev, NULL); | |
1084 | ||
1085 | mutex_lock(&global_mutex); | |
1086 | global_sdcp = NULL; | |
1087 | mutex_unlock(&global_mutex); | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static const struct of_device_id mxs_dcp_dt_ids[] = { | |
1093 | { .compatible = "fsl,imx23-dcp", .data = NULL, }, | |
1094 | { .compatible = "fsl,imx28-dcp", .data = NULL, }, | |
1095 | { /* sentinel */ } | |
1096 | }; | |
1097 | ||
1098 | MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids); | |
1099 | ||
1100 | static struct platform_driver mxs_dcp_driver = { | |
1101 | .probe = mxs_dcp_probe, | |
1102 | .remove = mxs_dcp_remove, | |
1103 | .driver = { | |
1104 | .name = "mxs-dcp", | |
1105 | .owner = THIS_MODULE, | |
1106 | .of_match_table = mxs_dcp_dt_ids, | |
1107 | }, | |
1108 | }; | |
1109 | ||
1110 | module_platform_driver(mxs_dcp_driver); | |
1111 | ||
1112 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
1113 | MODULE_DESCRIPTION("Freescale MXS DCP Driver"); | |
1114 | MODULE_LICENSE("GPL"); | |
1115 | MODULE_ALIAS("platform:mxs-dcp"); |