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crypto: remove a duplicate checks in __cbc_decrypt()
[deliverable/linux.git] / drivers / crypto / mxs-dcp.c
CommitLineData
15b59e7c
MV		 1/*
2 * Freescale i.MX23/i.MX28 Data Co-Processor driver
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/crypto.h>
15#include <linux/dma-mapping.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/kthread.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/stmp_device.h>
24
25#include <crypto/aes.h>
26#include <crypto/sha.h>
27#include <crypto/internal/hash.h>
28
29#define DCP_MAX_CHANS 4
30#define DCP_BUF_SZ PAGE_SIZE
31
32/* DCP DMA descriptor. */
33struct dcp_dma_desc {
34 uint32_t next_cmd_addr;
35 uint32_t control0;
36 uint32_t control1;
37 uint32_t source;
38 uint32_t destination;
39 uint32_t size;
40 uint32_t payload;
41 uint32_t status;
42};
43
44/* Coherent aligned block for bounce buffering. */
45struct dcp_coherent_block {
46 uint8_t aes_in_buf[DCP_BUF_SZ];
47 uint8_t aes_out_buf[DCP_BUF_SZ];
48 uint8_t sha_in_buf[DCP_BUF_SZ];
49
50 uint8_t aes_key[2 * AES_KEYSIZE_128];
51 uint8_t sha_digest[SHA256_DIGEST_SIZE];
52
53 struct dcp_dma_desc desc[DCP_MAX_CHANS];
54};
55
56struct dcp {
57 struct device *dev;
58 void __iomem *base;
59
60 uint32_t caps;
61
62 struct dcp_coherent_block *coh;
63
64 struct completion completion[DCP_MAX_CHANS];
65 struct mutex mutex[DCP_MAX_CHANS];
66 struct task_struct *thread[DCP_MAX_CHANS];
67 struct crypto_queue queue[DCP_MAX_CHANS];
68};
69
70enum dcp_chan {
71 DCP_CHAN_HASH_SHA = 0,
72 DCP_CHAN_CRYPTO = 2,
73};
74
75struct dcp_async_ctx {
76 /* Common context */
77 enum dcp_chan chan;
78 uint32_t fill;
79
80 /* SHA Hash-specific context */
81 struct mutex mutex;
82 uint32_t alg;
83 unsigned int hot:1;
84
85 /* Crypto-specific context */
15b59e7c
MV		 86 struct crypto_ablkcipher *fallback;
87 unsigned int key_len;
88 uint8_t key[AES_KEYSIZE_128];
89};
90
2021abaa
MV		 91struct dcp_aes_req_ctx {
92 unsigned int enc:1;
93 unsigned int ecb:1;
94};
95
15b59e7c
MV		 96struct dcp_sha_req_ctx {
97 unsigned int init:1;
98 unsigned int fini:1;
99};
100
101/*
102 * There can even be only one instance of the MXS DCP due to the
103 * design of Linux Crypto API.
104 */
105static struct dcp *global_sdcp;
fe70be5c 106static DEFINE_MUTEX(global_mutex);
15b59e7c
MV		 107
108/* DCP register layout. */
109#define MXS_DCP_CTRL 0x00
110#define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
111#define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
112
113#define MXS_DCP_STAT 0x10
114#define MXS_DCP_STAT_CLR 0x18
115#define MXS_DCP_STAT_IRQ_MASK 0xf
116
117#define MXS_DCP_CHANNELCTRL 0x20
118#define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
119
120#define MXS_DCP_CAPABILITY1 0x40
121#define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
122#define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
123#define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
124
125#define MXS_DCP_CONTEXT 0x50
126
127#define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
128
129#define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
130
131#define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
132#define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
133
134/* DMA descriptor bits. */
135#define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
136#define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
137#define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
138#define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
139#define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
140#define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
141#define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
142#define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
143#define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
144
145#define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
146#define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
147#define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
148#define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
149#define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
150
151static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
152{
153 struct dcp *sdcp = global_sdcp;
154 const int chan = actx->chan;
155 uint32_t stat;
156 int ret;
157 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
158
159 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
160 DMA_TO_DEVICE);
161
162 reinit_completion(&sdcp->completion[chan]);
163
164 /* Clear status register. */
165 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
166
167 /* Load the DMA descriptor. */
168 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
169
170 /* Increment the semaphore to start the DMA transfer. */
171 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
172
173 ret = wait_for_completion_timeout(&sdcp->completion[chan],
174 msecs_to_jiffies(1000));
175 if (!ret) {
176 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
177 chan, readl(sdcp->base + MXS_DCP_STAT));
178 return -ETIMEDOUT;
179 }
180
181 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
182 if (stat & 0xff) {
183 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
184 chan, stat);
185 return -EINVAL;
186 }
187
188 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
189
190 return 0;
191}
192
193/*
194 * Encryption (AES128)
195 */
2021abaa
MV		 196static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
197 struct ablkcipher_request *req, int init)
15b59e7c
MV		 198{
199 struct dcp *sdcp = global_sdcp;
200 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
2021abaa 201 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 202 int ret;
203
204 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
205 2 * AES_KEYSIZE_128,
206 DMA_TO_DEVICE);
207 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
208 DCP_BUF_SZ, DMA_TO_DEVICE);
209 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
210 DCP_BUF_SZ, DMA_FROM_DEVICE);
211
212 /* Fill in the DMA descriptor. */
213 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
214 MXS_DCP_CONTROL0_INTERRUPT |
215 MXS_DCP_CONTROL0_ENABLE_CIPHER;
216
217 /* Payload contains the key. */
218 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
219
2021abaa 220 if (rctx->enc)
15b59e7c
MV		 221 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
222 if (init)
223 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
224
225 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
226
2021abaa 227 if (rctx->ecb)
15b59e7c
MV		 228 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
229 else
230 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
231
232 desc->next_cmd_addr = 0;
233 desc->source = src_phys;
234 desc->destination = dst_phys;
235 desc->size = actx->fill;
236 desc->payload = key_phys;
237 desc->status = 0;
238
239 ret = mxs_dcp_start_dma(actx);
240
241 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
242 DMA_TO_DEVICE);
243 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
244 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
245
246 return ret;
247}
248
249static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
250{
251 struct dcp *sdcp = global_sdcp;
252
253 struct ablkcipher_request *req = ablkcipher_request_cast(arq);
254 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
2021abaa 255 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 256
257 struct scatterlist *dst = req->dst;
258 struct scatterlist *src = req->src;
259 const int nents = sg_nents(req->src);
260
261 const int out_off = DCP_BUF_SZ;
262 uint8_t *in_buf = sdcp->coh->aes_in_buf;
263 uint8_t *out_buf = sdcp->coh->aes_out_buf;
264
265 uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
266 uint32_t dst_off = 0;
267
268 uint8_t *key = sdcp->coh->aes_key;
269
270 int ret = 0;
271 int split = 0;
272 unsigned int i, len, clen, rem = 0;
273 int init = 0;
274
275 actx->fill = 0;
276
277 /* Copy the key from the temporary location. */
278 memcpy(key, actx->key, actx->key_len);
279
2021abaa 280 if (!rctx->ecb) {
15b59e7c
MV		 281 /* Copy the CBC IV just past the key. */
282 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
283 /* CBC needs the INIT set. */
284 init = 1;
285 } else {
286 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
287 }
288
289 for_each_sg(req->src, src, nents, i) {
290 src_buf = sg_virt(src);
291 len = sg_dma_len(src);
292
293 do {
294 if (actx->fill + len > out_off)
295 clen = out_off - actx->fill;
296 else
297 clen = len;
298
299 memcpy(in_buf + actx->fill, src_buf, clen);
300 len -= clen;
301 src_buf += clen;
302 actx->fill += clen;
303
304 /*
305 * If we filled the buffer or this is the last SG,
306 * submit the buffer.
307 */
308 if (actx->fill == out_off || sg_is_last(src)) {
2021abaa 309 ret = mxs_dcp_run_aes(actx, req, init);
15b59e7c
MV		 310 if (ret)
311 return ret;
312 init = 0;
313
314 out_tmp = out_buf;
315 while (dst && actx->fill) {
316 if (!split) {
317 dst_buf = sg_virt(dst);
318 dst_off = 0;
319 }
320 rem = min(sg_dma_len(dst) - dst_off,
321 actx->fill);
322
323 memcpy(dst_buf + dst_off, out_tmp, rem);
324 out_tmp += rem;
325 dst_off += rem;
326 actx->fill -= rem;
327
328 if (dst_off == sg_dma_len(dst)) {
329 dst = sg_next(dst);
330 split = 0;
331 } else {
332 split = 1;
333 }
334 }
335 }
336 } while (len);
337 }
338
339 return ret;
340}
341
342static int dcp_chan_thread_aes(void *data)
343{
344 struct dcp *sdcp = global_sdcp;
345 const int chan = DCP_CHAN_CRYPTO;
346
347 struct crypto_async_request *backlog;
348 struct crypto_async_request *arq;
349
350 int ret;
351
352 do {
353 __set_current_state(TASK_INTERRUPTIBLE);
354
355 mutex_lock(&sdcp->mutex[chan]);
356 backlog = crypto_get_backlog(&sdcp->queue[chan]);
357 arq = crypto_dequeue_request(&sdcp->queue[chan]);
358 mutex_unlock(&sdcp->mutex[chan]);
359
360 if (backlog)
361 backlog->complete(backlog, -EINPROGRESS);
362
363 if (arq) {
364 ret = mxs_dcp_aes_block_crypt(arq);
365 arq->complete(arq, ret);
366 continue;
367 }
368
369 schedule();
370 } while (!kthread_should_stop());
371
372 return 0;
373}
374
375static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
376{
377 struct crypto_tfm *tfm =
378 crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
379 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(
380 crypto_ablkcipher_reqtfm(req));
381 int ret;
382
383 ablkcipher_request_set_tfm(req, ctx->fallback);
384
385 if (enc)
386 ret = crypto_ablkcipher_encrypt(req);
387 else
388 ret = crypto_ablkcipher_decrypt(req);
389
390 ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm));
391
392 return ret;
393}
394
395static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
396{
397 struct dcp *sdcp = global_sdcp;
398 struct crypto_async_request *arq = &req->base;
399 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
2021abaa 400 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 401 int ret;
402
403 if (unlikely(actx->key_len != AES_KEYSIZE_128))
404 return mxs_dcp_block_fallback(req, enc);
405
2021abaa
MV		 406 rctx->enc = enc;
407 rctx->ecb = ecb;
15b59e7c
MV		 408 actx->chan = DCP_CHAN_CRYPTO;
409
410 mutex_lock(&sdcp->mutex[actx->chan]);
411 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
412 mutex_unlock(&sdcp->mutex[actx->chan]);
413
414 wake_up_process(sdcp->thread[actx->chan]);
415
416 return -EINPROGRESS;
417}
418
419static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
420{
421 return mxs_dcp_aes_enqueue(req, 0, 1);
422}
423
424static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
425{
426 return mxs_dcp_aes_enqueue(req, 1, 1);
427}
428
429static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
430{
431 return mxs_dcp_aes_enqueue(req, 0, 0);
432}
433
434static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
435{
436 return mxs_dcp_aes_enqueue(req, 1, 0);
437}
438
439static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
440 unsigned int len)
441{
442 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
443 unsigned int ret;
444
445 /*
446 * AES 128 is supposed by the hardware, store key into temporary
447 * buffer and exit. We must use the temporary buffer here, since
448 * there can still be an operation in progress.
449 */
450 actx->key_len = len;
451 if (len == AES_KEYSIZE_128) {
452 memcpy(actx->key, key, len);
453 return 0;
454 }
455
456 /* Check if the key size is supported by kernel at all. */
457 if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
458 tfm->base.crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
459 return -EINVAL;
460 }
461
462 /*
463 * If the requested AES key size is not supported by the hardware,
464 * but is supported by in-kernel software implementation, we use
465 * software fallback.
466 */
467 actx->fallback->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
468 actx->fallback->base.crt_flags |=
469 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK;
470
471 ret = crypto_ablkcipher_setkey(actx->fallback, key, len);
472 if (!ret)
473 return 0;
474
475 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
476 tfm->base.crt_flags |=
477 actx->fallback->base.crt_flags & CRYPTO_TFM_RES_MASK;
478
479 return ret;
480}
481
482static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
483{
484 const char *name = tfm->__crt_alg->cra_name;
485 const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
486 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
487 struct crypto_ablkcipher *blk;
488
489 blk = crypto_alloc_ablkcipher(name, 0, flags);
490 if (IS_ERR(blk))
491 return PTR_ERR(blk);
492
493 actx->fallback = blk;
2021abaa 494 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
15b59e7c
MV		 495 return 0;
496}
497
498static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
499{
500 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
501
502 crypto_free_ablkcipher(actx->fallback);
503 actx->fallback = NULL;
504}
505
506/*
507 * Hashing (SHA1/SHA256)
508 */
509static int mxs_dcp_run_sha(struct ahash_request *req)
510{
511 struct dcp *sdcp = global_sdcp;
512 int ret;
513
514 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
515 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
516 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
517
518 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
519 dma_addr_t digest_phys = dma_map_single(sdcp->dev,
520 sdcp->coh->sha_digest,
521 SHA256_DIGEST_SIZE,
522 DMA_FROM_DEVICE);
523
524 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
525 DCP_BUF_SZ, DMA_TO_DEVICE);
526
527 /* Fill in the DMA descriptor. */
528 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
529 MXS_DCP_CONTROL0_INTERRUPT |
530 MXS_DCP_CONTROL0_ENABLE_HASH;
531 if (rctx->init)
532 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
533
534 desc->control1 = actx->alg;
535 desc->next_cmd_addr = 0;
536 desc->source = buf_phys;
537 desc->destination = 0;
538 desc->size = actx->fill;
539 desc->payload = 0;
540 desc->status = 0;
541
542 /* Set HASH_TERM bit for last transfer block. */
543 if (rctx->fini) {
544 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
545 desc->payload = digest_phys;
546 }
547
548 ret = mxs_dcp_start_dma(actx);
549
550 dma_unmap_single(sdcp->dev, digest_phys, SHA256_DIGEST_SIZE,
551 DMA_FROM_DEVICE);
552 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
553
554 return ret;
555}
556
557static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
558{
559 struct dcp *sdcp = global_sdcp;
560
561 struct ahash_request *req = ahash_request_cast(arq);
562 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
563 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
564 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
565 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
566 const int nents = sg_nents(req->src);
567
568 uint8_t *digest = sdcp->coh->sha_digest;
569 uint8_t *in_buf = sdcp->coh->sha_in_buf;
570
571 uint8_t *src_buf;
572
573 struct scatterlist *src;
574
575 unsigned int i, len, clen;
576 int ret;
577
578 int fin = rctx->fini;
579 if (fin)
580 rctx->fini = 0;
581
582 for_each_sg(req->src, src, nents, i) {
583 src_buf = sg_virt(src);
584 len = sg_dma_len(src);
585
586 do {
587 if (actx->fill + len > DCP_BUF_SZ)
588 clen = DCP_BUF_SZ - actx->fill;
589 else
590 clen = len;
591
592 memcpy(in_buf + actx->fill, src_buf, clen);
593 len -= clen;
594 src_buf += clen;
595 actx->fill += clen;
596
597 /*
598 * If we filled the buffer and still have some
599 * more data, submit the buffer.
600 */
601 if (len && actx->fill == DCP_BUF_SZ) {
602 ret = mxs_dcp_run_sha(req);
603 if (ret)
604 return ret;
605 actx->fill = 0;
606 rctx->init = 0;
607 }
608 } while (len);
609 }
610
611 if (fin) {
612 rctx->fini = 1;
613
614 /* Submit whatever is left. */
615 ret = mxs_dcp_run_sha(req);
616 if (ret || !req->result)
617 return ret;
618 actx->fill = 0;
619
620 /* For some reason, the result is flipped. */
621 for (i = 0; i < halg->digestsize; i++)
622 req->result[i] = digest[halg->digestsize - i - 1];
623 }
624
625 return 0;
626}
627
628static int dcp_chan_thread_sha(void *data)
629{
630 struct dcp *sdcp = global_sdcp;
631 const int chan = DCP_CHAN_HASH_SHA;
632
633 struct crypto_async_request *backlog;
634 struct crypto_async_request *arq;
635
636 struct dcp_sha_req_ctx *rctx;
637
638 struct ahash_request *req;
639 int ret, fini;
640
641 do {
642 __set_current_state(TASK_INTERRUPTIBLE);
643
644 mutex_lock(&sdcp->mutex[chan]);
645 backlog = crypto_get_backlog(&sdcp->queue[chan]);
646 arq = crypto_dequeue_request(&sdcp->queue[chan]);
647 mutex_unlock(&sdcp->mutex[chan]);
648
649 if (backlog)
650 backlog->complete(backlog, -EINPROGRESS);
651
652 if (arq) {
653 req = ahash_request_cast(arq);
654 rctx = ahash_request_ctx(req);
655
656 ret = dcp_sha_req_to_buf(arq);
657 fini = rctx->fini;
658 arq->complete(arq, ret);
659 if (!fini)
660 continue;
661 }
662
663 schedule();
664 } while (!kthread_should_stop());
665
666 return 0;
667}
668
669static int dcp_sha_init(struct ahash_request *req)
670{
671 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
672 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
673
674 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
675
676 /*
677 * Start hashing session. The code below only inits the
678 * hashing session context, nothing more.
679 */
680 memset(actx, 0, sizeof(*actx));
681
682 if (strcmp(halg->base.cra_name, "sha1") == 0)
683 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
684 else
685 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
686
687 actx->fill = 0;
688 actx->hot = 0;
689 actx->chan = DCP_CHAN_HASH_SHA;
690
691 mutex_init(&actx->mutex);
692
693 return 0;
694}
695
696static int dcp_sha_update_fx(struct ahash_request *req, int fini)
697{
698 struct dcp *sdcp = global_sdcp;
699
700 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
701 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
702 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
703
704 int ret;
705
706 /*
707 * Ignore requests that have no data in them and are not
708 * the trailing requests in the stream of requests.
709 */
710 if (!req->nbytes && !fini)
711 return 0;
712
713 mutex_lock(&actx->mutex);
714
715 rctx->fini = fini;
716
717 if (!actx->hot) {
718 actx->hot = 1;
719 rctx->init = 1;
720 }
721
722 mutex_lock(&sdcp->mutex[actx->chan]);
723 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
724 mutex_unlock(&sdcp->mutex[actx->chan]);
725
726 wake_up_process(sdcp->thread[actx->chan]);
727 mutex_unlock(&actx->mutex);
728
729 return -EINPROGRESS;
730}
731
732static int dcp_sha_update(struct ahash_request *req)
733{
734 return dcp_sha_update_fx(req, 0);
735}
736
737static int dcp_sha_final(struct ahash_request *req)
738{
739 ahash_request_set_crypt(req, NULL, req->result, 0);
740 req->nbytes = 0;
741 return dcp_sha_update_fx(req, 1);
742}
743
744static int dcp_sha_finup(struct ahash_request *req)
745{
746 return dcp_sha_update_fx(req, 1);
747}
748
749static int dcp_sha_digest(struct ahash_request *req)
750{
751 int ret;
752
753 ret = dcp_sha_init(req);
754 if (ret)
755 return ret;
756
757 return dcp_sha_finup(req);
758}
759
760static int dcp_sha_cra_init(struct crypto_tfm *tfm)
761{
762 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
763 sizeof(struct dcp_sha_req_ctx));
764 return 0;
765}
766
767static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
768{
769}
770
771/* AES 128 ECB and AES 128 CBC */
772static struct crypto_alg dcp_aes_algs[] = {
773 {
774 .cra_name = "ecb(aes)",
775 .cra_driver_name = "ecb-aes-dcp",
776 .cra_priority = 400,
777 .cra_alignmask = 15,
778 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
779 CRYPTO_ALG_ASYNC |
780 CRYPTO_ALG_NEED_FALLBACK,
781 .cra_init = mxs_dcp_aes_fallback_init,
782 .cra_exit = mxs_dcp_aes_fallback_exit,
783 .cra_blocksize = AES_BLOCK_SIZE,
784 .cra_ctxsize = sizeof(struct dcp_async_ctx),
785 .cra_type = &crypto_ablkcipher_type,
786 .cra_module = THIS_MODULE,
787 .cra_u = {
788 .ablkcipher = {
789 .min_keysize = AES_MIN_KEY_SIZE,
790 .max_keysize = AES_MAX_KEY_SIZE,
791 .setkey = mxs_dcp_aes_setkey,
792 .encrypt = mxs_dcp_aes_ecb_encrypt,
793 .decrypt = mxs_dcp_aes_ecb_decrypt
794 },
795 },
796 }, {
797 .cra_name = "cbc(aes)",
798 .cra_driver_name = "cbc-aes-dcp",
799 .cra_priority = 400,
800 .cra_alignmask = 15,
801 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
802 CRYPTO_ALG_ASYNC |
803 CRYPTO_ALG_NEED_FALLBACK,
804 .cra_init = mxs_dcp_aes_fallback_init,
805 .cra_exit = mxs_dcp_aes_fallback_exit,
806 .cra_blocksize = AES_BLOCK_SIZE,
807 .cra_ctxsize = sizeof(struct dcp_async_ctx),
808 .cra_type = &crypto_ablkcipher_type,
809 .cra_module = THIS_MODULE,
810 .cra_u = {
811 .ablkcipher = {
812 .min_keysize = AES_MIN_KEY_SIZE,
813 .max_keysize = AES_MAX_KEY_SIZE,
814 .setkey = mxs_dcp_aes_setkey,
815 .encrypt = mxs_dcp_aes_cbc_encrypt,
816 .decrypt = mxs_dcp_aes_cbc_decrypt,
817 .ivsize = AES_BLOCK_SIZE,
818 },
819 },
820 },
821};
822
823/* SHA1 */
824static struct ahash_alg dcp_sha1_alg = {
825 .init = dcp_sha_init,
826 .update = dcp_sha_update,
827 .final = dcp_sha_final,
828 .finup = dcp_sha_finup,
829 .digest = dcp_sha_digest,
830 .halg = {
831 .digestsize = SHA1_DIGEST_SIZE,
832 .base = {
833 .cra_name = "sha1",
834 .cra_driver_name = "sha1-dcp",
835 .cra_priority = 400,
836 .cra_alignmask = 63,
837 .cra_flags = CRYPTO_ALG_ASYNC,
838 .cra_blocksize = SHA1_BLOCK_SIZE,
839 .cra_ctxsize = sizeof(struct dcp_async_ctx),
840 .cra_module = THIS_MODULE,
841 .cra_init = dcp_sha_cra_init,
842 .cra_exit = dcp_sha_cra_exit,
843 },
844 },
845};
846
847/* SHA256 */
848static struct ahash_alg dcp_sha256_alg = {
849 .init = dcp_sha_init,
850 .update = dcp_sha_update,
851 .final = dcp_sha_final,
852 .finup = dcp_sha_finup,
853 .digest = dcp_sha_digest,
854 .halg = {
855 .digestsize = SHA256_DIGEST_SIZE,
856 .base = {
857 .cra_name = "sha256",
858 .cra_driver_name = "sha256-dcp",
859 .cra_priority = 400,
860 .cra_alignmask = 63,
861 .cra_flags = CRYPTO_ALG_ASYNC,
862 .cra_blocksize = SHA256_BLOCK_SIZE,
863 .cra_ctxsize = sizeof(struct dcp_async_ctx),
864 .cra_module = THIS_MODULE,
865 .cra_init = dcp_sha_cra_init,
866 .cra_exit = dcp_sha_cra_exit,
867 },
868 },
869};
870
871static irqreturn_t mxs_dcp_irq(int irq, void *context)
872{
873 struct dcp *sdcp = context;
874 uint32_t stat;
875 int i;
876
877 stat = readl(sdcp->base + MXS_DCP_STAT);
878 stat &= MXS_DCP_STAT_IRQ_MASK;
879 if (!stat)
880 return IRQ_NONE;
881
882 /* Clear the interrupts. */
883 writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
884
885 /* Complete the DMA requests that finished. */
886 for (i = 0; i < DCP_MAX_CHANS; i++)
887 if (stat & (1 << i))
888 complete(&sdcp->completion[i]);
889
890 return IRQ_HANDLED;
891}
892
893static int mxs_dcp_probe(struct platform_device *pdev)
894{
895 struct device *dev = &pdev->dev;
896 struct dcp *sdcp = NULL;
897 int i, ret;
898
899 struct resource *iores;
900 int dcp_vmi_irq, dcp_irq;
901
902 mutex_lock(&global_mutex);
903 if (global_sdcp) {
904 dev_err(dev, "Only one DCP instance allowed!\n");
905 ret = -ENODEV;
906 goto err_mutex;
907 }
908
909 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910 dcp_vmi_irq = platform_get_irq(pdev, 0);
911 dcp_irq = platform_get_irq(pdev, 1);
912 if (dcp_vmi_irq < 0 || dcp_irq < 0) {
913 ret = -EINVAL;
914 goto err_mutex;
915 }
916
917 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
918 if (!sdcp) {
919 ret = -ENOMEM;
920 goto err_mutex;
921 }
922
923 sdcp->dev = dev;
924 sdcp->base = devm_ioremap_resource(dev, iores);
925 if (IS_ERR(sdcp->base)) {
926 ret = PTR_ERR(sdcp->base);
927 goto err_mutex;
928 }
929
930 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
931 "dcp-vmi-irq", sdcp);
932 if (ret) {
933 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
934 goto err_mutex;
935 }
936
937 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
938 "dcp-irq", sdcp);
939 if (ret) {
940 dev_err(dev, "Failed to claim DCP IRQ!\n");
941 goto err_mutex;
942 }
943
944 /* Allocate coherent helper block. */
e921f030 945 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh), GFP_KERNEL);
15b59e7c 946 if (!sdcp->coh) {
15b59e7c
MV		 947 ret = -ENOMEM;
948 goto err_mutex;
949 }
950
951 /* Restart the DCP block. */
fecfd7f7
FE		 952 ret = stmp_reset_block(sdcp->base);
953 if (ret)
954 goto err_mutex;
15b59e7c
MV		 955
956 /* Initialize control register. */
957 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
958 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
959 sdcp->base + MXS_DCP_CTRL);
960
961 /* Enable all DCP DMA channels. */
962 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
963 sdcp->base + MXS_DCP_CHANNELCTRL);
964
965 /*
966 * We do not enable context switching. Give the context buffer a
967 * pointer to an illegal address so if context switching is
968 * inadvertantly enabled, the DCP will return an error instead of
969 * trashing good memory. The DCP DMA cannot access ROM, so any ROM
970 * address will do.
971 */
972 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
973 for (i = 0; i < DCP_MAX_CHANS; i++)
974 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
975 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
976
977 global_sdcp = sdcp;
978
979 platform_set_drvdata(pdev, sdcp);
980
981 for (i = 0; i < DCP_MAX_CHANS; i++) {
982 mutex_init(&sdcp->mutex[i]);
983 init_completion(&sdcp->completion[i]);
984 crypto_init_queue(&sdcp->queue[i], 50);
985 }
986
987 /* Create the SHA and AES handler threads. */
988 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
989 NULL, "mxs_dcp_chan/sha");
990 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
991 dev_err(dev, "Error starting SHA thread!\n");
992 ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
e921f030 993 goto err_mutex;
15b59e7c
MV		 994 }
995
996 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
997 NULL, "mxs_dcp_chan/aes");
998 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
999 dev_err(dev, "Error starting SHA thread!\n");
1000 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1001 goto err_destroy_sha_thread;
1002 }
1003
1004 /* Register the various crypto algorithms. */
1005 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1006
1007 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1008 ret = crypto_register_algs(dcp_aes_algs,
1009 ARRAY_SIZE(dcp_aes_algs));
1010 if (ret) {
1011 /* Failed to register algorithm. */
1012 dev_err(dev, "Failed to register AES crypto!\n");
1013 goto err_destroy_aes_thread;
1014 }
1015 }
1016
1017 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1018 ret = crypto_register_ahash(&dcp_sha1_alg);
1019 if (ret) {
1020 dev_err(dev, "Failed to register %s hash!\n",
1021 dcp_sha1_alg.halg.base.cra_name);
1022 goto err_unregister_aes;
1023 }
1024 }
1025
1026 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1027 ret = crypto_register_ahash(&dcp_sha256_alg);
1028 if (ret) {
1029 dev_err(dev, "Failed to register %s hash!\n",
1030 dcp_sha256_alg.halg.base.cra_name);
1031 goto err_unregister_sha1;
1032 }
1033 }
1034
1035 return 0;
1036
1037err_unregister_sha1:
1038 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1039 crypto_unregister_ahash(&dcp_sha1_alg);
1040
1041err_unregister_aes:
1042 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1043 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1044
1045err_destroy_aes_thread:
1046 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1047
1048err_destroy_sha_thread:
1049 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1050
15b59e7c
MV		 1051err_mutex:
1052 mutex_unlock(&global_mutex);
1053 return ret;
1054}
1055
1056static int mxs_dcp_remove(struct platform_device *pdev)
1057{
1058 struct dcp *sdcp = platform_get_drvdata(pdev);
1059
15b59e7c
MV		 1060 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1061 crypto_unregister_ahash(&dcp_sha256_alg);
1062
1063 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1064 crypto_unregister_ahash(&dcp_sha1_alg);
1065
1066 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1067 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1068
1069 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1070 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1071
1072 platform_set_drvdata(pdev, NULL);
1073
1074 mutex_lock(&global_mutex);
1075 global_sdcp = NULL;
1076 mutex_unlock(&global_mutex);
1077
1078 return 0;
1079}
1080
1081static const struct of_device_id mxs_dcp_dt_ids[] = {
1082 { .compatible = "fsl,imx23-dcp", .data = NULL, },
1083 { .compatible = "fsl,imx28-dcp", .data = NULL, },
1084 { /* sentinel */ }
1085};
1086
1087MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1088
1089static struct platform_driver mxs_dcp_driver = {
1090 .probe = mxs_dcp_probe,
1091 .remove = mxs_dcp_remove,
1092 .driver = {
1093 .name = "mxs-dcp",
1094 .owner = THIS_MODULE,
1095 .of_match_table = mxs_dcp_dt_ids,
1096 },
1097};
1098
1099module_platform_driver(mxs_dcp_driver);
1100
1101MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1102MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1103MODULE_LICENSE("GPL");
1104MODULE_ALIAS("platform:mxs-dcp");
Linux kernel - Deliverables
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