[deliverable/linux.git] / drivers / crypto / nx / nx-sha256.c

/**
 * SHA-256 routines supporting the Power 7+ Nest Accelerators driver
 *
 * Copyright (C) 2011-2012 International Business Machines Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 only.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Author: Kent Yoder <yoder1@us.ibm.com>
 */

#include <crypto/internal/hash.h>
#include <crypto/sha.h>
#include <linux/module.h>
#include <asm/vio.h>
#include <asm/byteorder.h>

#include "nx_csbcpb.h"
#include "nx.h"


static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
{
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
	int err;

	err = nx_crypto_ctx_sha_init(tfm);
	if (err)
		return err;

	nx_ctx_init(nx_ctx, HCOP_FC_SHA);

	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];

	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);

	return 0;
}

static int nx_sha256_init(struct shash_desc *desc) {
	struct sha256_state *sctx = shash_desc_ctx(desc);

	memset(sctx, 0, sizeof *sctx);

	sctx->state[0] = __cpu_to_be32(SHA256_H0);
	sctx->state[1] = __cpu_to_be32(SHA256_H1);
	sctx->state[2] = __cpu_to_be32(SHA256_H2);
	sctx->state[3] = __cpu_to_be32(SHA256_H3);
	sctx->state[4] = __cpu_to_be32(SHA256_H4);
	sctx->state[5] = __cpu_to_be32(SHA256_H5);
	sctx->state[6] = __cpu_to_be32(SHA256_H6);
	sctx->state[7] = __cpu_to_be32(SHA256_H7);
	sctx->count = 0;

	return 0;
}

static int nx_sha256_update(struct shash_desc *desc, const u8 *data,
			    unsigned int len)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	struct nx_sg *out_sg;
	u64 to_process = 0, leftover, total;
	unsigned long irq_flags;
	int rc = 0;
	int data_len;
	u32 max_sg_len;
	u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	/* 2 cases for total data len:
	 *  1: < SHA256_BLOCK_SIZE: copy into state, return 0
	 *  2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
	 */
	total = (sctx->count % SHA256_BLOCK_SIZE) + len;
	if (total < SHA256_BLOCK_SIZE) {
		memcpy(sctx->buf + buf_len, data, len);
		sctx->count += len;
		goto out;
	}

	memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
	NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
	NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;

	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
			nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	max_sg_len = min_t(u64, max_sg_len,
			nx_ctx->ap->databytelen/NX_PAGE_SIZE);

	data_len = SHA256_DIGEST_SIZE;
	out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
				  &data_len, max_sg_len);
	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);

	if (data_len != SHA256_DIGEST_SIZE) {
		rc = -EINVAL;
		goto out;
	}

	do {
		int used_sgs = 0;
		struct nx_sg *in_sg = nx_ctx->in_sg;

		if (buf_len) {
			data_len = buf_len;
			in_sg = nx_build_sg_list(in_sg,
						 (u8 *) sctx->buf,
						 &data_len,
						 max_sg_len);

			if (data_len != buf_len) {
				rc = -EINVAL;
				goto out;
			}
			used_sgs = in_sg - nx_ctx->in_sg;
		}

		/* to_process: SHA256_BLOCK_SIZE aligned chunk to be
		 * processed in this iteration. This value is restricted
		 * by sg list limits and number of sgs we already used
		 * for leftover data. (see above)
		 * In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
		 * but because data may not be aligned, we need to account
		 * for that too. */
		to_process = min_t(u64, total,
			(max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
		to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);

		data_len = to_process - buf_len;
		in_sg = nx_build_sg_list(in_sg, (u8 *) data,
					 &data_len, max_sg_len);

		nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);

		to_process = data_len + buf_len;
		leftover = total - to_process;

		/*
		 * we've hit the nx chip previously and we're updating
		 * again, so copy over the partial digest.
		 */
		memcpy(csbcpb->cpb.sha256.input_partial_digest,
			       csbcpb->cpb.sha256.message_digest,
			       SHA256_DIGEST_SIZE);

		if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
			rc = -EINVAL;
			goto out;
		}

		rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
				   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
		if (rc)
			goto out;

		atomic_inc(&(nx_ctx->stats->sha256_ops));

		total -= to_process;
		data += to_process - buf_len;
		buf_len = 0;

	} while (leftover >= SHA256_BLOCK_SIZE);

	/* copy the leftover back into the state struct */
	if (leftover)
		memcpy(sctx->buf, data, leftover);

	sctx->count += len;
	memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha256_final(struct shash_desc *desc, u8 *out)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	struct nx_sg *in_sg, *out_sg;
	unsigned long irq_flags;
	u32 max_sg_len;
	int rc = 0;
	int len;

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
			nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	max_sg_len = min_t(u64, max_sg_len,
			nx_ctx->ap->databytelen/NX_PAGE_SIZE);

	/* final is represented by continuing the operation and indicating that
	 * this is not an intermediate operation */
	if (sctx->count >= SHA256_BLOCK_SIZE) {
		/* we've hit the nx chip previously, now we're finalizing,
		 * so copy over the partial digest */
		memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
	} else {
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
	}

	csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);

	len = sctx->count & (SHA256_BLOCK_SIZE - 1);
	in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
				 &len, max_sg_len);

	if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
		rc = -EINVAL;
		goto out;
	}

	len = SHA256_DIGEST_SIZE;
	out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);

	if (len != SHA256_DIGEST_SIZE) {
		rc = -EINVAL;
		goto out;
	}

	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
	if (!nx_ctx->op.outlen) {
		rc = -EINVAL;
		goto out;
	}

	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
			   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	if (rc)
		goto out;

	atomic_inc(&(nx_ctx->stats->sha256_ops));

	atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
	memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha256_export(struct shash_desc *desc, void *out)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, sizeof(*sctx));

	return 0;
}

static int nx_sha256_import(struct shash_desc *desc, const void *in)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, sizeof(*sctx));

	return 0;
}

struct shash_alg nx_shash_sha256_alg = {
	.digestsize = SHA256_DIGEST_SIZE,
	.init       = nx_sha256_init,
	.update     = nx_sha256_update,
	.final      = nx_sha256_final,
	.export     = nx_sha256_export,
	.import     = nx_sha256_import,
	.descsize   = sizeof(struct sha256_state),
	.statesize  = sizeof(struct sha256_state),
	.base       = {
		.cra_name        = "sha256",
		.cra_driver_name = "sha256-nx",
		.cra_priority    = 300,
		.cra_flags       = CRYPTO_ALG_TYPE_SHASH,
		.cra_blocksize   = SHA256_BLOCK_SIZE,
		.cra_module      = THIS_MODULE,
		.cra_ctxsize     = sizeof(struct nx_crypto_ctx),
		.cra_init        = nx_crypto_ctx_sha256_init,
		.cra_exit        = nx_crypto_ctx_exit,
	}
};
Commit	Line	Data
528e3962 KY	1	/**
	2	* SHA-256 routines supporting the Power 7+ Nest Accelerators driver
	3	*
	4	* Copyright (C) 2011-2012 International Business Machines Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; version 2 only.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*
	19	* Author: Kent Yoder <yoder1@us.ibm.com>
	20	*/
	21
	22	#include <crypto/internal/hash.h>
	23	#include <crypto/sha.h>
	24	#include <linux/module.h>
	25	#include <asm/vio.h>
00085111	26	#include <asm/byteorder.h>
528e3962 KY	27
	28	#include "nx_csbcpb.h"
	29	#include "nx.h"
	30
	31
030f4e96	32	static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
528e3962	33	{
030f4e96 HX	34	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
030f4e96 HX	35	int err;
528e3962	36
030f4e96 HX	37	err = nx_crypto_ctx_sha_init(tfm);
	38	if (err)
	39	return err;
528e3962	40
030f4e96	41	nx_ctx_init(nx_ctx, HCOP_FC_SHA);
528e3962 KY	42
	43	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];
	44
	45	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);
528e3962	46
030f4e96 HX	47	return 0;
030f4e96 HX	48	}
10d87b73	49
030f4e96 HX	50	static int nx_sha256_init(struct shash_desc *desc) {
030f4e96 HX	51	struct sha256_state *sctx = shash_desc_ctx(desc);
00085111	52
030f4e96	53	memset(sctx, 0, sizeof *sctx);
00085111 LB	54
	55	sctx->state[0] = __cpu_to_be32(SHA256_H0);
	56	sctx->state[1] = __cpu_to_be32(SHA256_H1);
	57	sctx->state[2] = __cpu_to_be32(SHA256_H2);
	58	sctx->state[3] = __cpu_to_be32(SHA256_H3);
	59	sctx->state[4] = __cpu_to_be32(SHA256_H4);
	60	sctx->state[5] = __cpu_to_be32(SHA256_H5);
	61	sctx->state[6] = __cpu_to_be32(SHA256_H6);
	62	sctx->state[7] = __cpu_to_be32(SHA256_H7);
	63	sctx->count = 0;
	64
528e3962 KY	65	return 0;
	66	}
	67
	68	static int nx_sha256_update(struct shash_desc desc, const u8 data,
	69	unsigned int len)
	70	{
	71	struct sha256_state *sctx = shash_desc_ctx(desc);
	72	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	73	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
030f4e96	74	struct nx_sg *out_sg;
00085111	75	u64 to_process = 0, leftover, total;
c849163b	76	unsigned long irq_flags;
528e3962	77	int rc = 0;
00085111	78	int data_len;
10d87b73	79	u32 max_sg_len;
00085111	80	u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);
528e3962	81
c849163b MC	82	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	83
528e3962	84	/* 2 cases for total data len:
d3111493 MC	85	* 1: < SHA256_BLOCK_SIZE: copy into state, return 0
d3111493 MC	86	* 2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
528e3962	87	*/
00085111	88	total = (sctx->count % SHA256_BLOCK_SIZE) + len;
d3111493	89	if (total < SHA256_BLOCK_SIZE) {
00085111	90	memcpy(sctx->buf + buf_len, data, len);
528e3962 KY	91	sctx->count += len;
	92	goto out;
	93	}
	94
00085111 LB	95	memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
	96	NX_CPB_FDM(csbcpb) \|= NX_FDM_INTERMEDIATE;
	97	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
d3111493	98
10d87b73 LDSB	99	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
	100	nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	101	max_sg_len = min_t(u64, max_sg_len,
	102	nx_ctx->ap->databytelen/NX_PAGE_SIZE);
	103
030f4e96 HX	104	data_len = SHA256_DIGEST_SIZE;
	105	out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
	106	&data_len, max_sg_len);
	107	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
	108
	109	if (data_len != SHA256_DIGEST_SIZE) {
	110	rc = -EINVAL;
	111	goto out;
	112	}
	113
d3111493	114	do {
d3392f41 JS	115	int used_sgs = 0;
d3392f41 JS	116	struct nx_sg *in_sg = nx_ctx->in_sg;
d3111493	117
00085111 LB	118	if (buf_len) {
00085111 LB	119	data_len = buf_len;
d3392f41	120	in_sg = nx_build_sg_list(in_sg,
10d87b73 LDSB	121	(u8 *) sctx->buf,
	122	&data_len,
	123	max_sg_len);
00085111	124
10d87b73 LDSB	125	if (data_len != buf_len) {
10d87b73 LDSB	126	rc = -EINVAL;
00085111	127	goto out;
10d87b73	128	}
d3392f41	129	used_sgs = in_sg - nx_ctx->in_sg;
d3111493	130	}
00085111	131
d3392f41 JS	132	/* to_process: SHA256_BLOCK_SIZE aligned chunk to be
	133	* processed in this iteration. This value is restricted
	134	* by sg list limits and number of sgs we already used
	135	* for leftover data. (see above)
	136	* In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
	137	* but because data may not be aligned, we need to account
	138	* for that too. */
	139	to_process = min_t(u64, total,
	140	(max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
	141	to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);
	142
00085111	143	data_len = to_process - buf_len;
10d87b73 LDSB	144	in_sg = nx_build_sg_list(in_sg, (u8 *) data,
10d87b73 LDSB	145	&data_len, max_sg_len);
00085111	146
10d87b73	147	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
00085111	148
d3392f41	149	to_process = data_len + buf_len;
00085111 LB	150	leftover = total - to_process;
	151
	152	/*
	153	* we've hit the nx chip previously and we're updating
	154	* again, so copy over the partial digest.
	155	*/
	156	memcpy(csbcpb->cpb.sha256.input_partial_digest,
d3111493 MC	157	csbcpb->cpb.sha256.message_digest,
d3111493 MC	158	SHA256_DIGEST_SIZE);
d3111493	159
d3111493 MC	160	if (!nx_ctx->op.inlen \|\| !nx_ctx->op.outlen) {
	161	rc = -EINVAL;
	162	goto out;
	163	}
	164
	165	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	166	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	167	if (rc)
	168	goto out;
	169
	170	atomic_inc(&(nx_ctx->stats->sha256_ops));
d3111493 MC	171
d3111493 MC	172	total -= to_process;
00085111 LB	173	data += to_process - buf_len;
	174	buf_len = 0;
	175
d3111493	176	} while (leftover >= SHA256_BLOCK_SIZE);
528e3962 KY	177
528e3962 KY	178	/* copy the leftover back into the state struct */
1ad936e8	179	if (leftover)
d3111493	180	memcpy(sctx->buf, data, leftover);
00085111 LB	181
	182	sctx->count += len;
	183	memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
528e3962	184	out:
c849163b	185	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
528e3962 KY	186	return rc;
	187	}
	188
	189	static int nx_sha256_final(struct shash_desc desc, u8 out)
	190	{
	191	struct sha256_state *sctx = shash_desc_ctx(desc);
	192	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	193	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
10d87b73	194	struct nx_sg in_sg, out_sg;
c849163b	195	unsigned long irq_flags;
10d87b73 LDSB	196	u32 max_sg_len;
10d87b73 LDSB	197	int rc = 0;
00085111	198	int len;
528e3962	199
c849163b MC	200	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	201
10d87b73 LDSB	202	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
	203	nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	204	max_sg_len = min_t(u64, max_sg_len,
	205	nx_ctx->ap->databytelen/NX_PAGE_SIZE);
	206
00085111 LB	207	/* final is represented by continuing the operation and indicating that
	208	* this is not an intermediate operation */
	209	if (sctx->count >= SHA256_BLOCK_SIZE) {
528e3962 KY	210	/* we've hit the nx chip previously, now we're finalizing,
528e3962 KY	211	* so copy over the partial digest */
00085111 LB	212	memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
	213	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	214	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
	215	} else {
	216	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	217	NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
528e3962 KY	218	}
528e3962 KY	219
00085111	220	csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);
528e3962	221
00085111	222	len = sctx->count & (SHA256_BLOCK_SIZE - 1);
10d87b73 LDSB	223	in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
10d87b73 LDSB	224	&len, max_sg_len);
528e3962	225
10d87b73 LDSB	226	if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
10d87b73 LDSB	227	rc = -EINVAL;
00085111	228	goto out;
10d87b73	229	}
00085111 LB	230
00085111 LB	231	len = SHA256_DIGEST_SIZE;
10d87b73	232	out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);
00085111	233
10d87b73 LDSB	234	if (len != SHA256_DIGEST_SIZE) {
10d87b73 LDSB	235	rc = -EINVAL;
00085111	236	goto out;
10d87b73	237	}
528e3962	238
10d87b73 LDSB	239	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
10d87b73 LDSB	240	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
528e3962 KY	241	if (!nx_ctx->op.outlen) {
	242	rc = -EINVAL;
	243	goto out;
	244	}
	245
	246	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	247	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	248	if (rc)
	249	goto out;
	250
	251	atomic_inc(&(nx_ctx->stats->sha256_ops));
	252
00085111	253	atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
528e3962 KY	254	memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
528e3962 KY	255	out:
c849163b	256	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
528e3962 KY	257	return rc;
	258	}
	259
	260	static int nx_sha256_export(struct shash_desc desc, void out)
	261	{
	262	struct sha256_state *sctx = shash_desc_ctx(desc);
528e3962	263
00085111	264	memcpy(out, sctx, sizeof(*sctx));
528e3962 KY	265
	266	return 0;
	267	}
	268
	269	static int nx_sha256_import(struct shash_desc desc, const void in)
	270	{
	271	struct sha256_state *sctx = shash_desc_ctx(desc);
528e3962	272
00085111	273	memcpy(sctx, in, sizeof(*sctx));
528e3962	274
528e3962 KY	275	return 0;
	276	}
	277
	278	struct shash_alg nx_shash_sha256_alg = {
	279	.digestsize = SHA256_DIGEST_SIZE,
	280	.init = nx_sha256_init,
	281	.update = nx_sha256_update,
	282	.final = nx_sha256_final,
	283	.export = nx_sha256_export,
	284	.import = nx_sha256_import,
	285	.descsize = sizeof(struct sha256_state),
	286	.statesize = sizeof(struct sha256_state),
	287	.base = {
	288	.cra_name = "sha256",
	289	.cra_driver_name = "sha256-nx",
	290	.cra_priority = 300,
	291	.cra_flags = CRYPTO_ALG_TYPE_SHASH,
	292	.cra_blocksize = SHA256_BLOCK_SIZE,
	293	.cra_module = THIS_MODULE,
	294	.cra_ctxsize = sizeof(struct nx_crypto_ctx),
030f4e96	295	.cra_init = nx_crypto_ctx_sha256_init,
528e3962 KY	296	.cra_exit = nx_crypto_ctx_exit,
	297	}
	298	};