[deliverable/linux.git] / drivers / crypto / nx / nx-sha512.c

/**
 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
 *
 * Copyright (C) 2011-2012 International Business Machines Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 only.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Author: Kent Yoder <yoder1@us.ibm.com>
 */

#include <crypto/internal/hash.h>
#include <crypto/sha.h>
#include <linux/module.h>
#include <asm/vio.h>

#include "nx_csbcpb.h"
#include "nx.h"


static int nx_crypto_ctx_sha512_init(struct crypto_tfm *tfm)
{
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
	int err;

	err = nx_crypto_ctx_sha_init(tfm);
	if (err)
		return err;

	nx_ctx_init(nx_ctx, HCOP_FC_SHA);

	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];

	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);

	return 0;
}

static int nx_sha512_init(struct shash_desc *desc)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);

	memset(sctx, 0, sizeof *sctx);

	sctx->state[0] = __cpu_to_be64(SHA512_H0);
	sctx->state[1] = __cpu_to_be64(SHA512_H1);
	sctx->state[2] = __cpu_to_be64(SHA512_H2);
	sctx->state[3] = __cpu_to_be64(SHA512_H3);
	sctx->state[4] = __cpu_to_be64(SHA512_H4);
	sctx->state[5] = __cpu_to_be64(SHA512_H5);
	sctx->state[6] = __cpu_to_be64(SHA512_H6);
	sctx->state[7] = __cpu_to_be64(SHA512_H7);
	sctx->count[0] = 0;

	return 0;
}

static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
			    unsigned int len)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	struct nx_sg *in_sg;
	struct nx_sg *out_sg;
	u64 to_process, leftover = 0, total;
	unsigned long irq_flags;
	int rc = 0;
	int data_len;
	u32 max_sg_len;
	u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	/* 2 cases for total data len:
	 *  1: < SHA512_BLOCK_SIZE: copy into state, return 0
	 *  2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
	 */
	total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
	if (total < SHA512_BLOCK_SIZE) {
		memcpy(sctx->buf + buf_len, data, len);
		sctx->count[0] += len;
		goto out;
	}

	memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
	NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
	NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;

	in_sg = nx_ctx->in_sg;
	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
			nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	max_sg_len = min_t(u64, max_sg_len,
			nx_ctx->ap->databytelen/NX_PAGE_SIZE);

	data_len = SHA512_DIGEST_SIZE;
	out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
				  &data_len, max_sg_len);
	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);

	if (data_len != SHA512_DIGEST_SIZE) {
		rc = -EINVAL;
		goto out;
	}

	do {
		/*
		 * to_process: the SHA512_BLOCK_SIZE data chunk to process in
		 * this update. This value is also restricted by the sg list
		 * limits.
		 */
		to_process = total - leftover;
		to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
		leftover = total - to_process;

		if (buf_len) {
			data_len = buf_len;
			in_sg = nx_build_sg_list(nx_ctx->in_sg,
						 (u8 *) sctx->buf,
						 &data_len, max_sg_len);

			if (data_len != buf_len) {
				rc = -EINVAL;
				goto out;
			}
		}

		data_len = to_process - buf_len;
		in_sg = nx_build_sg_list(in_sg, (u8 *) data,
					 &data_len, max_sg_len);

		nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);

		if (data_len != (to_process - buf_len)) {
			rc = -EINVAL;
			goto out;
		}

		to_process = (data_len + buf_len);
		leftover = total - to_process;

		/*
		 * we've hit the nx chip previously and we're updating
		 * again, so copy over the partial digest.
		 */
		memcpy(csbcpb->cpb.sha512.input_partial_digest,
			       csbcpb->cpb.sha512.message_digest,
			       SHA512_DIGEST_SIZE);

		if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
			rc = -EINVAL;
			goto out;
		}

		rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
				   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
		if (rc)
			goto out;

		atomic_inc(&(nx_ctx->stats->sha512_ops));

		total -= to_process;
		data += to_process - buf_len;
		buf_len = 0;

	} while (leftover >= SHA512_BLOCK_SIZE);

	/* copy the leftover back into the state struct */
	if (leftover)
		memcpy(sctx->buf, data, leftover);
	sctx->count[0] += len;
	memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha512_final(struct shash_desc *desc, u8 *out)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	struct nx_sg *in_sg, *out_sg;
	u32 max_sg_len;
	u64 count0;
	unsigned long irq_flags;
	int rc = 0;
	int len;

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
			nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	max_sg_len = min_t(u64, max_sg_len,
			nx_ctx->ap->databytelen/NX_PAGE_SIZE);

	/* final is represented by continuing the operation and indicating that
	 * this is not an intermediate operation */
	if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
		/* we've hit the nx chip previously, now we're finalizing,
		 * so copy over the partial digest */
		memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
							SHA512_DIGEST_SIZE);
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
	} else {
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
	}

	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;

	count0 = sctx->count[0] * 8;

	csbcpb->cpb.sha512.message_bit_length_lo = count0;

	len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
	in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len,
				 max_sg_len);

	if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) {
		rc = -EINVAL;
		goto out;
	}

	len = SHA512_DIGEST_SIZE;
	out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
				 max_sg_len);

	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);

	if (!nx_ctx->op.outlen) {
		rc = -EINVAL;
		goto out;
	}

	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
			   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	if (rc)
		goto out;

	atomic_inc(&(nx_ctx->stats->sha512_ops));
	atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));

	memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha512_export(struct shash_desc *desc, void *out)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, sizeof(*sctx));

	return 0;
}

static int nx_sha512_import(struct shash_desc *desc, const void *in)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, sizeof(*sctx));

	return 0;
}

struct shash_alg nx_shash_sha512_alg = {
	.digestsize = SHA512_DIGEST_SIZE,
	.init       = nx_sha512_init,
	.update     = nx_sha512_update,
	.final      = nx_sha512_final,
	.export     = nx_sha512_export,
	.import     = nx_sha512_import,
	.descsize   = sizeof(struct sha512_state),
	.statesize  = sizeof(struct sha512_state),
	.base       = {
		.cra_name        = "sha512",
		.cra_driver_name = "sha512-nx",
		.cra_priority    = 300,
		.cra_flags       = CRYPTO_ALG_TYPE_SHASH,
		.cra_blocksize   = SHA512_BLOCK_SIZE,
		.cra_module      = THIS_MODULE,
		.cra_ctxsize     = sizeof(struct nx_crypto_ctx),
		.cra_init        = nx_crypto_ctx_sha512_init,
		.cra_exit        = nx_crypto_ctx_exit,
	}
};
Commit	Line	Data
fc482a86 KY	1	/**
	2	* SHA-512 routines supporting the Power 7+ Nest Accelerators driver
	3	*
	4	* Copyright (C) 2011-2012 International Business Machines Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; version 2 only.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*
	19	* Author: Kent Yoder <yoder1@us.ibm.com>
	20	*/
	21
	22	#include <crypto/internal/hash.h>
	23	#include <crypto/sha.h>
	24	#include <linux/module.h>
	25	#include <asm/vio.h>
	26
	27	#include "nx_csbcpb.h"
	28	#include "nx.h"
	29
	30
030f4e96	31	static int nx_crypto_ctx_sha512_init(struct crypto_tfm *tfm)
fc482a86	32	{
030f4e96 HX	33	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
030f4e96 HX	34	int err;
fc482a86	35
030f4e96 HX	36	err = nx_crypto_ctx_sha_init(tfm);
	37	if (err)
	38	return err;
fc482a86	39
030f4e96	40	nx_ctx_init(nx_ctx, HCOP_FC_SHA);
fc482a86 KY	41
	42	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
	43
	44	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
fc482a86	45
030f4e96 HX	46	return 0;
030f4e96 HX	47	}
10d87b73	48
030f4e96 HX	49	static int nx_sha512_init(struct shash_desc *desc)
	50	{
	51	struct sha512_state *sctx = shash_desc_ctx(desc);
00085111	52
030f4e96	53	memset(sctx, 0, sizeof *sctx);
00085111 LB	54
	55	sctx->state[0] = __cpu_to_be64(SHA512_H0);
	56	sctx->state[1] = __cpu_to_be64(SHA512_H1);
	57	sctx->state[2] = __cpu_to_be64(SHA512_H2);
	58	sctx->state[3] = __cpu_to_be64(SHA512_H3);
	59	sctx->state[4] = __cpu_to_be64(SHA512_H4);
	60	sctx->state[5] = __cpu_to_be64(SHA512_H5);
	61	sctx->state[6] = __cpu_to_be64(SHA512_H6);
	62	sctx->state[7] = __cpu_to_be64(SHA512_H7);
	63	sctx->count[0] = 0;
	64
fc482a86 KY	65	return 0;
	66	}
	67
	68	static int nx_sha512_update(struct shash_desc desc, const u8 data,
	69	unsigned int len)
	70	{
	71	struct sha512_state *sctx = shash_desc_ctx(desc);
	72	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	73	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
10d87b73	74	struct nx_sg *in_sg;
030f4e96	75	struct nx_sg *out_sg;
00085111	76	u64 to_process, leftover = 0, total;
c849163b	77	unsigned long irq_flags;
fc482a86	78	int rc = 0;
00085111	79	int data_len;
10d87b73	80	u32 max_sg_len;
00085111	81	u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);
fc482a86	82
c849163b MC	83	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	84
fc482a86	85	/* 2 cases for total data len:
d3111493 MC	86	* 1: < SHA512_BLOCK_SIZE: copy into state, return 0
d3111493 MC	87	* 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
fc482a86	88	*/
00085111	89	total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
d3111493	90	if (total < SHA512_BLOCK_SIZE) {
00085111	91	memcpy(sctx->buf + buf_len, data, len);
fc482a86 KY	92	sctx->count[0] += len;
	93	goto out;
	94	}
	95
00085111 LB	96	memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
	97	NX_CPB_FDM(csbcpb) \|= NX_FDM_INTERMEDIATE;
	98	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
d3111493	99
10d87b73 LDSB	100	in_sg = nx_ctx->in_sg;
	101	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
	102	nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	103	max_sg_len = min_t(u64, max_sg_len,
	104	nx_ctx->ap->databytelen/NX_PAGE_SIZE);
	105
030f4e96 HX	106	data_len = SHA512_DIGEST_SIZE;
	107	out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
	108	&data_len, max_sg_len);
	109	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
	110
	111	if (data_len != SHA512_DIGEST_SIZE) {
	112	rc = -EINVAL;
	113	goto out;
	114	}
	115
d3111493 MC	116	do {
	117	/*
	118	* to_process: the SHA512_BLOCK_SIZE data chunk to process in
	119	* this update. This value is also restricted by the sg list
	120	* limits.
	121	*/
00085111	122	to_process = total - leftover;
d3111493 MC	123	to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
	124	leftover = total - to_process;
	125
00085111 LB	126	if (buf_len) {
00085111 LB	127	data_len = buf_len;
10d87b73 LDSB	128	in_sg = nx_build_sg_list(nx_ctx->in_sg,
	129	(u8 *) sctx->buf,
	130	&data_len, max_sg_len);
00085111	131
10d87b73 LDSB	132	if (data_len != buf_len) {
10d87b73 LDSB	133	rc = -EINVAL;
00085111	134	goto out;
10d87b73	135	}
d3111493	136	}
00085111 LB	137
00085111 LB	138	data_len = to_process - buf_len;
10d87b73 LDSB	139	in_sg = nx_build_sg_list(in_sg, (u8 *) data,
10d87b73 LDSB	140	&data_len, max_sg_len);
00085111	141
10d87b73 LDSB	142	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
	143
	144	if (data_len != (to_process - buf_len)) {
	145	rc = -EINVAL;
00085111	146	goto out;
10d87b73	147	}
00085111 LB	148
	149	to_process = (data_len + buf_len);
	150	leftover = total - to_process;
	151
	152	/*
	153	* we've hit the nx chip previously and we're updating
	154	* again, so copy over the partial digest.
	155	*/
	156	memcpy(csbcpb->cpb.sha512.input_partial_digest,
d3111493 MC	157	csbcpb->cpb.sha512.message_digest,
d3111493 MC	158	SHA512_DIGEST_SIZE);
d3111493	159
d3111493 MC	160	if (!nx_ctx->op.inlen \|\| !nx_ctx->op.outlen) {
	161	rc = -EINVAL;
	162	goto out;
	163	}
	164
	165	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	166	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	167	if (rc)
	168	goto out;
	169
	170	atomic_inc(&(nx_ctx->stats->sha512_ops));
d3111493 MC	171
d3111493 MC	172	total -= to_process;
00085111 LB	173	data += to_process - buf_len;
	174	buf_len = 0;
	175
d3111493	176	} while (leftover >= SHA512_BLOCK_SIZE);
fc482a86 KY	177
fc482a86 KY	178	/* copy the leftover back into the state struct */
1ad936e8	179	if (leftover)
d3111493	180	memcpy(sctx->buf, data, leftover);
00085111 LB	181	sctx->count[0] += len;
00085111 LB	182	memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
fc482a86	183	out:
c849163b	184	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
fc482a86 KY	185	return rc;
	186	}
	187
	188	static int nx_sha512_final(struct shash_desc desc, u8 out)
	189	{
	190	struct sha512_state *sctx = shash_desc_ctx(desc);
	191	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	192	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
10d87b73 LDSB	193	struct nx_sg in_sg, out_sg;
10d87b73 LDSB	194	u32 max_sg_len;
fc482a86	195	u64 count0;
c849163b	196	unsigned long irq_flags;
10d87b73	197	int rc = 0;
00085111	198	int len;
fc482a86	199
c849163b MC	200	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	201
10d87b73 LDSB	202	max_sg_len = min_t(u64, nx_ctx->ap->sglen,
	203	nx_driver.of.max_sg_len/sizeof(struct nx_sg));
	204	max_sg_len = min_t(u64, max_sg_len,
	205	nx_ctx->ap->databytelen/NX_PAGE_SIZE);
	206
00085111 LB	207	/* final is represented by continuing the operation and indicating that
	208	* this is not an intermediate operation */
	209	if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
fc482a86 KY	210	/* we've hit the nx chip previously, now we're finalizing,
fc482a86 KY	211	* so copy over the partial digest */
00085111 LB	212	memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
	213	SHA512_DIGEST_SIZE);
	214	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	215	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
	216	} else {
	217	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	218	NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
fc482a86 KY	219	}
fc482a86 KY	220
fc482a86 KY	221	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	222
	223	count0 = sctx->count[0] * 8;
	224
00085111	225	csbcpb->cpb.sha512.message_bit_length_lo = count0;
fc482a86	226
00085111	227	len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
10d87b73 LDSB	228	in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len,
10d87b73 LDSB	229	max_sg_len);
00085111	230
10d87b73 LDSB	231	if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) {
10d87b73 LDSB	232	rc = -EINVAL;
00085111	233	goto out;
10d87b73	234	}
00085111 LB	235
00085111 LB	236	len = SHA512_DIGEST_SIZE;
10d87b73 LDSB	237	out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
10d87b73 LDSB	238	max_sg_len);
00085111	239
10d87b73 LDSB	240	nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
10d87b73 LDSB	241	nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
fc482a86 KY	242
	243	if (!nx_ctx->op.outlen) {
	244	rc = -EINVAL;
	245	goto out;
	246	}
	247
	248	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	249	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	250	if (rc)
	251	goto out;
	252
	253	atomic_inc(&(nx_ctx->stats->sha512_ops));
00085111	254	atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));
fc482a86 KY	255
	256	memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
	257	out:
c849163b	258	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
fc482a86 KY	259	return rc;
	260	}
	261
	262	static int nx_sha512_export(struct shash_desc desc, void out)
	263	{
	264	struct sha512_state *sctx = shash_desc_ctx(desc);
c849163b	265
00085111	266	memcpy(out, sctx, sizeof(*sctx));
fc482a86	267
fc482a86 KY	268	return 0;
	269	}
	270
	271	static int nx_sha512_import(struct shash_desc desc, const void in)
	272	{
	273	struct sha512_state *sctx = shash_desc_ctx(desc);
fc482a86	274
00085111	275	memcpy(sctx, in, sizeof(*sctx));
fc482a86 KY	276
	277	return 0;
	278	}
	279
	280	struct shash_alg nx_shash_sha512_alg = {
	281	.digestsize = SHA512_DIGEST_SIZE,
	282	.init = nx_sha512_init,
	283	.update = nx_sha512_update,
	284	.final = nx_sha512_final,
	285	.export = nx_sha512_export,
	286	.import = nx_sha512_import,
	287	.descsize = sizeof(struct sha512_state),
	288	.statesize = sizeof(struct sha512_state),
	289	.base = {
	290	.cra_name = "sha512",
	291	.cra_driver_name = "sha512-nx",
	292	.cra_priority = 300,
	293	.cra_flags = CRYPTO_ALG_TYPE_SHASH,
	294	.cra_blocksize = SHA512_BLOCK_SIZE,
	295	.cra_module = THIS_MODULE,
	296	.cra_ctxsize = sizeof(struct nx_crypto_ctx),
030f4e96	297	.cra_init = nx_crypto_ctx_sha512_init,
fc482a86 KY	298	.cra_exit = nx_crypto_ctx_exit,
	299	}
	300	};