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crypto: omap-aes - Add useful debug macros
[deliverable/linux.git] / drivers / crypto / omap-aes.c
CommitLineData
537559a5
DK		 1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
0d35583a 8 * Copyright (c) 2011 Texas Instruments Incorporated
537559a5
DK		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15
016af9b5
JF		 16#define pr_fmt(fmt) "%20s: " fmt, __func__
17#define prn(num) pr_debug(#num "=%d\n", num)
18#define prx(num) pr_debug(#num "=%x\n", num)
537559a5
DK		 19
20#include <linux/err.h>
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/kernel.h>
537559a5
DK		 25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
27#include <linux/dma-mapping.h>
ebedbf79
MG		 28#include <linux/dmaengine.h>
29#include <linux/omap-dma.h>
5946c4a5 30#include <linux/pm_runtime.h>
bc69d124
MG		 31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/of_address.h>
537559a5
DK		 34#include <linux/io.h>
35#include <linux/crypto.h>
36#include <linux/interrupt.h>
37#include <crypto/scatterwalk.h>
38#include <crypto/aes.h>
39
ebedbf79
MG		 40#define DST_MAXBURST 4
41#define DMA_MIN (DST_MAXBURST * sizeof(u32))
537559a5
DK		 42
43/* OMAP TRM gives bitfields as start:end, where start is the higher bit
44 number. For example 7:0 */
45#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
46#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
47
0d35583a
MG		 48#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
49 ((x ^ 0x01) * 0x04))
50#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
537559a5 51
0d35583a 52#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
f9fb69e7
MG		 53#define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7)
54#define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7)
55#define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7)
56#define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7)
57#define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7)
537559a5
DK		 58#define AES_REG_CTRL_CTR (1 << 6)
59#define AES_REG_CTRL_CBC (1 << 5)
60#define AES_REG_CTRL_KEY_SIZE (3 << 3)
61#define AES_REG_CTRL_DIRECTION (1 << 2)
62#define AES_REG_CTRL_INPUT_READY (1 << 1)
63#define AES_REG_CTRL_OUTPUT_READY (1 << 0)
64
0d35583a 65#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
537559a5 66
0d35583a 67#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
537559a5 68
0d35583a 69#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
537559a5
DK		 70#define AES_REG_MASK_SIDLE (1 << 6)
71#define AES_REG_MASK_START (1 << 5)
72#define AES_REG_MASK_DMA_OUT_EN (1 << 3)
73#define AES_REG_MASK_DMA_IN_EN (1 << 2)
74#define AES_REG_MASK_SOFTRESET (1 << 1)
75#define AES_REG_AUTOIDLE (1 << 0)
76
0d35583a 77#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
537559a5
DK		 78
79#define DEFAULT_TIMEOUT (5*HZ)
80
81#define FLAGS_MODE_MASK 0x000f
82#define FLAGS_ENCRYPT BIT(0)
83#define FLAGS_CBC BIT(1)
84#define FLAGS_GIV BIT(2)
f9fb69e7 85#define FLAGS_CTR BIT(3)
537559a5 86
67a730ce
DK		 87#define FLAGS_INIT BIT(4)
88#define FLAGS_FAST BIT(5)
89#define FLAGS_BUSY BIT(6)
537559a5
DK		 90
91struct omap_aes_ctx {
92 struct omap_aes_dev *dd;
93
94 int keylen;
95 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
96 unsigned long flags;
97};
98
99struct omap_aes_reqctx {
100 unsigned long mode;
101};
102
103#define OMAP_AES_QUEUE_LENGTH 1
104#define OMAP_AES_CACHE_SIZE 0
105
f9fb69e7
MG		 106struct omap_aes_algs_info {
107 struct crypto_alg *algs_list;
108 unsigned int size;
109 unsigned int registered;
110};
111
0d35583a 112struct omap_aes_pdata {
f9fb69e7
MG		 113 struct omap_aes_algs_info *algs_info;
114 unsigned int algs_info_size;
115
0d35583a
MG		 116 void (*trigger)(struct omap_aes_dev *dd, int length);
117
118 u32 key_ofs;
119 u32 iv_ofs;
120 u32 ctrl_ofs;
121 u32 data_ofs;
122 u32 rev_ofs;
123 u32 mask_ofs;
124
125 u32 dma_enable_in;
126 u32 dma_enable_out;
127 u32 dma_start;
128
129 u32 major_mask;
130 u32 major_shift;
131 u32 minor_mask;
132 u32 minor_shift;
133};
134
537559a5
DK		 135struct omap_aes_dev {
136 struct list_head list;
137 unsigned long phys_base;
efce41b6 138 void __iomem *io_base;
537559a5
DK		 139 struct omap_aes_ctx *ctx;
140 struct device *dev;
141 unsigned long flags;
21fe9767 142 int err;
537559a5 143
21fe9767
DK		 144 spinlock_t lock;
145 struct crypto_queue queue;
537559a5 146
21fe9767
DK		 147 struct tasklet_struct done_task;
148 struct tasklet_struct queue_task;
537559a5
DK		 149
150 struct ablkcipher_request *req;
151 size_t total;
152 struct scatterlist *in_sg;
ebedbf79 153 struct scatterlist in_sgl;
537559a5
DK		 154 size_t in_offset;
155 struct scatterlist *out_sg;
ebedbf79 156 struct scatterlist out_sgl;
537559a5
DK		 157 size_t out_offset;
158
159 size_t buflen;
160 void *buf_in;
161 size_t dma_size;
162 int dma_in;
ebedbf79 163 struct dma_chan *dma_lch_in;
537559a5
DK		 164 dma_addr_t dma_addr_in;
165 void *buf_out;
166 int dma_out;
ebedbf79 167 struct dma_chan *dma_lch_out;
537559a5 168 dma_addr_t dma_addr_out;
0d35583a
MG		 169
170 const struct omap_aes_pdata *pdata;
537559a5
DK		 171};
172
173/* keep registered devices data here */
174static LIST_HEAD(dev_list);
175static DEFINE_SPINLOCK(list_lock);
176
016af9b5
JF		 177#ifdef DEBUG
178#define omap_aes_read(dd, offset) \
179({ \
180 int _read_ret; \
181 _read_ret = __raw_readl(dd->io_base + offset); \
182 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
183 offset, _read_ret); \
184 _read_ret; \
185})
186#else
537559a5
DK		 187static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
188{
189 return __raw_readl(dd->io_base + offset);
190}
016af9b5
JF		 191#endif
192
193#ifdef DEBUG
194#define omap_aes_write(dd, offset, value) \
195 do { \
196 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
197 offset, value); \
198 __raw_writel(value, dd->io_base + offset); \
199 } while (0)
200#else
537559a5
DK		 201static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
202 u32 value)
203{
204 __raw_writel(value, dd->io_base + offset);
205}
016af9b5 206#endif
537559a5
DK		 207
208static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
209 u32 value, u32 mask)
210{
211 u32 val;
212
213 val = omap_aes_read(dd, offset);
214 val &= ~mask;
215 val |= value;
216 omap_aes_write(dd, offset, val);
217}
218
219static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
220 u32 *value, int count)
221{
222 for (; count--; value++, offset += 4)
223 omap_aes_write(dd, offset, *value);
224}
225
537559a5
DK		 226static int omap_aes_hw_init(struct omap_aes_dev *dd)
227{
537559a5 228 if (!(dd->flags & FLAGS_INIT)) {
eeb2b202 229 dd->flags |= FLAGS_INIT;
21fe9767 230 dd->err = 0;
537559a5
DK		 231 }
232
eeb2b202 233 return 0;
537559a5
DK		 234}
235
21fe9767 236static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
537559a5
DK		 237{
238 unsigned int key32;
67a730ce 239 int i, err;
f9fb69e7 240 u32 val, mask = 0;
537559a5 241
21fe9767
DK		 242 err = omap_aes_hw_init(dd);
243 if (err)
244 return err;
245
537559a5 246 key32 = dd->ctx->keylen / sizeof(u32);
67a730ce
DK		 247
248 /* it seems a key should always be set even if it has not changed */
537559a5 249 for (i = 0; i < key32; i++) {
0d35583a 250 omap_aes_write(dd, AES_REG_KEY(dd, i),
537559a5
DK		 251 __le32_to_cpu(dd->ctx->key[i]));
252 }
537559a5 253
f9fb69e7 254 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
0d35583a 255 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
67a730ce
DK		 256
257 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
258 if (dd->flags & FLAGS_CBC)
259 val |= AES_REG_CTRL_CBC;
f9fb69e7
MG		 260 if (dd->flags & FLAGS_CTR) {
261 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
262 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
263 }
67a730ce
DK		 264 if (dd->flags & FLAGS_ENCRYPT)
265 val |= AES_REG_CTRL_DIRECTION;
537559a5 266
f9fb69e7 267 mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
537559a5
DK		 268 AES_REG_CTRL_KEY_SIZE;
269
0d35583a 270 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
537559a5 271
21fe9767 272 return 0;
537559a5
DK		 273}
274
0d35583a
MG		 275static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
276{
277 u32 mask, val;
278
279 val = dd->pdata->dma_start;
280
281 if (dd->dma_lch_out != NULL)
282 val |= dd->pdata->dma_enable_out;
283 if (dd->dma_lch_in != NULL)
284 val |= dd->pdata->dma_enable_in;
285
286 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
287 dd->pdata->dma_start;
288
289 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
290
291}
292
293static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
294{
295 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
296 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
297
298 omap_aes_dma_trigger_omap2(dd, length);
299}
300
301static void omap_aes_dma_stop(struct omap_aes_dev *dd)
302{
303 u32 mask;
304
305 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
306 dd->pdata->dma_start;
307
308 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
309}
310
537559a5
DK		 311static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
312{
313 struct omap_aes_dev *dd = NULL, *tmp;
314
315 spin_lock_bh(&list_lock);
316 if (!ctx->dd) {
317 list_for_each_entry(tmp, &dev_list, list) {
318 /* FIXME: take fist available aes core */
319 dd = tmp;
320 break;
321 }
322 ctx->dd = dd;
323 } else {
324 /* already found before */
325 dd = ctx->dd;
326 }
327 spin_unlock_bh(&list_lock);
328
329 return dd;
330}
331
ebedbf79
MG		 332static void omap_aes_dma_out_callback(void *data)
333{
334 struct omap_aes_dev *dd = data;
335
336 /* dma_lch_out - completed */
337 tasklet_schedule(&dd->done_task);
338}
537559a5
DK		 339
340static int omap_aes_dma_init(struct omap_aes_dev *dd)
341{
342 int err = -ENOMEM;
ebedbf79 343 dma_cap_mask_t mask;
537559a5 344
ebedbf79
MG		 345 dd->dma_lch_out = NULL;
346 dd->dma_lch_in = NULL;
537559a5
DK		 347
348 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
349 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
350 dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE;
351 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
352
353 if (!dd->buf_in || !dd->buf_out) {
354 dev_err(dd->dev, "unable to alloc pages.\n");
355 goto err_alloc;
356 }
357
358 /* MAP here */
359 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen,
360 DMA_TO_DEVICE);
361 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
362 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
363 err = -EINVAL;
364 goto err_map_in;
365 }
366
367 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen,
368 DMA_FROM_DEVICE);
369 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
370 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
371 err = -EINVAL;
372 goto err_map_out;
373 }
374
ebedbf79
MG		 375 dma_cap_zero(mask);
376 dma_cap_set(DMA_SLAVE, mask);
377
b4b87a93
MG		 378 dd->dma_lch_in = dma_request_slave_channel_compat(mask,
379 omap_dma_filter_fn,
380 &dd->dma_in,
381 dd->dev, "rx");
ebedbf79
MG		 382 if (!dd->dma_lch_in) {
383 dev_err(dd->dev, "Unable to request in DMA channel\n");
384 goto err_dma_in;
385 }
386
b4b87a93
MG		 387 dd->dma_lch_out = dma_request_slave_channel_compat(mask,
388 omap_dma_filter_fn,
389 &dd->dma_out,
390 dd->dev, "tx");
ebedbf79
MG		 391 if (!dd->dma_lch_out) {
392 dev_err(dd->dev, "Unable to request out DMA channel\n");
393 goto err_dma_out;
394 }
537559a5 395
537559a5
DK		 396 return 0;
397
398err_dma_out:
ebedbf79 399 dma_release_channel(dd->dma_lch_in);
537559a5
DK		 400err_dma_in:
401 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
402 DMA_FROM_DEVICE);
403err_map_out:
404 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
405err_map_in:
406 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
407 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
408err_alloc:
409 if (err)
410 pr_err("error: %d\n", err);
411 return err;
412}
413
414static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
415{
ebedbf79
MG		 416 dma_release_channel(dd->dma_lch_out);
417 dma_release_channel(dd->dma_lch_in);
537559a5
DK		 418 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
419 DMA_FROM_DEVICE);
420 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
421 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
422 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
423}
424
425static void sg_copy_buf(void *buf, struct scatterlist *sg,
426 unsigned int start, unsigned int nbytes, int out)
427{
428 struct scatter_walk walk;
429
430 if (!nbytes)
431 return;
432
433 scatterwalk_start(&walk, sg);
434 scatterwalk_advance(&walk, start);
435 scatterwalk_copychunks(buf, &walk, nbytes, out);
436 scatterwalk_done(&walk, out, 0);
437}
438
439static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
440 size_t buflen, size_t total, int out)
441{
442 unsigned int count, off = 0;
443
444 while (buflen && total) {
445 count = min((*sg)->length - *offset, total);
446 count = min(count, buflen);
447
448 if (!count)
449 return off;
450
21fe9767
DK		 451 /*
452 * buflen and total are AES_BLOCK_SIZE size aligned,
453 * so count should be also aligned
454 */
455
537559a5
DK		 456 sg_copy_buf(buf + off, *sg, *offset, count, out);
457
458 off += count;
459 buflen -= count;
460 *offset += count;
461 total -= count;
462
463 if (*offset == (*sg)->length) {
464 *sg = sg_next(*sg);
465 if (*sg)
466 *offset = 0;
467 else
468 total = 0;
469 }
470 }
471
472 return off;
473}
474
ebedbf79
MG		 475static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
476 struct scatterlist *in_sg, struct scatterlist *out_sg)
537559a5
DK		 477{
478 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
479 struct omap_aes_dev *dd = ctx->dd;
ebedbf79
MG		 480 struct dma_async_tx_descriptor *tx_in, *tx_out;
481 struct dma_slave_config cfg;
482 dma_addr_t dma_addr_in = sg_dma_address(in_sg);
483 int ret, length = sg_dma_len(in_sg);
537559a5
DK		 484
485 pr_debug("len: %d\n", length);
486
487 dd->dma_size = length;
488
489 if (!(dd->flags & FLAGS_FAST))
490 dma_sync_single_for_device(dd->dev, dma_addr_in, length,
491 DMA_TO_DEVICE);
492
ebedbf79
MG		 493 memset(&cfg, 0, sizeof(cfg));
494
0d35583a
MG		 495 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
496 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
ebedbf79
MG		 497 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
498 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
499 cfg.src_maxburst = DST_MAXBURST;
500 cfg.dst_maxburst = DST_MAXBURST;
501
502 /* IN */
503 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
504 if (ret) {
505 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
506 ret);
507 return ret;
508 }
509
510 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, 1,
511 DMA_MEM_TO_DEV,
512 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
513 if (!tx_in) {
514 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
515 return -EINVAL;
516 }
517
518 /* No callback necessary */
519 tx_in->callback_param = dd;
520
521 /* OUT */
522 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
523 if (ret) {
524 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
525 ret);
526 return ret;
527 }
528
529 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 1,
530 DMA_DEV_TO_MEM,
531 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
532 if (!tx_out) {
533 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
534 return -EINVAL;
535 }
536
537 tx_out->callback = omap_aes_dma_out_callback;
538 tx_out->callback_param = dd;
539
540 dmaengine_submit(tx_in);
541 dmaengine_submit(tx_out);
542
543 dma_async_issue_pending(dd->dma_lch_in);
544 dma_async_issue_pending(dd->dma_lch_out);
537559a5 545
0d35583a
MG		 546 /* start DMA */
547 dd->pdata->trigger(dd, length);
83ea7e0f 548
537559a5
DK		 549 return 0;
550}
551
552static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
553{
554 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
555 crypto_ablkcipher_reqtfm(dd->req));
556 int err, fast = 0, in, out;
557 size_t count;
558 dma_addr_t addr_in, addr_out;
ebedbf79
MG		 559 struct scatterlist *in_sg, *out_sg;
560 int len32;
537559a5
DK		 561
562 pr_debug("total: %d\n", dd->total);
563
564 if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
565 /* check for alignment */
566 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
567 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
568
569 fast = in && out;
570 }
571
572 if (fast) {
573 count = min(dd->total, sg_dma_len(dd->in_sg));
574 count = min(count, sg_dma_len(dd->out_sg));
575
21fe9767
DK		 576 if (count != dd->total) {
577 pr_err("request length != buffer length\n");
537559a5 578 return -EINVAL;
21fe9767 579 }
537559a5
DK		 580
581 pr_debug("fast\n");
582
583 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
584 if (!err) {
585 dev_err(dd->dev, "dma_map_sg() error\n");
586 return -EINVAL;
587 }
588
589 err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
590 if (!err) {
591 dev_err(dd->dev, "dma_map_sg() error\n");
592 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
593 return -EINVAL;
594 }
595
596 addr_in = sg_dma_address(dd->in_sg);
597 addr_out = sg_dma_address(dd->out_sg);
598
ebedbf79
MG		 599 in_sg = dd->in_sg;
600 out_sg = dd->out_sg;
ebedbf79 601
537559a5
DK		 602 dd->flags |= FLAGS_FAST;
603
604 } else {
605 /* use cache buffers */
606 count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
607 dd->buflen, dd->total, 0);
608
ebedbf79
MG		 609 len32 = DIV_ROUND_UP(count, DMA_MIN) * DMA_MIN;
610
611 /*
612 * The data going into the AES module has been copied
613 * to a local buffer and the data coming out will go
614 * into a local buffer so set up local SG entries for
615 * both.
616 */
617 sg_init_table(&dd->in_sgl, 1);
618 dd->in_sgl.offset = dd->in_offset;
619 sg_dma_len(&dd->in_sgl) = len32;
620 sg_dma_address(&dd->in_sgl) = dd->dma_addr_in;
621
622 sg_init_table(&dd->out_sgl, 1);
623 dd->out_sgl.offset = dd->out_offset;
624 sg_dma_len(&dd->out_sgl) = len32;
625 sg_dma_address(&dd->out_sgl) = dd->dma_addr_out;
626
627 in_sg = &dd->in_sgl;
628 out_sg = &dd->out_sgl;
ebedbf79 629
537559a5
DK		 630 addr_in = dd->dma_addr_in;
631 addr_out = dd->dma_addr_out;
632
633 dd->flags &= ~FLAGS_FAST;
634
635 }
636
637 dd->total -= count;
638
ebedbf79 639 err = omap_aes_crypt_dma(tfm, in_sg, out_sg);
21fe9767
DK		 640 if (err) {
641 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
642 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
643 }
537559a5
DK		 644
645 return err;
646}
647
648static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
649{
21fe9767 650 struct ablkcipher_request *req = dd->req;
537559a5
DK		 651
652 pr_debug("err: %d\n", err);
653
eeb2b202
DK		 654 dd->flags &= ~FLAGS_BUSY;
655
67a730ce 656 req->base.complete(&req->base, err);
537559a5
DK		 657}
658
659static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
660{
661 int err = 0;
662 size_t count;
663
664 pr_debug("total: %d\n", dd->total);
665
0d35583a 666 omap_aes_dma_stop(dd);
537559a5 667
ebedbf79
MG		 668 dmaengine_terminate_all(dd->dma_lch_in);
669 dmaengine_terminate_all(dd->dma_lch_out);
537559a5
DK		 670
671 if (dd->flags & FLAGS_FAST) {
672 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
673 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
674 } else {
675 dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
676 dd->dma_size, DMA_FROM_DEVICE);
677
678 /* copy data */
679 count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out,
680 dd->buflen, dd->dma_size, 1);
681 if (count != dd->dma_size) {
682 err = -EINVAL;
683 pr_err("not all data converted: %u\n", count);
684 }
685 }
686
537559a5
DK		 687 return err;
688}
689
21fe9767 690static int omap_aes_handle_queue(struct omap_aes_dev *dd,
eeb2b202 691 struct ablkcipher_request *req)
537559a5
DK		 692{
693 struct crypto_async_request *async_req, *backlog;
694 struct omap_aes_ctx *ctx;
695 struct omap_aes_reqctx *rctx;
537559a5 696 unsigned long flags;
21fe9767 697 int err, ret = 0;
537559a5
DK		 698
699 spin_lock_irqsave(&dd->lock, flags);
eeb2b202 700 if (req)
21fe9767 701 ret = ablkcipher_enqueue_request(&dd->queue, req);
eeb2b202
DK		 702 if (dd->flags & FLAGS_BUSY) {
703 spin_unlock_irqrestore(&dd->lock, flags);
21fe9767 704 return ret;
eeb2b202 705 }
537559a5
DK		 706 backlog = crypto_get_backlog(&dd->queue);
707 async_req = crypto_dequeue_request(&dd->queue);
eeb2b202
DK		 708 if (async_req)
709 dd->flags |= FLAGS_BUSY;
537559a5
DK		 710 spin_unlock_irqrestore(&dd->lock, flags);
711
712 if (!async_req)
21fe9767 713 return ret;
537559a5
DK		 714
715 if (backlog)
716 backlog->complete(backlog, -EINPROGRESS);
717
718 req = ablkcipher_request_cast(async_req);
719
537559a5
DK		 720 /* assign new request to device */
721 dd->req = req;
722 dd->total = req->nbytes;
723 dd->in_offset = 0;
724 dd->in_sg = req->src;
725 dd->out_offset = 0;
726 dd->out_sg = req->dst;
727
728 rctx = ablkcipher_request_ctx(req);
729 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
730 rctx->mode &= FLAGS_MODE_MASK;
731 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
732
67a730ce 733 dd->ctx = ctx;
537559a5 734 ctx->dd = dd;
537559a5 735
83ea7e0f
DK		 736 err = omap_aes_write_ctrl(dd);
737 if (!err)
738 err = omap_aes_crypt_dma_start(dd);
21fe9767
DK		 739 if (err) {
740 /* aes_task will not finish it, so do it here */
741 omap_aes_finish_req(dd, err);
742 tasklet_schedule(&dd->queue_task);
743 }
eeb2b202 744
21fe9767 745 return ret; /* return ret, which is enqueue return value */
537559a5
DK		 746}
747
21fe9767 748static void omap_aes_done_task(unsigned long data)
537559a5
DK		 749{
750 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
21fe9767 751 int err;
537559a5
DK		 752
753 pr_debug("enter\n");
754
21fe9767 755 err = omap_aes_crypt_dma_stop(dd);
537559a5 756
21fe9767
DK		 757 err = dd->err ? : err;
758
759 if (dd->total && !err) {
760 err = omap_aes_crypt_dma_start(dd);
761 if (!err)
762 return; /* DMA started. Not fininishing. */
763 }
764
765 omap_aes_finish_req(dd, err);
766 omap_aes_handle_queue(dd, NULL);
537559a5
DK		 767
768 pr_debug("exit\n");
769}
770
21fe9767
DK		 771static void omap_aes_queue_task(unsigned long data)
772{
773 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
774
775 omap_aes_handle_queue(dd, NULL);
776}
777
537559a5
DK		 778static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
779{
780 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
781 crypto_ablkcipher_reqtfm(req));
782 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
783 struct omap_aes_dev *dd;
537559a5
DK		 784
785 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
786 !!(mode & FLAGS_ENCRYPT),
787 !!(mode & FLAGS_CBC));
788
21fe9767
DK		 789 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
790 pr_err("request size is not exact amount of AES blocks\n");
791 return -EINVAL;
792 }
793
537559a5
DK		 794 dd = omap_aes_find_dev(ctx);
795 if (!dd)
796 return -ENODEV;
797
798 rctx->mode = mode;
799
21fe9767 800 return omap_aes_handle_queue(dd, req);
537559a5
DK		 801}
802
803/* ********************** ALG API ************************************ */
804
805static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
806 unsigned int keylen)
807{
808 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
809
810 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
811 keylen != AES_KEYSIZE_256)
812 return -EINVAL;
813
814 pr_debug("enter, keylen: %d\n", keylen);
815
816 memcpy(ctx->key, key, keylen);
817 ctx->keylen = keylen;
537559a5
DK		 818
819 return 0;
820}
821
822static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
823{
824 return omap_aes_crypt(req, FLAGS_ENCRYPT);
825}
826
827static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
828{
829 return omap_aes_crypt(req, 0);
830}
831
832static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
833{
834 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
835}
836
837static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
838{
839 return omap_aes_crypt(req, FLAGS_CBC);
840}
841
f9fb69e7
MG		 842static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
843{
844 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
845}
846
847static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
848{
849 return omap_aes_crypt(req, FLAGS_CTR);
850}
851
537559a5
DK		 852static int omap_aes_cra_init(struct crypto_tfm *tfm)
853{
a3485e68
JF		 854 struct omap_aes_dev *dd = NULL;
855
856 /* Find AES device, currently picks the first device */
857 spin_lock_bh(&list_lock);
858 list_for_each_entry(dd, &dev_list, list) {
859 break;
860 }
861 spin_unlock_bh(&list_lock);
537559a5 862
a3485e68 863 pm_runtime_get_sync(dd->dev);
537559a5
DK		 864 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
865
866 return 0;
867}
868
869static void omap_aes_cra_exit(struct crypto_tfm *tfm)
870{
a3485e68
JF		 871 struct omap_aes_dev *dd = NULL;
872
873 /* Find AES device, currently picks the first device */
874 spin_lock_bh(&list_lock);
875 list_for_each_entry(dd, &dev_list, list) {
876 break;
877 }
878 spin_unlock_bh(&list_lock);
879
880 pm_runtime_put_sync(dd->dev);
537559a5
DK		 881}
882
883/* ********************** ALGS ************************************ */
884
f9fb69e7 885static struct crypto_alg algs_ecb_cbc[] = {
537559a5
DK		 886{
887 .cra_name = "ecb(aes)",
888 .cra_driver_name = "ecb-aes-omap",
889 .cra_priority = 100,
d912bb76
NM		 890 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
891 CRYPTO_ALG_KERN_DRIVER_ONLY |
892 CRYPTO_ALG_ASYNC,
537559a5
DK		 893 .cra_blocksize = AES_BLOCK_SIZE,
894 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 895 .cra_alignmask = 0,
537559a5
DK		 896 .cra_type = &crypto_ablkcipher_type,
897 .cra_module = THIS_MODULE,
898 .cra_init = omap_aes_cra_init,
899 .cra_exit = omap_aes_cra_exit,
900 .cra_u.ablkcipher = {
901 .min_keysize = AES_MIN_KEY_SIZE,
902 .max_keysize = AES_MAX_KEY_SIZE,
903 .setkey = omap_aes_setkey,
904 .encrypt = omap_aes_ecb_encrypt,
905 .decrypt = omap_aes_ecb_decrypt,
906 }
907},
908{
909 .cra_name = "cbc(aes)",
910 .cra_driver_name = "cbc-aes-omap",
911 .cra_priority = 100,
d912bb76
NM		 912 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
913 CRYPTO_ALG_KERN_DRIVER_ONLY |
914 CRYPTO_ALG_ASYNC,
537559a5
DK		 915 .cra_blocksize = AES_BLOCK_SIZE,
916 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 917 .cra_alignmask = 0,
537559a5
DK		 918 .cra_type = &crypto_ablkcipher_type,
919 .cra_module = THIS_MODULE,
920 .cra_init = omap_aes_cra_init,
921 .cra_exit = omap_aes_cra_exit,
922 .cra_u.ablkcipher = {
923 .min_keysize = AES_MIN_KEY_SIZE,
924 .max_keysize = AES_MAX_KEY_SIZE,
925 .ivsize = AES_BLOCK_SIZE,
926 .setkey = omap_aes_setkey,
927 .encrypt = omap_aes_cbc_encrypt,
928 .decrypt = omap_aes_cbc_decrypt,
929 }
930}
931};
932
f9fb69e7
MG		 933static struct crypto_alg algs_ctr[] = {
934{
935 .cra_name = "ctr(aes)",
936 .cra_driver_name = "ctr-aes-omap",
937 .cra_priority = 100,
938 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
939 CRYPTO_ALG_KERN_DRIVER_ONLY |
940 CRYPTO_ALG_ASYNC,
941 .cra_blocksize = AES_BLOCK_SIZE,
942 .cra_ctxsize = sizeof(struct omap_aes_ctx),
943 .cra_alignmask = 0,
944 .cra_type = &crypto_ablkcipher_type,
945 .cra_module = THIS_MODULE,
946 .cra_init = omap_aes_cra_init,
947 .cra_exit = omap_aes_cra_exit,
948 .cra_u.ablkcipher = {
949 .min_keysize = AES_MIN_KEY_SIZE,
950 .max_keysize = AES_MAX_KEY_SIZE,
951 .geniv = "eseqiv",
952 .ivsize = AES_BLOCK_SIZE,
953 .setkey = omap_aes_setkey,
954 .encrypt = omap_aes_ctr_encrypt,
955 .decrypt = omap_aes_ctr_decrypt,
956 }
957} ,
958};
959
960static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
961 {
962 .algs_list = algs_ecb_cbc,
963 .size = ARRAY_SIZE(algs_ecb_cbc),
964 },
965};
966
0d35583a 967static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
f9fb69e7
MG		 968 .algs_info = omap_aes_algs_info_ecb_cbc,
969 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
0d35583a
MG		 970 .trigger = omap_aes_dma_trigger_omap2,
971 .key_ofs = 0x1c,
972 .iv_ofs = 0x20,
973 .ctrl_ofs = 0x30,
974 .data_ofs = 0x34,
975 .rev_ofs = 0x44,
976 .mask_ofs = 0x48,
977 .dma_enable_in = BIT(2),
978 .dma_enable_out = BIT(3),
979 .dma_start = BIT(5),
980 .major_mask = 0xf0,
981 .major_shift = 4,
982 .minor_mask = 0x0f,
983 .minor_shift = 0,
984};
985
bc69d124 986#ifdef CONFIG_OF
f9fb69e7
MG		 987static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
988 {
989 .algs_list = algs_ecb_cbc,
990 .size = ARRAY_SIZE(algs_ecb_cbc),
991 },
992 {
993 .algs_list = algs_ctr,
994 .size = ARRAY_SIZE(algs_ctr),
995 },
996};
997
998static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
999 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
1000 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
1001 .trigger = omap_aes_dma_trigger_omap2,
1002 .key_ofs = 0x1c,
1003 .iv_ofs = 0x20,
1004 .ctrl_ofs = 0x30,
1005 .data_ofs = 0x34,
1006 .rev_ofs = 0x44,
1007 .mask_ofs = 0x48,
1008 .dma_enable_in = BIT(2),
1009 .dma_enable_out = BIT(3),
1010 .dma_start = BIT(5),
1011 .major_mask = 0xf0,
1012 .major_shift = 4,
1013 .minor_mask = 0x0f,
1014 .minor_shift = 0,
1015};
1016
0d35583a 1017static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
f9fb69e7
MG		 1018 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
1019 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
0d35583a
MG		 1020 .trigger = omap_aes_dma_trigger_omap4,
1021 .key_ofs = 0x3c,
1022 .iv_ofs = 0x40,
1023 .ctrl_ofs = 0x50,
1024 .data_ofs = 0x60,
1025 .rev_ofs = 0x80,
1026 .mask_ofs = 0x84,
1027 .dma_enable_in = BIT(5),
1028 .dma_enable_out = BIT(6),
1029 .major_mask = 0x0700,
1030 .major_shift = 8,
1031 .minor_mask = 0x003f,
1032 .minor_shift = 0,
1033};
1034
bc69d124
MG		 1035static const struct of_device_id omap_aes_of_match[] = {
1036 {
1037 .compatible = "ti,omap2-aes",
0d35583a
MG		 1038 .data = &omap_aes_pdata_omap2,
1039 },
f9fb69e7
MG		 1040 {
1041 .compatible = "ti,omap3-aes",
1042 .data = &omap_aes_pdata_omap3,
1043 },
0d35583a
MG		 1044 {
1045 .compatible = "ti,omap4-aes",
1046 .data = &omap_aes_pdata_omap4,
bc69d124
MG		 1047 },
1048 {},
1049};
1050MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1051
1052static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1053 struct device *dev, struct resource *res)
1054{
1055 struct device_node *node = dev->of_node;
1056 const struct of_device_id *match;
1057 int err = 0;
1058
1059 match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1060 if (!match) {
1061 dev_err(dev, "no compatible OF match\n");
1062 err = -EINVAL;
1063 goto err;
1064 }
1065
1066 err = of_address_to_resource(node, 0, res);
1067 if (err < 0) {
1068 dev_err(dev, "can't translate OF node address\n");
1069 err = -EINVAL;
1070 goto err;
1071 }
1072
1073 dd->dma_out = -1; /* Dummy value that's unused */
1074 dd->dma_in = -1; /* Dummy value that's unused */
1075
0d35583a
MG		 1076 dd->pdata = match->data;
1077
bc69d124
MG		 1078err:
1079 return err;
1080}
1081#else
1082static const struct of_device_id omap_aes_of_match[] = {
1083 {},
1084};
1085
1086static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1087 struct device *dev, struct resource *res)
1088{
1089 return -EINVAL;
1090}
1091#endif
1092
1093static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1094 struct platform_device *pdev, struct resource *res)
1095{
1096 struct device *dev = &pdev->dev;
1097 struct resource *r;
1098 int err = 0;
1099
1100 /* Get the base address */
1101 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102 if (!r) {
1103 dev_err(dev, "no MEM resource info\n");
1104 err = -ENODEV;
1105 goto err;
1106 }
1107 memcpy(res, r, sizeof(*res));
1108
1109 /* Get the DMA out channel */
1110 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1111 if (!r) {
1112 dev_err(dev, "no DMA out resource info\n");
1113 err = -ENODEV;
1114 goto err;
1115 }
1116 dd->dma_out = r->start;
1117
1118 /* Get the DMA in channel */
1119 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1120 if (!r) {
1121 dev_err(dev, "no DMA in resource info\n");
1122 err = -ENODEV;
1123 goto err;
1124 }
1125 dd->dma_in = r->start;
1126
0d35583a
MG		 1127 /* Only OMAP2/3 can be non-DT */
1128 dd->pdata = &omap_aes_pdata_omap2;
1129
bc69d124
MG		 1130err:
1131 return err;
1132}
1133
537559a5
DK		 1134static int omap_aes_probe(struct platform_device *pdev)
1135{
1136 struct device *dev = &pdev->dev;
1137 struct omap_aes_dev *dd;
f9fb69e7 1138 struct crypto_alg *algp;
bc69d124 1139 struct resource res;
537559a5
DK		 1140 int err = -ENOMEM, i, j;
1141 u32 reg;
1142
1143 dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
1144 if (dd == NULL) {
1145 dev_err(dev, "unable to alloc data struct.\n");
1146 goto err_data;
1147 }
1148 dd->dev = dev;
1149 platform_set_drvdata(pdev, dd);
1150
1151 spin_lock_init(&dd->lock);
1152 crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1153
bc69d124
MG		 1154 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1155 omap_aes_get_res_pdev(dd, pdev, &res);
1156 if (err)
537559a5 1157 goto err_res;
bc69d124 1158
30862281
LN		 1159 dd->io_base = devm_ioremap_resource(dev, &res);
1160 if (IS_ERR(dd->io_base)) {
1161 err = PTR_ERR(dd->io_base);
5946c4a5 1162 goto err_res;
537559a5 1163 }
bc69d124 1164 dd->phys_base = res.start;
537559a5 1165
5946c4a5
MG		 1166 pm_runtime_enable(dev);
1167 pm_runtime_get_sync(dev);
1168
0d35583a
MG		 1169 omap_aes_dma_stop(dd);
1170
1171 reg = omap_aes_read(dd, AES_REG_REV(dd));
5946c4a5
MG		 1172
1173 pm_runtime_put_sync(dev);
537559a5 1174
0d35583a
MG		 1175 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1176 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1177 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1178
21fe9767
DK		 1179 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1180 tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
537559a5
DK		 1181
1182 err = omap_aes_dma_init(dd);
1183 if (err)
1184 goto err_dma;
1185
1186 INIT_LIST_HEAD(&dd->list);
1187 spin_lock(&list_lock);
1188 list_add_tail(&dd->list, &dev_list);
1189 spin_unlock(&list_lock);
1190
f9fb69e7
MG		 1191 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1192 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1193 algp = &dd->pdata->algs_info[i].algs_list[j];
1194
1195 pr_debug("reg alg: %s\n", algp->cra_name);
1196 INIT_LIST_HEAD(&algp->cra_list);
1197
1198 err = crypto_register_alg(algp);
1199 if (err)
1200 goto err_algs;
1201
1202 dd->pdata->algs_info[i].registered++;
1203 }
537559a5
DK		 1204 }
1205
537559a5
DK		 1206 return 0;
1207err_algs:
f9fb69e7
MG		 1208 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1209 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1210 crypto_unregister_alg(
1211 &dd->pdata->algs_info[i].algs_list[j]);
537559a5
DK		 1212 omap_aes_dma_cleanup(dd);
1213err_dma:
21fe9767
DK		 1214 tasklet_kill(&dd->done_task);
1215 tasklet_kill(&dd->queue_task);
5946c4a5 1216 pm_runtime_disable(dev);
537559a5
DK		 1217err_res:
1218 kfree(dd);
1219 dd = NULL;
1220err_data:
1221 dev_err(dev, "initialization failed.\n");
1222 return err;
1223}
1224
1225static int omap_aes_remove(struct platform_device *pdev)
1226{
1227 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
f9fb69e7 1228 int i, j;
537559a5
DK		 1229
1230 if (!dd)
1231 return -ENODEV;
1232
1233 spin_lock(&list_lock);
1234 list_del(&dd->list);
1235 spin_unlock(&list_lock);
1236
f9fb69e7
MG		 1237 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1238 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1239 crypto_unregister_alg(
1240 &dd->pdata->algs_info[i].algs_list[j]);
537559a5 1241
21fe9767
DK		 1242 tasklet_kill(&dd->done_task);
1243 tasklet_kill(&dd->queue_task);
537559a5 1244 omap_aes_dma_cleanup(dd);
5946c4a5 1245 pm_runtime_disable(dd->dev);
537559a5
DK		 1246 kfree(dd);
1247 dd = NULL;
1248
1249 return 0;
1250}
1251
0635fb3a
MG		 1252#ifdef CONFIG_PM_SLEEP
1253static int omap_aes_suspend(struct device *dev)
1254{
1255 pm_runtime_put_sync(dev);
1256 return 0;
1257}
1258
1259static int omap_aes_resume(struct device *dev)
1260{
1261 pm_runtime_get_sync(dev);
1262 return 0;
1263}
1264#endif
1265
1266static const struct dev_pm_ops omap_aes_pm_ops = {
1267 SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
1268};
1269
537559a5
DK		 1270static struct platform_driver omap_aes_driver = {
1271 .probe = omap_aes_probe,
1272 .remove = omap_aes_remove,
1273 .driver = {
1274 .name = "omap-aes",
1275 .owner = THIS_MODULE,
0635fb3a 1276 .pm = &omap_aes_pm_ops,
bc69d124 1277 .of_match_table = omap_aes_of_match,
537559a5
DK		 1278 },
1279};
1280
94e51df9 1281module_platform_driver(omap_aes_driver);
537559a5
DK		 1282
1283MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1284MODULE_LICENSE("GPL v2");
1285MODULE_AUTHOR("Dmitry Kasatkin");
1286
Linux kernel - Deliverables
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