Commit | Line | Data |
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537559a5 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP AES HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | * | |
13 | */ | |
14 | ||
15 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
16 | ||
17 | #include <linux/err.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/scatterlist.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/crypto.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <crypto/scatterwalk.h> | |
30 | #include <crypto/aes.h> | |
31 | ||
32 | #include <plat/cpu.h> | |
33 | #include <plat/dma.h> | |
34 | ||
35 | /* OMAP TRM gives bitfields as start:end, where start is the higher bit | |
36 | number. For example 7:0 */ | |
37 | #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) | |
38 | #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) | |
39 | ||
40 | #define AES_REG_KEY(x) (0x1C - ((x ^ 0x01) * 0x04)) | |
41 | #define AES_REG_IV(x) (0x20 + ((x) * 0x04)) | |
42 | ||
43 | #define AES_REG_CTRL 0x30 | |
44 | #define AES_REG_CTRL_CTR_WIDTH (1 << 7) | |
45 | #define AES_REG_CTRL_CTR (1 << 6) | |
46 | #define AES_REG_CTRL_CBC (1 << 5) | |
47 | #define AES_REG_CTRL_KEY_SIZE (3 << 3) | |
48 | #define AES_REG_CTRL_DIRECTION (1 << 2) | |
49 | #define AES_REG_CTRL_INPUT_READY (1 << 1) | |
50 | #define AES_REG_CTRL_OUTPUT_READY (1 << 0) | |
51 | ||
52 | #define AES_REG_DATA 0x34 | |
53 | #define AES_REG_DATA_N(x) (0x34 + ((x) * 0x04)) | |
54 | ||
55 | #define AES_REG_REV 0x44 | |
56 | #define AES_REG_REV_MAJOR 0xF0 | |
57 | #define AES_REG_REV_MINOR 0x0F | |
58 | ||
59 | #define AES_REG_MASK 0x48 | |
60 | #define AES_REG_MASK_SIDLE (1 << 6) | |
61 | #define AES_REG_MASK_START (1 << 5) | |
62 | #define AES_REG_MASK_DMA_OUT_EN (1 << 3) | |
63 | #define AES_REG_MASK_DMA_IN_EN (1 << 2) | |
64 | #define AES_REG_MASK_SOFTRESET (1 << 1) | |
65 | #define AES_REG_AUTOIDLE (1 << 0) | |
66 | ||
67 | #define AES_REG_SYSSTATUS 0x4C | |
68 | #define AES_REG_SYSSTATUS_RESETDONE (1 << 0) | |
69 | ||
70 | #define DEFAULT_TIMEOUT (5*HZ) | |
71 | ||
72 | #define FLAGS_MODE_MASK 0x000f | |
73 | #define FLAGS_ENCRYPT BIT(0) | |
74 | #define FLAGS_CBC BIT(1) | |
75 | #define FLAGS_GIV BIT(2) | |
76 | ||
77 | #define FLAGS_NEW_KEY BIT(4) | |
78 | #define FLAGS_NEW_IV BIT(5) | |
79 | #define FLAGS_INIT BIT(6) | |
80 | #define FLAGS_FAST BIT(7) | |
eeb2b202 | 81 | #define FLAGS_BUSY BIT(8) |
537559a5 DK |
82 | |
83 | struct omap_aes_ctx { | |
84 | struct omap_aes_dev *dd; | |
85 | ||
86 | int keylen; | |
87 | u32 key[AES_KEYSIZE_256 / sizeof(u32)]; | |
88 | unsigned long flags; | |
89 | }; | |
90 | ||
91 | struct omap_aes_reqctx { | |
92 | unsigned long mode; | |
93 | }; | |
94 | ||
95 | #define OMAP_AES_QUEUE_LENGTH 1 | |
96 | #define OMAP_AES_CACHE_SIZE 0 | |
97 | ||
98 | struct omap_aes_dev { | |
99 | struct list_head list; | |
100 | unsigned long phys_base; | |
101 | void __iomem *io_base; | |
102 | struct clk *iclk; | |
103 | struct omap_aes_ctx *ctx; | |
104 | struct device *dev; | |
105 | unsigned long flags; | |
21fe9767 | 106 | int err; |
537559a5 DK |
107 | |
108 | u32 *iv; | |
109 | u32 ctrl; | |
110 | ||
21fe9767 DK |
111 | spinlock_t lock; |
112 | struct crypto_queue queue; | |
537559a5 | 113 | |
21fe9767 DK |
114 | struct tasklet_struct done_task; |
115 | struct tasklet_struct queue_task; | |
537559a5 DK |
116 | |
117 | struct ablkcipher_request *req; | |
118 | size_t total; | |
119 | struct scatterlist *in_sg; | |
120 | size_t in_offset; | |
121 | struct scatterlist *out_sg; | |
122 | size_t out_offset; | |
123 | ||
124 | size_t buflen; | |
125 | void *buf_in; | |
126 | size_t dma_size; | |
127 | int dma_in; | |
128 | int dma_lch_in; | |
129 | dma_addr_t dma_addr_in; | |
130 | void *buf_out; | |
131 | int dma_out; | |
132 | int dma_lch_out; | |
133 | dma_addr_t dma_addr_out; | |
134 | }; | |
135 | ||
136 | /* keep registered devices data here */ | |
137 | static LIST_HEAD(dev_list); | |
138 | static DEFINE_SPINLOCK(list_lock); | |
139 | ||
140 | static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) | |
141 | { | |
142 | return __raw_readl(dd->io_base + offset); | |
143 | } | |
144 | ||
145 | static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, | |
146 | u32 value) | |
147 | { | |
148 | __raw_writel(value, dd->io_base + offset); | |
149 | } | |
150 | ||
151 | static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, | |
152 | u32 value, u32 mask) | |
153 | { | |
154 | u32 val; | |
155 | ||
156 | val = omap_aes_read(dd, offset); | |
157 | val &= ~mask; | |
158 | val |= value; | |
159 | omap_aes_write(dd, offset, val); | |
160 | } | |
161 | ||
162 | static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, | |
163 | u32 *value, int count) | |
164 | { | |
165 | for (; count--; value++, offset += 4) | |
166 | omap_aes_write(dd, offset, *value); | |
167 | } | |
168 | ||
169 | static int omap_aes_wait(struct omap_aes_dev *dd, u32 offset, u32 bit) | |
170 | { | |
171 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT; | |
172 | ||
173 | while (!(omap_aes_read(dd, offset) & bit)) { | |
174 | if (time_is_before_jiffies(timeout)) { | |
175 | dev_err(dd->dev, "omap-aes timeout\n"); | |
176 | return -ETIMEDOUT; | |
177 | } | |
178 | } | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int omap_aes_hw_init(struct omap_aes_dev *dd) | |
183 | { | |
537559a5 | 184 | clk_enable(dd->iclk); |
eeb2b202 | 185 | |
537559a5 DK |
186 | if (!(dd->flags & FLAGS_INIT)) { |
187 | /* is it necessary to reset before every operation? */ | |
188 | omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_SOFTRESET, | |
189 | AES_REG_MASK_SOFTRESET); | |
190 | /* | |
191 | * prevent OCP bus error (SRESP) in case an access to the module | |
192 | * is performed while the module is coming out of soft reset | |
193 | */ | |
194 | __asm__ __volatile__("nop"); | |
195 | __asm__ __volatile__("nop"); | |
196 | ||
eeb2b202 DK |
197 | if (omap_aes_wait(dd, AES_REG_SYSSTATUS, |
198 | AES_REG_SYSSTATUS_RESETDONE)) { | |
199 | clk_disable(dd->iclk); | |
200 | return -ETIMEDOUT; | |
201 | } | |
202 | dd->flags |= FLAGS_INIT; | |
21fe9767 | 203 | dd->err = 0; |
537559a5 DK |
204 | } |
205 | ||
eeb2b202 | 206 | return 0; |
537559a5 DK |
207 | } |
208 | ||
21fe9767 | 209 | static int omap_aes_write_ctrl(struct omap_aes_dev *dd) |
537559a5 DK |
210 | { |
211 | unsigned int key32; | |
21fe9767 | 212 | int i, err, init = dd->flags & FLAGS_INIT; |
537559a5 DK |
213 | u32 val, mask; |
214 | ||
21fe9767 DK |
215 | err = omap_aes_hw_init(dd); |
216 | if (err) | |
217 | return err; | |
218 | ||
537559a5 DK |
219 | val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); |
220 | if (dd->flags & FLAGS_CBC) | |
221 | val |= AES_REG_CTRL_CBC; | |
222 | if (dd->flags & FLAGS_ENCRYPT) | |
223 | val |= AES_REG_CTRL_DIRECTION; | |
224 | ||
21fe9767 DK |
225 | /* check if hw state & mode have not changed */ |
226 | if (init && dd->ctrl == val && !(dd->flags & FLAGS_NEW_IV) && | |
537559a5 DK |
227 | !(dd->ctx->flags & FLAGS_NEW_KEY)) |
228 | goto out; | |
229 | ||
230 | /* only need to write control registers for new settings */ | |
231 | ||
232 | dd->ctrl = val; | |
233 | ||
234 | val = 0; | |
235 | if (dd->dma_lch_out >= 0) | |
236 | val |= AES_REG_MASK_DMA_OUT_EN; | |
237 | if (dd->dma_lch_in >= 0) | |
238 | val |= AES_REG_MASK_DMA_IN_EN; | |
239 | ||
240 | mask = AES_REG_MASK_DMA_IN_EN | AES_REG_MASK_DMA_OUT_EN; | |
241 | ||
242 | omap_aes_write_mask(dd, AES_REG_MASK, val, mask); | |
243 | ||
244 | pr_debug("Set key\n"); | |
245 | key32 = dd->ctx->keylen / sizeof(u32); | |
246 | /* set a key */ | |
247 | for (i = 0; i < key32; i++) { | |
248 | omap_aes_write(dd, AES_REG_KEY(i), | |
249 | __le32_to_cpu(dd->ctx->key[i])); | |
250 | } | |
251 | dd->ctx->flags &= ~FLAGS_NEW_KEY; | |
252 | ||
253 | if (dd->flags & FLAGS_NEW_IV) { | |
254 | pr_debug("Set IV\n"); | |
255 | omap_aes_write_n(dd, AES_REG_IV(0), dd->iv, 4); | |
256 | dd->flags &= ~FLAGS_NEW_IV; | |
257 | } | |
258 | ||
259 | mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION | | |
260 | AES_REG_CTRL_KEY_SIZE; | |
261 | ||
262 | omap_aes_write_mask(dd, AES_REG_CTRL, dd->ctrl, mask); | |
263 | ||
264 | out: | |
265 | /* start DMA or disable idle mode */ | |
266 | omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START, | |
267 | AES_REG_MASK_START); | |
21fe9767 DK |
268 | |
269 | return 0; | |
537559a5 DK |
270 | } |
271 | ||
272 | static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) | |
273 | { | |
274 | struct omap_aes_dev *dd = NULL, *tmp; | |
275 | ||
276 | spin_lock_bh(&list_lock); | |
277 | if (!ctx->dd) { | |
278 | list_for_each_entry(tmp, &dev_list, list) { | |
279 | /* FIXME: take fist available aes core */ | |
280 | dd = tmp; | |
281 | break; | |
282 | } | |
283 | ctx->dd = dd; | |
284 | } else { | |
285 | /* already found before */ | |
286 | dd = ctx->dd; | |
287 | } | |
288 | spin_unlock_bh(&list_lock); | |
289 | ||
290 | return dd; | |
291 | } | |
292 | ||
293 | static void omap_aes_dma_callback(int lch, u16 ch_status, void *data) | |
294 | { | |
295 | struct omap_aes_dev *dd = data; | |
296 | ||
21fe9767 DK |
297 | if (ch_status != OMAP_DMA_BLOCK_IRQ) { |
298 | pr_err("omap-aes DMA error status: 0x%hx\n", ch_status); | |
299 | dd->err = -EIO; | |
300 | dd->flags &= ~FLAGS_INIT; /* request to re-initialize */ | |
301 | } else if (lch == dd->dma_lch_in) { | |
302 | return; | |
303 | } | |
304 | ||
305 | /* dma_lch_out - completed */ | |
306 | tasklet_schedule(&dd->done_task); | |
537559a5 DK |
307 | } |
308 | ||
309 | static int omap_aes_dma_init(struct omap_aes_dev *dd) | |
310 | { | |
311 | int err = -ENOMEM; | |
312 | ||
313 | dd->dma_lch_out = -1; | |
314 | dd->dma_lch_in = -1; | |
315 | ||
316 | dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE); | |
317 | dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE); | |
318 | dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE; | |
319 | dd->buflen &= ~(AES_BLOCK_SIZE - 1); | |
320 | ||
321 | if (!dd->buf_in || !dd->buf_out) { | |
322 | dev_err(dd->dev, "unable to alloc pages.\n"); | |
323 | goto err_alloc; | |
324 | } | |
325 | ||
326 | /* MAP here */ | |
327 | dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen, | |
328 | DMA_TO_DEVICE); | |
329 | if (dma_mapping_error(dd->dev, dd->dma_addr_in)) { | |
330 | dev_err(dd->dev, "dma %d bytes error\n", dd->buflen); | |
331 | err = -EINVAL; | |
332 | goto err_map_in; | |
333 | } | |
334 | ||
335 | dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen, | |
336 | DMA_FROM_DEVICE); | |
337 | if (dma_mapping_error(dd->dev, dd->dma_addr_out)) { | |
338 | dev_err(dd->dev, "dma %d bytes error\n", dd->buflen); | |
339 | err = -EINVAL; | |
340 | goto err_map_out; | |
341 | } | |
342 | ||
343 | err = omap_request_dma(dd->dma_in, "omap-aes-rx", | |
344 | omap_aes_dma_callback, dd, &dd->dma_lch_in); | |
345 | if (err) { | |
346 | dev_err(dd->dev, "Unable to request DMA channel\n"); | |
347 | goto err_dma_in; | |
348 | } | |
349 | err = omap_request_dma(dd->dma_out, "omap-aes-tx", | |
350 | omap_aes_dma_callback, dd, &dd->dma_lch_out); | |
351 | if (err) { | |
352 | dev_err(dd->dev, "Unable to request DMA channel\n"); | |
353 | goto err_dma_out; | |
354 | } | |
355 | ||
537559a5 DK |
356 | return 0; |
357 | ||
358 | err_dma_out: | |
359 | omap_free_dma(dd->dma_lch_in); | |
360 | err_dma_in: | |
361 | dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen, | |
362 | DMA_FROM_DEVICE); | |
363 | err_map_out: | |
364 | dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE); | |
365 | err_map_in: | |
366 | free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE); | |
367 | free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE); | |
368 | err_alloc: | |
369 | if (err) | |
370 | pr_err("error: %d\n", err); | |
371 | return err; | |
372 | } | |
373 | ||
374 | static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) | |
375 | { | |
376 | omap_free_dma(dd->dma_lch_out); | |
377 | omap_free_dma(dd->dma_lch_in); | |
378 | dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen, | |
379 | DMA_FROM_DEVICE); | |
380 | dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE); | |
381 | free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE); | |
382 | free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE); | |
383 | } | |
384 | ||
385 | static void sg_copy_buf(void *buf, struct scatterlist *sg, | |
386 | unsigned int start, unsigned int nbytes, int out) | |
387 | { | |
388 | struct scatter_walk walk; | |
389 | ||
390 | if (!nbytes) | |
391 | return; | |
392 | ||
393 | scatterwalk_start(&walk, sg); | |
394 | scatterwalk_advance(&walk, start); | |
395 | scatterwalk_copychunks(buf, &walk, nbytes, out); | |
396 | scatterwalk_done(&walk, out, 0); | |
397 | } | |
398 | ||
399 | static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf, | |
400 | size_t buflen, size_t total, int out) | |
401 | { | |
402 | unsigned int count, off = 0; | |
403 | ||
404 | while (buflen && total) { | |
405 | count = min((*sg)->length - *offset, total); | |
406 | count = min(count, buflen); | |
407 | ||
408 | if (!count) | |
409 | return off; | |
410 | ||
21fe9767 DK |
411 | /* |
412 | * buflen and total are AES_BLOCK_SIZE size aligned, | |
413 | * so count should be also aligned | |
414 | */ | |
415 | ||
537559a5 DK |
416 | sg_copy_buf(buf + off, *sg, *offset, count, out); |
417 | ||
418 | off += count; | |
419 | buflen -= count; | |
420 | *offset += count; | |
421 | total -= count; | |
422 | ||
423 | if (*offset == (*sg)->length) { | |
424 | *sg = sg_next(*sg); | |
425 | if (*sg) | |
426 | *offset = 0; | |
427 | else | |
428 | total = 0; | |
429 | } | |
430 | } | |
431 | ||
432 | return off; | |
433 | } | |
434 | ||
435 | static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in, | |
436 | dma_addr_t dma_addr_out, int length) | |
437 | { | |
438 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
439 | struct omap_aes_dev *dd = ctx->dd; | |
440 | int len32; | |
21fe9767 | 441 | int err; |
537559a5 DK |
442 | |
443 | pr_debug("len: %d\n", length); | |
444 | ||
445 | dd->dma_size = length; | |
446 | ||
447 | if (!(dd->flags & FLAGS_FAST)) | |
448 | dma_sync_single_for_device(dd->dev, dma_addr_in, length, | |
449 | DMA_TO_DEVICE); | |
450 | ||
451 | len32 = DIV_ROUND_UP(length, sizeof(u32)); | |
452 | ||
453 | /* IN */ | |
3bd2e221 DK |
454 | omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT, |
455 | dd->phys_base + AES_REG_DATA, 0, 4); | |
456 | ||
457 | omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4); | |
458 | omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4); | |
459 | ||
537559a5 DK |
460 | omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32, |
461 | len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in, | |
462 | OMAP_DMA_DST_SYNC); | |
463 | ||
464 | omap_set_dma_src_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_POST_INC, | |
465 | dma_addr_in, 0, 0); | |
466 | ||
467 | /* OUT */ | |
3bd2e221 DK |
468 | omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT, |
469 | dd->phys_base + AES_REG_DATA, 0, 4); | |
470 | ||
471 | omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4); | |
472 | omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4); | |
473 | ||
537559a5 DK |
474 | omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32, |
475 | len32, 1, OMAP_DMA_SYNC_PACKET, | |
476 | dd->dma_out, OMAP_DMA_SRC_SYNC); | |
477 | ||
478 | omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC, | |
479 | dma_addr_out, 0, 0); | |
480 | ||
21fe9767 DK |
481 | err = omap_aes_write_ctrl(dd); |
482 | if (err) | |
483 | return err; | |
484 | ||
537559a5 DK |
485 | omap_start_dma(dd->dma_lch_in); |
486 | omap_start_dma(dd->dma_lch_out); | |
487 | ||
537559a5 DK |
488 | return 0; |
489 | } | |
490 | ||
491 | static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) | |
492 | { | |
493 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm( | |
494 | crypto_ablkcipher_reqtfm(dd->req)); | |
495 | int err, fast = 0, in, out; | |
496 | size_t count; | |
497 | dma_addr_t addr_in, addr_out; | |
498 | ||
499 | pr_debug("total: %d\n", dd->total); | |
500 | ||
501 | if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) { | |
502 | /* check for alignment */ | |
503 | in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)); | |
504 | out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)); | |
505 | ||
506 | fast = in && out; | |
507 | } | |
508 | ||
509 | if (fast) { | |
510 | count = min(dd->total, sg_dma_len(dd->in_sg)); | |
511 | count = min(count, sg_dma_len(dd->out_sg)); | |
512 | ||
21fe9767 DK |
513 | if (count != dd->total) { |
514 | pr_err("request length != buffer length\n"); | |
537559a5 | 515 | return -EINVAL; |
21fe9767 | 516 | } |
537559a5 DK |
517 | |
518 | pr_debug("fast\n"); | |
519 | ||
520 | err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); | |
521 | if (!err) { | |
522 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
526 | err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); | |
527 | if (!err) { | |
528 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
529 | dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | addr_in = sg_dma_address(dd->in_sg); | |
534 | addr_out = sg_dma_address(dd->out_sg); | |
535 | ||
536 | dd->flags |= FLAGS_FAST; | |
537 | ||
538 | } else { | |
539 | /* use cache buffers */ | |
540 | count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in, | |
541 | dd->buflen, dd->total, 0); | |
542 | ||
543 | addr_in = dd->dma_addr_in; | |
544 | addr_out = dd->dma_addr_out; | |
545 | ||
546 | dd->flags &= ~FLAGS_FAST; | |
547 | ||
548 | } | |
549 | ||
550 | dd->total -= count; | |
551 | ||
537559a5 | 552 | err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count); |
21fe9767 DK |
553 | if (err) { |
554 | dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); | |
555 | dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE); | |
556 | } | |
537559a5 DK |
557 | |
558 | return err; | |
559 | } | |
560 | ||
561 | static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) | |
562 | { | |
21fe9767 | 563 | struct ablkcipher_request *req = dd->req; |
537559a5 DK |
564 | struct omap_aes_ctx *ctx; |
565 | ||
566 | pr_debug("err: %d\n", err); | |
567 | ||
eeb2b202 DK |
568 | dd->flags &= ~FLAGS_BUSY; |
569 | ||
21fe9767 | 570 | ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); |
537559a5 | 571 | |
21fe9767 DK |
572 | if (req->base.complete) |
573 | req->base.complete(&req->base, err); | |
537559a5 DK |
574 | } |
575 | ||
576 | static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) | |
577 | { | |
578 | int err = 0; | |
579 | size_t count; | |
580 | ||
581 | pr_debug("total: %d\n", dd->total); | |
582 | ||
583 | omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START); | |
584 | ||
537559a5 DK |
585 | omap_stop_dma(dd->dma_lch_in); |
586 | omap_stop_dma(dd->dma_lch_out); | |
587 | ||
21fe9767 DK |
588 | clk_disable(dd->iclk); |
589 | ||
537559a5 DK |
590 | if (dd->flags & FLAGS_FAST) { |
591 | dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); | |
592 | dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); | |
593 | } else { | |
594 | dma_sync_single_for_device(dd->dev, dd->dma_addr_out, | |
595 | dd->dma_size, DMA_FROM_DEVICE); | |
596 | ||
597 | /* copy data */ | |
598 | count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out, | |
599 | dd->buflen, dd->dma_size, 1); | |
600 | if (count != dd->dma_size) { | |
601 | err = -EINVAL; | |
602 | pr_err("not all data converted: %u\n", count); | |
603 | } | |
604 | } | |
605 | ||
537559a5 DK |
606 | return err; |
607 | } | |
608 | ||
21fe9767 | 609 | static int omap_aes_handle_queue(struct omap_aes_dev *dd, |
eeb2b202 | 610 | struct ablkcipher_request *req) |
537559a5 DK |
611 | { |
612 | struct crypto_async_request *async_req, *backlog; | |
613 | struct omap_aes_ctx *ctx; | |
614 | struct omap_aes_reqctx *rctx; | |
537559a5 | 615 | unsigned long flags; |
21fe9767 | 616 | int err, ret = 0; |
537559a5 DK |
617 | |
618 | spin_lock_irqsave(&dd->lock, flags); | |
eeb2b202 | 619 | if (req) |
21fe9767 | 620 | ret = ablkcipher_enqueue_request(&dd->queue, req); |
eeb2b202 DK |
621 | if (dd->flags & FLAGS_BUSY) { |
622 | spin_unlock_irqrestore(&dd->lock, flags); | |
21fe9767 | 623 | return ret; |
eeb2b202 | 624 | } |
537559a5 DK |
625 | backlog = crypto_get_backlog(&dd->queue); |
626 | async_req = crypto_dequeue_request(&dd->queue); | |
eeb2b202 DK |
627 | if (async_req) |
628 | dd->flags |= FLAGS_BUSY; | |
537559a5 DK |
629 | spin_unlock_irqrestore(&dd->lock, flags); |
630 | ||
631 | if (!async_req) | |
21fe9767 | 632 | return ret; |
537559a5 DK |
633 | |
634 | if (backlog) | |
635 | backlog->complete(backlog, -EINPROGRESS); | |
636 | ||
637 | req = ablkcipher_request_cast(async_req); | |
638 | ||
639 | pr_debug("get new req\n"); | |
640 | ||
641 | /* assign new request to device */ | |
642 | dd->req = req; | |
643 | dd->total = req->nbytes; | |
644 | dd->in_offset = 0; | |
645 | dd->in_sg = req->src; | |
646 | dd->out_offset = 0; | |
647 | dd->out_sg = req->dst; | |
648 | ||
649 | rctx = ablkcipher_request_ctx(req); | |
650 | ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); | |
651 | rctx->mode &= FLAGS_MODE_MASK; | |
652 | dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; | |
653 | ||
654 | dd->iv = req->info; | |
655 | if ((dd->flags & FLAGS_CBC) && dd->iv) | |
656 | dd->flags |= FLAGS_NEW_IV; | |
657 | else | |
658 | dd->flags &= ~FLAGS_NEW_IV; | |
659 | ||
660 | ctx->dd = dd; | |
661 | if (dd->ctx != ctx) { | |
662 | /* assign new context to device */ | |
663 | dd->ctx = ctx; | |
664 | ctx->flags |= FLAGS_NEW_KEY; | |
665 | } | |
666 | ||
21fe9767 DK |
667 | err = omap_aes_crypt_dma_start(dd); |
668 | if (err) { | |
669 | /* aes_task will not finish it, so do it here */ | |
670 | omap_aes_finish_req(dd, err); | |
671 | tasklet_schedule(&dd->queue_task); | |
672 | } | |
eeb2b202 | 673 | |
21fe9767 | 674 | return ret; /* return ret, which is enqueue return value */ |
537559a5 DK |
675 | } |
676 | ||
21fe9767 | 677 | static void omap_aes_done_task(unsigned long data) |
537559a5 DK |
678 | { |
679 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
21fe9767 | 680 | int err; |
537559a5 DK |
681 | |
682 | pr_debug("enter\n"); | |
683 | ||
21fe9767 | 684 | err = omap_aes_crypt_dma_stop(dd); |
537559a5 | 685 | |
21fe9767 DK |
686 | err = dd->err ? : err; |
687 | ||
688 | if (dd->total && !err) { | |
689 | err = omap_aes_crypt_dma_start(dd); | |
690 | if (!err) | |
691 | return; /* DMA started. Not fininishing. */ | |
692 | } | |
693 | ||
694 | omap_aes_finish_req(dd, err); | |
695 | omap_aes_handle_queue(dd, NULL); | |
537559a5 DK |
696 | |
697 | pr_debug("exit\n"); | |
698 | } | |
699 | ||
21fe9767 DK |
700 | static void omap_aes_queue_task(unsigned long data) |
701 | { | |
702 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
703 | ||
704 | omap_aes_handle_queue(dd, NULL); | |
705 | } | |
706 | ||
537559a5 DK |
707 | static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) |
708 | { | |
709 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( | |
710 | crypto_ablkcipher_reqtfm(req)); | |
711 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
712 | struct omap_aes_dev *dd; | |
537559a5 DK |
713 | |
714 | pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, | |
715 | !!(mode & FLAGS_ENCRYPT), | |
716 | !!(mode & FLAGS_CBC)); | |
717 | ||
21fe9767 DK |
718 | if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { |
719 | pr_err("request size is not exact amount of AES blocks\n"); | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
537559a5 DK |
723 | dd = omap_aes_find_dev(ctx); |
724 | if (!dd) | |
725 | return -ENODEV; | |
726 | ||
727 | rctx->mode = mode; | |
728 | ||
21fe9767 | 729 | return omap_aes_handle_queue(dd, req); |
537559a5 DK |
730 | } |
731 | ||
732 | /* ********************** ALG API ************************************ */ | |
733 | ||
734 | static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
735 | unsigned int keylen) | |
736 | { | |
737 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
738 | ||
739 | if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && | |
740 | keylen != AES_KEYSIZE_256) | |
741 | return -EINVAL; | |
742 | ||
743 | pr_debug("enter, keylen: %d\n", keylen); | |
744 | ||
745 | memcpy(ctx->key, key, keylen); | |
746 | ctx->keylen = keylen; | |
747 | ctx->flags |= FLAGS_NEW_KEY; | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) | |
753 | { | |
754 | return omap_aes_crypt(req, FLAGS_ENCRYPT); | |
755 | } | |
756 | ||
757 | static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) | |
758 | { | |
759 | return omap_aes_crypt(req, 0); | |
760 | } | |
761 | ||
762 | static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) | |
763 | { | |
764 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); | |
765 | } | |
766 | ||
767 | static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) | |
768 | { | |
769 | return omap_aes_crypt(req, FLAGS_CBC); | |
770 | } | |
771 | ||
772 | static int omap_aes_cra_init(struct crypto_tfm *tfm) | |
773 | { | |
774 | pr_debug("enter\n"); | |
775 | ||
776 | tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | static void omap_aes_cra_exit(struct crypto_tfm *tfm) | |
782 | { | |
783 | pr_debug("enter\n"); | |
784 | } | |
785 | ||
786 | /* ********************** ALGS ************************************ */ | |
787 | ||
788 | static struct crypto_alg algs[] = { | |
789 | { | |
790 | .cra_name = "ecb(aes)", | |
791 | .cra_driver_name = "ecb-aes-omap", | |
792 | .cra_priority = 100, | |
793 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, | |
794 | .cra_blocksize = AES_BLOCK_SIZE, | |
795 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
796 | .cra_alignmask = 0, | |
797 | .cra_type = &crypto_ablkcipher_type, | |
798 | .cra_module = THIS_MODULE, | |
799 | .cra_init = omap_aes_cra_init, | |
800 | .cra_exit = omap_aes_cra_exit, | |
801 | .cra_u.ablkcipher = { | |
802 | .min_keysize = AES_MIN_KEY_SIZE, | |
803 | .max_keysize = AES_MAX_KEY_SIZE, | |
804 | .setkey = omap_aes_setkey, | |
805 | .encrypt = omap_aes_ecb_encrypt, | |
806 | .decrypt = omap_aes_ecb_decrypt, | |
807 | } | |
808 | }, | |
809 | { | |
810 | .cra_name = "cbc(aes)", | |
811 | .cra_driver_name = "cbc-aes-omap", | |
812 | .cra_priority = 100, | |
813 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, | |
814 | .cra_blocksize = AES_BLOCK_SIZE, | |
815 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
816 | .cra_alignmask = 0, | |
817 | .cra_type = &crypto_ablkcipher_type, | |
818 | .cra_module = THIS_MODULE, | |
819 | .cra_init = omap_aes_cra_init, | |
820 | .cra_exit = omap_aes_cra_exit, | |
821 | .cra_u.ablkcipher = { | |
822 | .min_keysize = AES_MIN_KEY_SIZE, | |
823 | .max_keysize = AES_MAX_KEY_SIZE, | |
824 | .ivsize = AES_BLOCK_SIZE, | |
825 | .setkey = omap_aes_setkey, | |
826 | .encrypt = omap_aes_cbc_encrypt, | |
827 | .decrypt = omap_aes_cbc_decrypt, | |
828 | } | |
829 | } | |
830 | }; | |
831 | ||
832 | static int omap_aes_probe(struct platform_device *pdev) | |
833 | { | |
834 | struct device *dev = &pdev->dev; | |
835 | struct omap_aes_dev *dd; | |
836 | struct resource *res; | |
837 | int err = -ENOMEM, i, j; | |
838 | u32 reg; | |
839 | ||
840 | dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL); | |
841 | if (dd == NULL) { | |
842 | dev_err(dev, "unable to alloc data struct.\n"); | |
843 | goto err_data; | |
844 | } | |
845 | dd->dev = dev; | |
846 | platform_set_drvdata(pdev, dd); | |
847 | ||
848 | spin_lock_init(&dd->lock); | |
849 | crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH); | |
850 | ||
851 | /* Get the base address */ | |
852 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
853 | if (!res) { | |
854 | dev_err(dev, "invalid resource type\n"); | |
855 | err = -ENODEV; | |
856 | goto err_res; | |
857 | } | |
858 | dd->phys_base = res->start; | |
859 | ||
860 | /* Get the DMA */ | |
861 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
862 | if (!res) | |
863 | dev_info(dev, "no DMA info\n"); | |
864 | else | |
865 | dd->dma_out = res->start; | |
866 | ||
867 | /* Get the DMA */ | |
868 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
869 | if (!res) | |
870 | dev_info(dev, "no DMA info\n"); | |
871 | else | |
872 | dd->dma_in = res->start; | |
873 | ||
874 | /* Initializing the clock */ | |
875 | dd->iclk = clk_get(dev, "ick"); | |
876 | if (!dd->iclk) { | |
877 | dev_err(dev, "clock intialization failed.\n"); | |
878 | err = -ENODEV; | |
879 | goto err_res; | |
880 | } | |
881 | ||
882 | dd->io_base = ioremap(dd->phys_base, SZ_4K); | |
883 | if (!dd->io_base) { | |
884 | dev_err(dev, "can't ioremap\n"); | |
885 | err = -ENOMEM; | |
886 | goto err_io; | |
887 | } | |
888 | ||
889 | clk_enable(dd->iclk); | |
890 | reg = omap_aes_read(dd, AES_REG_REV); | |
891 | dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", | |
892 | (reg & AES_REG_REV_MAJOR) >> 4, reg & AES_REG_REV_MINOR); | |
893 | clk_disable(dd->iclk); | |
894 | ||
21fe9767 DK |
895 | tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); |
896 | tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd); | |
537559a5 DK |
897 | |
898 | err = omap_aes_dma_init(dd); | |
899 | if (err) | |
900 | goto err_dma; | |
901 | ||
902 | INIT_LIST_HEAD(&dd->list); | |
903 | spin_lock(&list_lock); | |
904 | list_add_tail(&dd->list, &dev_list); | |
905 | spin_unlock(&list_lock); | |
906 | ||
907 | for (i = 0; i < ARRAY_SIZE(algs); i++) { | |
908 | pr_debug("i: %d\n", i); | |
909 | INIT_LIST_HEAD(&algs[i].cra_list); | |
910 | err = crypto_register_alg(&algs[i]); | |
911 | if (err) | |
912 | goto err_algs; | |
913 | } | |
914 | ||
915 | pr_info("probe() done\n"); | |
916 | ||
917 | return 0; | |
918 | err_algs: | |
919 | for (j = 0; j < i; j++) | |
920 | crypto_unregister_alg(&algs[j]); | |
921 | omap_aes_dma_cleanup(dd); | |
922 | err_dma: | |
21fe9767 DK |
923 | tasklet_kill(&dd->done_task); |
924 | tasklet_kill(&dd->queue_task); | |
537559a5 DK |
925 | iounmap(dd->io_base); |
926 | err_io: | |
927 | clk_put(dd->iclk); | |
928 | err_res: | |
929 | kfree(dd); | |
930 | dd = NULL; | |
931 | err_data: | |
932 | dev_err(dev, "initialization failed.\n"); | |
933 | return err; | |
934 | } | |
935 | ||
936 | static int omap_aes_remove(struct platform_device *pdev) | |
937 | { | |
938 | struct omap_aes_dev *dd = platform_get_drvdata(pdev); | |
939 | int i; | |
940 | ||
941 | if (!dd) | |
942 | return -ENODEV; | |
943 | ||
944 | spin_lock(&list_lock); | |
945 | list_del(&dd->list); | |
946 | spin_unlock(&list_lock); | |
947 | ||
948 | for (i = 0; i < ARRAY_SIZE(algs); i++) | |
949 | crypto_unregister_alg(&algs[i]); | |
950 | ||
21fe9767 DK |
951 | tasklet_kill(&dd->done_task); |
952 | tasklet_kill(&dd->queue_task); | |
537559a5 DK |
953 | omap_aes_dma_cleanup(dd); |
954 | iounmap(dd->io_base); | |
955 | clk_put(dd->iclk); | |
956 | kfree(dd); | |
957 | dd = NULL; | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | static struct platform_driver omap_aes_driver = { | |
963 | .probe = omap_aes_probe, | |
964 | .remove = omap_aes_remove, | |
965 | .driver = { | |
966 | .name = "omap-aes", | |
967 | .owner = THIS_MODULE, | |
968 | }, | |
969 | }; | |
970 | ||
971 | static int __init omap_aes_mod_init(void) | |
972 | { | |
973 | pr_info("loading %s driver\n", "omap-aes"); | |
974 | ||
975 | if (!cpu_class_is_omap2() || omap_type() != OMAP2_DEVICE_TYPE_SEC) { | |
976 | pr_err("Unsupported cpu\n"); | |
977 | return -ENODEV; | |
978 | } | |
979 | ||
980 | return platform_driver_register(&omap_aes_driver); | |
981 | } | |
982 | ||
983 | static void __exit omap_aes_mod_exit(void) | |
984 | { | |
985 | platform_driver_unregister(&omap_aes_driver); | |
986 | } | |
987 | ||
988 | module_init(omap_aes_mod_init); | |
989 | module_exit(omap_aes_mod_exit); | |
990 | ||
991 | MODULE_DESCRIPTION("OMAP AES hw acceleration support."); | |
992 | MODULE_LICENSE("GPL v2"); | |
993 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
994 |