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crypto: omap-aes - Don't reset controller for every operation
[deliverable/linux.git] / drivers / crypto / omap-aes.c
CommitLineData
537559a5
DK		 1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 */
14
15#define pr_fmt(fmt) "%s: " fmt, __func__
16
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/platform_device.h>
24#include <linux/scatterlist.h>
25#include <linux/dma-mapping.h>
26#include <linux/io.h>
27#include <linux/crypto.h>
28#include <linux/interrupt.h>
29#include <crypto/scatterwalk.h>
30#include <crypto/aes.h>
31
45c3eb7d 32#include <linux/omap-dma.h>
537559a5
DK		 33
34/* OMAP TRM gives bitfields as start:end, where start is the higher bit
35 number. For example 7:0 */
36#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
37#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
38
39#define AES_REG_KEY(x) (0x1C - ((x ^ 0x01) * 0x04))
40#define AES_REG_IV(x) (0x20 + ((x) * 0x04))
41
42#define AES_REG_CTRL 0x30
43#define AES_REG_CTRL_CTR_WIDTH (1 << 7)
44#define AES_REG_CTRL_CTR (1 << 6)
45#define AES_REG_CTRL_CBC (1 << 5)
46#define AES_REG_CTRL_KEY_SIZE (3 << 3)
47#define AES_REG_CTRL_DIRECTION (1 << 2)
48#define AES_REG_CTRL_INPUT_READY (1 << 1)
49#define AES_REG_CTRL_OUTPUT_READY (1 << 0)
50
51#define AES_REG_DATA 0x34
52#define AES_REG_DATA_N(x) (0x34 + ((x) * 0x04))
53
54#define AES_REG_REV 0x44
55#define AES_REG_REV_MAJOR 0xF0
56#define AES_REG_REV_MINOR 0x0F
57
58#define AES_REG_MASK 0x48
59#define AES_REG_MASK_SIDLE (1 << 6)
60#define AES_REG_MASK_START (1 << 5)
61#define AES_REG_MASK_DMA_OUT_EN (1 << 3)
62#define AES_REG_MASK_DMA_IN_EN (1 << 2)
63#define AES_REG_MASK_SOFTRESET (1 << 1)
64#define AES_REG_AUTOIDLE (1 << 0)
65
66#define AES_REG_SYSSTATUS 0x4C
67#define AES_REG_SYSSTATUS_RESETDONE (1 << 0)
68
69#define DEFAULT_TIMEOUT (5*HZ)
70
71#define FLAGS_MODE_MASK 0x000f
72#define FLAGS_ENCRYPT BIT(0)
73#define FLAGS_CBC BIT(1)
74#define FLAGS_GIV BIT(2)
75
67a730ce
DK		 76#define FLAGS_INIT BIT(4)
77#define FLAGS_FAST BIT(5)
78#define FLAGS_BUSY BIT(6)
537559a5
DK		 79
80struct omap_aes_ctx {
81 struct omap_aes_dev *dd;
82
83 int keylen;
84 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
85 unsigned long flags;
86};
87
88struct omap_aes_reqctx {
89 unsigned long mode;
90};
91
92#define OMAP_AES_QUEUE_LENGTH 1
93#define OMAP_AES_CACHE_SIZE 0
94
95struct omap_aes_dev {
96 struct list_head list;
97 unsigned long phys_base;
efce41b6 98 void __iomem *io_base;
537559a5
DK		 99 struct clk *iclk;
100 struct omap_aes_ctx *ctx;
101 struct device *dev;
102 unsigned long flags;
21fe9767 103 int err;
537559a5 104
21fe9767
DK		 105 spinlock_t lock;
106 struct crypto_queue queue;
537559a5 107
21fe9767
DK		 108 struct tasklet_struct done_task;
109 struct tasklet_struct queue_task;
537559a5
DK		 110
111 struct ablkcipher_request *req;
112 size_t total;
113 struct scatterlist *in_sg;
114 size_t in_offset;
115 struct scatterlist *out_sg;
116 size_t out_offset;
117
118 size_t buflen;
119 void *buf_in;
120 size_t dma_size;
121 int dma_in;
122 int dma_lch_in;
123 dma_addr_t dma_addr_in;
124 void *buf_out;
125 int dma_out;
126 int dma_lch_out;
127 dma_addr_t dma_addr_out;
128};
129
130/* keep registered devices data here */
131static LIST_HEAD(dev_list);
132static DEFINE_SPINLOCK(list_lock);
133
134static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
135{
136 return __raw_readl(dd->io_base + offset);
137}
138
139static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
140 u32 value)
141{
142 __raw_writel(value, dd->io_base + offset);
143}
144
145static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
146 u32 value, u32 mask)
147{
148 u32 val;
149
150 val = omap_aes_read(dd, offset);
151 val &= ~mask;
152 val |= value;
153 omap_aes_write(dd, offset, val);
154}
155
156static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
157 u32 *value, int count)
158{
159 for (; count--; value++, offset += 4)
160 omap_aes_write(dd, offset, *value);
161}
162
537559a5
DK		 163static int omap_aes_hw_init(struct omap_aes_dev *dd)
164{
83ea7e0f
DK		 165 /*
166 * clocks are enabled when request starts and disabled when finished.
167 * It may be long delays between requests.
168 * Device might go to off mode to save power.
169 */
537559a5 170 clk_enable(dd->iclk);
eeb2b202 171
537559a5 172 if (!(dd->flags & FLAGS_INIT)) {
eeb2b202 173 dd->flags |= FLAGS_INIT;
21fe9767 174 dd->err = 0;
537559a5
DK		 175 }
176
eeb2b202 177 return 0;
537559a5
DK		 178}
179
21fe9767 180static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
537559a5
DK		 181{
182 unsigned int key32;
67a730ce 183 int i, err;
537559a5
DK		 184 u32 val, mask;
185
21fe9767
DK		 186 err = omap_aes_hw_init(dd);
187 if (err)
188 return err;
189
537559a5
DK		 190 val = 0;
191 if (dd->dma_lch_out >= 0)
192 val |= AES_REG_MASK_DMA_OUT_EN;
193 if (dd->dma_lch_in >= 0)
194 val |= AES_REG_MASK_DMA_IN_EN;
195
196 mask = AES_REG_MASK_DMA_IN_EN | AES_REG_MASK_DMA_OUT_EN;
197
198 omap_aes_write_mask(dd, AES_REG_MASK, val, mask);
199
537559a5 200 key32 = dd->ctx->keylen / sizeof(u32);
67a730ce
DK		 201
202 /* it seems a key should always be set even if it has not changed */
537559a5
DK		 203 for (i = 0; i < key32; i++) {
204 omap_aes_write(dd, AES_REG_KEY(i),
205 __le32_to_cpu(dd->ctx->key[i]));
206 }
537559a5 207
67a730ce
DK		 208 if ((dd->flags & FLAGS_CBC) && dd->req->info)
209 omap_aes_write_n(dd, AES_REG_IV(0), dd->req->info, 4);
210
211 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
212 if (dd->flags & FLAGS_CBC)
213 val |= AES_REG_CTRL_CBC;
214 if (dd->flags & FLAGS_ENCRYPT)
215 val |= AES_REG_CTRL_DIRECTION;
537559a5
DK		 216
217 mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
218 AES_REG_CTRL_KEY_SIZE;
219
67a730ce 220 omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
537559a5 221
83ea7e0f
DK		 222 /* IN */
223 omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
224 dd->phys_base + AES_REG_DATA, 0, 4);
225
226 omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
227 omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
228
229 /* OUT */
230 omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
231 dd->phys_base + AES_REG_DATA, 0, 4);
232
233 omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
234 omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
21fe9767
DK		 235
236 return 0;
537559a5
DK		 237}
238
239static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
240{
241 struct omap_aes_dev *dd = NULL, *tmp;
242
243 spin_lock_bh(&list_lock);
244 if (!ctx->dd) {
245 list_for_each_entry(tmp, &dev_list, list) {
246 /* FIXME: take fist available aes core */
247 dd = tmp;
248 break;
249 }
250 ctx->dd = dd;
251 } else {
252 /* already found before */
253 dd = ctx->dd;
254 }
255 spin_unlock_bh(&list_lock);
256
257 return dd;
258}
259
260static void omap_aes_dma_callback(int lch, u16 ch_status, void *data)
261{
262 struct omap_aes_dev *dd = data;
263
21fe9767
DK		 264 if (ch_status != OMAP_DMA_BLOCK_IRQ) {
265 pr_err("omap-aes DMA error status: 0x%hx\n", ch_status);
266 dd->err = -EIO;
267 dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
268 } else if (lch == dd->dma_lch_in) {
269 return;
270 }
271
272 /* dma_lch_out - completed */
273 tasklet_schedule(&dd->done_task);
537559a5
DK		 274}
275
276static int omap_aes_dma_init(struct omap_aes_dev *dd)
277{
278 int err = -ENOMEM;
279
280 dd->dma_lch_out = -1;
281 dd->dma_lch_in = -1;
282
283 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
284 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
285 dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE;
286 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
287
288 if (!dd->buf_in || !dd->buf_out) {
289 dev_err(dd->dev, "unable to alloc pages.\n");
290 goto err_alloc;
291 }
292
293 /* MAP here */
294 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen,
295 DMA_TO_DEVICE);
296 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
297 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
298 err = -EINVAL;
299 goto err_map_in;
300 }
301
302 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen,
303 DMA_FROM_DEVICE);
304 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
305 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
306 err = -EINVAL;
307 goto err_map_out;
308 }
309
310 err = omap_request_dma(dd->dma_in, "omap-aes-rx",
311 omap_aes_dma_callback, dd, &dd->dma_lch_in);
312 if (err) {
313 dev_err(dd->dev, "Unable to request DMA channel\n");
314 goto err_dma_in;
315 }
316 err = omap_request_dma(dd->dma_out, "omap-aes-tx",
317 omap_aes_dma_callback, dd, &dd->dma_lch_out);
318 if (err) {
319 dev_err(dd->dev, "Unable to request DMA channel\n");
320 goto err_dma_out;
321 }
322
537559a5
DK		 323 return 0;
324
325err_dma_out:
326 omap_free_dma(dd->dma_lch_in);
327err_dma_in:
328 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
329 DMA_FROM_DEVICE);
330err_map_out:
331 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
332err_map_in:
333 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
334 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
335err_alloc:
336 if (err)
337 pr_err("error: %d\n", err);
338 return err;
339}
340
341static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
342{
343 omap_free_dma(dd->dma_lch_out);
344 omap_free_dma(dd->dma_lch_in);
345 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
346 DMA_FROM_DEVICE);
347 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
348 free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
349 free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
350}
351
352static void sg_copy_buf(void *buf, struct scatterlist *sg,
353 unsigned int start, unsigned int nbytes, int out)
354{
355 struct scatter_walk walk;
356
357 if (!nbytes)
358 return;
359
360 scatterwalk_start(&walk, sg);
361 scatterwalk_advance(&walk, start);
362 scatterwalk_copychunks(buf, &walk, nbytes, out);
363 scatterwalk_done(&walk, out, 0);
364}
365
366static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
367 size_t buflen, size_t total, int out)
368{
369 unsigned int count, off = 0;
370
371 while (buflen && total) {
372 count = min((*sg)->length - *offset, total);
373 count = min(count, buflen);
374
375 if (!count)
376 return off;
377
21fe9767
DK		 378 /*
379 * buflen and total are AES_BLOCK_SIZE size aligned,
380 * so count should be also aligned
381 */
382
537559a5
DK		 383 sg_copy_buf(buf + off, *sg, *offset, count, out);
384
385 off += count;
386 buflen -= count;
387 *offset += count;
388 total -= count;
389
390 if (*offset == (*sg)->length) {
391 *sg = sg_next(*sg);
392 if (*sg)
393 *offset = 0;
394 else
395 total = 0;
396 }
397 }
398
399 return off;
400}
401
402static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
403 dma_addr_t dma_addr_out, int length)
404{
405 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
406 struct omap_aes_dev *dd = ctx->dd;
407 int len32;
408
409 pr_debug("len: %d\n", length);
410
411 dd->dma_size = length;
412
413 if (!(dd->flags & FLAGS_FAST))
414 dma_sync_single_for_device(dd->dev, dma_addr_in, length,
415 DMA_TO_DEVICE);
416
417 len32 = DIV_ROUND_UP(length, sizeof(u32));
418
419 /* IN */
420 omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32,
421 len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in,
422 OMAP_DMA_DST_SYNC);
423
424 omap_set_dma_src_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_POST_INC,
425 dma_addr_in, 0, 0);
426
427 /* OUT */
428 omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32,
429 len32, 1, OMAP_DMA_SYNC_PACKET,
430 dd->dma_out, OMAP_DMA_SRC_SYNC);
431
432 omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
433 dma_addr_out, 0, 0);
434
435 omap_start_dma(dd->dma_lch_in);
436 omap_start_dma(dd->dma_lch_out);
437
83ea7e0f
DK		 438 /* start DMA or disable idle mode */
439 omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
440 AES_REG_MASK_START);
441
537559a5
DK		 442 return 0;
443}
444
445static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
446{
447 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
448 crypto_ablkcipher_reqtfm(dd->req));
449 int err, fast = 0, in, out;
450 size_t count;
451 dma_addr_t addr_in, addr_out;
452
453 pr_debug("total: %d\n", dd->total);
454
455 if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
456 /* check for alignment */
457 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
458 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
459
460 fast = in && out;
461 }
462
463 if (fast) {
464 count = min(dd->total, sg_dma_len(dd->in_sg));
465 count = min(count, sg_dma_len(dd->out_sg));
466
21fe9767
DK		 467 if (count != dd->total) {
468 pr_err("request length != buffer length\n");
537559a5 469 return -EINVAL;
21fe9767 470 }
537559a5
DK		 471
472 pr_debug("fast\n");
473
474 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
475 if (!err) {
476 dev_err(dd->dev, "dma_map_sg() error\n");
477 return -EINVAL;
478 }
479
480 err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
481 if (!err) {
482 dev_err(dd->dev, "dma_map_sg() error\n");
483 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
484 return -EINVAL;
485 }
486
487 addr_in = sg_dma_address(dd->in_sg);
488 addr_out = sg_dma_address(dd->out_sg);
489
490 dd->flags |= FLAGS_FAST;
491
492 } else {
493 /* use cache buffers */
494 count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
495 dd->buflen, dd->total, 0);
496
497 addr_in = dd->dma_addr_in;
498 addr_out = dd->dma_addr_out;
499
500 dd->flags &= ~FLAGS_FAST;
501
502 }
503
504 dd->total -= count;
505
537559a5 506 err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count);
21fe9767
DK		 507 if (err) {
508 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
509 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
510 }
537559a5
DK		 511
512 return err;
513}
514
515static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
516{
21fe9767 517 struct ablkcipher_request *req = dd->req;
537559a5
DK		 518
519 pr_debug("err: %d\n", err);
520
83ea7e0f 521 clk_disable(dd->iclk);
eeb2b202
DK		 522 dd->flags &= ~FLAGS_BUSY;
523
67a730ce 524 req->base.complete(&req->base, err);
537559a5
DK		 525}
526
527static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
528{
529 int err = 0;
530 size_t count;
531
532 pr_debug("total: %d\n", dd->total);
533
534 omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START);
535
537559a5
DK		 536 omap_stop_dma(dd->dma_lch_in);
537 omap_stop_dma(dd->dma_lch_out);
538
539 if (dd->flags & FLAGS_FAST) {
540 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
541 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
542 } else {
543 dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
544 dd->dma_size, DMA_FROM_DEVICE);
545
546 /* copy data */
547 count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out,
548 dd->buflen, dd->dma_size, 1);
549 if (count != dd->dma_size) {
550 err = -EINVAL;
551 pr_err("not all data converted: %u\n", count);
552 }
553 }
554
537559a5
DK		 555 return err;
556}
557
21fe9767 558static int omap_aes_handle_queue(struct omap_aes_dev *dd,
eeb2b202 559 struct ablkcipher_request *req)
537559a5
DK		 560{
561 struct crypto_async_request *async_req, *backlog;
562 struct omap_aes_ctx *ctx;
563 struct omap_aes_reqctx *rctx;
537559a5 564 unsigned long flags;
21fe9767 565 int err, ret = 0;
537559a5
DK		 566
567 spin_lock_irqsave(&dd->lock, flags);
eeb2b202 568 if (req)
21fe9767 569 ret = ablkcipher_enqueue_request(&dd->queue, req);
eeb2b202
DK		 570 if (dd->flags & FLAGS_BUSY) {
571 spin_unlock_irqrestore(&dd->lock, flags);
21fe9767 572 return ret;
eeb2b202 573 }
537559a5
DK		 574 backlog = crypto_get_backlog(&dd->queue);
575 async_req = crypto_dequeue_request(&dd->queue);
eeb2b202
DK		 576 if (async_req)
577 dd->flags |= FLAGS_BUSY;
537559a5
DK		 578 spin_unlock_irqrestore(&dd->lock, flags);
579
580 if (!async_req)
21fe9767 581 return ret;
537559a5
DK		 582
583 if (backlog)
584 backlog->complete(backlog, -EINPROGRESS);
585
586 req = ablkcipher_request_cast(async_req);
587
537559a5
DK		 588 /* assign new request to device */
589 dd->req = req;
590 dd->total = req->nbytes;
591 dd->in_offset = 0;
592 dd->in_sg = req->src;
593 dd->out_offset = 0;
594 dd->out_sg = req->dst;
595
596 rctx = ablkcipher_request_ctx(req);
597 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
598 rctx->mode &= FLAGS_MODE_MASK;
599 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
600
67a730ce 601 dd->ctx = ctx;
537559a5 602 ctx->dd = dd;
537559a5 603
83ea7e0f
DK		 604 err = omap_aes_write_ctrl(dd);
605 if (!err)
606 err = omap_aes_crypt_dma_start(dd);
21fe9767
DK		 607 if (err) {
608 /* aes_task will not finish it, so do it here */
609 omap_aes_finish_req(dd, err);
610 tasklet_schedule(&dd->queue_task);
611 }
eeb2b202 612
21fe9767 613 return ret; /* return ret, which is enqueue return value */
537559a5
DK		 614}
615
21fe9767 616static void omap_aes_done_task(unsigned long data)
537559a5
DK		 617{
618 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
21fe9767 619 int err;
537559a5
DK		 620
621 pr_debug("enter\n");
622
21fe9767 623 err = omap_aes_crypt_dma_stop(dd);
537559a5 624
21fe9767
DK		 625 err = dd->err ? : err;
626
627 if (dd->total && !err) {
628 err = omap_aes_crypt_dma_start(dd);
629 if (!err)
630 return; /* DMA started. Not fininishing. */
631 }
632
633 omap_aes_finish_req(dd, err);
634 omap_aes_handle_queue(dd, NULL);
537559a5
DK		 635
636 pr_debug("exit\n");
637}
638
21fe9767
DK		 639static void omap_aes_queue_task(unsigned long data)
640{
641 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
642
643 omap_aes_handle_queue(dd, NULL);
644}
645
537559a5
DK		 646static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
647{
648 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
649 crypto_ablkcipher_reqtfm(req));
650 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
651 struct omap_aes_dev *dd;
537559a5
DK		 652
653 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
654 !!(mode & FLAGS_ENCRYPT),
655 !!(mode & FLAGS_CBC));
656
21fe9767
DK		 657 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
658 pr_err("request size is not exact amount of AES blocks\n");
659 return -EINVAL;
660 }
661
537559a5
DK		 662 dd = omap_aes_find_dev(ctx);
663 if (!dd)
664 return -ENODEV;
665
666 rctx->mode = mode;
667
21fe9767 668 return omap_aes_handle_queue(dd, req);
537559a5
DK		 669}
670
671/* ********************** ALG API ************************************ */
672
673static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
674 unsigned int keylen)
675{
676 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
677
678 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
679 keylen != AES_KEYSIZE_256)
680 return -EINVAL;
681
682 pr_debug("enter, keylen: %d\n", keylen);
683
684 memcpy(ctx->key, key, keylen);
685 ctx->keylen = keylen;
537559a5
DK		 686
687 return 0;
688}
689
690static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
691{
692 return omap_aes_crypt(req, FLAGS_ENCRYPT);
693}
694
695static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
696{
697 return omap_aes_crypt(req, 0);
698}
699
700static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
701{
702 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
703}
704
705static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
706{
707 return omap_aes_crypt(req, FLAGS_CBC);
708}
709
710static int omap_aes_cra_init(struct crypto_tfm *tfm)
711{
712 pr_debug("enter\n");
713
714 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
715
716 return 0;
717}
718
719static void omap_aes_cra_exit(struct crypto_tfm *tfm)
720{
721 pr_debug("enter\n");
722}
723
724/* ********************** ALGS ************************************ */
725
726static struct crypto_alg algs[] = {
727{
728 .cra_name = "ecb(aes)",
729 .cra_driver_name = "ecb-aes-omap",
730 .cra_priority = 100,
d912bb76
NM		 731 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
732 CRYPTO_ALG_KERN_DRIVER_ONLY |
733 CRYPTO_ALG_ASYNC,
537559a5
DK		 734 .cra_blocksize = AES_BLOCK_SIZE,
735 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 736 .cra_alignmask = 0,
537559a5
DK		 737 .cra_type = &crypto_ablkcipher_type,
738 .cra_module = THIS_MODULE,
739 .cra_init = omap_aes_cra_init,
740 .cra_exit = omap_aes_cra_exit,
741 .cra_u.ablkcipher = {
742 .min_keysize = AES_MIN_KEY_SIZE,
743 .max_keysize = AES_MAX_KEY_SIZE,
744 .setkey = omap_aes_setkey,
745 .encrypt = omap_aes_ecb_encrypt,
746 .decrypt = omap_aes_ecb_decrypt,
747 }
748},
749{
750 .cra_name = "cbc(aes)",
751 .cra_driver_name = "cbc-aes-omap",
752 .cra_priority = 100,
d912bb76
NM		 753 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
754 CRYPTO_ALG_KERN_DRIVER_ONLY |
755 CRYPTO_ALG_ASYNC,
537559a5
DK		 756 .cra_blocksize = AES_BLOCK_SIZE,
757 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 758 .cra_alignmask = 0,
537559a5
DK		 759 .cra_type = &crypto_ablkcipher_type,
760 .cra_module = THIS_MODULE,
761 .cra_init = omap_aes_cra_init,
762 .cra_exit = omap_aes_cra_exit,
763 .cra_u.ablkcipher = {
764 .min_keysize = AES_MIN_KEY_SIZE,
765 .max_keysize = AES_MAX_KEY_SIZE,
766 .ivsize = AES_BLOCK_SIZE,
767 .setkey = omap_aes_setkey,
768 .encrypt = omap_aes_cbc_encrypt,
769 .decrypt = omap_aes_cbc_decrypt,
770 }
771}
772};
773
774static int omap_aes_probe(struct platform_device *pdev)
775{
776 struct device *dev = &pdev->dev;
777 struct omap_aes_dev *dd;
778 struct resource *res;
779 int err = -ENOMEM, i, j;
780 u32 reg;
781
782 dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
783 if (dd == NULL) {
784 dev_err(dev, "unable to alloc data struct.\n");
785 goto err_data;
786 }
787 dd->dev = dev;
788 platform_set_drvdata(pdev, dd);
789
790 spin_lock_init(&dd->lock);
791 crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
792
793 /* Get the base address */
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 if (!res) {
796 dev_err(dev, "invalid resource type\n");
797 err = -ENODEV;
798 goto err_res;
799 }
800 dd->phys_base = res->start;
801
802 /* Get the DMA */
803 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
804 if (!res)
805 dev_info(dev, "no DMA info\n");
806 else
807 dd->dma_out = res->start;
808
809 /* Get the DMA */
810 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
811 if (!res)
812 dev_info(dev, "no DMA info\n");
813 else
814 dd->dma_in = res->start;
815
816 /* Initializing the clock */
817 dd->iclk = clk_get(dev, "ick");
3e50191d 818 if (IS_ERR(dd->iclk)) {
537559a5 819 dev_err(dev, "clock intialization failed.\n");
3e50191d 820 err = PTR_ERR(dd->iclk);
537559a5
DK		 821 goto err_res;
822 }
823
824 dd->io_base = ioremap(dd->phys_base, SZ_4K);
825 if (!dd->io_base) {
826 dev_err(dev, "can't ioremap\n");
827 err = -ENOMEM;
828 goto err_io;
829 }
830
831 clk_enable(dd->iclk);
832 reg = omap_aes_read(dd, AES_REG_REV);
833 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
834 (reg & AES_REG_REV_MAJOR) >> 4, reg & AES_REG_REV_MINOR);
835 clk_disable(dd->iclk);
836
21fe9767
DK		 837 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
838 tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
537559a5
DK		 839
840 err = omap_aes_dma_init(dd);
841 if (err)
842 goto err_dma;
843
844 INIT_LIST_HEAD(&dd->list);
845 spin_lock(&list_lock);
846 list_add_tail(&dd->list, &dev_list);
847 spin_unlock(&list_lock);
848
849 for (i = 0; i < ARRAY_SIZE(algs); i++) {
850 pr_debug("i: %d\n", i);
537559a5
DK		 851 err = crypto_register_alg(&algs[i]);
852 if (err)
853 goto err_algs;
854 }
855
537559a5
DK		 856 return 0;
857err_algs:
858 for (j = 0; j < i; j++)
859 crypto_unregister_alg(&algs[j]);
860 omap_aes_dma_cleanup(dd);
861err_dma:
21fe9767
DK		 862 tasklet_kill(&dd->done_task);
863 tasklet_kill(&dd->queue_task);
537559a5
DK		 864 iounmap(dd->io_base);
865err_io:
866 clk_put(dd->iclk);
867err_res:
868 kfree(dd);
869 dd = NULL;
870err_data:
871 dev_err(dev, "initialization failed.\n");
872 return err;
873}
874
875static int omap_aes_remove(struct platform_device *pdev)
876{
877 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
878 int i;
879
880 if (!dd)
881 return -ENODEV;
882
883 spin_lock(&list_lock);
884 list_del(&dd->list);
885 spin_unlock(&list_lock);
886
887 for (i = 0; i < ARRAY_SIZE(algs); i++)
888 crypto_unregister_alg(&algs[i]);
889
21fe9767
DK		 890 tasklet_kill(&dd->done_task);
891 tasklet_kill(&dd->queue_task);
537559a5
DK		 892 omap_aes_dma_cleanup(dd);
893 iounmap(dd->io_base);
894 clk_put(dd->iclk);
895 kfree(dd);
896 dd = NULL;
897
898 return 0;
899}
900
901static struct platform_driver omap_aes_driver = {
902 .probe = omap_aes_probe,
903 .remove = omap_aes_remove,
904 .driver = {
905 .name = "omap-aes",
906 .owner = THIS_MODULE,
907 },
908};
909
910static int __init omap_aes_mod_init(void)
911{
537559a5
DK		 912 return platform_driver_register(&omap_aes_driver);
913}
914
915static void __exit omap_aes_mod_exit(void)
916{
917 platform_driver_unregister(&omap_aes_driver);
918}
919
920module_init(omap_aes_mod_init);
921module_exit(omap_aes_mod_exit);
922
923MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
924MODULE_LICENSE("GPL v2");
925MODULE_AUTHOR("Dmitry Kasatkin");
926
Linux kernel - Deliverables
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