[deliverable/linux.git] / drivers / crypto / padlock-aes.c

/* 
 * Cryptographic API.
 *
 * Support for VIA PadLock hardware crypto engine.
 *
 * Copyright (c) 2004  Michal Ludvig <michal@logix.cz>
 *
 */

#include <crypto/algapi.h>
#include <crypto/aes.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <asm/byteorder.h>
#include <asm/processor.h>
#include <asm/i387.h>
#include "padlock.h"

/*
 * Number of data blocks actually fetched for each xcrypt insn.
 * Processors with prefetch errata will fetch extra blocks.
 */
static unsigned int ecb_fetch_blocks = 2;
#define MAX_ECB_FETCH_BLOCKS (8)
#define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)

static unsigned int cbc_fetch_blocks = 1;
#define MAX_CBC_FETCH_BLOCKS (4)
#define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)

/* Control word. */
struct cword {
	unsigned int __attribute__ ((__packed__))
		rounds:4,
		algo:3,
		keygen:1,
		interm:1,
		encdec:1,
		ksize:2;
} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));

/* Whenever making any changes to the following
 * structure *make sure* you keep E, d_data
 * and cword aligned on 16 Bytes boundaries and
 * the Hardware can access 16 * 16 bytes of E and d_data
 * (only the first 15 * 16 bytes matter but the HW reads
 * more).
 */
struct aes_ctx {
	u32 E[AES_MAX_KEYLENGTH_U32]
		__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	u32 d_data[AES_MAX_KEYLENGTH_U32]
		__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	struct {
		struct cword encrypt;
		struct cword decrypt;
	} cword;
	u32 *D;
};

static DEFINE_PER_CPU(struct cword *, paes_last_cword);

/* Tells whether the ACE is capable to generate
   the extended key for a given key_len. */
static inline int
aes_hw_extkey_available(uint8_t key_len)
{
	/* TODO: We should check the actual CPU model/stepping
	         as it's possible that the capability will be
	         added in the next CPU revisions. */
	if (key_len == 16)
		return 1;
	return 0;
}

static inline struct aes_ctx *aes_ctx_common(void *ctx)
{
	unsigned long addr = (unsigned long)ctx;
	unsigned long align = PADLOCK_ALIGNMENT;

	if (align <= crypto_tfm_ctx_alignment())
		align = 1;
	return (struct aes_ctx *)ALIGN(addr, align);
}

static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
{
	return aes_ctx_common(crypto_tfm_ctx(tfm));
}

static inline struct aes_ctx *blk_aes_ctx(struct crypto_blkcipher *tfm)
{
	return aes_ctx_common(crypto_blkcipher_ctx(tfm));
}

static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
		       unsigned int key_len)
{
	struct aes_ctx *ctx = aes_ctx(tfm);
	const __le32 *key = (const __le32 *)in_key;
	u32 *flags = &tfm->crt_flags;
	struct crypto_aes_ctx gen_aes;
	int cpu;

	if (key_len % 8) {
		*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
		return -EINVAL;
	}

	/*
	 * If the hardware is capable of generating the extended key
	 * itself we must supply the plain key for both encryption
	 * and decryption.
	 */
	ctx->D = ctx->E;

	ctx->E[0] = le32_to_cpu(key[0]);
	ctx->E[1] = le32_to_cpu(key[1]);
	ctx->E[2] = le32_to_cpu(key[2]);
	ctx->E[3] = le32_to_cpu(key[3]);

	/* Prepare control words. */
	memset(&ctx->cword, 0, sizeof(ctx->cword));

	ctx->cword.decrypt.encdec = 1;
	ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
	ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
	ctx->cword.encrypt.ksize = (key_len - 16) / 8;
	ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;

	/* Don't generate extended keys if the hardware can do it. */
	if (aes_hw_extkey_available(key_len))
		goto ok;

	ctx->D = ctx->d_data;
	ctx->cword.encrypt.keygen = 1;
	ctx->cword.decrypt.keygen = 1;

	if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
		*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
		return -EINVAL;
	}

	memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
	memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);

ok:
	for_each_online_cpu(cpu)
		if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) ||
		    &ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
			per_cpu(paes_last_cword, cpu) = NULL;

	return 0;
}

/* ====== Encryption/decryption routines ====== */

/* These are the real call to PadLock. */
static inline void padlock_reset_key(struct cword *cword)
{
	int cpu = raw_smp_processor_id();

	if (cword != per_cpu(paes_last_cword, cpu))
#ifndef CONFIG_X86_64
		asm volatile ("pushfl; popfl");
#else
		asm volatile ("pushfq; popfq");
#endif
}

static inline void padlock_store_cword(struct cword *cword)
{
	per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
}

/*
 * While the padlock instructions don't use FP/SSE registers, they
 * generate a spurious DNA fault when cr0.ts is '1'. These instructions
 * should be used only inside the irq_ts_save/restore() context
 */

static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key,
				  struct cword *control_word, int count)
{
	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
		      : "+S"(input), "+D"(output)
		      : "d"(control_word), "b"(key), "c"(count));
}

static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key,
				 u8 *iv, struct cword *control_word, int count)
{
	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
		      : "+S" (input), "+D" (output), "+a" (iv)
		      : "d" (control_word), "b" (key), "c" (count));
	return iv;
}

static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key,
			   struct cword *cword, int count)
{
	/*
	 * Padlock prefetches extra data so we must provide mapped input buffers.
	 * Assume there are at least 16 bytes of stack already in use.
	 */
	u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	rep_xcrypt_ecb(tmp, out, key, cword, count);
}

static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key,
			   u8 *iv, struct cword *cword, int count)
{
	/*
	 * Padlock prefetches extra data so we must provide mapped input buffers.
	 * Assume there are at least 16 bytes of stack already in use.
	 */
	u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
}

static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key,
			     struct cword *cword, int count)
{
	/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
	 * We could avoid some copying here but it's probably not worth it.
	 */
	if (unlikely(((unsigned long)in & ~PAGE_MASK) + ecb_fetch_bytes > PAGE_SIZE)) {
		ecb_crypt_copy(in, out, key, cword, count);
		return;
	}

	rep_xcrypt_ecb(in, out, key, cword, count);
}

static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key,
			    u8 *iv, struct cword *cword, int count)
{
	/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
	if (unlikely(((unsigned long)in & ~PAGE_MASK) + cbc_fetch_bytes > PAGE_SIZE))
		return cbc_crypt_copy(in, out, key, iv, cword, count);

	return rep_xcrypt_cbc(in, out, key, iv, cword, count);
}

static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
				      void *control_word, u32 count)
{
	u32 initial = count & (ecb_fetch_blocks - 1);

	if (count < ecb_fetch_blocks) {
		ecb_crypt(input, output, key, control_word, count);
		return;
	}

	if (initial)
		asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
			      : "+S"(input), "+D"(output)
			      : "d"(control_word), "b"(key), "c"(initial));

	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
		      : "+S"(input), "+D"(output)
		      : "d"(control_word), "b"(key), "c"(count - initial));
}

static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
				     u8 *iv, void *control_word, u32 count)
{
	u32 initial = count & (cbc_fetch_blocks - 1);

	if (count < cbc_fetch_blocks)
		return cbc_crypt(input, output, key, iv, control_word, count);

	if (initial)
		asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
			      : "+S" (input), "+D" (output), "+a" (iv)
			      : "d" (control_word), "b" (key), "c" (count));

	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
		      : "+S" (input), "+D" (output), "+a" (iv)
		      : "d" (control_word), "b" (key), "c" (count-initial));
	return iv;
}

static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
{
	struct aes_ctx *ctx = aes_ctx(tfm);
	int ts_state;

	padlock_reset_key(&ctx->cword.encrypt);
	ts_state = irq_ts_save();
	ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
	irq_ts_restore(ts_state);
	padlock_store_cword(&ctx->cword.encrypt);
}

static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
{
	struct aes_ctx *ctx = aes_ctx(tfm);
	int ts_state;

	padlock_reset_key(&ctx->cword.encrypt);
	ts_state = irq_ts_save();
	ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
	irq_ts_restore(ts_state);
	padlock_store_cword(&ctx->cword.encrypt);
}

static struct crypto_alg aes_alg = {
	.cra_name		=	"aes",
	.cra_driver_name	=	"aes-padlock",
	.cra_priority		=	PADLOCK_CRA_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_CIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_module		=	THIS_MODULE,
	.cra_list		=	LIST_HEAD_INIT(aes_alg.cra_list),
	.cra_u			=	{
		.cipher = {
			.cia_min_keysize	=	AES_MIN_KEY_SIZE,
			.cia_max_keysize	=	AES_MAX_KEY_SIZE,
			.cia_setkey	   	= 	aes_set_key,
			.cia_encrypt	 	=	aes_encrypt,
			.cia_decrypt	  	=	aes_decrypt,
		}
	}
};

static int ecb_aes_encrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;
	int ts_state;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	ts_state = irq_ts_save();
	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->E, &ctx->cword.encrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}
	irq_ts_restore(ts_state);

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static int ecb_aes_decrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;
	int ts_state;

	padlock_reset_key(&ctx->cword.decrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	ts_state = irq_ts_save();
	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->D, &ctx->cword.decrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}
	irq_ts_restore(ts_state);

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static struct crypto_alg ecb_aes_alg = {
	.cra_name		=	"ecb(aes)",
	.cra_driver_name	=	"ecb-aes-padlock",
	.cra_priority		=	PADLOCK_COMPOSITE_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_BLKCIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_type		=	&crypto_blkcipher_type,
	.cra_module		=	THIS_MODULE,
	.cra_list		=	LIST_HEAD_INIT(ecb_aes_alg.cra_list),
	.cra_u			=	{
		.blkcipher = {
			.min_keysize		=	AES_MIN_KEY_SIZE,
			.max_keysize		=	AES_MAX_KEY_SIZE,
			.setkey	   		= 	aes_set_key,
			.encrypt		=	ecb_aes_encrypt,
			.decrypt		=	ecb_aes_decrypt,
		}
	}
};

static int cbc_aes_encrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;
	int ts_state;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	ts_state = irq_ts_save();
	while ((nbytes = walk.nbytes)) {
		u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
					    walk.dst.virt.addr, ctx->E,
					    walk.iv, &ctx->cword.encrypt,
					    nbytes / AES_BLOCK_SIZE);
		memcpy(walk.iv, iv, AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}
	irq_ts_restore(ts_state);

	padlock_store_cword(&ctx->cword.decrypt);

	return err;
}

static int cbc_aes_decrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;
	int ts_state;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	ts_state = irq_ts_save();
	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->D, walk.iv, &ctx->cword.decrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}

	irq_ts_restore(ts_state);

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static struct crypto_alg cbc_aes_alg = {
	.cra_name		=	"cbc(aes)",
	.cra_driver_name	=	"cbc-aes-padlock",
	.cra_priority		=	PADLOCK_COMPOSITE_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_BLKCIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_type		=	&crypto_blkcipher_type,
	.cra_module		=	THIS_MODULE,
	.cra_list		=	LIST_HEAD_INIT(cbc_aes_alg.cra_list),
	.cra_u			=	{
		.blkcipher = {
			.min_keysize		=	AES_MIN_KEY_SIZE,
			.max_keysize		=	AES_MAX_KEY_SIZE,
			.ivsize			=	AES_BLOCK_SIZE,
			.setkey	   		= 	aes_set_key,
			.encrypt		=	cbc_aes_encrypt,
			.decrypt		=	cbc_aes_decrypt,
		}
	}
};

static int __init padlock_init(void)
{
	int ret;
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (!cpu_has_xcrypt) {
		printk(KERN_NOTICE PFX "VIA PadLock not detected.\n");
		return -ENODEV;
	}

	if (!cpu_has_xcrypt_enabled) {
		printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
		return -ENODEV;
	}

	if ((ret = crypto_register_alg(&aes_alg)))
		goto aes_err;

	if ((ret = crypto_register_alg(&ecb_aes_alg)))
		goto ecb_aes_err;

	if ((ret = crypto_register_alg(&cbc_aes_alg)))
		goto cbc_aes_err;

	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");

	if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
		ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
		cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
		printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
	}

out:
	return ret;

cbc_aes_err:
	crypto_unregister_alg(&ecb_aes_alg);
ecb_aes_err:
	crypto_unregister_alg(&aes_alg);
aes_err:
	printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
	goto out;
}

static void __exit padlock_fini(void)
{
	crypto_unregister_alg(&cbc_aes_alg);
	crypto_unregister_alg(&ecb_aes_alg);
	crypto_unregister_alg(&aes_alg);
}

module_init(padlock_init);
module_exit(padlock_fini);

MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Ludvig");

MODULE_ALIAS("aes");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Cryptographic API.
	3	*
	4	* Support for VIA PadLock hardware crypto engine.
	5	*
	6	* Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
	7	*
1da177e4 LT	8	*/
1da177e4 LT	9
28ce728a	10	#include <crypto/algapi.h>
89e12654	11	#include <crypto/aes.h>
1da177e4 LT	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/types.h>
	15	#include <linux/errno.h>
1da177e4	16	#include <linux/interrupt.h>
6789b2dc	17	#include <linux/kernel.h>
420a4b20 HX	18	#include <linux/percpu.h>
420a4b20 HX	19	#include <linux/smp.h>
1da177e4	20	#include <asm/byteorder.h>
a76c1c23	21	#include <asm/processor.h>
e4914012	22	#include <asm/i387.h>
1da177e4 LT	23	#include "padlock.h"
1da177e4 LT	24
8d8409f7 CE	25	/*
	26	* Number of data blocks actually fetched for each xcrypt insn.
	27	* Processors with prefetch errata will fetch extra blocks.
	28	*/
a76c1c23	29	static unsigned int ecb_fetch_blocks = 2;
8d8409f7	30	#define MAX_ECB_FETCH_BLOCKS (8)
a76c1c23	31	#define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)
8d8409f7 CE	32
	33	static unsigned int cbc_fetch_blocks = 1;
	34	#define MAX_CBC_FETCH_BLOCKS (4)
a76c1c23 CE	35	#define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)
a76c1c23 CE	36
ccc17c34 ML	37	/* Control word. */
	38	struct cword {
	39	unsigned int __attribute__ ((__packed__))
	40	rounds:4,
	41	algo:3,
	42	keygen:1,
	43	interm:1,
	44	encdec:1,
	45	ksize:2;
	46	} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	47
cc08632f ML	48	/* Whenever making any changes to the following
cc08632f ML	49	* structure make sure you keep E, d_data
7dc748e4 SS	50	* and cword aligned on 16 Bytes boundaries and
	51	* the Hardware can access 16 * 16 bytes of E and d_data
	52	* (only the first 15 * 16 bytes matter but the HW reads
	53	* more).
	54	*/
1da177e4	55	struct aes_ctx {
7dc748e4 SS	56	u32 E[AES_MAX_KEYLENGTH_U32]
	57	__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	58	u32 d_data[AES_MAX_KEYLENGTH_U32]
	59	__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
6789b2dc HX	60	struct {
	61	struct cword encrypt;
	62	struct cword decrypt;
	63	} cword;
82062c72	64	u32 *D;
1da177e4 LT	65	};
1da177e4 LT	66
390dfd95	67	static DEFINE_PER_CPU(struct cword *, paes_last_cword);
420a4b20	68
1da177e4 LT	69	/* Tells whether the ACE is capable to generate
	70	the extended key for a given key_len. */
	71	static inline int
	72	aes_hw_extkey_available(uint8_t key_len)
	73	{
	74	/* TODO: We should check the actual CPU model/stepping
	75	as it's possible that the capability will be
	76	added in the next CPU revisions. */
	77	if (key_len == 16)
	78	return 1;
	79	return 0;
	80	}
	81
28ce728a	82	static inline struct aes_ctx aes_ctx_common(void ctx)
6789b2dc	83	{
28ce728a	84	unsigned long addr = (unsigned long)ctx;
f10b7897 HX	85	unsigned long align = PADLOCK_ALIGNMENT;
	86
	87	if (align <= crypto_tfm_ctx_alignment())
	88	align = 1;
6c2bb98b	89	return (struct aes_ctx *)ALIGN(addr, align);
6789b2dc HX	90	}
6789b2dc HX	91
28ce728a HX	92	static inline struct aes_ctx aes_ctx(struct crypto_tfm tfm)
	93	{
	94	return aes_ctx_common(crypto_tfm_ctx(tfm));
	95	}
	96
	97	static inline struct aes_ctx blk_aes_ctx(struct crypto_blkcipher tfm)
	98	{
	99	return aes_ctx_common(crypto_blkcipher_ctx(tfm));
	100	}
	101
6c2bb98b	102	static int aes_set_key(struct crypto_tfm tfm, const u8 in_key,
560c06ae	103	unsigned int key_len)
1da177e4	104	{
6c2bb98b	105	struct aes_ctx *ctx = aes_ctx(tfm);
06ace7a9	106	const __le32 key = (const __le32 )in_key;
560c06ae	107	u32 *flags = &tfm->crt_flags;
7dc748e4	108	struct crypto_aes_ctx gen_aes;
420a4b20	109	int cpu;
1da177e4	110
560c06ae	111	if (key_len % 8) {
1da177e4 LT	112	*flags \|= CRYPTO_TFM_RES_BAD_KEY_LEN;
	113	return -EINVAL;
	114	}
	115
6789b2dc HX	116	/*
	117	* If the hardware is capable of generating the extended key
	118	* itself we must supply the plain key for both encryption
	119	* and decryption.
	120	*/
82062c72	121	ctx->D = ctx->E;
1da177e4	122
7dc748e4 SS	123	ctx->E[0] = le32_to_cpu(key[0]);
	124	ctx->E[1] = le32_to_cpu(key[1]);
	125	ctx->E[2] = le32_to_cpu(key[2]);
	126	ctx->E[3] = le32_to_cpu(key[3]);
1da177e4	127
6789b2dc HX	128	/* Prepare control words. */
	129	memset(&ctx->cword, 0, sizeof(ctx->cword));
	130
	131	ctx->cword.decrypt.encdec = 1;
	132	ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
	133	ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
	134	ctx->cword.encrypt.ksize = (key_len - 16) / 8;
	135	ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
	136
1da177e4 LT	137	/* Don't generate extended keys if the hardware can do it. */
1da177e4 LT	138	if (aes_hw_extkey_available(key_len))
420a4b20	139	goto ok;
1da177e4	140
6789b2dc HX	141	ctx->D = ctx->d_data;
	142	ctx->cword.encrypt.keygen = 1;
	143	ctx->cword.decrypt.keygen = 1;
	144
7dc748e4 SS	145	if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
	146	*flags \|= CRYPTO_TFM_RES_BAD_KEY_LEN;
	147	return -EINVAL;
1da177e4 LT	148	}
1da177e4 LT	149
7dc748e4 SS	150	memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
7dc748e4 SS	151	memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);
420a4b20 HX	152
	153	ok:
	154	for_each_online_cpu(cpu)
390dfd95 TH	155	if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) \|\|
	156	&ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
	157	per_cpu(paes_last_cword, cpu) = NULL;
420a4b20	158
1da177e4 LT	159	return 0;
	160	}
	161
	162	/* ====== Encryption/decryption routines ====== */
	163
28e8c3ad	164	/* These are the real call to PadLock. */
420a4b20 HX	165	static inline void padlock_reset_key(struct cword *cword)
	166	{
	167	int cpu = raw_smp_processor_id();
	168
390dfd95	169	if (cword != per_cpu(paes_last_cword, cpu))
d1c8b0a7	170	#ifndef CONFIG_X86_64
420a4b20	171	asm volatile ("pushfl; popfl");
d1c8b0a7 SAS	172	#else
	173	asm volatile ("pushfq; popfq");
	174	#endif
420a4b20 HX	175	}
	176
	177	static inline void padlock_store_cword(struct cword *cword)
866cd902	178	{
390dfd95	179	per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
866cd902 HX	180	}
866cd902 HX	181
e4914012 SS	182	/*
	183	* While the padlock instructions don't use FP/SSE registers, they
	184	* generate a spurious DNA fault when cr0.ts is '1'. These instructions
	185	* should be used only inside the irq_ts_save/restore() context
	186	*/
	187
8d8409f7	188	static inline void rep_xcrypt_ecb(const u8 input, u8 output, void *key,
a76c1c23	189	struct cword *control_word, int count)
d4a7dd8e HX	190	{
	191	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
	192	: "+S"(input), "+D"(output)
a76c1c23	193	: "d"(control_word), "b"(key), "c"(count));
d4a7dd8e HX	194	}
d4a7dd8e HX	195
8d8409f7 CE	196	static inline u8 rep_xcrypt_cbc(const u8 input, u8 output, void key,
	197	u8 iv, struct cword control_word, int count)
	198	{
	199	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
	200	: "+S" (input), "+D" (output), "+a" (iv)
	201	: "d" (control_word), "b" (key), "c" (count));
	202	return iv;
	203	}
	204
	205	static void ecb_crypt_copy(const u8 in, u8 out, u32 *key,
a76c1c23	206	struct cword *cword, int count)
d4a7dd8e	207	{
a76c1c23 CE	208	/*
	209	* Padlock prefetches extra data so we must provide mapped input buffers.
	210	* Assume there are at least 16 bytes of stack already in use.
	211	*/
8d8409f7	212	u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
490fe3f0	213	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
d4a7dd8e	214
a76c1c23	215	memcpy(tmp, in, count * AES_BLOCK_SIZE);
8d8409f7	216	rep_xcrypt_ecb(tmp, out, key, cword, count);
d4a7dd8e HX	217	}
d4a7dd8e HX	218
8d8409f7 CE	219	static u8 cbc_crypt_copy(const u8 in, u8 out, u32 key,
	220	u8 iv, struct cword cword, int count)
	221	{
	222	/*
	223	* Padlock prefetches extra data so we must provide mapped input buffers.
	224	* Assume there are at least 16 bytes of stack already in use.
	225	*/
	226	u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	227	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	228
	229	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	230	return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
	231	}
	232
	233	static inline void ecb_crypt(const u8 in, u8 out, u32 *key,
a76c1c23	234	struct cword *cword, int count)
d4a7dd8e	235	{
a76c1c23 CE	236	/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
	237	* We could avoid some copying here but it's probably not worth it.
	238	*/
e8edb3cb	239	if (unlikely(((unsigned long)in & ~PAGE_MASK) + ecb_fetch_bytes > PAGE_SIZE)) {
8d8409f7	240	ecb_crypt_copy(in, out, key, cword, count);
d4a7dd8e HX	241	return;
	242	}
	243
8d8409f7 CE	244	rep_xcrypt_ecb(in, out, key, cword, count);
	245	}
	246
	247	static inline u8 cbc_crypt(const u8 in, u8 out, u32 key,
	248	u8 iv, struct cword cword, int count)
	249	{
	250	/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
e8edb3cb	251	if (unlikely(((unsigned long)in & ~PAGE_MASK) + cbc_fetch_bytes > PAGE_SIZE))
8d8409f7 CE	252	return cbc_crypt_copy(in, out, key, iv, cword, count);
	253
	254	return rep_xcrypt_cbc(in, out, key, iv, cword, count);
d4a7dd8e HX	255	}
d4a7dd8e HX	256
6789b2dc HX	257	static inline void padlock_xcrypt_ecb(const u8 input, u8 output, void *key,
6789b2dc HX	258	void *control_word, u32 count)
1da177e4	259	{
a76c1c23 CE	260	u32 initial = count & (ecb_fetch_blocks - 1);
	261
	262	if (count < ecb_fetch_blocks) {
8d8409f7	263	ecb_crypt(input, output, key, control_word, count);
d4a7dd8e HX	264	return;
	265	}
	266
a76c1c23 CE	267	if (initial)
	268	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
	269	: "+S"(input), "+D"(output)
	270	: "d"(control_word), "b"(key), "c"(initial));
	271
	272	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
1da177e4	273	: "+S"(input), "+D"(output)
a76c1c23	274	: "d"(control_word), "b"(key), "c"(count - initial));
1da177e4 LT	275	}
1da177e4 LT	276
476df259 HX	277	static inline u8 padlock_xcrypt_cbc(const u8 input, u8 output, void key,
476df259 HX	278	u8 iv, void control_word, u32 count)
28e8c3ad	279	{
8d8409f7 CE	280	u32 initial = count & (cbc_fetch_blocks - 1);
	281
	282	if (count < cbc_fetch_blocks)
	283	return cbc_crypt(input, output, key, iv, control_word, count);
	284
	285	if (initial)
	286	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
	287	: "+S" (input), "+D" (output), "+a" (iv)
	288	: "d" (control_word), "b" (key), "c" (count));
	289
	290	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
28e8c3ad	291	: "+S" (input), "+D" (output), "+a" (iv)
8d8409f7	292	: "d" (control_word), "b" (key), "c" (count-initial));
476df259	293	return iv;
28e8c3ad HX	294	}
28e8c3ad HX	295
6c2bb98b	296	static void aes_encrypt(struct crypto_tfm tfm, u8 out, const u8 *in)
1da177e4	297	{
6c2bb98b	298	struct aes_ctx *ctx = aes_ctx(tfm);
e4914012	299	int ts_state;
e4914012	300
420a4b20	301	padlock_reset_key(&ctx->cword.encrypt);
e4914012	302	ts_state = irq_ts_save();
8d8409f7	303	ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
e4914012	304	irq_ts_restore(ts_state);
420a4b20	305	padlock_store_cword(&ctx->cword.encrypt);
1da177e4 LT	306	}
1da177e4 LT	307
6c2bb98b	308	static void aes_decrypt(struct crypto_tfm tfm, u8 out, const u8 *in)
1da177e4	309	{
6c2bb98b	310	struct aes_ctx *ctx = aes_ctx(tfm);
e4914012	311	int ts_state;
e4914012	312
420a4b20	313	padlock_reset_key(&ctx->cword.encrypt);
e4914012	314	ts_state = irq_ts_save();
8d8409f7	315	ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
e4914012	316	irq_ts_restore(ts_state);
420a4b20	317	padlock_store_cword(&ctx->cword.encrypt);
1da177e4 LT	318	}
	319
	320	static struct crypto_alg aes_alg = {
	321	.cra_name = "aes",
c8a19c91	322	.cra_driver_name = "aes-padlock",
ccc17c34	323	.cra_priority = PADLOCK_CRA_PRIORITY,
1da177e4 LT	324	.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
1da177e4 LT	325	.cra_blocksize = AES_BLOCK_SIZE,
fbdae9f3	326	.cra_ctxsize = sizeof(struct aes_ctx),
6789b2dc	327	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
1da177e4 LT	328	.cra_module = THIS_MODULE,
	329	.cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
	330	.cra_u = {
	331	.cipher = {
	332	.cia_min_keysize = AES_MIN_KEY_SIZE,
	333	.cia_max_keysize = AES_MAX_KEY_SIZE,
	334	.cia_setkey = aes_set_key,
	335	.cia_encrypt = aes_encrypt,
28e8c3ad	336	.cia_decrypt = aes_decrypt,
1da177e4 LT	337	}
	338	}
	339	};
	340
28ce728a HX	341	static int ecb_aes_encrypt(struct blkcipher_desc *desc,
	342	struct scatterlist dst, struct scatterlist src,
	343	unsigned int nbytes)
	344	{
	345	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	346	struct blkcipher_walk walk;
	347	int err;
e4914012	348	int ts_state;
28ce728a	349
420a4b20	350	padlock_reset_key(&ctx->cword.encrypt);
866cd902	351
28ce728a HX	352	blkcipher_walk_init(&walk, dst, src, nbytes);
	353	err = blkcipher_walk_virt(desc, &walk);
	354
e4914012	355	ts_state = irq_ts_save();
28ce728a HX	356	while ((nbytes = walk.nbytes)) {
	357	padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
	358	ctx->E, &ctx->cword.encrypt,
	359	nbytes / AES_BLOCK_SIZE);
	360	nbytes &= AES_BLOCK_SIZE - 1;
	361	err = blkcipher_walk_done(desc, &walk, nbytes);
	362	}
e4914012	363	irq_ts_restore(ts_state);
28ce728a	364
420a4b20 HX	365	padlock_store_cword(&ctx->cword.encrypt);
420a4b20 HX	366
28ce728a HX	367	return err;
	368	}
	369
	370	static int ecb_aes_decrypt(struct blkcipher_desc *desc,
	371	struct scatterlist dst, struct scatterlist src,
	372	unsigned int nbytes)
	373	{
	374	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	375	struct blkcipher_walk walk;
	376	int err;
e4914012	377	int ts_state;
28ce728a	378
420a4b20	379	padlock_reset_key(&ctx->cword.decrypt);
866cd902	380
28ce728a HX	381	blkcipher_walk_init(&walk, dst, src, nbytes);
	382	err = blkcipher_walk_virt(desc, &walk);
	383
e4914012	384	ts_state = irq_ts_save();
28ce728a HX	385	while ((nbytes = walk.nbytes)) {
	386	padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
	387	ctx->D, &ctx->cword.decrypt,
	388	nbytes / AES_BLOCK_SIZE);
	389	nbytes &= AES_BLOCK_SIZE - 1;
	390	err = blkcipher_walk_done(desc, &walk, nbytes);
	391	}
e4914012	392	irq_ts_restore(ts_state);
420a4b20 HX	393
	394	padlock_store_cword(&ctx->cword.encrypt);
	395
28ce728a HX	396	return err;
	397	}
	398
	399	static struct crypto_alg ecb_aes_alg = {
	400	.cra_name = "ecb(aes)",
	401	.cra_driver_name = "ecb-aes-padlock",
	402	.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
	403	.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
	404	.cra_blocksize = AES_BLOCK_SIZE,
	405	.cra_ctxsize = sizeof(struct aes_ctx),
	406	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
	407	.cra_type = &crypto_blkcipher_type,
	408	.cra_module = THIS_MODULE,
	409	.cra_list = LIST_HEAD_INIT(ecb_aes_alg.cra_list),
	410	.cra_u = {
	411	.blkcipher = {
	412	.min_keysize = AES_MIN_KEY_SIZE,
	413	.max_keysize = AES_MAX_KEY_SIZE,
	414	.setkey = aes_set_key,
	415	.encrypt = ecb_aes_encrypt,
	416	.decrypt = ecb_aes_decrypt,
	417	}
	418	}
	419	};
	420
	421	static int cbc_aes_encrypt(struct blkcipher_desc *desc,
	422	struct scatterlist dst, struct scatterlist src,
	423	unsigned int nbytes)
	424	{
	425	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	426	struct blkcipher_walk walk;
	427	int err;
e4914012	428	int ts_state;
28ce728a	429
420a4b20	430	padlock_reset_key(&ctx->cword.encrypt);
866cd902	431
28ce728a HX	432	blkcipher_walk_init(&walk, dst, src, nbytes);
	433	err = blkcipher_walk_virt(desc, &walk);
	434
e4914012	435	ts_state = irq_ts_save();
28ce728a HX	436	while ((nbytes = walk.nbytes)) {
	437	u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
	438	walk.dst.virt.addr, ctx->E,
	439	walk.iv, &ctx->cword.encrypt,
	440	nbytes / AES_BLOCK_SIZE);
	441	memcpy(walk.iv, iv, AES_BLOCK_SIZE);
	442	nbytes &= AES_BLOCK_SIZE - 1;
	443	err = blkcipher_walk_done(desc, &walk, nbytes);
	444	}
e4914012	445	irq_ts_restore(ts_state);
28ce728a	446
420a4b20 HX	447	padlock_store_cword(&ctx->cword.decrypt);
420a4b20 HX	448
28ce728a HX	449	return err;
	450	}
	451
	452	static int cbc_aes_decrypt(struct blkcipher_desc *desc,
	453	struct scatterlist dst, struct scatterlist src,
	454	unsigned int nbytes)
	455	{
	456	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	457	struct blkcipher_walk walk;
	458	int err;
e4914012	459	int ts_state;
28ce728a	460
420a4b20	461	padlock_reset_key(&ctx->cword.encrypt);
866cd902	462
28ce728a HX	463	blkcipher_walk_init(&walk, dst, src, nbytes);
	464	err = blkcipher_walk_virt(desc, &walk);
	465
e4914012	466	ts_state = irq_ts_save();
28ce728a HX	467	while ((nbytes = walk.nbytes)) {
	468	padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
	469	ctx->D, walk.iv, &ctx->cword.decrypt,
	470	nbytes / AES_BLOCK_SIZE);
	471	nbytes &= AES_BLOCK_SIZE - 1;
	472	err = blkcipher_walk_done(desc, &walk, nbytes);
	473	}
	474
e4914012	475	irq_ts_restore(ts_state);
420a4b20 HX	476
	477	padlock_store_cword(&ctx->cword.encrypt);
	478
28ce728a HX	479	return err;
	480	}
	481
	482	static struct crypto_alg cbc_aes_alg = {
	483	.cra_name = "cbc(aes)",
	484	.cra_driver_name = "cbc-aes-padlock",
	485	.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
	486	.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
	487	.cra_blocksize = AES_BLOCK_SIZE,
	488	.cra_ctxsize = sizeof(struct aes_ctx),
	489	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
	490	.cra_type = &crypto_blkcipher_type,
	491	.cra_module = THIS_MODULE,
	492	.cra_list = LIST_HEAD_INIT(cbc_aes_alg.cra_list),
	493	.cra_u = {
	494	.blkcipher = {
	495	.min_keysize = AES_MIN_KEY_SIZE,
	496	.max_keysize = AES_MAX_KEY_SIZE,
	497	.ivsize = AES_BLOCK_SIZE,
	498	.setkey = aes_set_key,
	499	.encrypt = cbc_aes_encrypt,
	500	.decrypt = cbc_aes_decrypt,
	501	}
	502	}
	503	};
	504
1191f0a4	505	static int __init padlock_init(void)
1da177e4	506	{
1191f0a4	507	int ret;
a76c1c23	508	struct cpuinfo_x86 *c = &cpu_data(0);
1191f0a4 ML	509
1191f0a4 ML	510	if (!cpu_has_xcrypt) {
b43e726b	511	printk(KERN_NOTICE PFX "VIA PadLock not detected.\n");
1191f0a4 ML	512	return -ENODEV;
	513	}
	514
	515	if (!cpu_has_xcrypt_enabled) {
b43e726b	516	printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
1191f0a4 ML	517	return -ENODEV;
1191f0a4 ML	518	}
1da177e4	519
28ce728a HX	520	if ((ret = crypto_register_alg(&aes_alg)))
	521	goto aes_err;
	522
	523	if ((ret = crypto_register_alg(&ecb_aes_alg)))
	524	goto ecb_aes_err;
	525
	526	if ((ret = crypto_register_alg(&cbc_aes_alg)))
	527	goto cbc_aes_err;
1191f0a4 ML	528
	529	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
	530
a76c1c23	531	if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
8d8409f7 CE	532	ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
8d8409f7 CE	533	cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
a76c1c23 CE	534	printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
	535	}
	536
28ce728a	537	out:
1191f0a4	538	return ret;
28ce728a HX	539
	540	cbc_aes_err:
	541	crypto_unregister_alg(&ecb_aes_alg);
	542	ecb_aes_err:
	543	crypto_unregister_alg(&aes_alg);
	544	aes_err:
	545	printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
	546	goto out;
1da177e4 LT	547	}
1da177e4 LT	548
1191f0a4	549	static void __exit padlock_fini(void)
1da177e4	550	{
28ce728a HX	551	crypto_unregister_alg(&cbc_aes_alg);
28ce728a HX	552	crypto_unregister_alg(&ecb_aes_alg);
1da177e4 LT	553	crypto_unregister_alg(&aes_alg);
1da177e4 LT	554	}
1191f0a4 ML	555
	556	module_init(padlock_init);
	557	module_exit(padlock_fini);
	558
	559	MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
	560	MODULE_LICENSE("GPL");
	561	MODULE_AUTHOR("Michal Ludvig");
	562
acd246b7	563	MODULE_ALIAS("aes");