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crypto: s5p-sss - Fix use after free of copied input buffer in error path
[deliverable/linux.git] / drivers / crypto / s5p-sss.c
CommitLineData
a49e490c
VZ		 1/*
2 * Cryptographic API.
3 *
4 * Support for Samsung S5PV210 HW acceleration.
5 *
6 * Copyright (C) 2011 NetUP Inc. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 */
13
3cf9d84e
KK		 14#include <linux/clk.h>
15#include <linux/crypto.h>
16#include <linux/dma-mapping.h>
a49e490c 17#include <linux/err.h>
a49e490c 18#include <linux/errno.h>
3cf9d84e
KK		 19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
a49e490c 22#include <linux/kernel.h>
3cf9d84e
KK		 23#include <linux/module.h>
24#include <linux/of.h>
a49e490c
VZ		 25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
a49e490c 27
a49e490c 28#include <crypto/ctr.h>
3cf9d84e
KK		 29#include <crypto/aes.h>
30#include <crypto/algapi.h>
9e4a1100 31#include <crypto/scatterwalk.h>
a49e490c 32
a49e490c
VZ		 33#define _SBF(s, v) ((v) << (s))
34#define _BIT(b) _SBF(b, 1)
35
36/* Feed control registers */
37#define SSS_REG_FCINTSTAT 0x0000
38#define SSS_FCINTSTAT_BRDMAINT _BIT(3)
39#define SSS_FCINTSTAT_BTDMAINT _BIT(2)
40#define SSS_FCINTSTAT_HRDMAINT _BIT(1)
41#define SSS_FCINTSTAT_PKDMAINT _BIT(0)
42
43#define SSS_REG_FCINTENSET 0x0004
44#define SSS_FCINTENSET_BRDMAINTENSET _BIT(3)
45#define SSS_FCINTENSET_BTDMAINTENSET _BIT(2)
46#define SSS_FCINTENSET_HRDMAINTENSET _BIT(1)
47#define SSS_FCINTENSET_PKDMAINTENSET _BIT(0)
48
49#define SSS_REG_FCINTENCLR 0x0008
50#define SSS_FCINTENCLR_BRDMAINTENCLR _BIT(3)
51#define SSS_FCINTENCLR_BTDMAINTENCLR _BIT(2)
52#define SSS_FCINTENCLR_HRDMAINTENCLR _BIT(1)
53#define SSS_FCINTENCLR_PKDMAINTENCLR _BIT(0)
54
55#define SSS_REG_FCINTPEND 0x000C
56#define SSS_FCINTPEND_BRDMAINTP _BIT(3)
57#define SSS_FCINTPEND_BTDMAINTP _BIT(2)
58#define SSS_FCINTPEND_HRDMAINTP _BIT(1)
59#define SSS_FCINTPEND_PKDMAINTP _BIT(0)
60
61#define SSS_REG_FCFIFOSTAT 0x0010
62#define SSS_FCFIFOSTAT_BRFIFOFUL _BIT(7)
63#define SSS_FCFIFOSTAT_BRFIFOEMP _BIT(6)
64#define SSS_FCFIFOSTAT_BTFIFOFUL _BIT(5)
65#define SSS_FCFIFOSTAT_BTFIFOEMP _BIT(4)
66#define SSS_FCFIFOSTAT_HRFIFOFUL _BIT(3)
67#define SSS_FCFIFOSTAT_HRFIFOEMP _BIT(2)
68#define SSS_FCFIFOSTAT_PKFIFOFUL _BIT(1)
69#define SSS_FCFIFOSTAT_PKFIFOEMP _BIT(0)
70
71#define SSS_REG_FCFIFOCTRL 0x0014
72#define SSS_FCFIFOCTRL_DESSEL _BIT(2)
73#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
74#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
75#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
76
77#define SSS_REG_FCBRDMAS 0x0020
78#define SSS_REG_FCBRDMAL 0x0024
79#define SSS_REG_FCBRDMAC 0x0028
80#define SSS_FCBRDMAC_BYTESWAP _BIT(1)
81#define SSS_FCBRDMAC_FLUSH _BIT(0)
82
83#define SSS_REG_FCBTDMAS 0x0030
84#define SSS_REG_FCBTDMAL 0x0034
85#define SSS_REG_FCBTDMAC 0x0038
86#define SSS_FCBTDMAC_BYTESWAP _BIT(1)
87#define SSS_FCBTDMAC_FLUSH _BIT(0)
88
89#define SSS_REG_FCHRDMAS 0x0040
90#define SSS_REG_FCHRDMAL 0x0044
91#define SSS_REG_FCHRDMAC 0x0048
92#define SSS_FCHRDMAC_BYTESWAP _BIT(1)
93#define SSS_FCHRDMAC_FLUSH _BIT(0)
94
95#define SSS_REG_FCPKDMAS 0x0050
96#define SSS_REG_FCPKDMAL 0x0054
97#define SSS_REG_FCPKDMAC 0x0058
98#define SSS_FCPKDMAC_BYTESWAP _BIT(3)
99#define SSS_FCPKDMAC_DESCEND _BIT(2)
100#define SSS_FCPKDMAC_TRANSMIT _BIT(1)
101#define SSS_FCPKDMAC_FLUSH _BIT(0)
102
103#define SSS_REG_FCPKDMAO 0x005C
104
105/* AES registers */
89245107 106#define SSS_REG_AES_CONTROL 0x00
a49e490c
VZ		 107#define SSS_AES_BYTESWAP_DI _BIT(11)
108#define SSS_AES_BYTESWAP_DO _BIT(10)
109#define SSS_AES_BYTESWAP_IV _BIT(9)
110#define SSS_AES_BYTESWAP_CNT _BIT(8)
111#define SSS_AES_BYTESWAP_KEY _BIT(7)
112#define SSS_AES_KEY_CHANGE_MODE _BIT(6)
113#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
114#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
115#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
116#define SSS_AES_FIFO_MODE _BIT(3)
117#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
118#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
119#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
120#define SSS_AES_MODE_DECRYPT _BIT(0)
121
89245107 122#define SSS_REG_AES_STATUS 0x04
a49e490c
VZ		 123#define SSS_AES_BUSY _BIT(2)
124#define SSS_AES_INPUT_READY _BIT(1)
125#define SSS_AES_OUTPUT_READY _BIT(0)
126
89245107
NKC		 127#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
128#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
129#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
130#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
131#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
a49e490c
VZ		 132
133#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
134#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
135#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
136
89245107
NKC		 137#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
138#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
139 SSS_AES_REG(dev, reg))
140
a49e490c
VZ		 141/* HW engine modes */
142#define FLAGS_AES_DECRYPT _BIT(0)
143#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
144#define FLAGS_AES_CBC _SBF(1, 0x01)
145#define FLAGS_AES_CTR _SBF(1, 0x02)
146
147#define AES_KEY_LEN 16
148#define CRYPTO_QUEUE_LEN 1
149
89245107
NKC		 150/**
151 * struct samsung_aes_variant - platform specific SSS driver data
152 * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
153 * @aes_offset: AES register offset from SSS module's base.
154 *
155 * Specifies platform specific configuration of SSS module.
156 * Note: A structure for driver specific platform data is used for future
157 * expansion of its usage.
158 */
159struct samsung_aes_variant {
160 bool has_hash_irq;
161 unsigned int aes_offset;
162};
163
a49e490c
VZ		 164struct s5p_aes_reqctx {
165 unsigned long mode;
166};
167
168struct s5p_aes_ctx {
169 struct s5p_aes_dev *dev;
170
171 uint8_t aes_key[AES_MAX_KEY_SIZE];
172 uint8_t nonce[CTR_RFC3686_NONCE_SIZE];
173 int keylen;
174};
175
176struct s5p_aes_dev {
177 struct device *dev;
178 struct clk *clk;
179 void __iomem *ioaddr;
89245107 180 void __iomem *aes_ioaddr;
a49e490c
VZ		 181 int irq_hash;
182 int irq_fc;
183
184 struct ablkcipher_request *req;
185 struct s5p_aes_ctx *ctx;
186 struct scatterlist *sg_src;
187 struct scatterlist *sg_dst;
188
9e4a1100
KK		 189 /* In case of unaligned access: */
190 struct scatterlist *sg_src_cpy;
191 struct scatterlist *sg_dst_cpy;
192
a49e490c
VZ		 193 struct tasklet_struct tasklet;
194 struct crypto_queue queue;
195 bool busy;
196 spinlock_t lock;
89245107
NKC		 197
198 struct samsung_aes_variant *variant;
a49e490c
VZ		 199};
200
201static struct s5p_aes_dev *s5p_dev;
202
89245107
NKC		 203static const struct samsung_aes_variant s5p_aes_data = {
204 .has_hash_irq = true,
205 .aes_offset = 0x4000,
206};
207
208static const struct samsung_aes_variant exynos_aes_data = {
209 .has_hash_irq = false,
210 .aes_offset = 0x200,
211};
212
6b9f16e6 213static const struct of_device_id s5p_sss_dt_match[] = {
89245107
NKC		 214 {
215 .compatible = "samsung,s5pv210-secss",
216 .data = &s5p_aes_data,
217 },
218 {
219 .compatible = "samsung,exynos4210-secss",
220 .data = &exynos_aes_data,
221 },
6b9f16e6
NKC		 222 { },
223};
224MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
225
89245107
NKC		 226static inline struct samsung_aes_variant *find_s5p_sss_version
227 (struct platform_device *pdev)
228{
229 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
230 const struct of_device_id *match;
313becd1 231
89245107
NKC		 232 match = of_match_node(s5p_sss_dt_match,
233 pdev->dev.of_node);
234 return (struct samsung_aes_variant *)match->data;
235 }
236 return (struct samsung_aes_variant *)
237 platform_get_device_id(pdev)->driver_data;
238}
239
a49e490c
VZ		 240static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
241{
242 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
243 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
244}
245
246static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
247{
248 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
249 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
250}
251
9e4a1100
KK		 252static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg)
253{
254 int len;
255
256 if (!*sg)
257 return;
258
259 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
260 free_pages((unsigned long)sg_virt(*sg), get_order(len));
261
262 kfree(*sg);
263 *sg = NULL;
264}
265
266static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg,
267 unsigned int nbytes, int out)
268{
269 struct scatter_walk walk;
270
271 if (!nbytes)
272 return;
273
274 scatterwalk_start(&walk, sg);
275 scatterwalk_copychunks(buf, &walk, nbytes, out);
276 scatterwalk_done(&walk, out, 0);
277}
278
a49e490c
VZ		 279static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)
280{
9e4a1100
KK		 281 if (dev->sg_dst_cpy) {
282 dev_dbg(dev->dev,
283 "Copying %d bytes of output data back to original place\n",
284 dev->req->nbytes);
285 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst,
286 dev->req->nbytes, 1);
287 }
288 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
289 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
290
a49e490c
VZ		 291 /* holding a lock outside */
292 dev->req->base.complete(&dev->req->base, err);
293 dev->busy = false;
294}
295
296static void s5p_unset_outdata(struct s5p_aes_dev *dev)
297{
298 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
299}
300
301static void s5p_unset_indata(struct s5p_aes_dev *dev)
302{
303 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
304}
305
9e4a1100
KK		 306static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src,
307 struct scatterlist **dst)
308{
309 void *pages;
310 int len;
311
312 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC);
313 if (!*dst)
314 return -ENOMEM;
315
316 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
317 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len));
318 if (!pages) {
319 kfree(*dst);
320 *dst = NULL;
321 return -ENOMEM;
322 }
323
324 s5p_sg_copy_buf(pages, src, dev->req->nbytes, 0);
325
326 sg_init_table(*dst, 1);
327 sg_set_buf(*dst, pages, len);
328
329 return 0;
330}
331
a49e490c
VZ		 332static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
333{
334 int err;
335
a49e490c
VZ		 336 if (!sg_dma_len(sg)) {
337 err = -EINVAL;
338 goto exit;
339 }
340
341 err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE);
342 if (!err) {
343 err = -ENOMEM;
344 goto exit;
345 }
346
347 dev->sg_dst = sg;
348 err = 0;
349
119c3ab4 350exit:
a49e490c
VZ		 351 return err;
352}
353
354static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
355{
356 int err;
357
a49e490c
VZ		 358 if (!sg_dma_len(sg)) {
359 err = -EINVAL;
360 goto exit;
361 }
362
363 err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE);
364 if (!err) {
365 err = -ENOMEM;
366 goto exit;
367 }
368
369 dev->sg_src = sg;
370 err = 0;
371
119c3ab4 372exit:
a49e490c
VZ		 373 return err;
374}
375
376static void s5p_aes_tx(struct s5p_aes_dev *dev)
377{
378 int err = 0;
379
380 s5p_unset_outdata(dev);
381
382 if (!sg_is_last(dev->sg_dst)) {
383 err = s5p_set_outdata(dev, sg_next(dev->sg_dst));
384 if (err) {
385 s5p_aes_complete(dev, err);
386 return;
387 }
388
389 s5p_set_dma_outdata(dev, dev->sg_dst);
dc5e3f19 390 } else {
a49e490c 391 s5p_aes_complete(dev, err);
dc5e3f19
NKC		 392
393 dev->busy = true;
394 tasklet_schedule(&dev->tasklet);
395 }
a49e490c
VZ		 396}
397
398static void s5p_aes_rx(struct s5p_aes_dev *dev)
399{
400 int err;
401
402 s5p_unset_indata(dev);
403
404 if (!sg_is_last(dev->sg_src)) {
405 err = s5p_set_indata(dev, sg_next(dev->sg_src));
406 if (err) {
407 s5p_aes_complete(dev, err);
408 return;
409 }
410
411 s5p_set_dma_indata(dev, dev->sg_src);
412 }
413}
414
415static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
416{
417 struct platform_device *pdev = dev_id;
418 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
419 uint32_t status;
420 unsigned long flags;
421
422 spin_lock_irqsave(&dev->lock, flags);
423
424 if (irq == dev->irq_fc) {
425 status = SSS_READ(dev, FCINTSTAT);
426 if (status & SSS_FCINTSTAT_BRDMAINT)
427 s5p_aes_rx(dev);
428 if (status & SSS_FCINTSTAT_BTDMAINT)
429 s5p_aes_tx(dev);
430
431 SSS_WRITE(dev, FCINTPEND, status);
432 }
433
434 spin_unlock_irqrestore(&dev->lock, flags);
435
436 return IRQ_HANDLED;
437}
438
439static void s5p_set_aes(struct s5p_aes_dev *dev,
440 uint8_t *key, uint8_t *iv, unsigned int keylen)
441{
442 void __iomem *keystart;
443
8f9702aa 444 if (iv)
1e3012d0 445 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
a49e490c
VZ		 446
447 if (keylen == AES_KEYSIZE_256)
89245107 448 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
a49e490c 449 else if (keylen == AES_KEYSIZE_192)
89245107 450 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
a49e490c 451 else
89245107 452 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
a49e490c 453
1e3012d0 454 memcpy_toio(keystart, key, keylen);
a49e490c
VZ		 455}
456
9e4a1100
KK		 457static bool s5p_is_sg_aligned(struct scatterlist *sg)
458{
459 while (sg) {
460 if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE))
461 return false;
462 sg = sg_next(sg);
463 }
464
465 return true;
466}
467
468static int s5p_set_indata_start(struct s5p_aes_dev *dev,
469 struct ablkcipher_request *req)
470{
471 struct scatterlist *sg;
472 int err;
473
474 dev->sg_src_cpy = NULL;
475 sg = req->src;
476 if (!s5p_is_sg_aligned(sg)) {
477 dev_dbg(dev->dev,
478 "At least one unaligned source scatter list, making a copy\n");
479 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy);
480 if (err)
481 return err;
482
483 sg = dev->sg_src_cpy;
484 }
485
486 err = s5p_set_indata(dev, sg);
487 if (err) {
488 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
489 return err;
490 }
491
492 return 0;
493}
494
495static int s5p_set_outdata_start(struct s5p_aes_dev *dev,
496 struct ablkcipher_request *req)
497{
498 struct scatterlist *sg;
499 int err;
500
501 dev->sg_dst_cpy = NULL;
502 sg = req->dst;
503 if (!s5p_is_sg_aligned(sg)) {
504 dev_dbg(dev->dev,
505 "At least one unaligned dest scatter list, making a copy\n");
506 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy);
507 if (err)
508 return err;
509
510 sg = dev->sg_dst_cpy;
511 }
512
513 err = s5p_set_outdata(dev, sg);
514 if (err) {
515 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
516 return err;
517 }
518
519 return 0;
520}
521
a49e490c
VZ		 522static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
523{
524 struct ablkcipher_request *req = dev->req;
a49e490c
VZ		 525 uint32_t aes_control;
526 int err;
527 unsigned long flags;
528
529 aes_control = SSS_AES_KEY_CHANGE_MODE;
530 if (mode & FLAGS_AES_DECRYPT)
531 aes_control |= SSS_AES_MODE_DECRYPT;
532
533 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC)
534 aes_control |= SSS_AES_CHAIN_MODE_CBC;
535 else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR)
536 aes_control |= SSS_AES_CHAIN_MODE_CTR;
537
538 if (dev->ctx->keylen == AES_KEYSIZE_192)
539 aes_control |= SSS_AES_KEY_SIZE_192;
540 else if (dev->ctx->keylen == AES_KEYSIZE_256)
541 aes_control |= SSS_AES_KEY_SIZE_256;
542
543 aes_control |= SSS_AES_FIFO_MODE;
544
545 /* as a variant it is possible to use byte swapping on DMA side */
546 aes_control |= SSS_AES_BYTESWAP_DI
547 | SSS_AES_BYTESWAP_DO
548 | SSS_AES_BYTESWAP_IV
549 | SSS_AES_BYTESWAP_KEY
550 | SSS_AES_BYTESWAP_CNT;
551
552 spin_lock_irqsave(&dev->lock, flags);
553
554 SSS_WRITE(dev, FCINTENCLR,
555 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
556 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
557
9e4a1100 558 err = s5p_set_indata_start(dev, req);
a49e490c
VZ		 559 if (err)
560 goto indata_error;
561
9e4a1100 562 err = s5p_set_outdata_start(dev, req);
a49e490c
VZ		 563 if (err)
564 goto outdata_error;
565
89245107 566 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
a49e490c
VZ		 567 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
568
9e4a1100
KK		 569 s5p_set_dma_indata(dev, dev->sg_src);
570 s5p_set_dma_outdata(dev, dev->sg_dst);
a49e490c
VZ		 571
572 SSS_WRITE(dev, FCINTENSET,
573 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
574
575 spin_unlock_irqrestore(&dev->lock, flags);
576
577 return;
578
119c3ab4 579outdata_error:
a49e490c
VZ		 580 s5p_unset_indata(dev);
581
119c3ab4 582indata_error:
a49e490c
VZ		 583 s5p_aes_complete(dev, err);
584 spin_unlock_irqrestore(&dev->lock, flags);
585}
586
587static void s5p_tasklet_cb(unsigned long data)
588{
589 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
590 struct crypto_async_request *async_req, *backlog;
591 struct s5p_aes_reqctx *reqctx;
592 unsigned long flags;
593
594 spin_lock_irqsave(&dev->lock, flags);
595 backlog = crypto_get_backlog(&dev->queue);
596 async_req = crypto_dequeue_request(&dev->queue);
a49e490c 597
dc5e3f19
NKC		 598 if (!async_req) {
599 dev->busy = false;
600 spin_unlock_irqrestore(&dev->lock, flags);
a49e490c 601 return;
dc5e3f19
NKC		 602 }
603 spin_unlock_irqrestore(&dev->lock, flags);
a49e490c
VZ		 604
605 if (backlog)
606 backlog->complete(backlog, -EINPROGRESS);
607
608 dev->req = ablkcipher_request_cast(async_req);
609 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
610 reqctx = ablkcipher_request_ctx(dev->req);
611
612 s5p_aes_crypt_start(dev, reqctx->mode);
613}
614
615static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
616 struct ablkcipher_request *req)
617{
618 unsigned long flags;
619 int err;
620
621 spin_lock_irqsave(&dev->lock, flags);
dc5e3f19 622 err = ablkcipher_enqueue_request(&dev->queue, req);
a49e490c 623 if (dev->busy) {
a49e490c
VZ		 624 spin_unlock_irqrestore(&dev->lock, flags);
625 goto exit;
626 }
627 dev->busy = true;
628
a49e490c
VZ		 629 spin_unlock_irqrestore(&dev->lock, flags);
630
631 tasklet_schedule(&dev->tasklet);
632
119c3ab4 633exit:
a49e490c
VZ		 634 return err;
635}
636
637static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
638{
639 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
640 struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
641 struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req);
642 struct s5p_aes_dev *dev = ctx->dev;
643
644 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
313becd1 645 dev_err(dev->dev, "request size is not exact amount of AES blocks\n");
a49e490c
VZ		 646 return -EINVAL;
647 }
648
649 reqctx->mode = mode;
650
651 return s5p_aes_handle_req(dev, req);
652}
653
654static int s5p_aes_setkey(struct crypto_ablkcipher *cipher,
655 const uint8_t *key, unsigned int keylen)
656{
657 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
658 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
659
660 if (keylen != AES_KEYSIZE_128 &&
661 keylen != AES_KEYSIZE_192 &&
662 keylen != AES_KEYSIZE_256)
663 return -EINVAL;
664
665 memcpy(ctx->aes_key, key, keylen);
666 ctx->keylen = keylen;
667
668 return 0;
669}
670
671static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req)
672{
673 return s5p_aes_crypt(req, 0);
674}
675
676static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req)
677{
678 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
679}
680
681static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req)
682{
683 return s5p_aes_crypt(req, FLAGS_AES_CBC);
684}
685
686static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req)
687{
688 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
689}
690
691static int s5p_aes_cra_init(struct crypto_tfm *tfm)
692{
313becd1 693 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
a49e490c
VZ		 694
695 ctx->dev = s5p_dev;
696 tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx);
697
698 return 0;
699}
700
701static struct crypto_alg algs[] = {
702 {
703 .cra_name = "ecb(aes)",
704 .cra_driver_name = "ecb-aes-s5p",
705 .cra_priority = 100,
706 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 707 CRYPTO_ALG_ASYNC |
708 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 709 .cra_blocksize = AES_BLOCK_SIZE,
710 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
711 .cra_alignmask = 0x0f,
712 .cra_type = &crypto_ablkcipher_type,
713 .cra_module = THIS_MODULE,
714 .cra_init = s5p_aes_cra_init,
715 .cra_u.ablkcipher = {
716 .min_keysize = AES_MIN_KEY_SIZE,
717 .max_keysize = AES_MAX_KEY_SIZE,
718 .setkey = s5p_aes_setkey,
719 .encrypt = s5p_aes_ecb_encrypt,
720 .decrypt = s5p_aes_ecb_decrypt,
721 }
722 },
723 {
724 .cra_name = "cbc(aes)",
725 .cra_driver_name = "cbc-aes-s5p",
726 .cra_priority = 100,
727 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 728 CRYPTO_ALG_ASYNC |
729 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 730 .cra_blocksize = AES_BLOCK_SIZE,
731 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
732 .cra_alignmask = 0x0f,
733 .cra_type = &crypto_ablkcipher_type,
734 .cra_module = THIS_MODULE,
735 .cra_init = s5p_aes_cra_init,
736 .cra_u.ablkcipher = {
737 .min_keysize = AES_MIN_KEY_SIZE,
738 .max_keysize = AES_MAX_KEY_SIZE,
739 .ivsize = AES_BLOCK_SIZE,
740 .setkey = s5p_aes_setkey,
741 .encrypt = s5p_aes_cbc_encrypt,
742 .decrypt = s5p_aes_cbc_decrypt,
743 }
744 },
745};
746
747static int s5p_aes_probe(struct platform_device *pdev)
748{
749 int i, j, err = -ENODEV;
750 struct s5p_aes_dev *pdata;
751 struct device *dev = &pdev->dev;
752 struct resource *res;
89245107 753 struct samsung_aes_variant *variant;
a49e490c
VZ		 754
755 if (s5p_dev)
756 return -EEXIST;
757
a49e490c
VZ		 758 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
759 if (!pdata)
760 return -ENOMEM;
761
0fdefe2c
JH		 762 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
763 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
764 if (IS_ERR(pdata->ioaddr))
765 return PTR_ERR(pdata->ioaddr);
a49e490c 766
89245107
NKC		 767 variant = find_s5p_sss_version(pdev);
768
5c22ba66 769 pdata->clk = devm_clk_get(dev, "secss");
a49e490c
VZ		 770 if (IS_ERR(pdata->clk)) {
771 dev_err(dev, "failed to find secss clock source\n");
772 return -ENOENT;
773 }
774
c1eb7ef2
NKC		 775 err = clk_prepare_enable(pdata->clk);
776 if (err < 0) {
777 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
778 return err;
779 }
a49e490c
VZ		 780
781 spin_lock_init(&pdata->lock);
a49e490c 782
89245107
NKC		 783 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
784
96fc70b6
NKC		 785 pdata->irq_fc = platform_get_irq(pdev, 0);
786 if (pdata->irq_fc < 0) {
787 err = pdata->irq_fc;
788 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 789 goto err_irq;
790 }
96fc70b6 791 err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
a49e490c
VZ		 792 IRQF_SHARED, pdev->name, pdev);
793 if (err < 0) {
96fc70b6 794 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 795 goto err_irq;
796 }
797
89245107
NKC		 798 if (variant->has_hash_irq) {
799 pdata->irq_hash = platform_get_irq(pdev, 1);
800 if (pdata->irq_hash < 0) {
801 err = pdata->irq_hash;
802 dev_warn(dev, "hash interrupt is not available.\n");
803 goto err_irq;
804 }
805 err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
806 IRQF_SHARED, pdev->name, pdev);
807 if (err < 0) {
808 dev_warn(dev, "hash interrupt is not available.\n");
809 goto err_irq;
810 }
a49e490c
VZ		 811 }
812
dc5e3f19 813 pdata->busy = false;
89245107 814 pdata->variant = variant;
a49e490c
VZ		 815 pdata->dev = dev;
816 platform_set_drvdata(pdev, pdata);
817 s5p_dev = pdata;
818
819 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
820 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
821
822 for (i = 0; i < ARRAY_SIZE(algs); i++) {
a49e490c
VZ		 823 err = crypto_register_alg(&algs[i]);
824 if (err)
825 goto err_algs;
826 }
827
313becd1 828 dev_info(dev, "s5p-sss driver registered\n");
a49e490c
VZ		 829
830 return 0;
831
119c3ab4 832err_algs:
a49e490c
VZ		 833 dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err);
834
835 for (j = 0; j < i; j++)
836 crypto_unregister_alg(&algs[j]);
837
838 tasklet_kill(&pdata->tasklet);
839
119c3ab4 840err_irq:
c1eb7ef2 841 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 842
843 s5p_dev = NULL;
a49e490c
VZ		 844
845 return err;
846}
847
848static int s5p_aes_remove(struct platform_device *pdev)
849{
850 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
851 int i;
852
853 if (!pdata)
854 return -ENODEV;
855
856 for (i = 0; i < ARRAY_SIZE(algs); i++)
857 crypto_unregister_alg(&algs[i]);
858
859 tasklet_kill(&pdata->tasklet);
860
c1eb7ef2 861 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 862
863 s5p_dev = NULL;
a49e490c
VZ		 864
865 return 0;
866}
867
868static struct platform_driver s5p_aes_crypto = {
869 .probe = s5p_aes_probe,
870 .remove = s5p_aes_remove,
871 .driver = {
a49e490c 872 .name = "s5p-secss",
6b9f16e6 873 .of_match_table = s5p_sss_dt_match,
a49e490c
VZ		 874 },
875};
876
741e8c2d 877module_platform_driver(s5p_aes_crypto);
a49e490c
VZ		 878
879MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
880MODULE_LICENSE("GPL v2");
881MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
Linux kernel - Deliverables
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