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crypto: mxc-scc - fix unwinding in mxc_scc_crypto_register()
[deliverable/linux.git] / drivers / crypto / s5p-sss.c
CommitLineData
a49e490c
VZ		 1/*
2 * Cryptographic API.
3 *
4 * Support for Samsung S5PV210 HW acceleration.
5 *
6 * Copyright (C) 2011 NetUP Inc. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 */
13
3cf9d84e
KK		 14#include <linux/clk.h>
15#include <linux/crypto.h>
16#include <linux/dma-mapping.h>
a49e490c 17#include <linux/err.h>
a49e490c 18#include <linux/errno.h>
3cf9d84e
KK		 19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
a49e490c 22#include <linux/kernel.h>
3cf9d84e
KK		 23#include <linux/module.h>
24#include <linux/of.h>
a49e490c
VZ		 25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
a49e490c 27
a49e490c 28#include <crypto/ctr.h>
3cf9d84e
KK		 29#include <crypto/aes.h>
30#include <crypto/algapi.h>
9e4a1100 31#include <crypto/scatterwalk.h>
a49e490c 32
a49e490c
VZ		 33#define _SBF(s, v) ((v) << (s))
34#define _BIT(b) _SBF(b, 1)
35
36/* Feed control registers */
37#define SSS_REG_FCINTSTAT 0x0000
38#define SSS_FCINTSTAT_BRDMAINT _BIT(3)
39#define SSS_FCINTSTAT_BTDMAINT _BIT(2)
40#define SSS_FCINTSTAT_HRDMAINT _BIT(1)
41#define SSS_FCINTSTAT_PKDMAINT _BIT(0)
42
43#define SSS_REG_FCINTENSET 0x0004
44#define SSS_FCINTENSET_BRDMAINTENSET _BIT(3)
45#define SSS_FCINTENSET_BTDMAINTENSET _BIT(2)
46#define SSS_FCINTENSET_HRDMAINTENSET _BIT(1)
47#define SSS_FCINTENSET_PKDMAINTENSET _BIT(0)
48
49#define SSS_REG_FCINTENCLR 0x0008
50#define SSS_FCINTENCLR_BRDMAINTENCLR _BIT(3)
51#define SSS_FCINTENCLR_BTDMAINTENCLR _BIT(2)
52#define SSS_FCINTENCLR_HRDMAINTENCLR _BIT(1)
53#define SSS_FCINTENCLR_PKDMAINTENCLR _BIT(0)
54
55#define SSS_REG_FCINTPEND 0x000C
56#define SSS_FCINTPEND_BRDMAINTP _BIT(3)
57#define SSS_FCINTPEND_BTDMAINTP _BIT(2)
58#define SSS_FCINTPEND_HRDMAINTP _BIT(1)
59#define SSS_FCINTPEND_PKDMAINTP _BIT(0)
60
61#define SSS_REG_FCFIFOSTAT 0x0010
62#define SSS_FCFIFOSTAT_BRFIFOFUL _BIT(7)
63#define SSS_FCFIFOSTAT_BRFIFOEMP _BIT(6)
64#define SSS_FCFIFOSTAT_BTFIFOFUL _BIT(5)
65#define SSS_FCFIFOSTAT_BTFIFOEMP _BIT(4)
66#define SSS_FCFIFOSTAT_HRFIFOFUL _BIT(3)
67#define SSS_FCFIFOSTAT_HRFIFOEMP _BIT(2)
68#define SSS_FCFIFOSTAT_PKFIFOFUL _BIT(1)
69#define SSS_FCFIFOSTAT_PKFIFOEMP _BIT(0)
70
71#define SSS_REG_FCFIFOCTRL 0x0014
72#define SSS_FCFIFOCTRL_DESSEL _BIT(2)
73#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
74#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
75#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
76
77#define SSS_REG_FCBRDMAS 0x0020
78#define SSS_REG_FCBRDMAL 0x0024
79#define SSS_REG_FCBRDMAC 0x0028
80#define SSS_FCBRDMAC_BYTESWAP _BIT(1)
81#define SSS_FCBRDMAC_FLUSH _BIT(0)
82
83#define SSS_REG_FCBTDMAS 0x0030
84#define SSS_REG_FCBTDMAL 0x0034
85#define SSS_REG_FCBTDMAC 0x0038
86#define SSS_FCBTDMAC_BYTESWAP _BIT(1)
87#define SSS_FCBTDMAC_FLUSH _BIT(0)
88
89#define SSS_REG_FCHRDMAS 0x0040
90#define SSS_REG_FCHRDMAL 0x0044
91#define SSS_REG_FCHRDMAC 0x0048
92#define SSS_FCHRDMAC_BYTESWAP _BIT(1)
93#define SSS_FCHRDMAC_FLUSH _BIT(0)
94
95#define SSS_REG_FCPKDMAS 0x0050
96#define SSS_REG_FCPKDMAL 0x0054
97#define SSS_REG_FCPKDMAC 0x0058
98#define SSS_FCPKDMAC_BYTESWAP _BIT(3)
99#define SSS_FCPKDMAC_DESCEND _BIT(2)
100#define SSS_FCPKDMAC_TRANSMIT _BIT(1)
101#define SSS_FCPKDMAC_FLUSH _BIT(0)
102
103#define SSS_REG_FCPKDMAO 0x005C
104
105/* AES registers */
89245107 106#define SSS_REG_AES_CONTROL 0x00
a49e490c
VZ		 107#define SSS_AES_BYTESWAP_DI _BIT(11)
108#define SSS_AES_BYTESWAP_DO _BIT(10)
109#define SSS_AES_BYTESWAP_IV _BIT(9)
110#define SSS_AES_BYTESWAP_CNT _BIT(8)
111#define SSS_AES_BYTESWAP_KEY _BIT(7)
112#define SSS_AES_KEY_CHANGE_MODE _BIT(6)
113#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
114#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
115#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
116#define SSS_AES_FIFO_MODE _BIT(3)
117#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
118#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
119#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
120#define SSS_AES_MODE_DECRYPT _BIT(0)
121
89245107 122#define SSS_REG_AES_STATUS 0x04
a49e490c
VZ		 123#define SSS_AES_BUSY _BIT(2)
124#define SSS_AES_INPUT_READY _BIT(1)
125#define SSS_AES_OUTPUT_READY _BIT(0)
126
89245107
NKC		 127#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
128#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
129#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
130#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
131#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
a49e490c
VZ		 132
133#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
134#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
135#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
136
89245107
NKC		 137#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
138#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
139 SSS_AES_REG(dev, reg))
140
a49e490c
VZ		 141/* HW engine modes */
142#define FLAGS_AES_DECRYPT _BIT(0)
143#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
144#define FLAGS_AES_CBC _SBF(1, 0x01)
145#define FLAGS_AES_CTR _SBF(1, 0x02)
146
147#define AES_KEY_LEN 16
148#define CRYPTO_QUEUE_LEN 1
149
89245107
NKC		 150/**
151 * struct samsung_aes_variant - platform specific SSS driver data
89245107
NKC		 152 * @aes_offset: AES register offset from SSS module's base.
153 *
154 * Specifies platform specific configuration of SSS module.
155 * Note: A structure for driver specific platform data is used for future
156 * expansion of its usage.
157 */
158struct samsung_aes_variant {
89245107
NKC		 159 unsigned int aes_offset;
160};
161
a49e490c
VZ		 162struct s5p_aes_reqctx {
163 unsigned long mode;
164};
165
166struct s5p_aes_ctx {
167 struct s5p_aes_dev *dev;
168
169 uint8_t aes_key[AES_MAX_KEY_SIZE];
170 uint8_t nonce[CTR_RFC3686_NONCE_SIZE];
171 int keylen;
172};
173
174struct s5p_aes_dev {
175 struct device *dev;
176 struct clk *clk;
177 void __iomem *ioaddr;
89245107 178 void __iomem *aes_ioaddr;
a49e490c
VZ		 179 int irq_fc;
180
181 struct ablkcipher_request *req;
182 struct s5p_aes_ctx *ctx;
183 struct scatterlist *sg_src;
184 struct scatterlist *sg_dst;
185
9e4a1100
KK		 186 /* In case of unaligned access: */
187 struct scatterlist *sg_src_cpy;
188 struct scatterlist *sg_dst_cpy;
189
a49e490c
VZ		 190 struct tasklet_struct tasklet;
191 struct crypto_queue queue;
192 bool busy;
193 spinlock_t lock;
89245107
NKC		 194
195 struct samsung_aes_variant *variant;
a49e490c
VZ		 196};
197
198static struct s5p_aes_dev *s5p_dev;
199
89245107 200static const struct samsung_aes_variant s5p_aes_data = {
89245107
NKC		 201 .aes_offset = 0x4000,
202};
203
204static const struct samsung_aes_variant exynos_aes_data = {
89245107
NKC		 205 .aes_offset = 0x200,
206};
207
6b9f16e6 208static const struct of_device_id s5p_sss_dt_match[] = {
89245107
NKC		 209 {
210 .compatible = "samsung,s5pv210-secss",
211 .data = &s5p_aes_data,
212 },
213 {
214 .compatible = "samsung,exynos4210-secss",
215 .data = &exynos_aes_data,
216 },
6b9f16e6
NKC		 217 { },
218};
219MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
220
89245107
NKC		 221static inline struct samsung_aes_variant *find_s5p_sss_version
222 (struct platform_device *pdev)
223{
224 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
225 const struct of_device_id *match;
313becd1 226
89245107
NKC		 227 match = of_match_node(s5p_sss_dt_match,
228 pdev->dev.of_node);
229 return (struct samsung_aes_variant *)match->data;
230 }
231 return (struct samsung_aes_variant *)
232 platform_get_device_id(pdev)->driver_data;
233}
234
a49e490c
VZ		 235static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
236{
237 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
238 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
239}
240
241static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
242{
243 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
244 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
245}
246
9e4a1100
KK		 247static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg)
248{
249 int len;
250
251 if (!*sg)
252 return;
253
254 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
255 free_pages((unsigned long)sg_virt(*sg), get_order(len));
256
257 kfree(*sg);
258 *sg = NULL;
259}
260
261static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg,
262 unsigned int nbytes, int out)
263{
264 struct scatter_walk walk;
265
266 if (!nbytes)
267 return;
268
269 scatterwalk_start(&walk, sg);
270 scatterwalk_copychunks(buf, &walk, nbytes, out);
271 scatterwalk_done(&walk, out, 0);
272}
273
a49e490c
VZ		 274static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)
275{
9e4a1100
KK		 276 if (dev->sg_dst_cpy) {
277 dev_dbg(dev->dev,
278 "Copying %d bytes of output data back to original place\n",
279 dev->req->nbytes);
280 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst,
281 dev->req->nbytes, 1);
282 }
283 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
284 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
285
a49e490c
VZ		 286 /* holding a lock outside */
287 dev->req->base.complete(&dev->req->base, err);
288 dev->busy = false;
289}
290
291static void s5p_unset_outdata(struct s5p_aes_dev *dev)
292{
293 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
294}
295
296static void s5p_unset_indata(struct s5p_aes_dev *dev)
297{
298 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
299}
300
9e4a1100
KK		 301static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src,
302 struct scatterlist **dst)
303{
304 void *pages;
305 int len;
306
307 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC);
308 if (!*dst)
309 return -ENOMEM;
310
311 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
312 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len));
313 if (!pages) {
314 kfree(*dst);
315 *dst = NULL;
316 return -ENOMEM;
317 }
318
319 s5p_sg_copy_buf(pages, src, dev->req->nbytes, 0);
320
321 sg_init_table(*dst, 1);
322 sg_set_buf(*dst, pages, len);
323
324 return 0;
325}
326
a49e490c
VZ		 327static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
328{
329 int err;
330
a49e490c
VZ		 331 if (!sg_dma_len(sg)) {
332 err = -EINVAL;
333 goto exit;
334 }
335
336 err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE);
337 if (!err) {
338 err = -ENOMEM;
339 goto exit;
340 }
341
342 dev->sg_dst = sg;
343 err = 0;
344
119c3ab4 345exit:
a49e490c
VZ		 346 return err;
347}
348
349static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
350{
351 int err;
352
a49e490c
VZ		 353 if (!sg_dma_len(sg)) {
354 err = -EINVAL;
355 goto exit;
356 }
357
358 err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE);
359 if (!err) {
360 err = -ENOMEM;
361 goto exit;
362 }
363
364 dev->sg_src = sg;
365 err = 0;
366
119c3ab4 367exit:
a49e490c
VZ		 368 return err;
369}
370
371static void s5p_aes_tx(struct s5p_aes_dev *dev)
372{
373 int err = 0;
374
375 s5p_unset_outdata(dev);
376
377 if (!sg_is_last(dev->sg_dst)) {
378 err = s5p_set_outdata(dev, sg_next(dev->sg_dst));
379 if (err) {
380 s5p_aes_complete(dev, err);
381 return;
382 }
383
384 s5p_set_dma_outdata(dev, dev->sg_dst);
dc5e3f19 385 } else {
a49e490c 386 s5p_aes_complete(dev, err);
dc5e3f19
NKC		 387
388 dev->busy = true;
389 tasklet_schedule(&dev->tasklet);
390 }
a49e490c
VZ		 391}
392
393static void s5p_aes_rx(struct s5p_aes_dev *dev)
394{
395 int err;
396
397 s5p_unset_indata(dev);
398
399 if (!sg_is_last(dev->sg_src)) {
400 err = s5p_set_indata(dev, sg_next(dev->sg_src));
401 if (err) {
402 s5p_aes_complete(dev, err);
403 return;
404 }
405
406 s5p_set_dma_indata(dev, dev->sg_src);
407 }
408}
409
410static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
411{
412 struct platform_device *pdev = dev_id;
413 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
414 uint32_t status;
415 unsigned long flags;
416
417 spin_lock_irqsave(&dev->lock, flags);
418
55124425
KK		 419 status = SSS_READ(dev, FCINTSTAT);
420 if (status & SSS_FCINTSTAT_BRDMAINT)
421 s5p_aes_rx(dev);
422 if (status & SSS_FCINTSTAT_BTDMAINT)
423 s5p_aes_tx(dev);
a49e490c 424
55124425 425 SSS_WRITE(dev, FCINTPEND, status);
a49e490c
VZ		 426
427 spin_unlock_irqrestore(&dev->lock, flags);
428
429 return IRQ_HANDLED;
430}
431
432static void s5p_set_aes(struct s5p_aes_dev *dev,
433 uint8_t *key, uint8_t *iv, unsigned int keylen)
434{
435 void __iomem *keystart;
436
8f9702aa 437 if (iv)
1e3012d0 438 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
a49e490c
VZ		 439
440 if (keylen == AES_KEYSIZE_256)
89245107 441 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
a49e490c 442 else if (keylen == AES_KEYSIZE_192)
89245107 443 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
a49e490c 444 else
89245107 445 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
a49e490c 446
1e3012d0 447 memcpy_toio(keystart, key, keylen);
a49e490c
VZ		 448}
449
9e4a1100
KK		 450static bool s5p_is_sg_aligned(struct scatterlist *sg)
451{
452 while (sg) {
453 if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE))
454 return false;
455 sg = sg_next(sg);
456 }
457
458 return true;
459}
460
461static int s5p_set_indata_start(struct s5p_aes_dev *dev,
462 struct ablkcipher_request *req)
463{
464 struct scatterlist *sg;
465 int err;
466
467 dev->sg_src_cpy = NULL;
468 sg = req->src;
469 if (!s5p_is_sg_aligned(sg)) {
470 dev_dbg(dev->dev,
471 "At least one unaligned source scatter list, making a copy\n");
472 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy);
473 if (err)
474 return err;
475
476 sg = dev->sg_src_cpy;
477 }
478
479 err = s5p_set_indata(dev, sg);
480 if (err) {
481 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
482 return err;
483 }
484
485 return 0;
486}
487
488static int s5p_set_outdata_start(struct s5p_aes_dev *dev,
489 struct ablkcipher_request *req)
490{
491 struct scatterlist *sg;
492 int err;
493
494 dev->sg_dst_cpy = NULL;
495 sg = req->dst;
496 if (!s5p_is_sg_aligned(sg)) {
497 dev_dbg(dev->dev,
498 "At least one unaligned dest scatter list, making a copy\n");
499 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy);
500 if (err)
501 return err;
502
503 sg = dev->sg_dst_cpy;
504 }
505
506 err = s5p_set_outdata(dev, sg);
507 if (err) {
508 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
509 return err;
510 }
511
512 return 0;
513}
514
a49e490c
VZ		 515static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
516{
517 struct ablkcipher_request *req = dev->req;
a49e490c
VZ		 518 uint32_t aes_control;
519 int err;
520 unsigned long flags;
521
522 aes_control = SSS_AES_KEY_CHANGE_MODE;
523 if (mode & FLAGS_AES_DECRYPT)
524 aes_control |= SSS_AES_MODE_DECRYPT;
525
526 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC)
527 aes_control |= SSS_AES_CHAIN_MODE_CBC;
528 else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR)
529 aes_control |= SSS_AES_CHAIN_MODE_CTR;
530
531 if (dev->ctx->keylen == AES_KEYSIZE_192)
532 aes_control |= SSS_AES_KEY_SIZE_192;
533 else if (dev->ctx->keylen == AES_KEYSIZE_256)
534 aes_control |= SSS_AES_KEY_SIZE_256;
535
536 aes_control |= SSS_AES_FIFO_MODE;
537
538 /* as a variant it is possible to use byte swapping on DMA side */
539 aes_control |= SSS_AES_BYTESWAP_DI
540 | SSS_AES_BYTESWAP_DO
541 | SSS_AES_BYTESWAP_IV
542 | SSS_AES_BYTESWAP_KEY
543 | SSS_AES_BYTESWAP_CNT;
544
545 spin_lock_irqsave(&dev->lock, flags);
546
547 SSS_WRITE(dev, FCINTENCLR,
548 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
549 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
550
9e4a1100 551 err = s5p_set_indata_start(dev, req);
a49e490c
VZ		 552 if (err)
553 goto indata_error;
554
9e4a1100 555 err = s5p_set_outdata_start(dev, req);
a49e490c
VZ		 556 if (err)
557 goto outdata_error;
558
89245107 559 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
a49e490c
VZ		 560 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
561
9e4a1100
KK		 562 s5p_set_dma_indata(dev, dev->sg_src);
563 s5p_set_dma_outdata(dev, dev->sg_dst);
a49e490c
VZ		 564
565 SSS_WRITE(dev, FCINTENSET,
566 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
567
568 spin_unlock_irqrestore(&dev->lock, flags);
569
570 return;
571
119c3ab4 572outdata_error:
a49e490c
VZ		 573 s5p_unset_indata(dev);
574
119c3ab4 575indata_error:
a49e490c
VZ		 576 s5p_aes_complete(dev, err);
577 spin_unlock_irqrestore(&dev->lock, flags);
578}
579
580static void s5p_tasklet_cb(unsigned long data)
581{
582 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
583 struct crypto_async_request *async_req, *backlog;
584 struct s5p_aes_reqctx *reqctx;
585 unsigned long flags;
586
587 spin_lock_irqsave(&dev->lock, flags);
588 backlog = crypto_get_backlog(&dev->queue);
589 async_req = crypto_dequeue_request(&dev->queue);
a49e490c 590
dc5e3f19
NKC		 591 if (!async_req) {
592 dev->busy = false;
593 spin_unlock_irqrestore(&dev->lock, flags);
a49e490c 594 return;
dc5e3f19
NKC		 595 }
596 spin_unlock_irqrestore(&dev->lock, flags);
a49e490c
VZ		 597
598 if (backlog)
599 backlog->complete(backlog, -EINPROGRESS);
600
601 dev->req = ablkcipher_request_cast(async_req);
602 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
603 reqctx = ablkcipher_request_ctx(dev->req);
604
605 s5p_aes_crypt_start(dev, reqctx->mode);
606}
607
608static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
609 struct ablkcipher_request *req)
610{
611 unsigned long flags;
612 int err;
613
614 spin_lock_irqsave(&dev->lock, flags);
dc5e3f19 615 err = ablkcipher_enqueue_request(&dev->queue, req);
a49e490c 616 if (dev->busy) {
a49e490c
VZ		 617 spin_unlock_irqrestore(&dev->lock, flags);
618 goto exit;
619 }
620 dev->busy = true;
621
a49e490c
VZ		 622 spin_unlock_irqrestore(&dev->lock, flags);
623
624 tasklet_schedule(&dev->tasklet);
625
119c3ab4 626exit:
a49e490c
VZ		 627 return err;
628}
629
630static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
631{
632 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
633 struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
634 struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req);
635 struct s5p_aes_dev *dev = ctx->dev;
636
637 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
313becd1 638 dev_err(dev->dev, "request size is not exact amount of AES blocks\n");
a49e490c
VZ		 639 return -EINVAL;
640 }
641
642 reqctx->mode = mode;
643
644 return s5p_aes_handle_req(dev, req);
645}
646
647static int s5p_aes_setkey(struct crypto_ablkcipher *cipher,
648 const uint8_t *key, unsigned int keylen)
649{
650 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
651 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
652
653 if (keylen != AES_KEYSIZE_128 &&
654 keylen != AES_KEYSIZE_192 &&
655 keylen != AES_KEYSIZE_256)
656 return -EINVAL;
657
658 memcpy(ctx->aes_key, key, keylen);
659 ctx->keylen = keylen;
660
661 return 0;
662}
663
664static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req)
665{
666 return s5p_aes_crypt(req, 0);
667}
668
669static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req)
670{
671 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
672}
673
674static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req)
675{
676 return s5p_aes_crypt(req, FLAGS_AES_CBC);
677}
678
679static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req)
680{
681 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
682}
683
684static int s5p_aes_cra_init(struct crypto_tfm *tfm)
685{
313becd1 686 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
a49e490c
VZ		 687
688 ctx->dev = s5p_dev;
689 tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx);
690
691 return 0;
692}
693
694static struct crypto_alg algs[] = {
695 {
696 .cra_name = "ecb(aes)",
697 .cra_driver_name = "ecb-aes-s5p",
698 .cra_priority = 100,
699 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 700 CRYPTO_ALG_ASYNC |
701 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 702 .cra_blocksize = AES_BLOCK_SIZE,
703 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
704 .cra_alignmask = 0x0f,
705 .cra_type = &crypto_ablkcipher_type,
706 .cra_module = THIS_MODULE,
707 .cra_init = s5p_aes_cra_init,
708 .cra_u.ablkcipher = {
709 .min_keysize = AES_MIN_KEY_SIZE,
710 .max_keysize = AES_MAX_KEY_SIZE,
711 .setkey = s5p_aes_setkey,
712 .encrypt = s5p_aes_ecb_encrypt,
713 .decrypt = s5p_aes_ecb_decrypt,
714 }
715 },
716 {
717 .cra_name = "cbc(aes)",
718 .cra_driver_name = "cbc-aes-s5p",
719 .cra_priority = 100,
720 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 721 CRYPTO_ALG_ASYNC |
722 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 723 .cra_blocksize = AES_BLOCK_SIZE,
724 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
725 .cra_alignmask = 0x0f,
726 .cra_type = &crypto_ablkcipher_type,
727 .cra_module = THIS_MODULE,
728 .cra_init = s5p_aes_cra_init,
729 .cra_u.ablkcipher = {
730 .min_keysize = AES_MIN_KEY_SIZE,
731 .max_keysize = AES_MAX_KEY_SIZE,
732 .ivsize = AES_BLOCK_SIZE,
733 .setkey = s5p_aes_setkey,
734 .encrypt = s5p_aes_cbc_encrypt,
735 .decrypt = s5p_aes_cbc_decrypt,
736 }
737 },
738};
739
740static int s5p_aes_probe(struct platform_device *pdev)
741{
742 int i, j, err = -ENODEV;
743 struct s5p_aes_dev *pdata;
744 struct device *dev = &pdev->dev;
745 struct resource *res;
89245107 746 struct samsung_aes_variant *variant;
a49e490c
VZ		 747
748 if (s5p_dev)
749 return -EEXIST;
750
a49e490c
VZ		 751 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
752 if (!pdata)
753 return -ENOMEM;
754
0fdefe2c
JH		 755 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
756 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
757 if (IS_ERR(pdata->ioaddr))
758 return PTR_ERR(pdata->ioaddr);
a49e490c 759
89245107
NKC		 760 variant = find_s5p_sss_version(pdev);
761
5c22ba66 762 pdata->clk = devm_clk_get(dev, "secss");
a49e490c
VZ		 763 if (IS_ERR(pdata->clk)) {
764 dev_err(dev, "failed to find secss clock source\n");
765 return -ENOENT;
766 }
767
c1eb7ef2
NKC		 768 err = clk_prepare_enable(pdata->clk);
769 if (err < 0) {
770 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
771 return err;
772 }
a49e490c
VZ		 773
774 spin_lock_init(&pdata->lock);
a49e490c 775
89245107
NKC		 776 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
777
96fc70b6
NKC		 778 pdata->irq_fc = platform_get_irq(pdev, 0);
779 if (pdata->irq_fc < 0) {
780 err = pdata->irq_fc;
781 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 782 goto err_irq;
783 }
96fc70b6 784 err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
a49e490c
VZ		 785 IRQF_SHARED, pdev->name, pdev);
786 if (err < 0) {
96fc70b6 787 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 788 goto err_irq;
789 }
790
dc5e3f19 791 pdata->busy = false;
89245107 792 pdata->variant = variant;
a49e490c
VZ		 793 pdata->dev = dev;
794 platform_set_drvdata(pdev, pdata);
795 s5p_dev = pdata;
796
797 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
798 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
799
800 for (i = 0; i < ARRAY_SIZE(algs); i++) {
a49e490c
VZ		 801 err = crypto_register_alg(&algs[i]);
802 if (err)
803 goto err_algs;
804 }
805
313becd1 806 dev_info(dev, "s5p-sss driver registered\n");
a49e490c
VZ		 807
808 return 0;
809
119c3ab4 810err_algs:
a49e490c
VZ		 811 dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err);
812
813 for (j = 0; j < i; j++)
814 crypto_unregister_alg(&algs[j]);
815
816 tasklet_kill(&pdata->tasklet);
817
119c3ab4 818err_irq:
c1eb7ef2 819 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 820
821 s5p_dev = NULL;
a49e490c
VZ		 822
823 return err;
824}
825
826static int s5p_aes_remove(struct platform_device *pdev)
827{
828 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
829 int i;
830
831 if (!pdata)
832 return -ENODEV;
833
834 for (i = 0; i < ARRAY_SIZE(algs); i++)
835 crypto_unregister_alg(&algs[i]);
836
837 tasklet_kill(&pdata->tasklet);
838
c1eb7ef2 839 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 840
841 s5p_dev = NULL;
a49e490c
VZ		 842
843 return 0;
844}
845
846static struct platform_driver s5p_aes_crypto = {
847 .probe = s5p_aes_probe,
848 .remove = s5p_aes_remove,
849 .driver = {
a49e490c 850 .name = "s5p-secss",
6b9f16e6 851 .of_match_table = s5p_sss_dt_match,
a49e490c
VZ		 852 },
853};
854
741e8c2d 855module_platform_driver(s5p_aes_crypto);
a49e490c
VZ		 856
857MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
858MODULE_LICENSE("GPL v2");
859MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
Linux kernel - Deliverables
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