projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
crypto: s5p-sss - Use clk_prepare/clk_unprepare
[deliverable/linux.git] / drivers / crypto / s5p-sss.c
CommitLineData
a49e490c
VZ		 1/*
2 * Cryptographic API.
3 *
4 * Support for Samsung S5PV210 HW acceleration.
5 *
6 * Copyright (C) 2011 NetUP Inc. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 */
13
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/platform_device.h>
22#include <linux/scatterlist.h>
23#include <linux/dma-mapping.h>
24#include <linux/io.h>
6b9f16e6 25#include <linux/of.h>
a49e490c
VZ		 26#include <linux/crypto.h>
27#include <linux/interrupt.h>
28
29#include <crypto/algapi.h>
30#include <crypto/aes.h>
31#include <crypto/ctr.h>
32
33#include <plat/cpu.h>
a465348f 34#include <mach/dma.h>
a49e490c
VZ		 35
36#define _SBF(s, v) ((v) << (s))
37#define _BIT(b) _SBF(b, 1)
38
39/* Feed control registers */
40#define SSS_REG_FCINTSTAT 0x0000
41#define SSS_FCINTSTAT_BRDMAINT _BIT(3)
42#define SSS_FCINTSTAT_BTDMAINT _BIT(2)
43#define SSS_FCINTSTAT_HRDMAINT _BIT(1)
44#define SSS_FCINTSTAT_PKDMAINT _BIT(0)
45
46#define SSS_REG_FCINTENSET 0x0004
47#define SSS_FCINTENSET_BRDMAINTENSET _BIT(3)
48#define SSS_FCINTENSET_BTDMAINTENSET _BIT(2)
49#define SSS_FCINTENSET_HRDMAINTENSET _BIT(1)
50#define SSS_FCINTENSET_PKDMAINTENSET _BIT(0)
51
52#define SSS_REG_FCINTENCLR 0x0008
53#define SSS_FCINTENCLR_BRDMAINTENCLR _BIT(3)
54#define SSS_FCINTENCLR_BTDMAINTENCLR _BIT(2)
55#define SSS_FCINTENCLR_HRDMAINTENCLR _BIT(1)
56#define SSS_FCINTENCLR_PKDMAINTENCLR _BIT(0)
57
58#define SSS_REG_FCINTPEND 0x000C
59#define SSS_FCINTPEND_BRDMAINTP _BIT(3)
60#define SSS_FCINTPEND_BTDMAINTP _BIT(2)
61#define SSS_FCINTPEND_HRDMAINTP _BIT(1)
62#define SSS_FCINTPEND_PKDMAINTP _BIT(0)
63
64#define SSS_REG_FCFIFOSTAT 0x0010
65#define SSS_FCFIFOSTAT_BRFIFOFUL _BIT(7)
66#define SSS_FCFIFOSTAT_BRFIFOEMP _BIT(6)
67#define SSS_FCFIFOSTAT_BTFIFOFUL _BIT(5)
68#define SSS_FCFIFOSTAT_BTFIFOEMP _BIT(4)
69#define SSS_FCFIFOSTAT_HRFIFOFUL _BIT(3)
70#define SSS_FCFIFOSTAT_HRFIFOEMP _BIT(2)
71#define SSS_FCFIFOSTAT_PKFIFOFUL _BIT(1)
72#define SSS_FCFIFOSTAT_PKFIFOEMP _BIT(0)
73
74#define SSS_REG_FCFIFOCTRL 0x0014
75#define SSS_FCFIFOCTRL_DESSEL _BIT(2)
76#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
77#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
78#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
79
80#define SSS_REG_FCBRDMAS 0x0020
81#define SSS_REG_FCBRDMAL 0x0024
82#define SSS_REG_FCBRDMAC 0x0028
83#define SSS_FCBRDMAC_BYTESWAP _BIT(1)
84#define SSS_FCBRDMAC_FLUSH _BIT(0)
85
86#define SSS_REG_FCBTDMAS 0x0030
87#define SSS_REG_FCBTDMAL 0x0034
88#define SSS_REG_FCBTDMAC 0x0038
89#define SSS_FCBTDMAC_BYTESWAP _BIT(1)
90#define SSS_FCBTDMAC_FLUSH _BIT(0)
91
92#define SSS_REG_FCHRDMAS 0x0040
93#define SSS_REG_FCHRDMAL 0x0044
94#define SSS_REG_FCHRDMAC 0x0048
95#define SSS_FCHRDMAC_BYTESWAP _BIT(1)
96#define SSS_FCHRDMAC_FLUSH _BIT(0)
97
98#define SSS_REG_FCPKDMAS 0x0050
99#define SSS_REG_FCPKDMAL 0x0054
100#define SSS_REG_FCPKDMAC 0x0058
101#define SSS_FCPKDMAC_BYTESWAP _BIT(3)
102#define SSS_FCPKDMAC_DESCEND _BIT(2)
103#define SSS_FCPKDMAC_TRANSMIT _BIT(1)
104#define SSS_FCPKDMAC_FLUSH _BIT(0)
105
106#define SSS_REG_FCPKDMAO 0x005C
107
108/* AES registers */
89245107 109#define SSS_REG_AES_CONTROL 0x00
a49e490c
VZ		 110#define SSS_AES_BYTESWAP_DI _BIT(11)
111#define SSS_AES_BYTESWAP_DO _BIT(10)
112#define SSS_AES_BYTESWAP_IV _BIT(9)
113#define SSS_AES_BYTESWAP_CNT _BIT(8)
114#define SSS_AES_BYTESWAP_KEY _BIT(7)
115#define SSS_AES_KEY_CHANGE_MODE _BIT(6)
116#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
117#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
118#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
119#define SSS_AES_FIFO_MODE _BIT(3)
120#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
121#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
122#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
123#define SSS_AES_MODE_DECRYPT _BIT(0)
124
89245107 125#define SSS_REG_AES_STATUS 0x04
a49e490c
VZ		 126#define SSS_AES_BUSY _BIT(2)
127#define SSS_AES_INPUT_READY _BIT(1)
128#define SSS_AES_OUTPUT_READY _BIT(0)
129
89245107
NKC		 130#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
131#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
132#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
133#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
134#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
a49e490c
VZ		 135
136#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
137#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
138#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
139
89245107
NKC		 140#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
141#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
142 SSS_AES_REG(dev, reg))
143
a49e490c
VZ		 144/* HW engine modes */
145#define FLAGS_AES_DECRYPT _BIT(0)
146#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
147#define FLAGS_AES_CBC _SBF(1, 0x01)
148#define FLAGS_AES_CTR _SBF(1, 0x02)
149
150#define AES_KEY_LEN 16
151#define CRYPTO_QUEUE_LEN 1
152
89245107
NKC		 153/**
154 * struct samsung_aes_variant - platform specific SSS driver data
155 * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
156 * @aes_offset: AES register offset from SSS module's base.
157 *
158 * Specifies platform specific configuration of SSS module.
159 * Note: A structure for driver specific platform data is used for future
160 * expansion of its usage.
161 */
162struct samsung_aes_variant {
163 bool has_hash_irq;
164 unsigned int aes_offset;
165};
166
a49e490c
VZ		 167struct s5p_aes_reqctx {
168 unsigned long mode;
169};
170
171struct s5p_aes_ctx {
172 struct s5p_aes_dev *dev;
173
174 uint8_t aes_key[AES_MAX_KEY_SIZE];
175 uint8_t nonce[CTR_RFC3686_NONCE_SIZE];
176 int keylen;
177};
178
179struct s5p_aes_dev {
180 struct device *dev;
181 struct clk *clk;
182 void __iomem *ioaddr;
89245107 183 void __iomem *aes_ioaddr;
a49e490c
VZ		 184 int irq_hash;
185 int irq_fc;
186
187 struct ablkcipher_request *req;
188 struct s5p_aes_ctx *ctx;
189 struct scatterlist *sg_src;
190 struct scatterlist *sg_dst;
191
192 struct tasklet_struct tasklet;
193 struct crypto_queue queue;
194 bool busy;
195 spinlock_t lock;
89245107
NKC		 196
197 struct samsung_aes_variant *variant;
a49e490c
VZ		 198};
199
200static struct s5p_aes_dev *s5p_dev;
201
89245107
NKC		 202static const struct samsung_aes_variant s5p_aes_data = {
203 .has_hash_irq = true,
204 .aes_offset = 0x4000,
205};
206
207static const struct samsung_aes_variant exynos_aes_data = {
208 .has_hash_irq = false,
209 .aes_offset = 0x200,
210};
211
6b9f16e6 212static const struct of_device_id s5p_sss_dt_match[] = {
89245107
NKC		 213 {
214 .compatible = "samsung,s5pv210-secss",
215 .data = &s5p_aes_data,
216 },
217 {
218 .compatible = "samsung,exynos4210-secss",
219 .data = &exynos_aes_data,
220 },
6b9f16e6
NKC		 221 { },
222};
223MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
224
89245107
NKC		 225static inline struct samsung_aes_variant *find_s5p_sss_version
226 (struct platform_device *pdev)
227{
228 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
229 const struct of_device_id *match;
230 match = of_match_node(s5p_sss_dt_match,
231 pdev->dev.of_node);
232 return (struct samsung_aes_variant *)match->data;
233 }
234 return (struct samsung_aes_variant *)
235 platform_get_device_id(pdev)->driver_data;
236}
237
a49e490c
VZ		 238static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
239{
240 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
241 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
242}
243
244static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
245{
246 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
247 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
248}
249
250static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)
251{
252 /* holding a lock outside */
253 dev->req->base.complete(&dev->req->base, err);
254 dev->busy = false;
255}
256
257static void s5p_unset_outdata(struct s5p_aes_dev *dev)
258{
259 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
260}
261
262static void s5p_unset_indata(struct s5p_aes_dev *dev)
263{
264 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
265}
266
267static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
268{
269 int err;
270
271 if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) {
272 err = -EINVAL;
273 goto exit;
274 }
275 if (!sg_dma_len(sg)) {
276 err = -EINVAL;
277 goto exit;
278 }
279
280 err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE);
281 if (!err) {
282 err = -ENOMEM;
283 goto exit;
284 }
285
286 dev->sg_dst = sg;
287 err = 0;
288
289 exit:
290 return err;
291}
292
293static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
294{
295 int err;
296
297 if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) {
298 err = -EINVAL;
299 goto exit;
300 }
301 if (!sg_dma_len(sg)) {
302 err = -EINVAL;
303 goto exit;
304 }
305
306 err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE);
307 if (!err) {
308 err = -ENOMEM;
309 goto exit;
310 }
311
312 dev->sg_src = sg;
313 err = 0;
314
315 exit:
316 return err;
317}
318
319static void s5p_aes_tx(struct s5p_aes_dev *dev)
320{
321 int err = 0;
322
323 s5p_unset_outdata(dev);
324
325 if (!sg_is_last(dev->sg_dst)) {
326 err = s5p_set_outdata(dev, sg_next(dev->sg_dst));
327 if (err) {
328 s5p_aes_complete(dev, err);
329 return;
330 }
331
332 s5p_set_dma_outdata(dev, dev->sg_dst);
333 } else
334 s5p_aes_complete(dev, err);
335}
336
337static void s5p_aes_rx(struct s5p_aes_dev *dev)
338{
339 int err;
340
341 s5p_unset_indata(dev);
342
343 if (!sg_is_last(dev->sg_src)) {
344 err = s5p_set_indata(dev, sg_next(dev->sg_src));
345 if (err) {
346 s5p_aes_complete(dev, err);
347 return;
348 }
349
350 s5p_set_dma_indata(dev, dev->sg_src);
351 }
352}
353
354static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
355{
356 struct platform_device *pdev = dev_id;
357 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
358 uint32_t status;
359 unsigned long flags;
360
361 spin_lock_irqsave(&dev->lock, flags);
362
363 if (irq == dev->irq_fc) {
364 status = SSS_READ(dev, FCINTSTAT);
365 if (status & SSS_FCINTSTAT_BRDMAINT)
366 s5p_aes_rx(dev);
367 if (status & SSS_FCINTSTAT_BTDMAINT)
368 s5p_aes_tx(dev);
369
370 SSS_WRITE(dev, FCINTPEND, status);
371 }
372
373 spin_unlock_irqrestore(&dev->lock, flags);
374
375 return IRQ_HANDLED;
376}
377
378static void s5p_set_aes(struct s5p_aes_dev *dev,
379 uint8_t *key, uint8_t *iv, unsigned int keylen)
380{
381 void __iomem *keystart;
382
8f9702aa
NKC		 383 if (iv)
384 memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
a49e490c
VZ		 385
386 if (keylen == AES_KEYSIZE_256)
89245107 387 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
a49e490c 388 else if (keylen == AES_KEYSIZE_192)
89245107 389 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
a49e490c 390 else
89245107 391 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
a49e490c
VZ		 392
393 memcpy(keystart, key, keylen);
394}
395
396static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
397{
398 struct ablkcipher_request *req = dev->req;
399
400 uint32_t aes_control;
401 int err;
402 unsigned long flags;
403
404 aes_control = SSS_AES_KEY_CHANGE_MODE;
405 if (mode & FLAGS_AES_DECRYPT)
406 aes_control |= SSS_AES_MODE_DECRYPT;
407
408 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC)
409 aes_control |= SSS_AES_CHAIN_MODE_CBC;
410 else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR)
411 aes_control |= SSS_AES_CHAIN_MODE_CTR;
412
413 if (dev->ctx->keylen == AES_KEYSIZE_192)
414 aes_control |= SSS_AES_KEY_SIZE_192;
415 else if (dev->ctx->keylen == AES_KEYSIZE_256)
416 aes_control |= SSS_AES_KEY_SIZE_256;
417
418 aes_control |= SSS_AES_FIFO_MODE;
419
420 /* as a variant it is possible to use byte swapping on DMA side */
421 aes_control |= SSS_AES_BYTESWAP_DI
422 | SSS_AES_BYTESWAP_DO
423 | SSS_AES_BYTESWAP_IV
424 | SSS_AES_BYTESWAP_KEY
425 | SSS_AES_BYTESWAP_CNT;
426
427 spin_lock_irqsave(&dev->lock, flags);
428
429 SSS_WRITE(dev, FCINTENCLR,
430 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
431 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
432
433 err = s5p_set_indata(dev, req->src);
434 if (err)
435 goto indata_error;
436
437 err = s5p_set_outdata(dev, req->dst);
438 if (err)
439 goto outdata_error;
440
89245107 441 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
a49e490c
VZ		 442 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
443
444 s5p_set_dma_indata(dev, req->src);
445 s5p_set_dma_outdata(dev, req->dst);
446
447 SSS_WRITE(dev, FCINTENSET,
448 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
449
450 spin_unlock_irqrestore(&dev->lock, flags);
451
452 return;
453
454 outdata_error:
455 s5p_unset_indata(dev);
456
457 indata_error:
458 s5p_aes_complete(dev, err);
459 spin_unlock_irqrestore(&dev->lock, flags);
460}
461
462static void s5p_tasklet_cb(unsigned long data)
463{
464 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
465 struct crypto_async_request *async_req, *backlog;
466 struct s5p_aes_reqctx *reqctx;
467 unsigned long flags;
468
469 spin_lock_irqsave(&dev->lock, flags);
470 backlog = crypto_get_backlog(&dev->queue);
471 async_req = crypto_dequeue_request(&dev->queue);
472 spin_unlock_irqrestore(&dev->lock, flags);
473
474 if (!async_req)
475 return;
476
477 if (backlog)
478 backlog->complete(backlog, -EINPROGRESS);
479
480 dev->req = ablkcipher_request_cast(async_req);
481 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
482 reqctx = ablkcipher_request_ctx(dev->req);
483
484 s5p_aes_crypt_start(dev, reqctx->mode);
485}
486
487static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
488 struct ablkcipher_request *req)
489{
490 unsigned long flags;
491 int err;
492
493 spin_lock_irqsave(&dev->lock, flags);
494 if (dev->busy) {
495 err = -EAGAIN;
496 spin_unlock_irqrestore(&dev->lock, flags);
497 goto exit;
498 }
499 dev->busy = true;
500
501 err = ablkcipher_enqueue_request(&dev->queue, req);
502 spin_unlock_irqrestore(&dev->lock, flags);
503
504 tasklet_schedule(&dev->tasklet);
505
506 exit:
507 return err;
508}
509
510static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
511{
512 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
513 struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
514 struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req);
515 struct s5p_aes_dev *dev = ctx->dev;
516
517 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
518 pr_err("request size is not exact amount of AES blocks\n");
519 return -EINVAL;
520 }
521
522 reqctx->mode = mode;
523
524 return s5p_aes_handle_req(dev, req);
525}
526
527static int s5p_aes_setkey(struct crypto_ablkcipher *cipher,
528 const uint8_t *key, unsigned int keylen)
529{
530 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
531 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
532
533 if (keylen != AES_KEYSIZE_128 &&
534 keylen != AES_KEYSIZE_192 &&
535 keylen != AES_KEYSIZE_256)
536 return -EINVAL;
537
538 memcpy(ctx->aes_key, key, keylen);
539 ctx->keylen = keylen;
540
541 return 0;
542}
543
544static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req)
545{
546 return s5p_aes_crypt(req, 0);
547}
548
549static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req)
550{
551 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
552}
553
554static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req)
555{
556 return s5p_aes_crypt(req, FLAGS_AES_CBC);
557}
558
559static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req)
560{
561 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
562}
563
564static int s5p_aes_cra_init(struct crypto_tfm *tfm)
565{
566 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
567
568 ctx->dev = s5p_dev;
569 tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx);
570
571 return 0;
572}
573
574static struct crypto_alg algs[] = {
575 {
576 .cra_name = "ecb(aes)",
577 .cra_driver_name = "ecb-aes-s5p",
578 .cra_priority = 100,
579 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 580 CRYPTO_ALG_ASYNC |
581 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 582 .cra_blocksize = AES_BLOCK_SIZE,
583 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
584 .cra_alignmask = 0x0f,
585 .cra_type = &crypto_ablkcipher_type,
586 .cra_module = THIS_MODULE,
587 .cra_init = s5p_aes_cra_init,
588 .cra_u.ablkcipher = {
589 .min_keysize = AES_MIN_KEY_SIZE,
590 .max_keysize = AES_MAX_KEY_SIZE,
591 .setkey = s5p_aes_setkey,
592 .encrypt = s5p_aes_ecb_encrypt,
593 .decrypt = s5p_aes_ecb_decrypt,
594 }
595 },
596 {
597 .cra_name = "cbc(aes)",
598 .cra_driver_name = "cbc-aes-s5p",
599 .cra_priority = 100,
600 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76
NM		 601 CRYPTO_ALG_ASYNC |
602 CRYPTO_ALG_KERN_DRIVER_ONLY,
a49e490c
VZ		 603 .cra_blocksize = AES_BLOCK_SIZE,
604 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
605 .cra_alignmask = 0x0f,
606 .cra_type = &crypto_ablkcipher_type,
607 .cra_module = THIS_MODULE,
608 .cra_init = s5p_aes_cra_init,
609 .cra_u.ablkcipher = {
610 .min_keysize = AES_MIN_KEY_SIZE,
611 .max_keysize = AES_MAX_KEY_SIZE,
612 .ivsize = AES_BLOCK_SIZE,
613 .setkey = s5p_aes_setkey,
614 .encrypt = s5p_aes_cbc_encrypt,
615 .decrypt = s5p_aes_cbc_decrypt,
616 }
617 },
618};
619
620static int s5p_aes_probe(struct platform_device *pdev)
621{
622 int i, j, err = -ENODEV;
623 struct s5p_aes_dev *pdata;
624 struct device *dev = &pdev->dev;
625 struct resource *res;
89245107 626 struct samsung_aes_variant *variant;
a49e490c
VZ		 627
628 if (s5p_dev)
629 return -EEXIST;
630
a49e490c
VZ		 631 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
632 if (!pdata)
633 return -ENOMEM;
634
0fdefe2c
JH		 635 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
636 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
637 if (IS_ERR(pdata->ioaddr))
638 return PTR_ERR(pdata->ioaddr);
a49e490c 639
89245107
NKC		 640 variant = find_s5p_sss_version(pdev);
641
5c22ba66 642 pdata->clk = devm_clk_get(dev, "secss");
a49e490c
VZ		 643 if (IS_ERR(pdata->clk)) {
644 dev_err(dev, "failed to find secss clock source\n");
645 return -ENOENT;
646 }
647
c1eb7ef2
NKC		 648 err = clk_prepare_enable(pdata->clk);
649 if (err < 0) {
650 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
651 return err;
652 }
a49e490c
VZ		 653
654 spin_lock_init(&pdata->lock);
a49e490c 655
89245107
NKC		 656 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
657
96fc70b6
NKC		 658 pdata->irq_fc = platform_get_irq(pdev, 0);
659 if (pdata->irq_fc < 0) {
660 err = pdata->irq_fc;
661 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 662 goto err_irq;
663 }
96fc70b6 664 err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
a49e490c
VZ		 665 IRQF_SHARED, pdev->name, pdev);
666 if (err < 0) {
96fc70b6 667 dev_warn(dev, "feed control interrupt is not available.\n");
a49e490c
VZ		 668 goto err_irq;
669 }
670
89245107
NKC		 671 if (variant->has_hash_irq) {
672 pdata->irq_hash = platform_get_irq(pdev, 1);
673 if (pdata->irq_hash < 0) {
674 err = pdata->irq_hash;
675 dev_warn(dev, "hash interrupt is not available.\n");
676 goto err_irq;
677 }
678 err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
679 IRQF_SHARED, pdev->name, pdev);
680 if (err < 0) {
681 dev_warn(dev, "hash interrupt is not available.\n");
682 goto err_irq;
683 }
a49e490c
VZ		 684 }
685
89245107 686 pdata->variant = variant;
a49e490c
VZ		 687 pdata->dev = dev;
688 platform_set_drvdata(pdev, pdata);
689 s5p_dev = pdata;
690
691 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
692 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
693
694 for (i = 0; i < ARRAY_SIZE(algs); i++) {
a49e490c
VZ		 695 err = crypto_register_alg(&algs[i]);
696 if (err)
697 goto err_algs;
698 }
699
700 pr_info("s5p-sss driver registered\n");
701
702 return 0;
703
704 err_algs:
705 dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err);
706
707 for (j = 0; j < i; j++)
708 crypto_unregister_alg(&algs[j]);
709
710 tasklet_kill(&pdata->tasklet);
711
712 err_irq:
c1eb7ef2 713 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 714
715 s5p_dev = NULL;
a49e490c
VZ		 716
717 return err;
718}
719
720static int s5p_aes_remove(struct platform_device *pdev)
721{
722 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
723 int i;
724
725 if (!pdata)
726 return -ENODEV;
727
728 for (i = 0; i < ARRAY_SIZE(algs); i++)
729 crypto_unregister_alg(&algs[i]);
730
731 tasklet_kill(&pdata->tasklet);
732
c1eb7ef2 733 clk_disable_unprepare(pdata->clk);
a49e490c
VZ		 734
735 s5p_dev = NULL;
a49e490c
VZ		 736
737 return 0;
738}
739
740static struct platform_driver s5p_aes_crypto = {
741 .probe = s5p_aes_probe,
742 .remove = s5p_aes_remove,
743 .driver = {
744 .owner = THIS_MODULE,
745 .name = "s5p-secss",
6b9f16e6 746 .of_match_table = s5p_sss_dt_match,
a49e490c
VZ		 747 },
748};
749
741e8c2d 750module_platform_driver(s5p_aes_crypto);
a49e490c
VZ		 751
752MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
753MODULE_LICENSE("GPL v2");
754MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
Linux kernel - Deliverables
This page took 0.272713 seconds and 5 git commands to generate.