projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
crypto: talitos - prune unneeded descriptor allocation param
[deliverable/linux.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
81eb024c
KP		 56static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
57{
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 59 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 60}
61
9c4a7965
KP		 62/*
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
64 */
65static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
68 unsigned char extent,
69 enum dma_data_direction dir)
70{
81eb024c
KP		 71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
72
9c4a7965 73 talitos_ptr->len = cpu_to_be16(len);
81eb024c 74 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 75 talitos_ptr->j_extent = extent;
76}
77
78/*
79 * unmap bus single (contiguous) h/w descriptor pointer
80 */
81static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
84{
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
87}
88
89static int reset_channel(struct device *dev, int ch)
90{
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
93
ad42d5fc 94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
9c4a7965 95
ad42d5fc 96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
9c4a7965
KP		 97 && --timeout)
98 cpu_relax();
99
100 if (timeout == 0) {
101 dev_err(dev, "failed to reset channel %d\n", ch);
102 return -EIO;
103 }
104
81eb024c 105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 108
fe5720e2
KP		 109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 112 TALITOS_CCCR_LO_IWSE);
113
9c4a7965
KP		 114 return 0;
115}
116
117static int reset_device(struct device *dev)
118{
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
c3e337f8 121 u32 mcr = TALITOS_MCR_SWR;
9c4a7965 122
c3e337f8 123 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965
KP		 124
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
126 && --timeout)
127 cpu_relax();
128
2cdba3cf 129 if (priv->irq[1]) {
c3e337f8
KP		 130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
132 }
133
9c4a7965
KP		 134 if (timeout == 0) {
135 dev_err(dev, "failed to reset device\n");
136 return -EIO;
137 }
138
139 return 0;
140}
141
142/*
143 * Reset and initialize the device
144 */
145static int init_device(struct device *dev)
146{
147 struct talitos_private *priv = dev_get_drvdata(dev);
148 int ch, err;
149
150 /*
151 * Master reset
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
155 */
156 err = reset_device(dev);
157 if (err)
158 return err;
159
160 err = reset_device(dev);
161 if (err)
162 return err;
163
164 /* reset channels */
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
167 if (err)
168 return err;
169 }
170
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
174
fe5720e2
KP		 175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
179
9c4a7965
KP		 180 return 0;
181}
182
183/**
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
5228f0f7 186 * @ch: the SEC device channel to be used
9c4a7965
KP		 187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
190 *
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
194 */
865d5061
HG		 195int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
199 void *context)
9c4a7965
KP		 200{
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
5228f0f7 203 unsigned long flags;
9c4a7965
KP		 204 int head;
205
4b992628 206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 207
4b992628 208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 209 /* h/w fifo is full */
4b992628 210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 211 return -EAGAIN;
212 }
213
4b992628
KP		 214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
ec6644d6 216
9c4a7965
KP		 217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
219 DMA_BIDIRECTIONAL);
220 request->callback = callback;
221 request->context = context;
222
223 /* increment fifo head */
4b992628 224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 225
226 smp_wmb();
227 request->desc = desc;
228
229 /* GO! */
230 wmb();
ad42d5fc
KP		 231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 234 lower_32_bits(request->dma_desc));
9c4a7965 235
4b992628 236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 237
238 return -EINPROGRESS;
239}
865d5061 240EXPORT_SYMBOL(talitos_submit);
9c4a7965
KP		 241
242/*
243 * process what was done, notify callback of error if not
244 */
245static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
246{
247 struct talitos_private *priv = dev_get_drvdata(dev);
248 struct talitos_request *request, saved_req;
249 unsigned long flags;
250 int tail, status;
251
4b992628 252 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 253
4b992628
KP		 254 tail = priv->chan[ch].tail;
255 while (priv->chan[ch].fifo[tail].desc) {
256 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 257
258 /* descriptors with their done bits set don't get the error */
259 rmb();
ca38a814 260 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 261 status = 0;
ca38a814 262 else
9c4a7965
KP		 263 if (!error)
264 break;
265 else
266 status = error;
267
268 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 269 sizeof(struct talitos_desc),
270 DMA_BIDIRECTIONAL);
9c4a7965
KP		 271
272 /* copy entries so we can call callback outside lock */
273 saved_req.desc = request->desc;
274 saved_req.callback = request->callback;
275 saved_req.context = request->context;
276
277 /* release request entry in fifo */
278 smp_wmb();
279 request->desc = NULL;
280
281 /* increment fifo tail */
4b992628 282 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 283
4b992628 284 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 285
4b992628 286 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 287
9c4a7965
KP		 288 saved_req.callback(dev, saved_req.desc, saved_req.context,
289 status);
290 /* channel may resume processing in single desc error case */
291 if (error && !reset_ch && status == error)
292 return;
4b992628
KP		 293 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
294 tail = priv->chan[ch].tail;
9c4a7965
KP		 295 }
296
4b992628 297 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 298}
299
300/*
301 * process completed requests for channels that have done status
302 */
c3e337f8
KP		 303#define DEF_TALITOS_DONE(name, ch_done_mask) \
304static void talitos_done_##name(unsigned long data) \
305{ \
306 struct device *dev = (struct device *)data; \
307 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 308 unsigned long flags; \
c3e337f8
KP		 309 \
310 if (ch_done_mask & 1) \
311 flush_channel(dev, 0, 0, 0); \
312 if (priv->num_channels == 1) \
313 goto out; \
314 if (ch_done_mask & (1 << 2)) \
315 flush_channel(dev, 1, 0, 0); \
316 if (ch_done_mask & (1 << 4)) \
317 flush_channel(dev, 2, 0, 0); \
318 if (ch_done_mask & (1 << 6)) \
319 flush_channel(dev, 3, 0, 0); \
320 \
321out: \
322 /* At this point, all completed channels have been processed */ \
323 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 324 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 325 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
326 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
511d63cb 327 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 328}
c3e337f8
KP		 329DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
330DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
331DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
9c4a7965
KP		 332
333/*
334 * locate current (offending) descriptor
335 */
3e721aeb 336static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 337{
338 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 339 int tail = priv->chan[ch].tail;
9c4a7965
KP		 340 dma_addr_t cur_desc;
341
ad42d5fc 342 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 343
4b992628 344 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 345 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 346 if (tail == priv->chan[ch].tail) {
9c4a7965 347 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 348 return 0;
9c4a7965
KP		 349 }
350 }
351
3e721aeb 352 return priv->chan[ch].fifo[tail].desc->hdr;
9c4a7965
KP		 353}
354
355/*
356 * user diagnostics; report root cause of error based on execution unit status
357 */
3e721aeb 358static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 359{
360 struct talitos_private *priv = dev_get_drvdata(dev);
361 int i;
362
3e721aeb 363 if (!desc_hdr)
ad42d5fc 364 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 365
366 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 367 case DESC_HDR_SEL0_AFEU:
368 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
369 in_be32(priv->reg + TALITOS_AFEUISR),
370 in_be32(priv->reg + TALITOS_AFEUISR_LO));
371 break;
372 case DESC_HDR_SEL0_DEU:
373 dev_err(dev, "DEUISR 0x%08x_%08x\n",
374 in_be32(priv->reg + TALITOS_DEUISR),
375 in_be32(priv->reg + TALITOS_DEUISR_LO));
376 break;
377 case DESC_HDR_SEL0_MDEUA:
378 case DESC_HDR_SEL0_MDEUB:
379 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
380 in_be32(priv->reg + TALITOS_MDEUISR),
381 in_be32(priv->reg + TALITOS_MDEUISR_LO));
382 break;
383 case DESC_HDR_SEL0_RNG:
384 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
385 in_be32(priv->reg + TALITOS_RNGUISR),
386 in_be32(priv->reg + TALITOS_RNGUISR_LO));
387 break;
388 case DESC_HDR_SEL0_PKEU:
389 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
390 in_be32(priv->reg + TALITOS_PKEUISR),
391 in_be32(priv->reg + TALITOS_PKEUISR_LO));
392 break;
393 case DESC_HDR_SEL0_AESU:
394 dev_err(dev, "AESUISR 0x%08x_%08x\n",
395 in_be32(priv->reg + TALITOS_AESUISR),
396 in_be32(priv->reg + TALITOS_AESUISR_LO));
397 break;
398 case DESC_HDR_SEL0_CRCU:
399 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
400 in_be32(priv->reg + TALITOS_CRCUISR),
401 in_be32(priv->reg + TALITOS_CRCUISR_LO));
402 break;
403 case DESC_HDR_SEL0_KEU:
404 dev_err(dev, "KEUISR 0x%08x_%08x\n",
405 in_be32(priv->reg + TALITOS_KEUISR),
406 in_be32(priv->reg + TALITOS_KEUISR_LO));
407 break;
408 }
409
3e721aeb 410 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 411 case DESC_HDR_SEL1_MDEUA:
412 case DESC_HDR_SEL1_MDEUB:
413 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
414 in_be32(priv->reg + TALITOS_MDEUISR),
415 in_be32(priv->reg + TALITOS_MDEUISR_LO));
416 break;
417 case DESC_HDR_SEL1_CRCU:
418 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
419 in_be32(priv->reg + TALITOS_CRCUISR),
420 in_be32(priv->reg + TALITOS_CRCUISR_LO));
421 break;
422 }
423
424 for (i = 0; i < 8; i++)
425 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
427 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 428}
429
430/*
431 * recover from error interrupts
432 */
5e718a09 433static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 434{
9c4a7965
KP		 435 struct talitos_private *priv = dev_get_drvdata(dev);
436 unsigned int timeout = TALITOS_TIMEOUT;
437 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 438 u32 v, v_lo;
9c4a7965
KP		 439
440 for (ch = 0; ch < priv->num_channels; ch++) {
441 /* skip channels without errors */
442 if (!(isr & (1 << (ch * 2 + 1))))
443 continue;
444
445 error = -EINVAL;
446
ad42d5fc
KP		 447 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
448 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 449
450 if (v_lo & TALITOS_CCPSR_LO_DOF) {
451 dev_err(dev, "double fetch fifo overflow error\n");
452 error = -EAGAIN;
453 reset_ch = 1;
454 }
455 if (v_lo & TALITOS_CCPSR_LO_SOF) {
456 /* h/w dropped descriptor */
457 dev_err(dev, "single fetch fifo overflow error\n");
458 error = -EAGAIN;
459 }
460 if (v_lo & TALITOS_CCPSR_LO_MDTE)
461 dev_err(dev, "master data transfer error\n");
462 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
463 dev_err(dev, "s/g data length zero error\n");
464 if (v_lo & TALITOS_CCPSR_LO_FPZ)
465 dev_err(dev, "fetch pointer zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_IDH)
467 dev_err(dev, "illegal descriptor header error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IEU)
469 dev_err(dev, "invalid execution unit error\n");
470 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 471 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
9c4a7965
KP		 472 if (v_lo & TALITOS_CCPSR_LO_GB)
473 dev_err(dev, "gather boundary error\n");
474 if (v_lo & TALITOS_CCPSR_LO_GRL)
475 dev_err(dev, "gather return/length error\n");
476 if (v_lo & TALITOS_CCPSR_LO_SB)
477 dev_err(dev, "scatter boundary error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SRL)
479 dev_err(dev, "scatter return/length error\n");
480
481 flush_channel(dev, ch, error, reset_ch);
482
483 if (reset_ch) {
484 reset_channel(dev, ch);
485 } else {
ad42d5fc 486 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
9c4a7965 487 TALITOS_CCCR_CONT);
ad42d5fc
KP		 488 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
489 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
9c4a7965
KP		 490 TALITOS_CCCR_CONT) && --timeout)
491 cpu_relax();
492 if (timeout == 0) {
493 dev_err(dev, "failed to restart channel %d\n",
494 ch);
495 reset_dev = 1;
496 }
497 }
498 }
c3e337f8 499 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
9c4a7965
KP		 500 dev_err(dev, "done overflow, internal time out, or rngu error: "
501 "ISR 0x%08x_%08x\n", isr, isr_lo);
502
503 /* purge request queues */
504 for (ch = 0; ch < priv->num_channels; ch++)
505 flush_channel(dev, ch, -EIO, 1);
506
507 /* reset and reinitialize the device */
508 init_device(dev);
509 }
510}
511
c3e337f8
KP		 512#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
513static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
514{ \
515 struct device *dev = data; \
516 struct talitos_private *priv = dev_get_drvdata(dev); \
517 u32 isr, isr_lo; \
511d63cb 518 unsigned long flags; \
c3e337f8 519 \
511d63cb 520 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 521 isr = in_be32(priv->reg + TALITOS_ISR); \
522 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
523 /* Acknowledge interrupt */ \
524 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
525 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
526 \
511d63cb
HG		 527 if (unlikely(isr & ch_err_mask || isr_lo)) { \
528 spin_unlock_irqrestore(&priv->reg_lock, flags); \
529 talitos_error(dev, isr & ch_err_mask, isr_lo); \
530 } \
531 else { \
c3e337f8
KP		 532 if (likely(isr & ch_done_mask)) { \
533 /* mask further done interrupts. */ \
534 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
535 /* done_task will unmask done interrupts at exit */ \
536 tasklet_schedule(&priv->done_task[tlet]); \
537 } \
511d63cb
HG		 538 spin_unlock_irqrestore(&priv->reg_lock, flags); \
539 } \
c3e337f8
KP		 540 \
541 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
542 IRQ_NONE; \
9c4a7965 543}
c3e337f8
KP		 544DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
545DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
546DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
9c4a7965
KP		 547
548/*
549 * hwrng
550 */
551static int talitos_rng_data_present(struct hwrng *rng, int wait)
552{
553 struct device *dev = (struct device *)rng->priv;
554 struct talitos_private *priv = dev_get_drvdata(dev);
555 u32 ofl;
556 int i;
557
558 for (i = 0; i < 20; i++) {
559 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
560 TALITOS_RNGUSR_LO_OFL;
561 if (ofl || !wait)
562 break;
563 udelay(10);
564 }
565
566 return !!ofl;
567}
568
569static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
570{
571 struct device *dev = (struct device *)rng->priv;
572 struct talitos_private *priv = dev_get_drvdata(dev);
573
574 /* rng fifo requires 64-bit accesses */
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
576 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
577
578 return sizeof(u32);
579}
580
581static int talitos_rng_init(struct hwrng *rng)
582{
583 struct device *dev = (struct device *)rng->priv;
584 struct talitos_private *priv = dev_get_drvdata(dev);
585 unsigned int timeout = TALITOS_TIMEOUT;
586
587 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
588 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
589 && --timeout)
590 cpu_relax();
591 if (timeout == 0) {
592 dev_err(dev, "failed to reset rng hw\n");
593 return -ENODEV;
594 }
595
596 /* start generating */
597 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
598
599 return 0;
600}
601
602static int talitos_register_rng(struct device *dev)
603{
604 struct talitos_private *priv = dev_get_drvdata(dev);
605
606 priv->rng.name = dev_driver_string(dev),
607 priv->rng.init = talitos_rng_init,
608 priv->rng.data_present = talitos_rng_data_present,
609 priv->rng.data_read = talitos_rng_data_read,
610 priv->rng.priv = (unsigned long)dev;
611
612 return hwrng_register(&priv->rng);
613}
614
615static void talitos_unregister_rng(struct device *dev)
616{
617 struct talitos_private *priv = dev_get_drvdata(dev);
618
619 hwrng_unregister(&priv->rng);
620}
621
622/*
623 * crypto alg
624 */
625#define TALITOS_CRA_PRIORITY 3000
357fb605 626#define TALITOS_MAX_KEY_SIZE 96
3952f17e 627#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 628
497f2e6b 629#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 630
631struct talitos_ctx {
632 struct device *dev;
5228f0f7 633 int ch;
9c4a7965
KP		 634 __be32 desc_hdr_template;
635 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 636 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 637 unsigned int keylen;
638 unsigned int enckeylen;
639 unsigned int authkeylen;
640 unsigned int authsize;
641};
642
497f2e6b
LN		 643#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
644#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
645
646struct talitos_ahash_req_ctx {
60f208d7 647 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 648 unsigned int hw_context_size;
649 u8 buf[HASH_MAX_BLOCK_SIZE];
650 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 651 unsigned int swinit;
497f2e6b
LN		 652 unsigned int first;
653 unsigned int last;
654 unsigned int to_hash_later;
5e833bc4 655 u64 nbuf;
497f2e6b
LN		 656 struct scatterlist bufsl[2];
657 struct scatterlist *psrc;
658};
659
56af8cd4
LN		 660static int aead_setauthsize(struct crypto_aead *authenc,
661 unsigned int authsize)
9c4a7965
KP		 662{
663 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
664
665 ctx->authsize = authsize;
666
667 return 0;
668}
669
56af8cd4
LN		 670static int aead_setkey(struct crypto_aead *authenc,
671 const u8 *key, unsigned int keylen)
9c4a7965
KP		 672{
673 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
674 struct rtattr *rta = (void *)key;
675 struct crypto_authenc_key_param *param;
676 unsigned int authkeylen;
677 unsigned int enckeylen;
678
679 if (!RTA_OK(rta, keylen))
680 goto badkey;
681
682 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
683 goto badkey;
684
685 if (RTA_PAYLOAD(rta) < sizeof(*param))
686 goto badkey;
687
688 param = RTA_DATA(rta);
689 enckeylen = be32_to_cpu(param->enckeylen);
690
691 key += RTA_ALIGN(rta->rta_len);
692 keylen -= RTA_ALIGN(rta->rta_len);
693
694 if (keylen < enckeylen)
695 goto badkey;
696
697 authkeylen = keylen - enckeylen;
698
699 if (keylen > TALITOS_MAX_KEY_SIZE)
700 goto badkey;
701
702 memcpy(&ctx->key, key, keylen);
703
704 ctx->keylen = keylen;
705 ctx->enckeylen = enckeylen;
706 ctx->authkeylen = authkeylen;
707
708 return 0;
709
710badkey:
711 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
712 return -EINVAL;
713}
714
715/*
56af8cd4 716 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 717 * @src_nents: number of segments in input scatterlist
718 * @dst_nents: number of segments in output scatterlist
719 * @dma_len: length of dma mapped link_tbl space
720 * @dma_link_tbl: bus physical address of link_tbl
721 * @desc: h/w descriptor
722 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
723 *
724 * if decrypting (with authcheck), or either one of src_nents or dst_nents
725 * is greater than 1, an integrity check value is concatenated to the end
726 * of link_tbl data
727 */
56af8cd4 728struct talitos_edesc {
9c4a7965
KP		 729 int src_nents;
730 int dst_nents;
4de9d0b5
LN		 731 int src_is_chained;
732 int dst_is_chained;
9c4a7965
KP		 733 int dma_len;
734 dma_addr_t dma_link_tbl;
735 struct talitos_desc desc;
736 struct talitos_ptr link_tbl[0];
737};
738
4de9d0b5
LN		 739static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
740 unsigned int nents, enum dma_data_direction dir,
741 int chained)
742{
743 if (unlikely(chained))
744 while (sg) {
745 dma_map_sg(dev, sg, 1, dir);
746 sg = scatterwalk_sg_next(sg);
747 }
748 else
749 dma_map_sg(dev, sg, nents, dir);
750 return nents;
751}
752
753static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
754 enum dma_data_direction dir)
755{
756 while (sg) {
757 dma_unmap_sg(dev, sg, 1, dir);
758 sg = scatterwalk_sg_next(sg);
759 }
760}
761
762static void talitos_sg_unmap(struct device *dev,
763 struct talitos_edesc *edesc,
764 struct scatterlist *src,
765 struct scatterlist *dst)
766{
767 unsigned int src_nents = edesc->src_nents ? : 1;
768 unsigned int dst_nents = edesc->dst_nents ? : 1;
769
770 if (src != dst) {
771 if (edesc->src_is_chained)
772 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
773 else
774 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
775
497f2e6b
LN		 776 if (dst) {
777 if (edesc->dst_is_chained)
778 talitos_unmap_sg_chain(dev, dst,
779 DMA_FROM_DEVICE);
780 else
781 dma_unmap_sg(dev, dst, dst_nents,
782 DMA_FROM_DEVICE);
783 }
4de9d0b5
LN		 784 } else
785 if (edesc->src_is_chained)
786 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
787 else
788 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
789}
790
9c4a7965 791static void ipsec_esp_unmap(struct device *dev,
56af8cd4 792 struct talitos_edesc *edesc,
9c4a7965
KP		 793 struct aead_request *areq)
794{
795 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
796 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
797 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
798 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
799
800 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
801
4de9d0b5 802 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 803
804 if (edesc->dma_len)
805 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
806 DMA_BIDIRECTIONAL);
807}
808
809/*
810 * ipsec_esp descriptor callbacks
811 */
812static void ipsec_esp_encrypt_done(struct device *dev,
813 struct talitos_desc *desc, void *context,
814 int err)
815{
816 struct aead_request *areq = context;
9c4a7965
KP		 817 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
818 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 819 struct talitos_edesc *edesc;
9c4a7965
KP		 820 struct scatterlist *sg;
821 void *icvdata;
822
19bbbc63
KP		 823 edesc = container_of(desc, struct talitos_edesc, desc);
824
9c4a7965
KP		 825 ipsec_esp_unmap(dev, edesc, areq);
826
827 /* copy the generated ICV to dst */
60542505 828 if (edesc->dst_nents) {
9c4a7965 829 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 830 edesc->dst_nents + 2];
9c4a7965
KP		 831 sg = sg_last(areq->dst, edesc->dst_nents);
832 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
833 icvdata, ctx->authsize);
834 }
835
836 kfree(edesc);
837
838 aead_request_complete(areq, err);
839}
840
fe5720e2 841static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 842 struct talitos_desc *desc,
843 void *context, int err)
9c4a7965
KP		 844{
845 struct aead_request *req = context;
9c4a7965
KP		 846 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
847 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 848 struct talitos_edesc *edesc;
9c4a7965
KP		 849 struct scatterlist *sg;
850 void *icvdata;
851
19bbbc63
KP		 852 edesc = container_of(desc, struct talitos_edesc, desc);
853
9c4a7965
KP		 854 ipsec_esp_unmap(dev, edesc, req);
855
856 if (!err) {
857 /* auth check */
858 if (edesc->dma_len)
859 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 860 edesc->dst_nents + 2];
9c4a7965
KP		 861 else
862 icvdata = &edesc->link_tbl[0];
863
864 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
865 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
866 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
867 }
868
869 kfree(edesc);
870
871 aead_request_complete(req, err);
872}
873
fe5720e2 874static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 875 struct talitos_desc *desc,
876 void *context, int err)
fe5720e2
KP		 877{
878 struct aead_request *req = context;
19bbbc63
KP		 879 struct talitos_edesc *edesc;
880
881 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 882
883 ipsec_esp_unmap(dev, edesc, req);
884
885 /* check ICV auth status */
e938e465
KP		 886 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
887 DESC_HDR_LO_ICCR1_PASS))
888 err = -EBADMSG;
fe5720e2
KP		 889
890 kfree(edesc);
891
892 aead_request_complete(req, err);
893}
894
9c4a7965
KP		 895/*
896 * convert scatterlist to SEC h/w link table format
897 * stop at cryptlen bytes
898 */
70bcaca7 899static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 900 int cryptlen, struct talitos_ptr *link_tbl_ptr)
901{
70bcaca7
LN		 902 int n_sg = sg_count;
903
904 while (n_sg--) {
81eb024c 905 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 906 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
907 link_tbl_ptr->j_extent = 0;
908 link_tbl_ptr++;
909 cryptlen -= sg_dma_len(sg);
4de9d0b5 910 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 911 }
912
70bcaca7 913 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 914 link_tbl_ptr--;
c0e741d4 915 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 916 /* Empty this entry, and move to previous one */
917 cryptlen += be16_to_cpu(link_tbl_ptr->len);
918 link_tbl_ptr->len = 0;
919 sg_count--;
920 link_tbl_ptr--;
921 }
9c4a7965
KP		 922 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
923 + cryptlen);
924
925 /* tag end of link table */
926 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 927
928 return sg_count;
9c4a7965
KP		 929}
930
931/*
932 * fill in and submit ipsec_esp descriptor
933 */
56af8cd4 934static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 935 u8 *giv, u64 seq,
936 void (*callback) (struct device *dev,
937 struct talitos_desc *desc,
938 void *context, int error))
939{
940 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
941 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
942 struct device *dev = ctx->dev;
943 struct talitos_desc *desc = &edesc->desc;
944 unsigned int cryptlen = areq->cryptlen;
945 unsigned int authsize = ctx->authsize;
e41256f1 946 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 947 int sg_count, ret;
fe5720e2 948 int sg_link_tbl_len;
9c4a7965
KP		 949
950 /* hmac key */
951 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
952 0, DMA_TO_DEVICE);
953 /* hmac data */
e41256f1
KP		 954 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
955 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 956 /* cipher iv */
9c4a7965
KP		 957 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
958 DMA_TO_DEVICE);
959
960 /* cipher key */
961 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
962 (char *)&ctx->key + ctx->authkeylen, 0,
963 DMA_TO_DEVICE);
964
965 /*
966 * cipher in
967 * map and adjust cipher len to aead request cryptlen.
968 * extent is bytes of HMAC postpended to ciphertext,
969 * typically 12 for ipsec
970 */
971 desc->ptr[4].len = cpu_to_be16(cryptlen);
972 desc->ptr[4].j_extent = authsize;
973
e938e465
KP		 974 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
975 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
976 : DMA_TO_DEVICE,
4de9d0b5 977 edesc->src_is_chained);
9c4a7965
KP		 978
979 if (sg_count == 1) {
81eb024c 980 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 981 } else {
fe5720e2
KP		 982 sg_link_tbl_len = cryptlen;
983
962a9c99 984 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 985 sg_link_tbl_len = cryptlen + authsize;
e938e465 986
fe5720e2 987 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 988 &edesc->link_tbl[0]);
989 if (sg_count > 1) {
990 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 991 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 992 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
993 edesc->dma_len,
994 DMA_BIDIRECTIONAL);
70bcaca7
LN		 995 } else {
996 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 997 to_talitos_ptr(&desc->ptr[4],
998 sg_dma_address(areq->src));
70bcaca7 999 }
9c4a7965
KP		 1000 }
1001
1002 /* cipher out */
1003 desc->ptr[5].len = cpu_to_be16(cryptlen);
1004 desc->ptr[5].j_extent = authsize;
1005
e938e465 1006 if (areq->src != areq->dst)
4de9d0b5
LN		 1007 sg_count = talitos_map_sg(dev, areq->dst,
1008 edesc->dst_nents ? : 1,
1009 DMA_FROM_DEVICE,
1010 edesc->dst_is_chained);
9c4a7965
KP		 1011
1012 if (sg_count == 1) {
81eb024c 1013 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1014 } else {
1015 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1016 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1017
81eb024c
KP		 1018 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1019 (edesc->src_nents + 1) *
1020 sizeof(struct talitos_ptr));
fe5720e2
KP		 1021 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1022 link_tbl_ptr);
1023
f3c85bc1 1024 /* Add an entry to the link table for ICV data */
9c4a7965 1025 link_tbl_ptr += sg_count - 1;
9c4a7965 1026 link_tbl_ptr->j_extent = 0;
f3c85bc1 1027 sg_count++;
9c4a7965
KP		 1028 link_tbl_ptr++;
1029 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1030 link_tbl_ptr->len = cpu_to_be16(authsize);
1031
1032 /* icv data follows link tables */
81eb024c
KP		 1033 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1034 (edesc->src_nents + edesc->dst_nents + 2) *
1035 sizeof(struct talitos_ptr));
9c4a7965
KP		 1036 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1037 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1038 edesc->dma_len, DMA_BIDIRECTIONAL);
1039 }
1040
1041 /* iv out */
1042 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1043 DMA_FROM_DEVICE);
1044
5228f0f7 1045 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1046 if (ret != -EINPROGRESS) {
1047 ipsec_esp_unmap(dev, edesc, areq);
1048 kfree(edesc);
1049 }
1050 return ret;
9c4a7965
KP		 1051}
1052
9c4a7965
KP		 1053/*
1054 * derive number of elements in scatterlist
1055 */
4de9d0b5 1056static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1057{
1058 struct scatterlist *sg = sg_list;
1059 int sg_nents = 0;
1060
4de9d0b5
LN		 1061 *chained = 0;
1062 while (nbytes > 0) {
9c4a7965
KP		 1063 sg_nents++;
1064 nbytes -= sg->length;
4de9d0b5
LN		 1065 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1066 *chained = 1;
1067 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1068 }
1069
1070 return sg_nents;
1071}
1072
497f2e6b
LN		 1073/**
1074 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1075 * @sgl: The SG list
1076 * @nents: Number of SG entries
1077 * @buf: Where to copy to
1078 * @buflen: The number of bytes to copy
1079 * @skip: The number of bytes to skip before copying.
1080 * Note: skip + buflen should equal SG total size.
1081 *
1082 * Returns the number of copied bytes.
1083 *
1084 **/
1085static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1086 void *buf, size_t buflen, unsigned int skip)
1087{
1088 unsigned int offset = 0;
1089 unsigned int boffset = 0;
1090 struct sg_mapping_iter miter;
1091 unsigned long flags;
1092 unsigned int sg_flags = SG_MITER_ATOMIC;
1093 size_t total_buffer = buflen + skip;
1094
1095 sg_flags |= SG_MITER_FROM_SG;
1096
1097 sg_miter_start(&miter, sgl, nents, sg_flags);
1098
1099 local_irq_save(flags);
1100
1101 while (sg_miter_next(&miter) && offset < total_buffer) {
1102 unsigned int len;
1103 unsigned int ignore;
1104
1105 if ((offset + miter.length) > skip) {
1106 if (offset < skip) {
1107 /* Copy part of this segment */
1108 ignore = skip - offset;
1109 len = miter.length - ignore;
7260042b
LN		 1110 if (boffset + len > buflen)
1111 len = buflen - boffset;
497f2e6b
LN		 1112 memcpy(buf + boffset, miter.addr + ignore, len);
1113 } else {
7260042b 1114 /* Copy all of this segment (up to buflen) */
497f2e6b 1115 len = miter.length;
7260042b
LN		 1116 if (boffset + len > buflen)
1117 len = buflen - boffset;
497f2e6b
LN		 1118 memcpy(buf + boffset, miter.addr, len);
1119 }
1120 boffset += len;
1121 }
1122 offset += miter.length;
1123 }
1124
1125 sg_miter_stop(&miter);
1126
1127 local_irq_restore(flags);
1128 return boffset;
1129}
1130
9c4a7965 1131/*
56af8cd4 1132 * allocate and map the extended descriptor
9c4a7965 1133 */
4de9d0b5
LN		 1134static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1135 struct scatterlist *src,
1136 struct scatterlist *dst,
1137 unsigned int cryptlen,
1138 unsigned int authsize,
1139 int icv_stashing,
1140 u32 cryptoflags)
9c4a7965 1141{
56af8cd4 1142 struct talitos_edesc *edesc;
9c4a7965 1143 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1144 int src_chained, dst_chained = 0;
1145 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1146 GFP_ATOMIC;
9c4a7965 1147
4de9d0b5
LN		 1148 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1149 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1150 return ERR_PTR(-EINVAL);
1151 }
1152
4de9d0b5 1153 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1154 src_nents = (src_nents == 1) ? 0 : src_nents;
1155
602499a3 1156 if (!dst) {
497f2e6b 1157 dst_nents = 0;
9c4a7965 1158 } else {
497f2e6b
LN		 1159 if (dst == src) {
1160 dst_nents = src_nents;
1161 } else {
1162 dst_nents = sg_count(dst, cryptlen + authsize,
1163 &dst_chained);
1164 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1165 }
9c4a7965
KP		 1166 }
1167
1168 /*
1169 * allocate space for base edesc plus the link tables,
f3c85bc1 1170 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1171 * and the ICV data itself
1172 */
56af8cd4 1173 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1174 if (src_nents || dst_nents) {
f3c85bc1 1175 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1176 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1177 alloc_len += dma_len;
1178 } else {
1179 dma_len = 0;
4de9d0b5 1180 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1181 }
1182
586725f8 1183 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1184 if (!edesc) {
4de9d0b5 1185 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1186 return ERR_PTR(-ENOMEM);
1187 }
1188
1189 edesc->src_nents = src_nents;
1190 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1191 edesc->src_is_chained = src_chained;
1192 edesc->dst_is_chained = dst_chained;
9c4a7965 1193 edesc->dma_len = dma_len;
497f2e6b
LN		 1194 if (dma_len)
1195 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1196 edesc->dma_len,
1197 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1198
1199 return edesc;
1200}
1201
4de9d0b5
LN		 1202static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1203 int icv_stashing)
1204{
1205 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1206 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1207
602499a3 1208 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
4de9d0b5
LN		 1209 areq->cryptlen, ctx->authsize, icv_stashing,
1210 areq->base.flags);
1211}
1212
56af8cd4 1213static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1214{
1215 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1216 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1217 struct talitos_edesc *edesc;
9c4a7965
KP		 1218
1219 /* allocate extended descriptor */
4de9d0b5 1220 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1221 if (IS_ERR(edesc))
1222 return PTR_ERR(edesc);
1223
1224 /* set encrypt */
70bcaca7 1225 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1226
1227 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1228}
1229
56af8cd4 1230static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1231{
1232 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1233 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1234 unsigned int authsize = ctx->authsize;
fe5720e2 1235 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1236 struct talitos_edesc *edesc;
9c4a7965
KP		 1237 struct scatterlist *sg;
1238 void *icvdata;
1239
1240 req->cryptlen -= authsize;
1241
1242 /* allocate extended descriptor */
4de9d0b5 1243 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1244 if (IS_ERR(edesc))
1245 return PTR_ERR(edesc);
1246
fe5720e2 1247 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1248 ((!edesc->src_nents && !edesc->dst_nents) ||
1249 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1250
fe5720e2 1251 /* decrypt and check the ICV */
e938e465
KP		 1252 edesc->desc.hdr = ctx->desc_hdr_template |
1253 DESC_HDR_DIR_INBOUND |
fe5720e2 1254 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1255
fe5720e2
KP		 1256 /* reset integrity check result bits */
1257 edesc->desc.hdr_lo = 0;
9c4a7965 1258
e938e465
KP		 1259 return ipsec_esp(edesc, req, NULL, 0,
1260 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1261
e938e465 1262 }
fe5720e2 1263
e938e465
KP		 1264 /* Have to check the ICV with software */
1265 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1266
e938e465
KP		 1267 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1268 if (edesc->dma_len)
1269 icvdata = &edesc->link_tbl[edesc->src_nents +
1270 edesc->dst_nents + 2];
1271 else
1272 icvdata = &edesc->link_tbl[0];
fe5720e2 1273
e938e465 1274 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1275
e938e465
KP		 1276 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1277 ctx->authsize);
fe5720e2 1278
e938e465 1279 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1280}
1281
56af8cd4 1282static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1283{
1284 struct aead_request *areq = &req->areq;
1285 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1286 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1287 struct talitos_edesc *edesc;
9c4a7965
KP		 1288
1289 /* allocate extended descriptor */
4de9d0b5 1290 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1291 if (IS_ERR(edesc))
1292 return PTR_ERR(edesc);
1293
1294 /* set encrypt */
70bcaca7 1295 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1296
1297 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1298 /* avoid consecutive packets going out with same IV */
1299 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1300
1301 return ipsec_esp(edesc, areq, req->giv, req->seq,
1302 ipsec_esp_encrypt_done);
1303}
1304
4de9d0b5
LN		 1305static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1306 const u8 *key, unsigned int keylen)
1307{
1308 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
4de9d0b5
LN		 1309
1310 memcpy(&ctx->key, key, keylen);
1311 ctx->keylen = keylen;
1312
1313 return 0;
4de9d0b5
LN		 1314}
1315
1316static void common_nonsnoop_unmap(struct device *dev,
1317 struct talitos_edesc *edesc,
1318 struct ablkcipher_request *areq)
1319{
1320 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1321 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1322 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1323
1324 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1325
1326 if (edesc->dma_len)
1327 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1328 DMA_BIDIRECTIONAL);
1329}
1330
1331static void ablkcipher_done(struct device *dev,
1332 struct talitos_desc *desc, void *context,
1333 int err)
1334{
1335 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1336 struct talitos_edesc *edesc;
1337
1338 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1339
1340 common_nonsnoop_unmap(dev, edesc, areq);
1341
1342 kfree(edesc);
1343
1344 areq->base.complete(&areq->base, err);
1345}
1346
1347static int common_nonsnoop(struct talitos_edesc *edesc,
1348 struct ablkcipher_request *areq,
4de9d0b5
LN		 1349 void (*callback) (struct device *dev,
1350 struct talitos_desc *desc,
1351 void *context, int error))
1352{
1353 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1354 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1355 struct device *dev = ctx->dev;
1356 struct talitos_desc *desc = &edesc->desc;
1357 unsigned int cryptlen = areq->nbytes;
1358 unsigned int ivsize;
1359 int sg_count, ret;
1360
1361 /* first DWORD empty */
1362 desc->ptr[0].len = 0;
81eb024c 1363 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1364 desc->ptr[0].j_extent = 0;
1365
1366 /* cipher iv */
1367 ivsize = crypto_ablkcipher_ivsize(cipher);
febec542 1368 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0,
4de9d0b5
LN		 1369 DMA_TO_DEVICE);
1370
1371 /* cipher key */
1372 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1373 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1374
1375 /*
1376 * cipher in
1377 */
1378 desc->ptr[3].len = cpu_to_be16(cryptlen);
1379 desc->ptr[3].j_extent = 0;
1380
1381 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1382 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1383 : DMA_TO_DEVICE,
1384 edesc->src_is_chained);
1385
1386 if (sg_count == 1) {
81eb024c 1387 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1388 } else {
1389 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1390 &edesc->link_tbl[0]);
1391 if (sg_count > 1) {
81eb024c 1392 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1393 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1394 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1395 edesc->dma_len,
1396 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1397 } else {
1398 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1399 to_talitos_ptr(&desc->ptr[3],
1400 sg_dma_address(areq->src));
4de9d0b5
LN		 1401 }
1402 }
1403
1404 /* cipher out */
1405 desc->ptr[4].len = cpu_to_be16(cryptlen);
1406 desc->ptr[4].j_extent = 0;
1407
1408 if (areq->src != areq->dst)
1409 sg_count = talitos_map_sg(dev, areq->dst,
1410 edesc->dst_nents ? : 1,
1411 DMA_FROM_DEVICE,
1412 edesc->dst_is_chained);
1413
1414 if (sg_count == 1) {
81eb024c 1415 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1416 } else {
1417 struct talitos_ptr *link_tbl_ptr =
1418 &edesc->link_tbl[edesc->src_nents + 1];
1419
81eb024c
KP		 1420 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1421 (edesc->src_nents + 1) *
1422 sizeof(struct talitos_ptr));
4de9d0b5 1423 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1424 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1425 link_tbl_ptr);
1426 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1427 edesc->dma_len, DMA_BIDIRECTIONAL);
1428 }
1429
1430 /* iv out */
1431 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1432 DMA_FROM_DEVICE);
1433
1434 /* last DWORD empty */
1435 desc->ptr[6].len = 0;
81eb024c 1436 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1437 desc->ptr[6].j_extent = 0;
1438
5228f0f7 1439 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1440 if (ret != -EINPROGRESS) {
1441 common_nonsnoop_unmap(dev, edesc, areq);
1442 kfree(edesc);
1443 }
1444 return ret;
1445}
1446
e938e465
KP		 1447static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1448 areq)
4de9d0b5
LN		 1449{
1450 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1451 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1452
602499a3
HG		 1453 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, areq->nbytes,
1454 0, 0, areq->base.flags);
4de9d0b5
LN		 1455}
1456
1457static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1458{
1459 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1460 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1461 struct talitos_edesc *edesc;
1462
1463 /* allocate extended descriptor */
1464 edesc = ablkcipher_edesc_alloc(areq);
1465 if (IS_ERR(edesc))
1466 return PTR_ERR(edesc);
1467
1468 /* set encrypt */
1469 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1470
febec542 1471 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1472}
1473
1474static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1475{
1476 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1477 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1478 struct talitos_edesc *edesc;
1479
1480 /* allocate extended descriptor */
1481 edesc = ablkcipher_edesc_alloc(areq);
1482 if (IS_ERR(edesc))
1483 return PTR_ERR(edesc);
1484
1485 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1486
febec542 1487 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1488}
1489
497f2e6b
LN		 1490static void common_nonsnoop_hash_unmap(struct device *dev,
1491 struct talitos_edesc *edesc,
1492 struct ahash_request *areq)
1493{
1494 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1495
1496 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1497
1498 /* When using hashctx-in, must unmap it. */
1499 if (edesc->desc.ptr[1].len)
1500 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1501 DMA_TO_DEVICE);
1502
1503 if (edesc->desc.ptr[2].len)
1504 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1505 DMA_TO_DEVICE);
1506
1507 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1508
1509 if (edesc->dma_len)
1510 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1511 DMA_BIDIRECTIONAL);
1512
1513}
1514
1515static void ahash_done(struct device *dev,
1516 struct talitos_desc *desc, void *context,
1517 int err)
1518{
1519 struct ahash_request *areq = context;
1520 struct talitos_edesc *edesc =
1521 container_of(desc, struct talitos_edesc, desc);
1522 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1523
1524 if (!req_ctx->last && req_ctx->to_hash_later) {
1525 /* Position any partial block for next update/final/finup */
1526 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1527 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1528 }
1529 common_nonsnoop_hash_unmap(dev, edesc, areq);
1530
1531 kfree(edesc);
1532
1533 areq->base.complete(&areq->base, err);
1534}
1535
1536static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1537 struct ahash_request *areq, unsigned int length,
1538 void (*callback) (struct device *dev,
1539 struct talitos_desc *desc,
1540 void *context, int error))
1541{
1542 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1543 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1544 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1545 struct device *dev = ctx->dev;
1546 struct talitos_desc *desc = &edesc->desc;
1547 int sg_count, ret;
1548
1549 /* first DWORD empty */
1550 desc->ptr[0] = zero_entry;
1551
60f208d7
KP		 1552 /* hash context in */
1553 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1554 map_single_talitos_ptr(dev, &desc->ptr[1],
1555 req_ctx->hw_context_size,
1556 (char *)req_ctx->hw_context, 0,
1557 DMA_TO_DEVICE);
60f208d7 1558 req_ctx->swinit = 0;
497f2e6b
LN		 1559 } else {
1560 desc->ptr[1] = zero_entry;
1561 /* Indicate next op is not the first. */
1562 req_ctx->first = 0;
1563 }
1564
1565 /* HMAC key */
1566 if (ctx->keylen)
1567 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1568 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1569 else
1570 desc->ptr[2] = zero_entry;
1571
1572 /*
1573 * data in
1574 */
1575 desc->ptr[3].len = cpu_to_be16(length);
1576 desc->ptr[3].j_extent = 0;
1577
1578 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1579 edesc->src_nents ? : 1,
1580 DMA_TO_DEVICE,
1581 edesc->src_is_chained);
1582
1583 if (sg_count == 1) {
1584 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1585 } else {
1586 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1587 &edesc->link_tbl[0]);
1588 if (sg_count > 1) {
1589 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1590 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1591 dma_sync_single_for_device(ctx->dev,
1592 edesc->dma_link_tbl,
1593 edesc->dma_len,
1594 DMA_BIDIRECTIONAL);
1595 } else {
1596 /* Only one segment now, so no link tbl needed */
1597 to_talitos_ptr(&desc->ptr[3],
1598 sg_dma_address(req_ctx->psrc));
1599 }
1600 }
1601
1602 /* fifth DWORD empty */
1603 desc->ptr[4] = zero_entry;
1604
1605 /* hash/HMAC out -or- hash context out */
1606 if (req_ctx->last)
1607 map_single_talitos_ptr(dev, &desc->ptr[5],
1608 crypto_ahash_digestsize(tfm),
1609 areq->result, 0, DMA_FROM_DEVICE);
1610 else
1611 map_single_talitos_ptr(dev, &desc->ptr[5],
1612 req_ctx->hw_context_size,
1613 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1614
1615 /* last DWORD empty */
1616 desc->ptr[6] = zero_entry;
1617
5228f0f7 1618 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1619 if (ret != -EINPROGRESS) {
1620 common_nonsnoop_hash_unmap(dev, edesc, areq);
1621 kfree(edesc);
1622 }
1623 return ret;
1624}
1625
1626static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1627 unsigned int nbytes)
1628{
1629 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1630 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1631 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1632
602499a3
HG		 1633 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, nbytes, 0, 0,
1634 areq->base.flags);
497f2e6b
LN		 1635}
1636
1637static int ahash_init(struct ahash_request *areq)
1638{
1639 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1640 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1641
1642 /* Initialize the context */
5e833bc4 1643 req_ctx->nbuf = 0;
60f208d7
KP		 1644 req_ctx->first = 1; /* first indicates h/w must init its context */
1645 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1646 req_ctx->hw_context_size =
1647 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1648 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1649 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1650
1651 return 0;
1652}
1653
60f208d7
KP		 1654/*
1655 * on h/w without explicit sha224 support, we initialize h/w context
1656 * manually with sha224 constants, and tell it to run sha256.
1657 */
1658static int ahash_init_sha224_swinit(struct ahash_request *areq)
1659{
1660 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1661
1662 ahash_init(areq);
1663 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1664
a752447a
KP		 1665 req_ctx->hw_context[0] = SHA224_H0;
1666 req_ctx->hw_context[1] = SHA224_H1;
1667 req_ctx->hw_context[2] = SHA224_H2;
1668 req_ctx->hw_context[3] = SHA224_H3;
1669 req_ctx->hw_context[4] = SHA224_H4;
1670 req_ctx->hw_context[5] = SHA224_H5;
1671 req_ctx->hw_context[6] = SHA224_H6;
1672 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1673
1674 /* init 64-bit count */
1675 req_ctx->hw_context[8] = 0;
1676 req_ctx->hw_context[9] = 0;
1677
1678 return 0;
1679}
1680
497f2e6b
LN		 1681static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1682{
1683 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1684 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1685 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1686 struct talitos_edesc *edesc;
1687 unsigned int blocksize =
1688 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1689 unsigned int nbytes_to_hash;
1690 unsigned int to_hash_later;
5e833bc4 1691 unsigned int nsg;
497f2e6b
LN		 1692 int chained;
1693
5e833bc4
LN		 1694 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1695 /* Buffer up to one whole block */
497f2e6b
LN		 1696 sg_copy_to_buffer(areq->src,
1697 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1698 req_ctx->buf + req_ctx->nbuf, nbytes);
1699 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1700 return 0;
1701 }
1702
5e833bc4
LN		 1703 /* At least (blocksize + 1) bytes are available to hash */
1704 nbytes_to_hash = nbytes + req_ctx->nbuf;
1705 to_hash_later = nbytes_to_hash & (blocksize - 1);
1706
1707 if (req_ctx->last)
1708 to_hash_later = 0;
1709 else if (to_hash_later)
1710 /* There is a partial block. Hash the full block(s) now */
1711 nbytes_to_hash -= to_hash_later;
1712 else {
1713 /* Keep one block buffered */
1714 nbytes_to_hash -= blocksize;
1715 to_hash_later = blocksize;
1716 }
1717
1718 /* Chain in any previously buffered data */
1719 if (req_ctx->nbuf) {
1720 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1721 sg_init_table(req_ctx->bufsl, nsg);
1722 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1723 if (nsg > 1)
1724 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1725 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1726 } else
497f2e6b 1727 req_ctx->psrc = areq->src;
5e833bc4
LN		 1728
1729 if (to_hash_later) {
1730 int nents = sg_count(areq->src, nbytes, &chained);
1731 sg_copy_end_to_buffer(areq->src, nents,
1732 req_ctx->bufnext,
1733 to_hash_later,
1734 nbytes - to_hash_later);
497f2e6b 1735 }
5e833bc4 1736 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1737
5e833bc4 1738 /* Allocate extended descriptor */
497f2e6b
LN		 1739 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1740 if (IS_ERR(edesc))
1741 return PTR_ERR(edesc);
1742
1743 edesc->desc.hdr = ctx->desc_hdr_template;
1744
1745 /* On last one, request SEC to pad; otherwise continue */
1746 if (req_ctx->last)
1747 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1748 else
1749 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1750
60f208d7
KP		 1751 /* request SEC to INIT hash. */
1752 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1753 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1754
1755 /* When the tfm context has a keylen, it's an HMAC.
1756 * A first or last (ie. not middle) descriptor must request HMAC.
1757 */
1758 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1759 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1760
1761 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1762 ahash_done);
1763}
1764
1765static int ahash_update(struct ahash_request *areq)
1766{
1767 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1768
1769 req_ctx->last = 0;
1770
1771 return ahash_process_req(areq, areq->nbytes);
1772}
1773
1774static int ahash_final(struct ahash_request *areq)
1775{
1776 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1777
1778 req_ctx->last = 1;
1779
1780 return ahash_process_req(areq, 0);
1781}
1782
1783static int ahash_finup(struct ahash_request *areq)
1784{
1785 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1786
1787 req_ctx->last = 1;
1788
1789 return ahash_process_req(areq, areq->nbytes);
1790}
1791
1792static int ahash_digest(struct ahash_request *areq)
1793{
1794 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1795 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1796
60f208d7 1797 ahash->init(areq);
497f2e6b
LN		 1798 req_ctx->last = 1;
1799
1800 return ahash_process_req(areq, areq->nbytes);
1801}
1802
79b3a418
LN		 1803struct keyhash_result {
1804 struct completion completion;
1805 int err;
1806};
1807
1808static void keyhash_complete(struct crypto_async_request *req, int err)
1809{
1810 struct keyhash_result *res = req->data;
1811
1812 if (err == -EINPROGRESS)
1813 return;
1814
1815 res->err = err;
1816 complete(&res->completion);
1817}
1818
1819static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1820 u8 *hash)
1821{
1822 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1823
1824 struct scatterlist sg[1];
1825 struct ahash_request *req;
1826 struct keyhash_result hresult;
1827 int ret;
1828
1829 init_completion(&hresult.completion);
1830
1831 req = ahash_request_alloc(tfm, GFP_KERNEL);
1832 if (!req)
1833 return -ENOMEM;
1834
1835 /* Keep tfm keylen == 0 during hash of the long key */
1836 ctx->keylen = 0;
1837 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1838 keyhash_complete, &hresult);
1839
1840 sg_init_one(&sg[0], key, keylen);
1841
1842 ahash_request_set_crypt(req, sg, hash, keylen);
1843 ret = crypto_ahash_digest(req);
1844 switch (ret) {
1845 case 0:
1846 break;
1847 case -EINPROGRESS:
1848 case -EBUSY:
1849 ret = wait_for_completion_interruptible(
1850 &hresult.completion);
1851 if (!ret)
1852 ret = hresult.err;
1853 break;
1854 default:
1855 break;
1856 }
1857 ahash_request_free(req);
1858
1859 return ret;
1860}
1861
1862static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1863 unsigned int keylen)
1864{
1865 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1866 unsigned int blocksize =
1867 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1868 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1869 unsigned int keysize = keylen;
1870 u8 hash[SHA512_DIGEST_SIZE];
1871 int ret;
1872
1873 if (keylen <= blocksize)
1874 memcpy(ctx->key, key, keysize);
1875 else {
1876 /* Must get the hash of the long key */
1877 ret = keyhash(tfm, key, keylen, hash);
1878
1879 if (ret) {
1880 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1881 return -EINVAL;
1882 }
1883
1884 keysize = digestsize;
1885 memcpy(ctx->key, hash, digestsize);
1886 }
1887
1888 ctx->keylen = keysize;
1889
1890 return 0;
1891}
1892
1893
9c4a7965 1894struct talitos_alg_template {
d5e4aaef
LN		 1895 u32 type;
1896 union {
1897 struct crypto_alg crypto;
acbf7c62 1898 struct ahash_alg hash;
d5e4aaef 1899 } alg;
9c4a7965
KP		 1900 __be32 desc_hdr_template;
1901};
1902
1903static struct talitos_alg_template driver_algs[] = {
56af8cd4 1904 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1905 { .type = CRYPTO_ALG_TYPE_AEAD,
1906 .alg.crypto = {
56af8cd4
LN		 1907 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1908 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1909 .cra_blocksize = AES_BLOCK_SIZE,
1910 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1911 .cra_aead = {
56af8cd4
LN		 1912 .ivsize = AES_BLOCK_SIZE,
1913 .maxauthsize = SHA1_DIGEST_SIZE,
1914 }
1915 },
9c4a7965
KP		 1916 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1917 DESC_HDR_SEL0_AESU |
1918 DESC_HDR_MODE0_AESU_CBC |
1919 DESC_HDR_SEL1_MDEUA |
1920 DESC_HDR_MODE1_MDEU_INIT |
1921 DESC_HDR_MODE1_MDEU_PAD |
1922 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1923 },
d5e4aaef
LN		 1924 { .type = CRYPTO_ALG_TYPE_AEAD,
1925 .alg.crypto = {
56af8cd4
LN		 1926 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1927 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1928 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1929 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1930 .cra_aead = {
56af8cd4
LN		 1931 .ivsize = DES3_EDE_BLOCK_SIZE,
1932 .maxauthsize = SHA1_DIGEST_SIZE,
1933 }
1934 },
70bcaca7
LN		 1935 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1936 DESC_HDR_SEL0_DEU |
1937 DESC_HDR_MODE0_DEU_CBC |
1938 DESC_HDR_MODE0_DEU_3DES |
1939 DESC_HDR_SEL1_MDEUA |
1940 DESC_HDR_MODE1_MDEU_INIT |
1941 DESC_HDR_MODE1_MDEU_PAD |
1942 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1943 },
357fb605
HG		 1944 { .type = CRYPTO_ALG_TYPE_AEAD,
1945 .alg.crypto = {
1946 .cra_name = "authenc(hmac(sha224),cbc(aes))",
1947 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1948 .cra_blocksize = AES_BLOCK_SIZE,
1949 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 1950 .cra_aead = {
357fb605
HG		 1951 .ivsize = AES_BLOCK_SIZE,
1952 .maxauthsize = SHA224_DIGEST_SIZE,
1953 }
1954 },
1955 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1956 DESC_HDR_SEL0_AESU |
1957 DESC_HDR_MODE0_AESU_CBC |
1958 DESC_HDR_SEL1_MDEUA |
1959 DESC_HDR_MODE1_MDEU_INIT |
1960 DESC_HDR_MODE1_MDEU_PAD |
1961 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1962 },
1963 { .type = CRYPTO_ALG_TYPE_AEAD,
1964 .alg.crypto = {
1965 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1966 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1967 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1968 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 1969 .cra_aead = {
357fb605
HG		 1970 .ivsize = DES3_EDE_BLOCK_SIZE,
1971 .maxauthsize = SHA224_DIGEST_SIZE,
1972 }
1973 },
1974 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1975 DESC_HDR_SEL0_DEU |
1976 DESC_HDR_MODE0_DEU_CBC |
1977 DESC_HDR_MODE0_DEU_3DES |
1978 DESC_HDR_SEL1_MDEUA |
1979 DESC_HDR_MODE1_MDEU_INIT |
1980 DESC_HDR_MODE1_MDEU_PAD |
1981 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1982 },
d5e4aaef
LN		 1983 { .type = CRYPTO_ALG_TYPE_AEAD,
1984 .alg.crypto = {
56af8cd4
LN		 1985 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1986 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1987 .cra_blocksize = AES_BLOCK_SIZE,
1988 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1989 .cra_aead = {
56af8cd4
LN		 1990 .ivsize = AES_BLOCK_SIZE,
1991 .maxauthsize = SHA256_DIGEST_SIZE,
1992 }
1993 },
3952f17e
LN		 1994 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1995 DESC_HDR_SEL0_AESU |
1996 DESC_HDR_MODE0_AESU_CBC |
1997 DESC_HDR_SEL1_MDEUA |
1998 DESC_HDR_MODE1_MDEU_INIT |
1999 DESC_HDR_MODE1_MDEU_PAD |
2000 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2001 },
d5e4aaef
LN		 2002 { .type = CRYPTO_ALG_TYPE_AEAD,
2003 .alg.crypto = {
56af8cd4
LN		 2004 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2005 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2006 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2007 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2008 .cra_aead = {
56af8cd4
LN		 2009 .ivsize = DES3_EDE_BLOCK_SIZE,
2010 .maxauthsize = SHA256_DIGEST_SIZE,
2011 }
2012 },
3952f17e
LN		 2013 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2014 DESC_HDR_SEL0_DEU |
2015 DESC_HDR_MODE0_DEU_CBC |
2016 DESC_HDR_MODE0_DEU_3DES |
2017 DESC_HDR_SEL1_MDEUA |
2018 DESC_HDR_MODE1_MDEU_INIT |
2019 DESC_HDR_MODE1_MDEU_PAD |
2020 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2021 },
d5e4aaef 2022 { .type = CRYPTO_ALG_TYPE_AEAD,
357fb605
HG		 2023 .alg.crypto = {
2024 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2025 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2026 .cra_blocksize = AES_BLOCK_SIZE,
2027 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2028 .cra_aead = {
357fb605
HG		 2029 .ivsize = AES_BLOCK_SIZE,
2030 .maxauthsize = SHA384_DIGEST_SIZE,
2031 }
2032 },
2033 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2034 DESC_HDR_SEL0_AESU |
2035 DESC_HDR_MODE0_AESU_CBC |
2036 DESC_HDR_SEL1_MDEUB |
2037 DESC_HDR_MODE1_MDEU_INIT |
2038 DESC_HDR_MODE1_MDEU_PAD |
2039 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2040 },
2041 { .type = CRYPTO_ALG_TYPE_AEAD,
2042 .alg.crypto = {
2043 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2044 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2045 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2046 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2047 .cra_aead = {
357fb605
HG		 2048 .ivsize = DES3_EDE_BLOCK_SIZE,
2049 .maxauthsize = SHA384_DIGEST_SIZE,
2050 }
2051 },
2052 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2053 DESC_HDR_SEL0_DEU |
2054 DESC_HDR_MODE0_DEU_CBC |
2055 DESC_HDR_MODE0_DEU_3DES |
2056 DESC_HDR_SEL1_MDEUB |
2057 DESC_HDR_MODE1_MDEU_INIT |
2058 DESC_HDR_MODE1_MDEU_PAD |
2059 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2060 },
2061 { .type = CRYPTO_ALG_TYPE_AEAD,
2062 .alg.crypto = {
2063 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2064 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2065 .cra_blocksize = AES_BLOCK_SIZE,
2066 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2067 .cra_aead = {
357fb605
HG		 2068 .ivsize = AES_BLOCK_SIZE,
2069 .maxauthsize = SHA512_DIGEST_SIZE,
2070 }
2071 },
2072 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2073 DESC_HDR_SEL0_AESU |
2074 DESC_HDR_MODE0_AESU_CBC |
2075 DESC_HDR_SEL1_MDEUB |
2076 DESC_HDR_MODE1_MDEU_INIT |
2077 DESC_HDR_MODE1_MDEU_PAD |
2078 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2079 },
2080 { .type = CRYPTO_ALG_TYPE_AEAD,
2081 .alg.crypto = {
2082 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2083 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2084 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2085 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2086 .cra_aead = {
357fb605
HG		 2087 .ivsize = DES3_EDE_BLOCK_SIZE,
2088 .maxauthsize = SHA512_DIGEST_SIZE,
2089 }
2090 },
2091 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2092 DESC_HDR_SEL0_DEU |
2093 DESC_HDR_MODE0_DEU_CBC |
2094 DESC_HDR_MODE0_DEU_3DES |
2095 DESC_HDR_SEL1_MDEUB |
2096 DESC_HDR_MODE1_MDEU_INIT |
2097 DESC_HDR_MODE1_MDEU_PAD |
2098 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2099 },
2100 { .type = CRYPTO_ALG_TYPE_AEAD,
d5e4aaef 2101 .alg.crypto = {
56af8cd4
LN		 2102 .cra_name = "authenc(hmac(md5),cbc(aes))",
2103 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2104 .cra_blocksize = AES_BLOCK_SIZE,
2105 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2106 .cra_aead = {
56af8cd4
LN		 2107 .ivsize = AES_BLOCK_SIZE,
2108 .maxauthsize = MD5_DIGEST_SIZE,
2109 }
2110 },
3952f17e
LN		 2111 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2112 DESC_HDR_SEL0_AESU |
2113 DESC_HDR_MODE0_AESU_CBC |
2114 DESC_HDR_SEL1_MDEUA |
2115 DESC_HDR_MODE1_MDEU_INIT |
2116 DESC_HDR_MODE1_MDEU_PAD |
2117 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2118 },
d5e4aaef
LN		 2119 { .type = CRYPTO_ALG_TYPE_AEAD,
2120 .alg.crypto = {
56af8cd4
LN		 2121 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2122 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2123 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2124 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2125 .cra_aead = {
56af8cd4
LN		 2126 .ivsize = DES3_EDE_BLOCK_SIZE,
2127 .maxauthsize = MD5_DIGEST_SIZE,
2128 }
2129 },
3952f17e
LN		 2130 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2131 DESC_HDR_SEL0_DEU |
2132 DESC_HDR_MODE0_DEU_CBC |
2133 DESC_HDR_MODE0_DEU_3DES |
2134 DESC_HDR_SEL1_MDEUA |
2135 DESC_HDR_MODE1_MDEU_INIT |
2136 DESC_HDR_MODE1_MDEU_PAD |
2137 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2138 },
2139 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2140 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2141 .alg.crypto = {
4de9d0b5
LN		 2142 .cra_name = "cbc(aes)",
2143 .cra_driver_name = "cbc-aes-talitos",
2144 .cra_blocksize = AES_BLOCK_SIZE,
2145 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2146 CRYPTO_ALG_ASYNC,
4de9d0b5 2147 .cra_ablkcipher = {
4de9d0b5
LN		 2148 .min_keysize = AES_MIN_KEY_SIZE,
2149 .max_keysize = AES_MAX_KEY_SIZE,
2150 .ivsize = AES_BLOCK_SIZE,
2151 }
2152 },
2153 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2154 DESC_HDR_SEL0_AESU |
2155 DESC_HDR_MODE0_AESU_CBC,
2156 },
d5e4aaef
LN		 2157 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2158 .alg.crypto = {
4de9d0b5
LN		 2159 .cra_name = "cbc(des3_ede)",
2160 .cra_driver_name = "cbc-3des-talitos",
2161 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2162 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2163 CRYPTO_ALG_ASYNC,
4de9d0b5 2164 .cra_ablkcipher = {
4de9d0b5
LN		 2165 .min_keysize = DES3_EDE_KEY_SIZE,
2166 .max_keysize = DES3_EDE_KEY_SIZE,
2167 .ivsize = DES3_EDE_BLOCK_SIZE,
2168 }
2169 },
2170 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2171 DESC_HDR_SEL0_DEU |
2172 DESC_HDR_MODE0_DEU_CBC |
2173 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2174 },
2175 /* AHASH algorithms. */
2176 { .type = CRYPTO_ALG_TYPE_AHASH,
2177 .alg.hash = {
497f2e6b
LN		 2178 .halg.digestsize = MD5_DIGEST_SIZE,
2179 .halg.base = {
2180 .cra_name = "md5",
2181 .cra_driver_name = "md5-talitos",
2182 .cra_blocksize = MD5_BLOCK_SIZE,
2183 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2184 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2185 }
2186 },
2187 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2188 DESC_HDR_SEL0_MDEUA |
2189 DESC_HDR_MODE0_MDEU_MD5,
2190 },
2191 { .type = CRYPTO_ALG_TYPE_AHASH,
2192 .alg.hash = {
497f2e6b
LN		 2193 .halg.digestsize = SHA1_DIGEST_SIZE,
2194 .halg.base = {
2195 .cra_name = "sha1",
2196 .cra_driver_name = "sha1-talitos",
2197 .cra_blocksize = SHA1_BLOCK_SIZE,
2198 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2199 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2200 }
2201 },
2202 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2203 DESC_HDR_SEL0_MDEUA |
2204 DESC_HDR_MODE0_MDEU_SHA1,
2205 },
60f208d7
KP		 2206 { .type = CRYPTO_ALG_TYPE_AHASH,
2207 .alg.hash = {
60f208d7
KP		 2208 .halg.digestsize = SHA224_DIGEST_SIZE,
2209 .halg.base = {
2210 .cra_name = "sha224",
2211 .cra_driver_name = "sha224-talitos",
2212 .cra_blocksize = SHA224_BLOCK_SIZE,
2213 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2214 CRYPTO_ALG_ASYNC,
60f208d7
KP		 2215 }
2216 },
2217 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2218 DESC_HDR_SEL0_MDEUA |
2219 DESC_HDR_MODE0_MDEU_SHA224,
2220 },
497f2e6b
LN		 2221 { .type = CRYPTO_ALG_TYPE_AHASH,
2222 .alg.hash = {
497f2e6b
LN		 2223 .halg.digestsize = SHA256_DIGEST_SIZE,
2224 .halg.base = {
2225 .cra_name = "sha256",
2226 .cra_driver_name = "sha256-talitos",
2227 .cra_blocksize = SHA256_BLOCK_SIZE,
2228 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2229 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2230 }
2231 },
2232 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2233 DESC_HDR_SEL0_MDEUA |
2234 DESC_HDR_MODE0_MDEU_SHA256,
2235 },
2236 { .type = CRYPTO_ALG_TYPE_AHASH,
2237 .alg.hash = {
497f2e6b
LN		 2238 .halg.digestsize = SHA384_DIGEST_SIZE,
2239 .halg.base = {
2240 .cra_name = "sha384",
2241 .cra_driver_name = "sha384-talitos",
2242 .cra_blocksize = SHA384_BLOCK_SIZE,
2243 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2244 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2245 }
2246 },
2247 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2248 DESC_HDR_SEL0_MDEUB |
2249 DESC_HDR_MODE0_MDEUB_SHA384,
2250 },
2251 { .type = CRYPTO_ALG_TYPE_AHASH,
2252 .alg.hash = {
497f2e6b
LN		 2253 .halg.digestsize = SHA512_DIGEST_SIZE,
2254 .halg.base = {
2255 .cra_name = "sha512",
2256 .cra_driver_name = "sha512-talitos",
2257 .cra_blocksize = SHA512_BLOCK_SIZE,
2258 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2259 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2260 }
2261 },
2262 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2263 DESC_HDR_SEL0_MDEUB |
2264 DESC_HDR_MODE0_MDEUB_SHA512,
2265 },
79b3a418
LN		 2266 { .type = CRYPTO_ALG_TYPE_AHASH,
2267 .alg.hash = {
79b3a418
LN		 2268 .halg.digestsize = MD5_DIGEST_SIZE,
2269 .halg.base = {
2270 .cra_name = "hmac(md5)",
2271 .cra_driver_name = "hmac-md5-talitos",
2272 .cra_blocksize = MD5_BLOCK_SIZE,
2273 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2274 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2275 }
2276 },
2277 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2278 DESC_HDR_SEL0_MDEUA |
2279 DESC_HDR_MODE0_MDEU_MD5,
2280 },
2281 { .type = CRYPTO_ALG_TYPE_AHASH,
2282 .alg.hash = {
79b3a418
LN		 2283 .halg.digestsize = SHA1_DIGEST_SIZE,
2284 .halg.base = {
2285 .cra_name = "hmac(sha1)",
2286 .cra_driver_name = "hmac-sha1-talitos",
2287 .cra_blocksize = SHA1_BLOCK_SIZE,
2288 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2289 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2290 }
2291 },
2292 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2293 DESC_HDR_SEL0_MDEUA |
2294 DESC_HDR_MODE0_MDEU_SHA1,
2295 },
2296 { .type = CRYPTO_ALG_TYPE_AHASH,
2297 .alg.hash = {
79b3a418
LN		 2298 .halg.digestsize = SHA224_DIGEST_SIZE,
2299 .halg.base = {
2300 .cra_name = "hmac(sha224)",
2301 .cra_driver_name = "hmac-sha224-talitos",
2302 .cra_blocksize = SHA224_BLOCK_SIZE,
2303 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2304 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2305 }
2306 },
2307 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2308 DESC_HDR_SEL0_MDEUA |
2309 DESC_HDR_MODE0_MDEU_SHA224,
2310 },
2311 { .type = CRYPTO_ALG_TYPE_AHASH,
2312 .alg.hash = {
79b3a418
LN		 2313 .halg.digestsize = SHA256_DIGEST_SIZE,
2314 .halg.base = {
2315 .cra_name = "hmac(sha256)",
2316 .cra_driver_name = "hmac-sha256-talitos",
2317 .cra_blocksize = SHA256_BLOCK_SIZE,
2318 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2319 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2320 }
2321 },
2322 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2323 DESC_HDR_SEL0_MDEUA |
2324 DESC_HDR_MODE0_MDEU_SHA256,
2325 },
2326 { .type = CRYPTO_ALG_TYPE_AHASH,
2327 .alg.hash = {
79b3a418
LN		 2328 .halg.digestsize = SHA384_DIGEST_SIZE,
2329 .halg.base = {
2330 .cra_name = "hmac(sha384)",
2331 .cra_driver_name = "hmac-sha384-talitos",
2332 .cra_blocksize = SHA384_BLOCK_SIZE,
2333 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2334 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2335 }
2336 },
2337 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2338 DESC_HDR_SEL0_MDEUB |
2339 DESC_HDR_MODE0_MDEUB_SHA384,
2340 },
2341 { .type = CRYPTO_ALG_TYPE_AHASH,
2342 .alg.hash = {
79b3a418
LN		 2343 .halg.digestsize = SHA512_DIGEST_SIZE,
2344 .halg.base = {
2345 .cra_name = "hmac(sha512)",
2346 .cra_driver_name = "hmac-sha512-talitos",
2347 .cra_blocksize = SHA512_BLOCK_SIZE,
2348 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2349 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2350 }
2351 },
2352 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2353 DESC_HDR_SEL0_MDEUB |
2354 DESC_HDR_MODE0_MDEUB_SHA512,
2355 }
9c4a7965
KP		 2356};
2357
2358struct talitos_crypto_alg {
2359 struct list_head entry;
2360 struct device *dev;
acbf7c62 2361 struct talitos_alg_template algt;
9c4a7965
KP		 2362};
2363
2364static int talitos_cra_init(struct crypto_tfm *tfm)
2365{
2366 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2367 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2368 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2369 struct talitos_private *priv;
9c4a7965 2370
497f2e6b
LN		 2371 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2372 talitos_alg = container_of(__crypto_ahash_alg(alg),
2373 struct talitos_crypto_alg,
2374 algt.alg.hash);
2375 else
2376 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2377 algt.alg.crypto);
19bbbc63 2378
9c4a7965
KP		 2379 /* update context with ptr to dev */
2380 ctx->dev = talitos_alg->dev;
19bbbc63 2381
5228f0f7
KP		 2382 /* assign SEC channel to tfm in round-robin fashion */
2383 priv = dev_get_drvdata(ctx->dev);
2384 ctx->ch = atomic_inc_return(&priv->last_chan) &
2385 (priv->num_channels - 1);
2386
9c4a7965 2387 /* copy descriptor header template value */
acbf7c62 2388 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2389
602dba5a
KP		 2390 /* select done notification */
2391 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2392
497f2e6b
LN		 2393 return 0;
2394}
2395
2396static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2397{
2398 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2399
2400 talitos_cra_init(tfm);
9c4a7965
KP		 2401
2402 /* random first IV */
70bcaca7 2403 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2404
2405 return 0;
2406}
2407
497f2e6b
LN		 2408static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2409{
2410 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2411
2412 talitos_cra_init(tfm);
2413
2414 ctx->keylen = 0;
2415 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2416 sizeof(struct talitos_ahash_req_ctx));
2417
2418 return 0;
2419}
2420
9c4a7965
KP		 2421/*
2422 * given the alg's descriptor header template, determine whether descriptor
2423 * type and primary/secondary execution units required match the hw
2424 * capabilities description provided in the device tree node.
2425 */
2426static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2427{
2428 struct talitos_private *priv = dev_get_drvdata(dev);
2429 int ret;
2430
2431 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2432 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2433
2434 if (SECONDARY_EU(desc_hdr_template))
2435 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2436 & priv->exec_units);
2437
2438 return ret;
2439}
2440
2dc11581 2441static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2442{
2443 struct device *dev = &ofdev->dev;
2444 struct talitos_private *priv = dev_get_drvdata(dev);
2445 struct talitos_crypto_alg *t_alg, *n;
2446 int i;
2447
2448 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2449 switch (t_alg->algt.type) {
2450 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2451 case CRYPTO_ALG_TYPE_AEAD:
2452 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2453 break;
2454 case CRYPTO_ALG_TYPE_AHASH:
2455 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2456 break;
2457 }
9c4a7965
KP		 2458 list_del(&t_alg->entry);
2459 kfree(t_alg);
2460 }
2461
2462 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2463 talitos_unregister_rng(dev);
2464
4b992628 2465 for (i = 0; i < priv->num_channels; i++)
0b798247 2466 kfree(priv->chan[i].fifo);
9c4a7965 2467
4b992628 2468 kfree(priv->chan);
9c4a7965 2469
c3e337f8 2470 for (i = 0; i < 2; i++)
2cdba3cf 2471 if (priv->irq[i]) {
c3e337f8
KP		 2472 free_irq(priv->irq[i], dev);
2473 irq_dispose_mapping(priv->irq[i]);
2474 }
9c4a7965 2475
c3e337f8 2476 tasklet_kill(&priv->done_task[0]);
2cdba3cf 2477 if (priv->irq[1])
c3e337f8 2478 tasklet_kill(&priv->done_task[1]);
9c4a7965
KP		 2479
2480 iounmap(priv->reg);
2481
2482 dev_set_drvdata(dev, NULL);
2483
2484 kfree(priv);
2485
2486 return 0;
2487}
2488
2489static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2490 struct talitos_alg_template
2491 *template)
2492{
60f208d7 2493 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2494 struct talitos_crypto_alg *t_alg;
2495 struct crypto_alg *alg;
2496
2497 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2498 if (!t_alg)
2499 return ERR_PTR(-ENOMEM);
2500
acbf7c62
LN		 2501 t_alg->algt = *template;
2502
2503 switch (t_alg->algt.type) {
2504 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2505 alg = &t_alg->algt.alg.crypto;
2506 alg->cra_init = talitos_cra_init;
d4cd3283 2507 alg->cra_type = &crypto_ablkcipher_type;
b286e003
KP		 2508 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2509 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2510 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2511 alg->cra_ablkcipher.geniv = "eseqiv";
497f2e6b 2512 break;
acbf7c62
LN		 2513 case CRYPTO_ALG_TYPE_AEAD:
2514 alg = &t_alg->algt.alg.crypto;
497f2e6b 2515 alg->cra_init = talitos_cra_init_aead;
d4cd3283 2516 alg->cra_type = &crypto_aead_type;
b286e003
KP		 2517 alg->cra_aead.setkey = aead_setkey;
2518 alg->cra_aead.setauthsize = aead_setauthsize;
2519 alg->cra_aead.encrypt = aead_encrypt;
2520 alg->cra_aead.decrypt = aead_decrypt;
2521 alg->cra_aead.givencrypt = aead_givencrypt;
2522 alg->cra_aead.geniv = "<built-in>";
acbf7c62
LN		 2523 break;
2524 case CRYPTO_ALG_TYPE_AHASH:
2525 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2526 alg->cra_init = talitos_cra_init_ahash;
d4cd3283 2527 alg->cra_type = &crypto_ahash_type;
b286e003
KP		 2528 t_alg->algt.alg.hash.init = ahash_init;
2529 t_alg->algt.alg.hash.update = ahash_update;
2530 t_alg->algt.alg.hash.final = ahash_final;
2531 t_alg->algt.alg.hash.finup = ahash_finup;
2532 t_alg->algt.alg.hash.digest = ahash_digest;
2533 t_alg->algt.alg.hash.setkey = ahash_setkey;
2534
79b3a418 2535 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8
KP		 2536 !strncmp(alg->cra_name, "hmac", 4)) {
2537 kfree(t_alg);
79b3a418 2538 return ERR_PTR(-ENOTSUPP);
0b2730d8 2539 }
60f208d7 2540 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 2541 (!strcmp(alg->cra_name, "sha224") ||
2542 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 2543 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2544 t_alg->algt.desc_hdr_template =
2545 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2546 DESC_HDR_SEL0_MDEUA |
2547 DESC_HDR_MODE0_MDEU_SHA256;
2548 }
497f2e6b 2549 break;
1d11911a
KP		 2550 default:
2551 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2552 return ERR_PTR(-EINVAL);
acbf7c62 2553 }
9c4a7965 2554
9c4a7965 2555 alg->cra_module = THIS_MODULE;
9c4a7965 2556 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2557 alg->cra_alignmask = 0;
9c4a7965 2558 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 2559 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 2560
9c4a7965
KP		 2561 t_alg->dev = dev;
2562
2563 return t_alg;
2564}
2565
c3e337f8
KP		 2566static int talitos_probe_irq(struct platform_device *ofdev)
2567{
2568 struct device *dev = &ofdev->dev;
2569 struct device_node *np = ofdev->dev.of_node;
2570 struct talitos_private *priv = dev_get_drvdata(dev);
2571 int err;
2572
2573 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 2574 if (!priv->irq[0]) {
c3e337f8
KP		 2575 dev_err(dev, "failed to map irq\n");
2576 return -EINVAL;
2577 }
2578
2579 priv->irq[1] = irq_of_parse_and_map(np, 1);
2580
2581 /* get the primary irq line */
2cdba3cf 2582 if (!priv->irq[1]) {
c3e337f8
KP		 2583 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2584 dev_driver_string(dev), dev);
2585 goto primary_out;
2586 }
2587
2588 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2589 dev_driver_string(dev), dev);
2590 if (err)
2591 goto primary_out;
2592
2593 /* get the secondary irq line */
2594 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2595 dev_driver_string(dev), dev);
2596 if (err) {
2597 dev_err(dev, "failed to request secondary irq\n");
2598 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 2599 priv->irq[1] = 0;
c3e337f8
KP		 2600 }
2601
2602 return err;
2603
2604primary_out:
2605 if (err) {
2606 dev_err(dev, "failed to request primary irq\n");
2607 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 2608 priv->irq[0] = 0;
c3e337f8
KP		 2609 }
2610
2611 return err;
2612}
2613
1c48a5c9 2614static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2615{
2616 struct device *dev = &ofdev->dev;
61c7a080 2617 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2618 struct talitos_private *priv;
2619 const unsigned int *prop;
2620 int i, err;
2621
2622 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2623 if (!priv)
2624 return -ENOMEM;
2625
2626 dev_set_drvdata(dev, priv);
2627
2628 priv->ofdev = ofdev;
2629
511d63cb
HG		 2630 spin_lock_init(&priv->reg_lock);
2631
c3e337f8
KP		 2632 err = talitos_probe_irq(ofdev);
2633 if (err)
9c4a7965 2634 goto err_out;
9c4a7965 2635
2cdba3cf 2636 if (!priv->irq[1]) {
c3e337f8
KP		 2637 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2638 (unsigned long)dev);
2639 } else {
2640 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2641 (unsigned long)dev);
2642 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2643 (unsigned long)dev);
9c4a7965
KP		 2644 }
2645
c3e337f8
KP		 2646 INIT_LIST_HEAD(&priv->alg_list);
2647
9c4a7965
KP		 2648 priv->reg = of_iomap(np, 0);
2649 if (!priv->reg) {
2650 dev_err(dev, "failed to of_iomap\n");
2651 err = -ENOMEM;
2652 goto err_out;
2653 }
2654
2655 /* get SEC version capabilities from device tree */
2656 prop = of_get_property(np, "fsl,num-channels", NULL);
2657 if (prop)
2658 priv->num_channels = *prop;
2659
2660 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2661 if (prop)
2662 priv->chfifo_len = *prop;
2663
2664 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2665 if (prop)
2666 priv->exec_units = *prop;
2667
2668 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2669 if (prop)
2670 priv->desc_types = *prop;
2671
2672 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2673 !priv->exec_units || !priv->desc_types) {
2674 dev_err(dev, "invalid property data in device tree node\n");
2675 err = -EINVAL;
2676 goto err_out;
2677 }
2678
f3c85bc1
LN		 2679 if (of_device_is_compatible(np, "fsl,sec3.0"))
2680 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2681
fe5720e2 2682 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 2683 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 2684 TALITOS_FTR_SHA224_HWINIT |
2685 TALITOS_FTR_HMAC_OK;
fe5720e2 2686
4b992628
KP		 2687 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2688 priv->num_channels, GFP_KERNEL);
2689 if (!priv->chan) {
2690 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2691 err = -ENOMEM;
2692 goto err_out;
2693 }
2694
c3e337f8
KP		 2695 for (i = 0; i < priv->num_channels; i++) {
2696 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2cdba3cf 2697 if (!priv->irq[1] || !(i & 1))
c3e337f8
KP		 2698 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2699 }
ad42d5fc 2700
9c4a7965 2701 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2702 spin_lock_init(&priv->chan[i].head_lock);
2703 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2704 }
2705
2706 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2707
2708 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2709 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2710 priv->fifo_len, GFP_KERNEL);
2711 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2712 dev_err(dev, "failed to allocate request fifo %d\n", i);
2713 err = -ENOMEM;
2714 goto err_out;
2715 }
2716 }
2717
ec6644d6 2718 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2719 atomic_set(&priv->chan[i].submit_count,
2720 -(priv->chfifo_len - 1));
9c4a7965 2721
81eb024c
KP		 2722 dma_set_mask(dev, DMA_BIT_MASK(36));
2723
9c4a7965
KP		 2724 /* reset and initialize the h/w */
2725 err = init_device(dev);
2726 if (err) {
2727 dev_err(dev, "failed to initialize device\n");
2728 goto err_out;
2729 }
2730
2731 /* register the RNG, if available */
2732 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2733 err = talitos_register_rng(dev);
2734 if (err) {
2735 dev_err(dev, "failed to register hwrng: %d\n", err);
2736 goto err_out;
2737 } else
2738 dev_info(dev, "hwrng\n");
2739 }
2740
2741 /* register crypto algorithms the device supports */
9c4a7965
KP		 2742 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2743 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2744 struct talitos_crypto_alg *t_alg;
acbf7c62 2745 char *name = NULL;
9c4a7965
KP		 2746
2747 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2748 if (IS_ERR(t_alg)) {
2749 err = PTR_ERR(t_alg);
0b2730d8 2750 if (err == -ENOTSUPP)
79b3a418 2751 continue;
9c4a7965
KP		 2752 goto err_out;
2753 }
2754
acbf7c62
LN		 2755 switch (t_alg->algt.type) {
2756 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2757 case CRYPTO_ALG_TYPE_AEAD:
2758 err = crypto_register_alg(
2759 &t_alg->algt.alg.crypto);
2760 name = t_alg->algt.alg.crypto.cra_driver_name;
2761 break;
2762 case CRYPTO_ALG_TYPE_AHASH:
2763 err = crypto_register_ahash(
2764 &t_alg->algt.alg.hash);
2765 name =
2766 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2767 break;
2768 }
9c4a7965
KP		 2769 if (err) {
2770 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2771 name);
9c4a7965 2772 kfree(t_alg);
5b859b6e 2773 } else
9c4a7965 2774 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 2775 }
2776 }
5b859b6e
KP		 2777 if (!list_empty(&priv->alg_list))
2778 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2779 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 2780
2781 return 0;
2782
2783err_out:
2784 talitos_remove(ofdev);
9c4a7965
KP		 2785
2786 return err;
2787}
2788
6c3f975a 2789static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2790 {
2791 .compatible = "fsl,sec2.0",
2792 },
2793 {},
2794};
2795MODULE_DEVICE_TABLE(of, talitos_match);
2796
1c48a5c9 2797static struct platform_driver talitos_driver = {
4018294b
GL		 2798 .driver = {
2799 .name = "talitos",
2800 .owner = THIS_MODULE,
2801 .of_match_table = talitos_match,
2802 },
9c4a7965 2803 .probe = talitos_probe,
596f1034 2804 .remove = talitos_remove,
9c4a7965
KP		 2805};
2806
741e8c2d 2807module_platform_driver(talitos_driver);
9c4a7965
KP		 2808
2809MODULE_LICENSE("GPL");
2810MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2811MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux kernel - Deliverables
This page took 0.552267 seconds and 5 git commands to generate.