[deliverable/linux.git] / drivers / devfreq / exynos / exynos5_bus.c

/*
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework
 * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com>
 * Support for only EXYNOS5250 is present.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/devfreq.h>
#include <linux/io.h>
#include <linux/opp.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <linux/opp.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm_qos.h>
#include <linux/regulator/consumer.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>

#include "exynos_ppmu.h"

#define MAX_SAFEVOLT			1100000 /* 1.10V */
/* Assume that the bus is saturated if the utilization is 25% */
#define INT_BUS_SATURATION_RATIO	25

enum int_level_idx {
	LV_0,
	LV_1,
	LV_2,
	LV_3,
	LV_4,
	_LV_END
};

enum exynos_ppmu_list {
	PPMU_RIGHT,
	PPMU_END,
};

struct busfreq_data_int {
	struct device *dev;
	struct devfreq *devfreq;
	struct regulator *vdd_int;
	struct exynos_ppmu ppmu[PPMU_END];
	unsigned long curr_freq;
	bool disabled;

	struct notifier_block pm_notifier;
	struct mutex lock;
	struct pm_qos_request int_req;
	struct clk *int_clk;
};

struct int_bus_opp_table {
	unsigned int idx;
	unsigned long clk;
	unsigned long volt;
};

static struct int_bus_opp_table exynos5_int_opp_table[] = {
	{LV_0, 266000, 1025000},
	{LV_1, 200000, 1025000},
	{LV_2, 160000, 1025000},
	{LV_3, 133000, 1025000},
	{LV_4, 100000, 1025000},
	{0, 0, 0},
};

static void busfreq_mon_reset(struct busfreq_data_int *data)
{
	unsigned int i;

	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
		void __iomem *ppmu_base = data->ppmu[i].hw_base;

		/* Reset the performance and cycle counters */
		exynos_ppmu_reset(ppmu_base);

		/* Setup count registers to monitor read/write transactions */
		data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
		exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
					data->ppmu[i].event[PPMU_PMNCNT3]);

		exynos_ppmu_start(ppmu_base);
	}
}

static void exynos5_read_ppmu(struct busfreq_data_int *data)
{
	int i, j;

	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
		void __iomem *ppmu_base = data->ppmu[i].hw_base;

		exynos_ppmu_stop(ppmu_base);

		/* Update local data from PPMU */
		data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);

		for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
			if (data->ppmu[i].event[j] == 0)
				data->ppmu[i].count[j] = 0;
			else
				data->ppmu[i].count[j] =
					exynos_ppmu_read(ppmu_base, j);
		}
	}

	busfreq_mon_reset(data);
}

static int exynos5_int_setvolt(struct busfreq_data_int *data,
				unsigned long volt)
{
	return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT);
}

static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq,
			      u32 flags)
{
	int err = 0;
	struct platform_device *pdev = container_of(dev, struct platform_device,
						    dev);
	struct busfreq_data_int *data = platform_get_drvdata(pdev);
	struct opp *opp;
	unsigned long old_freq, freq;
	unsigned long volt;

	rcu_read_lock();
	opp = devfreq_recommended_opp(dev, _freq, flags);
	if (IS_ERR(opp)) {
		rcu_read_unlock();
		dev_err(dev, "%s: Invalid OPP.\n", __func__);
		return PTR_ERR(opp);
	}

	freq = opp_get_freq(opp);
	volt = opp_get_voltage(opp);
	rcu_read_unlock();

	old_freq = data->curr_freq;

	if (old_freq == freq)
		return 0;

	dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt);

	mutex_lock(&data->lock);

	if (data->disabled)
		goto out;

	if (freq > exynos5_int_opp_table[0].clk)
		pm_qos_update_request(&data->int_req, freq * 16 / 1000);
	else
		pm_qos_update_request(&data->int_req, -1);

	if (old_freq < freq)
		err = exynos5_int_setvolt(data, volt);
	if (err)
		goto out;

	err = clk_set_rate(data->int_clk, freq * 1000);

	if (err)
		goto out;

	if (old_freq > freq)
		err = exynos5_int_setvolt(data, volt);
	if (err)
		goto out;

	data->curr_freq = freq;
out:
	mutex_unlock(&data->lock);
	return err;
}

static int exynos5_get_busier_dmc(struct busfreq_data_int *data)
{
	int i, j;
	int busy = 0;
	unsigned int temp = 0;

	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
		for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
			if (data->ppmu[i].count[j] > temp) {
				temp = data->ppmu[i].count[j];
				busy = i;
			}
		}
	}

	return busy;
}

static int exynos5_int_get_dev_status(struct device *dev,
				      struct devfreq_dev_status *stat)
{
	struct platform_device *pdev = container_of(dev, struct platform_device,
						    dev);
	struct busfreq_data_int *data = platform_get_drvdata(pdev);
	int busier_dmc;

	exynos5_read_ppmu(data);
	busier_dmc = exynos5_get_busier_dmc(data);

	stat->current_frequency = data->curr_freq;

	/* Number of cycles spent on memory access */
	stat->busy_time = data->ppmu[busier_dmc].count[PPMU_PMNCNT3];
	stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO;
	stat->total_time = data->ppmu[busier_dmc].ccnt;

	return 0;
}
static void exynos5_int_exit(struct device *dev)
{
	struct platform_device *pdev = container_of(dev, struct platform_device,
						    dev);
	struct busfreq_data_int *data = platform_get_drvdata(pdev);

	devfreq_unregister_opp_notifier(dev, data->devfreq);
}

static struct devfreq_dev_profile exynos5_devfreq_int_profile = {
	.initial_freq		= 160000,
	.polling_ms		= 100,
	.target			= exynos5_busfreq_int_target,
	.get_dev_status		= exynos5_int_get_dev_status,
	.exit			= exynos5_int_exit,
};

static int exynos5250_init_int_tables(struct busfreq_data_int *data)
{
	int i, err = 0;

	for (i = LV_0; i < _LV_END; i++) {
		err = opp_add(data->dev, exynos5_int_opp_table[i].clk,
				exynos5_int_opp_table[i].volt);
		if (err) {
			dev_err(data->dev, "Cannot add opp entries.\n");
			return err;
		}
	}

	return 0;
}

static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this,
		unsigned long event, void *ptr)
{
	struct busfreq_data_int *data = container_of(this,
					struct busfreq_data_int, pm_notifier);
	struct opp *opp;
	unsigned long maxfreq = ULONG_MAX;
	unsigned long freq;
	unsigned long volt;
	int err = 0;

	switch (event) {
	case PM_SUSPEND_PREPARE:
		/* Set Fastest and Deactivate DVFS */
		mutex_lock(&data->lock);

		data->disabled = true;

		rcu_read_lock();
		opp = opp_find_freq_floor(data->dev, &maxfreq);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			err = PTR_ERR(opp);
			goto unlock;
		}
		freq = opp_get_freq(opp);
		volt = opp_get_voltage(opp);
		rcu_read_unlock();

		err = exynos5_int_setvolt(data, volt);
		if (err)
			goto unlock;

		err = clk_set_rate(data->int_clk, freq * 1000);

		if (err)
			goto unlock;

		data->curr_freq = freq;
unlock:
		mutex_unlock(&data->lock);
		if (err)
			return NOTIFY_BAD;
		return NOTIFY_OK;
	case PM_POST_RESTORE:
	case PM_POST_SUSPEND:
		/* Reactivate */
		mutex_lock(&data->lock);
		data->disabled = false;
		mutex_unlock(&data->lock);
		return NOTIFY_OK;
	}

	return NOTIFY_DONE;
}

static int exynos5_busfreq_int_probe(struct platform_device *pdev)
{
	struct busfreq_data_int *data;
	struct opp *opp;
	struct device *dev = &pdev->dev;
	struct device_node *np;
	unsigned long initial_freq;
	unsigned long initial_volt;
	int err = 0;
	int i;

	data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int),
				GFP_KERNEL);
	if (data == NULL) {
		dev_err(dev, "Cannot allocate memory.\n");
		return -ENOMEM;
	}

	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu");
	if (np == NULL) {
		pr_err("Unable to find PPMU node\n");
		return -ENOENT;
	}

	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
		/* map PPMU memory region */
		data->ppmu[i].hw_base = of_iomap(np, i);
		if (data->ppmu[i].hw_base == NULL) {
			dev_err(&pdev->dev, "failed to map memory region\n");
			return -ENOMEM;
		}
	}
	data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event;
	data->dev = dev;
	mutex_init(&data->lock);

	err = exynos5250_init_int_tables(data);
	if (err)
		return err;

	data->vdd_int = devm_regulator_get(dev, "vdd_int");
	if (IS_ERR(data->vdd_int)) {
		dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
		return PTR_ERR(data->vdd_int);
	}

	data->int_clk = devm_clk_get(dev, "int_clk");
	if (IS_ERR(data->int_clk)) {
		dev_err(dev, "Cannot get clock \"int_clk\"\n");
		return PTR_ERR(data->int_clk);
	}

	rcu_read_lock();
	opp = opp_find_freq_floor(dev,
			&exynos5_devfreq_int_profile.initial_freq);
	if (IS_ERR(opp)) {
		rcu_read_unlock();
		dev_err(dev, "Invalid initial frequency %lu kHz.\n",
		       exynos5_devfreq_int_profile.initial_freq);
		return PTR_ERR(opp);
	}
	initial_freq = opp_get_freq(opp);
	initial_volt = opp_get_voltage(opp);
	rcu_read_unlock();
	data->curr_freq = initial_freq;

	err = clk_set_rate(data->int_clk, initial_freq * 1000);
	if (err) {
		dev_err(dev, "Failed to set initial frequency\n");
		return err;
	}

	err = exynos5_int_setvolt(data, initial_volt);
	if (err)
		return err;

	platform_set_drvdata(pdev, data);

	busfreq_mon_reset(data);

	data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile,
					   "simple_ondemand", NULL);

	if (IS_ERR(data->devfreq)) {
		err = PTR_ERR(data->devfreq);
		goto err_devfreq_add;
	}

	devfreq_register_opp_notifier(dev, data->devfreq);

	err = register_pm_notifier(&data->pm_notifier);
	if (err) {
		dev_err(dev, "Failed to setup pm notifier\n");
		goto err_devfreq_add;
	}

	/* TODO: Add a new QOS class for int/mif bus */
	pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1);

	return 0;

err_devfreq_add:
	devfreq_remove_device(data->devfreq);
	return err;
}

static int exynos5_busfreq_int_remove(struct platform_device *pdev)
{
	struct busfreq_data_int *data = platform_get_drvdata(pdev);

	pm_qos_remove_request(&data->int_req);
	unregister_pm_notifier(&data->pm_notifier);
	devfreq_remove_device(data->devfreq);

	return 0;
}

static int exynos5_busfreq_int_resume(struct device *dev)
{
	struct platform_device *pdev = container_of(dev, struct platform_device,
						    dev);
	struct busfreq_data_int *data = platform_get_drvdata(pdev);

	busfreq_mon_reset(data);
	return 0;
}

static const struct dev_pm_ops exynos5_busfreq_int_pm = {
	.resume	= exynos5_busfreq_int_resume,
};

/* platform device pointer for exynos5 devfreq device. */
static struct platform_device *exynos5_devfreq_pdev;

static struct platform_driver exynos5_busfreq_int_driver = {
	.probe		= exynos5_busfreq_int_probe,
	.remove		= exynos5_busfreq_int_remove,
	.driver		= {
		.name		= "exynos5-bus-int",
		.owner		= THIS_MODULE,
		.pm		= &exynos5_busfreq_int_pm,
	},
};

static int __init exynos5_busfreq_int_init(void)
{
	int ret;

	ret = platform_driver_register(&exynos5_busfreq_int_driver);
	if (ret < 0)
		goto out;

	exynos5_devfreq_pdev =
		platform_device_register_simple("exynos5-bus-int", -1, NULL, 0);
	if (IS_ERR(exynos5_devfreq_pdev)) {
		ret = PTR_ERR(exynos5_devfreq_pdev);
		goto out1;
	}

	return 0;
out1:
	platform_driver_unregister(&exynos5_busfreq_int_driver);
out:
	return ret;
}
late_initcall(exynos5_busfreq_int_init);

static void __exit exynos5_busfreq_int_exit(void)
{
	platform_device_unregister(exynos5_devfreq_pdev);
	platform_driver_unregister(&exynos5_busfreq_int_driver);
}
module_exit(exynos5_busfreq_int_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework");
Commit	Line	Data
6ccce699 AK	1	/*
	2	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com/
	4	*
	5	* EXYNOS5 INT clock frequency scaling support using DEVFREQ framework
	6	* Based on work done by Jonghwan Choi <jhbird.choi@samsung.com>
	7	* Support for only EXYNOS5250 is present.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/devfreq.h>
	17	#include <linux/io.h>
	18	#include <linux/opp.h>
	19	#include <linux/slab.h>
	20	#include <linux/suspend.h>
	21	#include <linux/opp.h>
	22	#include <linux/clk.h>
	23	#include <linux/delay.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/pm_qos.h>
	26	#include <linux/regulator/consumer.h>
	27	#include <linux/of_address.h>
	28	#include <linux/of_platform.h>
	29
	30	#include "exynos_ppmu.h"
	31
	32	#define MAX_SAFEVOLT 1100000 /* 1.10V */
	33	/* Assume that the bus is saturated if the utilization is 25% */
	34	#define INT_BUS_SATURATION_RATIO 25
	35
	36	enum int_level_idx {
	37	LV_0,
	38	LV_1,
	39	LV_2,
	40	LV_3,
	41	LV_4,
	42	_LV_END
	43	};
	44
	45	enum exynos_ppmu_list {
	46	PPMU_RIGHT,
	47	PPMU_END,
	48	};
	49
	50	struct busfreq_data_int {
	51	struct device *dev;
	52	struct devfreq *devfreq;
	53	struct regulator *vdd_int;
	54	struct exynos_ppmu ppmu[PPMU_END];
	55	unsigned long curr_freq;
	56	bool disabled;
	57
	58	struct notifier_block pm_notifier;
	59	struct mutex lock;
	60	struct pm_qos_request int_req;
	61	struct clk *int_clk;
	62	};
	63
	64	struct int_bus_opp_table {
65	unsigned int idx;
66	unsigned long clk;
67	unsigned long volt;
68	};
69
70	static struct int_bus_opp_table exynos5_int_opp_table[] = {
71	{LV_0, 266000, 1025000},
72	{LV_1, 200000, 1025000},
73	{LV_2, 160000, 1025000},
74	{LV_3, 133000, 1025000},
75	{LV_4, 100000, 1025000},
76	{0, 0, 0},
77	};
78
79	static void busfreq_mon_reset(struct busfreq_data_int *data)
80	{
81	unsigned int i;
82
83	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
84	void __iomem *ppmu_base = data->ppmu[i].hw_base;
85
86	/* Reset the performance and cycle counters */
87	exynos_ppmu_reset(ppmu_base);
88
89	/* Setup count registers to monitor read/write transactions */
90	data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
91	exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
92	data->ppmu[i].event[PPMU_PMNCNT3]);
93
94	exynos_ppmu_start(ppmu_base);
95	}
96	}
97
98	static void exynos5_read_ppmu(struct busfreq_data_int *data)
99	{
100	int i, j;
101
102	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
103	void __iomem *ppmu_base = data->ppmu[i].hw_base;
104
105	exynos_ppmu_stop(ppmu_base);
106
107	/* Update local data from PPMU */
108	data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
109
110	for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
111	if (data->ppmu[i].event[j] == 0)
112	data->ppmu[i].count[j] = 0;
113	else
114	data->ppmu[i].count[j] =
115	exynos_ppmu_read(ppmu_base, j);
116	}
117	}
118
119	busfreq_mon_reset(data);
120	}
121
122	static int exynos5_int_setvolt(struct busfreq_data_int *data,
123	unsigned long volt)
124	{
125	return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT);
126	}
127
128	static int exynos5_busfreq_int_target(struct device dev, unsigned long _freq,
129	u32 flags)
130	{
131	int err = 0;
132	struct platform_device *pdev = container_of(dev, struct platform_device,
133	dev);
134	struct busfreq_data_int *data = platform_get_drvdata(pdev);
135	struct opp *opp;
136	unsigned long old_freq, freq;
137	unsigned long volt;
138
139	rcu_read_lock();
140	opp = devfreq_recommended_opp(dev, _freq, flags);
141	if (IS_ERR(opp)) {
142	rcu_read_unlock();
143	dev_err(dev, "%s: Invalid OPP.\n", __func__);
144	return PTR_ERR(opp);
145	}
146
147	freq = opp_get_freq(opp);
148	volt = opp_get_voltage(opp);
149	rcu_read_unlock();
150
151	old_freq = data->curr_freq;
152
153	if (old_freq == freq)
154	return 0;
155
156	dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt);
157
158	mutex_lock(&data->lock);
159
160	if (data->disabled)
161	goto out;
162
163	if (freq > exynos5_int_opp_table[0].clk)
164	pm_qos_update_request(&data->int_req, freq * 16 / 1000);
165	else
166	pm_qos_update_request(&data->int_req, -1);
167
168	if (old_freq < freq)
169	err = exynos5_int_setvolt(data, volt);
170	if (err)
171	goto out;
172
173	err = clk_set_rate(data->int_clk, freq * 1000);
174
175	if (err)
176	goto out;
177
178	if (old_freq > freq)
179	err = exynos5_int_setvolt(data, volt);
180	if (err)
181	goto out;
182
183	data->curr_freq = freq;
184	out:
185	mutex_unlock(&data->lock);
186	return err;
187	}
188
189	static int exynos5_get_busier_dmc(struct busfreq_data_int *data)
190	{
191	int i, j;
192	int busy = 0;
193	unsigned int temp = 0;
194
195	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
196	for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
197	if (data->ppmu[i].count[j] > temp) {
198	temp = data->ppmu[i].count[j];
199	busy = i;
200	}
201	}
202	}
203
204	return busy;
205	}
206
207	static int exynos5_int_get_dev_status(struct device *dev,
208	struct devfreq_dev_status *stat)
209	{
210	struct platform_device *pdev = container_of(dev, struct platform_device,
211	dev);
212	struct busfreq_data_int *data = platform_get_drvdata(pdev);
213	int busier_dmc;
214
215	exynos5_read_ppmu(data);
216	busier_dmc = exynos5_get_busier_dmc(data);
217
218	stat->current_frequency = data->curr_freq;
219
220	/* Number of cycles spent on memory access */
221	stat->busy_time = data->ppmu[busier_dmc].count[PPMU_PMNCNT3];
222	stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO;
223	stat->total_time = data->ppmu[busier_dmc].ccnt;
224
225	return 0;
226	}
227	static void exynos5_int_exit(struct device *dev)
228	{
229	struct platform_device *pdev = container_of(dev, struct platform_device,
230	dev);
231	struct busfreq_data_int *data = platform_get_drvdata(pdev);
232
233	devfreq_unregister_opp_notifier(dev, data->devfreq);
234	}
235
236	static struct devfreq_dev_profile exynos5_devfreq_int_profile = {
237	.initial_freq = 160000,
238	.polling_ms = 100,
239	.target = exynos5_busfreq_int_target,
240	.get_dev_status = exynos5_int_get_dev_status,
241	.exit = exynos5_int_exit,
242	};
243
244	static int exynos5250_init_int_tables(struct busfreq_data_int *data)
245	{
246	int i, err = 0;
247
248	for (i = LV_0; i < _LV_END; i++) {
249	err = opp_add(data->dev, exynos5_int_opp_table[i].clk,
250	exynos5_int_opp_table[i].volt);
251	if (err) {
252	dev_err(data->dev, "Cannot add opp entries.\n");
253	return err;
254	}
255	}
256
257	return 0;
258	}
259
260	static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this,
261	unsigned long event, void *ptr)
262	{
263	struct busfreq_data_int *data = container_of(this,
264	struct busfreq_data_int, pm_notifier);
265	struct opp *opp;
266	unsigned long maxfreq = ULONG_MAX;
267	unsigned long freq;
268	unsigned long volt;
269	int err = 0;
270
271	switch (event) {
272	case PM_SUSPEND_PREPARE:
273	/* Set Fastest and Deactivate DVFS */
274	mutex_lock(&data->lock);
275
276	data->disabled = true;
277
278	rcu_read_lock();
279	opp = opp_find_freq_floor(data->dev, &maxfreq);
280	if (IS_ERR(opp)) {
281	rcu_read_unlock();
282	err = PTR_ERR(opp);
283	goto unlock;
284	}
285	freq = opp_get_freq(opp);
286	volt = opp_get_voltage(opp);
287	rcu_read_unlock();
288
289	err = exynos5_int_setvolt(data, volt);
290	if (err)
291	goto unlock;
292
293	err = clk_set_rate(data->int_clk, freq * 1000);
294
295	if (err)
296	goto unlock;
297
298	data->curr_freq = freq;
299	unlock:
300	mutex_unlock(&data->lock);
301	if (err)
302	return NOTIFY_BAD;
303	return NOTIFY_OK;
304	case PM_POST_RESTORE:
305	case PM_POST_SUSPEND:
306	/* Reactivate */
307	mutex_lock(&data->lock);
308	data->disabled = false;
309	mutex_unlock(&data->lock);
310	return NOTIFY_OK;
311	}
312
313	return NOTIFY_DONE;
314	}
315
316	static int exynos5_busfreq_int_probe(struct platform_device *pdev)
317	{
318	struct busfreq_data_int *data;
319	struct opp *opp;
320	struct device *dev = &pdev->dev;
321	struct device_node *np;
322	unsigned long initial_freq;
323	unsigned long initial_volt;
324	int err = 0;
325	int i;
326
327	data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int),
328	GFP_KERNEL);
329	if (data == NULL) {
330	dev_err(dev, "Cannot allocate memory.\n");
331	return -ENOMEM;
332	}
333
334	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu");
335	if (np == NULL) {
336	pr_err("Unable to find PPMU node\n");
337	return -ENOENT;
338	}
339
340	for (i = PPMU_RIGHT; i < PPMU_END; i++) {
341	/* map PPMU memory region */
342	data->ppmu[i].hw_base = of_iomap(np, i);
343	if (data->ppmu[i].hw_base == NULL) {
344	dev_err(&pdev->dev, "failed to map memory region\n");
345	return -ENOMEM;
346	}
347	}
348	data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event;
349	data->dev = dev;
350	mutex_init(&data->lock);
351
352	err = exynos5250_init_int_tables(data);
353	if (err)
02844f74	354	return err;
6ccce699	355
02844f74	356	data->vdd_int = devm_regulator_get(dev, "vdd_int");
6ccce699 AK	357	if (IS_ERR(data->vdd_int)) {
6ccce699 AK	358	dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
02844f74	359	return PTR_ERR(data->vdd_int);
6ccce699 AK	360	}
6ccce699 AK	361
02844f74	362	data->int_clk = devm_clk_get(dev, "int_clk");
6ccce699 AK	363	if (IS_ERR(data->int_clk)) {
6ccce699 AK	364	dev_err(dev, "Cannot get clock \"int_clk\"\n");
02844f74	365	return PTR_ERR(data->int_clk);
6ccce699 AK	366	}
	367
	368	rcu_read_lock();
	369	opp = opp_find_freq_floor(dev,
	370	&exynos5_devfreq_int_profile.initial_freq);
	371	if (IS_ERR(opp)) {
	372	rcu_read_unlock();
	373	dev_err(dev, "Invalid initial frequency %lu kHz.\n",
	374	exynos5_devfreq_int_profile.initial_freq);
02844f74	375	return PTR_ERR(opp);
6ccce699 AK	376	}
	377	initial_freq = opp_get_freq(opp);
	378	initial_volt = opp_get_voltage(opp);
	379	rcu_read_unlock();
	380	data->curr_freq = initial_freq;
	381
	382	err = clk_set_rate(data->int_clk, initial_freq * 1000);
	383	if (err) {
	384	dev_err(dev, "Failed to set initial frequency\n");
02844f74	385	return err;
6ccce699 AK	386	}
	387
	388	err = exynos5_int_setvolt(data, initial_volt);
	389	if (err)
02844f74	390	return err;
6ccce699 AK	391
	392	platform_set_drvdata(pdev, data);
	393
	394	busfreq_mon_reset(data);
	395
	396	data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile,
	397	"simple_ondemand", NULL);
	398
	399	if (IS_ERR(data->devfreq)) {
	400	err = PTR_ERR(data->devfreq);
	401	goto err_devfreq_add;
	402	}
	403
	404	devfreq_register_opp_notifier(dev, data->devfreq);
	405
	406	err = register_pm_notifier(&data->pm_notifier);
	407	if (err) {
	408	dev_err(dev, "Failed to setup pm notifier\n");
	409	goto err_devfreq_add;
	410	}
	411
	412	/* TODO: Add a new QOS class for int/mif bus */
	413	pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1);
	414
	415	return 0;
	416
	417	err_devfreq_add:
	418	devfreq_remove_device(data->devfreq);
6ccce699 AK	419	return err;
	420	}
	421
	422	static int exynos5_busfreq_int_remove(struct platform_device *pdev)
	423	{
	424	struct busfreq_data_int *data = platform_get_drvdata(pdev);
	425
	426	pm_qos_remove_request(&data->int_req);
	427	unregister_pm_notifier(&data->pm_notifier);
	428	devfreq_remove_device(data->devfreq);
6ccce699 AK	429
	430	return 0;
	431	}
	432
	433	static int exynos5_busfreq_int_resume(struct device *dev)
	434	{
	435	struct platform_device *pdev = container_of(dev, struct platform_device,
	436	dev);
	437	struct busfreq_data_int *data = platform_get_drvdata(pdev);
	438
	439	busfreq_mon_reset(data);
	440	return 0;
	441	}
	442
	443	static const struct dev_pm_ops exynos5_busfreq_int_pm = {
	444	.resume = exynos5_busfreq_int_resume,
	445	};
	446
	447	/* platform device pointer for exynos5 devfreq device. */
	448	static struct platform_device *exynos5_devfreq_pdev;
	449
	450	static struct platform_driver exynos5_busfreq_int_driver = {
	451	.probe = exynos5_busfreq_int_probe,
	452	.remove = exynos5_busfreq_int_remove,
	453	.driver = {
	454	.name = "exynos5-bus-int",
	455	.owner = THIS_MODULE,
	456	.pm = &exynos5_busfreq_int_pm,
	457	},
	458	};
	459
	460	static int __init exynos5_busfreq_int_init(void)
	461	{
	462	int ret;
	463
	464	ret = platform_driver_register(&exynos5_busfreq_int_driver);
	465	if (ret < 0)
	466	goto out;
	467
	468	exynos5_devfreq_pdev =
	469	platform_device_register_simple("exynos5-bus-int", -1, NULL, 0);
8ab8831a	470	if (IS_ERR(exynos5_devfreq_pdev)) {
6ccce699 AK	471	ret = PTR_ERR(exynos5_devfreq_pdev);
	472	goto out1;
	473	}
	474
	475	return 0;
	476	out1:
	477	platform_driver_unregister(&exynos5_busfreq_int_driver);
	478	out:
	479	return ret;
	480	}
	481	late_initcall(exynos5_busfreq_int_init);
	482
	483	static void __exit exynos5_busfreq_int_exit(void)
	484	{
	485	platform_device_unregister(exynos5_devfreq_pdev);
	486	platform_driver_unregister(&exynos5_busfreq_int_driver);
	487	}
	488	module_exit(exynos5_busfreq_int_exit);
	489
	490	MODULE_LICENSE("GPL");
	491	MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework");