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6234f380 TV |
1 | /* |
2 | * A devfreq driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | |
5 | * Copyright (C) 2014 Google, Inc | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/devfreq.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_opp.h> | |
29 | #include <linux/reset.h> | |
30 | ||
31 | #include "governor.h" | |
32 | ||
33 | #define ACTMON_GLB_STATUS 0x0 | |
34 | #define ACTMON_GLB_PERIOD_CTRL 0x4 | |
35 | ||
36 | #define ACTMON_DEV_CTRL 0x0 | |
37 | #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10 | |
38 | #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) | |
39 | #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) | |
40 | #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) | |
41 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23 | |
42 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26 | |
43 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) | |
44 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) | |
45 | #define ACTMON_DEV_CTRL_ENB BIT(31) | |
46 | ||
47 | #define ACTMON_DEV_UPPER_WMARK 0x4 | |
48 | #define ACTMON_DEV_LOWER_WMARK 0x8 | |
49 | #define ACTMON_DEV_INIT_AVG 0xc | |
50 | #define ACTMON_DEV_AVG_UPPER_WMARK 0x10 | |
51 | #define ACTMON_DEV_AVG_LOWER_WMARK 0x14 | |
52 | #define ACTMON_DEV_COUNT_WEIGHT 0x18 | |
53 | #define ACTMON_DEV_AVG_COUNT 0x20 | |
54 | #define ACTMON_DEV_INTR_STATUS 0x24 | |
55 | ||
56 | #define ACTMON_INTR_STATUS_CLEAR 0xffffffff | |
57 | ||
58 | #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31) | |
59 | #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30) | |
60 | ||
61 | #define ACTMON_ABOVE_WMARK_WINDOW 1 | |
62 | #define ACTMON_BELOW_WMARK_WINDOW 3 | |
63 | #define ACTMON_BOOST_FREQ_STEP 16000 | |
64 | ||
11573e91 TV |
65 | /* |
66 | * Activity counter is incremented every 256 memory transactions, and each | |
6234f380 TV |
67 | * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is |
68 | * 4 * 256 = 1024. | |
69 | */ | |
70 | #define ACTMON_COUNT_WEIGHT 0x400 | |
71 | ||
72 | /* | |
73 | * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which | |
74 | * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 | |
75 | */ | |
76 | #define ACTMON_AVERAGE_WINDOW_LOG2 6 | |
77 | #define ACTMON_SAMPLING_PERIOD 12 /* ms */ | |
78 | #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */ | |
79 | ||
80 | #define KHZ 1000 | |
81 | ||
82 | /* Assume that the bus is saturated if the utilization is 25% */ | |
83 | #define BUS_SATURATION_RATIO 25 | |
84 | ||
85 | /** | |
86 | * struct tegra_devfreq_device_config - configuration specific to an ACTMON | |
87 | * device | |
88 | * | |
11573e91 | 89 | * Coefficients and thresholds are percentages unless otherwise noted |
6234f380 TV |
90 | */ |
91 | struct tegra_devfreq_device_config { | |
92 | u32 offset; | |
93 | u32 irq_mask; | |
94 | ||
11573e91 | 95 | /* Factors applied to boost_freq every consecutive watermark breach */ |
6234f380 TV |
96 | unsigned int boost_up_coeff; |
97 | unsigned int boost_down_coeff; | |
11573e91 TV |
98 | |
99 | /* Define the watermark bounds when applied to the current avg */ | |
6234f380 TV |
100 | unsigned int boost_up_threshold; |
101 | unsigned int boost_down_threshold; | |
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102 | |
103 | /* | |
104 | * Threshold of activity (cycles) below which the CPU frequency isn't | |
105 | * to be taken into account. This is to avoid increasing the EMC | |
106 | * frequency when the CPU is very busy but not accessing the bus often. | |
107 | */ | |
6234f380 TV |
108 | u32 avg_dependency_threshold; |
109 | }; | |
110 | ||
111 | enum tegra_actmon_device { | |
112 | MCALL = 0, | |
113 | MCCPU, | |
114 | }; | |
115 | ||
116 | static struct tegra_devfreq_device_config actmon_device_configs[] = { | |
117 | { | |
11573e91 | 118 | /* MCALL: All memory accesses (including from the CPUs) */ |
6234f380 TV |
119 | .offset = 0x1c0, |
120 | .irq_mask = 1 << 26, | |
121 | .boost_up_coeff = 200, | |
122 | .boost_down_coeff = 50, | |
123 | .boost_up_threshold = 60, | |
124 | .boost_down_threshold = 40, | |
125 | }, | |
126 | { | |
11573e91 | 127 | /* MCCPU: memory accesses from the CPUs */ |
6234f380 TV |
128 | .offset = 0x200, |
129 | .irq_mask = 1 << 25, | |
130 | .boost_up_coeff = 800, | |
131 | .boost_down_coeff = 90, | |
132 | .boost_up_threshold = 27, | |
133 | .boost_down_threshold = 10, | |
134 | .avg_dependency_threshold = 50000, | |
135 | }, | |
136 | }; | |
137 | ||
138 | /** | |
139 | * struct tegra_devfreq_device - state specific to an ACTMON device | |
140 | * | |
141 | * Frequencies are in kHz. | |
142 | */ | |
143 | struct tegra_devfreq_device { | |
144 | const struct tegra_devfreq_device_config *config; | |
11573e91 TV |
145 | void __iomem *regs; |
146 | spinlock_t lock; | |
6234f380 | 147 | |
11573e91 TV |
148 | /* Average event count sampled in the last interrupt */ |
149 | u32 avg_count; | |
6234f380 | 150 | |
11573e91 TV |
151 | /* |
152 | * Extra frequency to increase the target by due to consecutive | |
153 | * watermark breaches. | |
154 | */ | |
155 | unsigned long boost_freq; | |
156 | ||
157 | /* Optimal frequency calculated from the stats for this device */ | |
158 | unsigned long target_freq; | |
6234f380 TV |
159 | }; |
160 | ||
161 | struct tegra_devfreq { | |
162 | struct devfreq *devfreq; | |
163 | ||
6234f380 TV |
164 | struct reset_control *reset; |
165 | struct clk *clock; | |
166 | void __iomem *regs; | |
167 | ||
6234f380 TV |
168 | struct clk *emc_clock; |
169 | unsigned long max_freq; | |
170 | unsigned long cur_freq; | |
171 | struct notifier_block rate_change_nb; | |
172 | ||
173 | struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)]; | |
174 | }; | |
175 | ||
176 | struct tegra_actmon_emc_ratio { | |
177 | unsigned long cpu_freq; | |
178 | unsigned long emc_freq; | |
179 | }; | |
180 | ||
181 | static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = { | |
182 | { 1400000, ULONG_MAX }, | |
183 | { 1200000, 750000 }, | |
184 | { 1100000, 600000 }, | |
185 | { 1000000, 500000 }, | |
186 | { 800000, 375000 }, | |
187 | { 500000, 200000 }, | |
188 | { 250000, 100000 }, | |
189 | }; | |
190 | ||
11573e91 TV |
191 | static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) |
192 | { | |
193 | return readl(tegra->regs + offset); | |
194 | } | |
195 | ||
196 | static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) | |
197 | { | |
198 | writel(val, tegra->regs + offset); | |
199 | } | |
200 | ||
201 | static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset) | |
202 | { | |
203 | return readl(dev->regs + offset); | |
204 | } | |
205 | ||
206 | static void device_writel(struct tegra_devfreq_device *dev, u32 val, | |
207 | u32 offset) | |
208 | { | |
209 | writel(val, dev->regs + offset); | |
210 | } | |
211 | ||
6234f380 TV |
212 | static unsigned long do_percent(unsigned long val, unsigned int pct) |
213 | { | |
214 | return val * pct / 100; | |
215 | } | |
216 | ||
11573e91 TV |
217 | static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, |
218 | struct tegra_devfreq_device *dev) | |
6234f380 TV |
219 | { |
220 | u32 avg = dev->avg_count; | |
11573e91 TV |
221 | u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; |
222 | u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD; | |
223 | ||
224 | device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK); | |
6234f380 | 225 | |
11573e91 TV |
226 | avg = max(dev->avg_count, band); |
227 | device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK); | |
6234f380 TV |
228 | } |
229 | ||
230 | static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, | |
231 | struct tegra_devfreq_device *dev) | |
232 | { | |
233 | u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; | |
234 | ||
11573e91 TV |
235 | device_writel(dev, do_percent(val, dev->config->boost_up_threshold), |
236 | ACTMON_DEV_UPPER_WMARK); | |
6234f380 | 237 | |
11573e91 TV |
238 | device_writel(dev, do_percent(val, dev->config->boost_down_threshold), |
239 | ACTMON_DEV_LOWER_WMARK); | |
6234f380 TV |
240 | } |
241 | ||
242 | static void actmon_write_barrier(struct tegra_devfreq *tegra) | |
243 | { | |
244 | /* ensure the update has reached the ACTMON */ | |
245 | wmb(); | |
11573e91 | 246 | actmon_readl(tegra, ACTMON_GLB_STATUS); |
6234f380 TV |
247 | } |
248 | ||
11573e91 TV |
249 | static void actmon_isr_device(struct tegra_devfreq *tegra, |
250 | struct tegra_devfreq_device *dev) | |
6234f380 | 251 | { |
6234f380 | 252 | unsigned long flags; |
11573e91 | 253 | u32 intr_status, dev_ctrl; |
6234f380 | 254 | |
11573e91 | 255 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 | 256 | |
11573e91 TV |
257 | dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT); |
258 | tegra_devfreq_update_avg_wmark(tegra, dev); | |
6234f380 | 259 | |
11573e91 TV |
260 | intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS); |
261 | dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL); | |
6234f380 | 262 | |
11573e91 | 263 | if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) { |
6234f380 TV |
264 | /* |
265 | * new_boost = min(old_boost * up_coef + step, max_freq) | |
266 | */ | |
267 | dev->boost_freq = do_percent(dev->boost_freq, | |
268 | dev->config->boost_up_coeff); | |
269 | dev->boost_freq += ACTMON_BOOST_FREQ_STEP; | |
6234f380 | 270 | |
11573e91 TV |
271 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
272 | ||
273 | if (dev->boost_freq >= tegra->max_freq) | |
274 | dev->boost_freq = tegra->max_freq; | |
275 | else | |
276 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
277 | } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) { | |
6234f380 TV |
278 | /* |
279 | * new_boost = old_boost * down_coef | |
280 | * or 0 if (old_boost * down_coef < step / 2) | |
281 | */ | |
282 | dev->boost_freq = do_percent(dev->boost_freq, | |
283 | dev->config->boost_down_coeff); | |
11573e91 TV |
284 | |
285 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
286 | ||
287 | if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) | |
6234f380 | 288 | dev->boost_freq = 0; |
11573e91 TV |
289 | else |
290 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
6234f380 TV |
291 | } |
292 | ||
293 | if (dev->config->avg_dependency_threshold) { | |
6234f380 | 294 | if (dev->avg_count >= dev->config->avg_dependency_threshold) |
11573e91 | 295 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 | 296 | else if (dev->boost_freq == 0) |
11573e91 | 297 | dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 TV |
298 | } |
299 | ||
11573e91 TV |
300 | device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL); |
301 | ||
302 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
6234f380 TV |
303 | |
304 | actmon_write_barrier(tegra); | |
305 | ||
11573e91 TV |
306 | spin_unlock_irqrestore(&dev->lock, flags); |
307 | } | |
6234f380 | 308 | |
11573e91 TV |
309 | static irqreturn_t actmon_isr(int irq, void *data) |
310 | { | |
311 | struct tegra_devfreq *tegra = data; | |
312 | bool handled = false; | |
313 | unsigned int i; | |
314 | u32 val; | |
315 | ||
316 | val = actmon_readl(tegra, ACTMON_GLB_STATUS); | |
317 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
318 | if (val & tegra->devices[i].config->irq_mask) { | |
319 | actmon_isr_device(tegra, tegra->devices + i); | |
320 | handled = true; | |
321 | } | |
322 | } | |
323 | ||
324 | return handled ? IRQ_WAKE_THREAD : IRQ_NONE; | |
6234f380 TV |
325 | } |
326 | ||
327 | static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra, | |
328 | unsigned long cpu_freq) | |
329 | { | |
330 | unsigned int i; | |
331 | struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios; | |
332 | ||
333 | for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) { | |
334 | if (cpu_freq >= ratio->cpu_freq) { | |
335 | if (ratio->emc_freq >= tegra->max_freq) | |
336 | return tegra->max_freq; | |
337 | else | |
338 | return ratio->emc_freq; | |
339 | } | |
340 | } | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static void actmon_update_target(struct tegra_devfreq *tegra, | |
346 | struct tegra_devfreq_device *dev) | |
347 | { | |
348 | unsigned long cpu_freq = 0; | |
349 | unsigned long static_cpu_emc_freq = 0; | |
350 | unsigned int avg_sustain_coef; | |
351 | unsigned long flags; | |
352 | ||
353 | if (dev->config->avg_dependency_threshold) { | |
354 | cpu_freq = cpufreq_get(0); | |
355 | static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq); | |
356 | } | |
357 | ||
11573e91 | 358 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 TV |
359 | |
360 | dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD; | |
361 | avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; | |
362 | dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef); | |
363 | dev->target_freq += dev->boost_freq; | |
364 | ||
365 | if (dev->avg_count >= dev->config->avg_dependency_threshold) | |
366 | dev->target_freq = max(dev->target_freq, static_cpu_emc_freq); | |
367 | ||
11573e91 | 368 | spin_unlock_irqrestore(&dev->lock, flags); |
6234f380 TV |
369 | } |
370 | ||
371 | static irqreturn_t actmon_thread_isr(int irq, void *data) | |
372 | { | |
373 | struct tegra_devfreq *tegra = data; | |
374 | ||
375 | mutex_lock(&tegra->devfreq->lock); | |
376 | update_devfreq(tegra->devfreq); | |
377 | mutex_unlock(&tegra->devfreq->lock); | |
378 | ||
379 | return IRQ_HANDLED; | |
380 | } | |
381 | ||
382 | static int tegra_actmon_rate_notify_cb(struct notifier_block *nb, | |
383 | unsigned long action, void *ptr) | |
384 | { | |
385 | struct clk_notifier_data *data = ptr; | |
11573e91 TV |
386 | struct tegra_devfreq *tegra; |
387 | struct tegra_devfreq_device *dev; | |
6234f380 TV |
388 | unsigned int i; |
389 | unsigned long flags; | |
390 | ||
11573e91 TV |
391 | if (action != POST_RATE_CHANGE) |
392 | return NOTIFY_OK; | |
6234f380 | 393 | |
11573e91 | 394 | tegra = container_of(nb, struct tegra_devfreq, rate_change_nb); |
6234f380 | 395 | |
11573e91 | 396 | tegra->cur_freq = data->new_rate / KHZ; |
6234f380 | 397 | |
11573e91 TV |
398 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
399 | dev = &tegra->devices[i]; | |
400 | ||
401 | spin_lock_irqsave(&dev->lock, flags); | |
402 | tegra_devfreq_update_wmark(tegra, dev); | |
403 | spin_unlock_irqrestore(&dev->lock, flags); | |
404 | } | |
6234f380 | 405 | |
11573e91 | 406 | actmon_write_barrier(tegra); |
6234f380 TV |
407 | |
408 | return NOTIFY_OK; | |
409 | } | |
410 | ||
11573e91 | 411 | static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 412 | { |
11573e91 | 413 | struct tegra_devfreq_device *dev; |
6234f380 | 414 | u32 val; |
11573e91 | 415 | unsigned int i; |
6234f380 | 416 | |
11573e91 TV |
417 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
418 | dev = &tegra->devices[i]; | |
6234f380 | 419 | |
11573e91 TV |
420 | val = device_readl(dev, ACTMON_DEV_CTRL); |
421 | val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
422 | val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
423 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
424 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 425 | |
11573e91 TV |
426 | device_writel(dev, val, ACTMON_DEV_CTRL); |
427 | } | |
6234f380 TV |
428 | |
429 | actmon_write_barrier(tegra); | |
430 | } | |
431 | ||
11573e91 | 432 | static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 433 | { |
11573e91 | 434 | struct tegra_devfreq_device *dev; |
6234f380 | 435 | u32 val; |
11573e91 | 436 | unsigned int i; |
6234f380 TV |
437 | |
438 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
11573e91 | 439 | dev = &tegra->devices[i]; |
6234f380 | 440 | |
11573e91 TV |
441 | val = device_readl(dev, ACTMON_DEV_CTRL); |
442 | val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
443 | val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
444 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
445 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 446 | |
11573e91 | 447 | device_writel(dev, val, ACTMON_DEV_CTRL); |
6234f380 TV |
448 | } |
449 | ||
11573e91 | 450 | actmon_write_barrier(tegra); |
6234f380 TV |
451 | } |
452 | ||
11573e91 TV |
453 | static void tegra_actmon_configure_device(struct tegra_devfreq *tegra, |
454 | struct tegra_devfreq_device *dev) | |
6234f380 | 455 | { |
11573e91 | 456 | u32 val = 0; |
6234f380 | 457 | |
11573e91 | 458 | dev->target_freq = tegra->cur_freq; |
6234f380 | 459 | |
11573e91 TV |
460 | dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; |
461 | device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG); | |
6234f380 | 462 | |
11573e91 TV |
463 | tegra_devfreq_update_avg_wmark(tegra, dev); |
464 | tegra_devfreq_update_wmark(tegra, dev); | |
6234f380 | 465 | |
11573e91 TV |
466 | device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT); |
467 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
468 | ||
469 | val |= ACTMON_DEV_CTRL_ENB_PERIODIC; | |
470 | val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1) | |
471 | << ACTMON_DEV_CTRL_K_VAL_SHIFT; | |
472 | val |= (ACTMON_BELOW_WMARK_WINDOW - 1) | |
473 | << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT; | |
474 | val |= (ACTMON_ABOVE_WMARK_WINDOW - 1) | |
475 | << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT; | |
476 | val |= ACTMON_DEV_CTRL_ENB; | |
477 | ||
478 | device_writel(dev, val, ACTMON_DEV_CTRL); | |
479 | ||
480 | actmon_write_barrier(tegra); | |
6234f380 TV |
481 | } |
482 | ||
483 | static int tegra_devfreq_target(struct device *dev, unsigned long *freq, | |
484 | u32 flags) | |
485 | { | |
11573e91 | 486 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
487 | struct dev_pm_opp *opp; |
488 | unsigned long rate = *freq * KHZ; | |
489 | ||
6234f380 TV |
490 | rcu_read_lock(); |
491 | opp = devfreq_recommended_opp(dev, &rate, flags); | |
492 | if (IS_ERR(opp)) { | |
493 | rcu_read_unlock(); | |
494 | dev_err(dev, "Failed to find opp for %lu KHz\n", *freq); | |
495 | return PTR_ERR(opp); | |
496 | } | |
497 | rate = dev_pm_opp_get_freq(opp); | |
498 | rcu_read_unlock(); | |
499 | ||
c70eea73 TV |
500 | clk_set_min_rate(tegra->emc_clock, rate); |
501 | clk_set_rate(tegra->emc_clock, 0); | |
6234f380 | 502 | |
dbb0c7c4 TV |
503 | *freq = rate; |
504 | ||
6234f380 TV |
505 | return 0; |
506 | } | |
507 | ||
508 | static int tegra_devfreq_get_dev_status(struct device *dev, | |
509 | struct devfreq_dev_status *stat) | |
510 | { | |
11573e91 | 511 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
512 | struct tegra_devfreq_device *actmon_dev; |
513 | ||
6234f380 TV |
514 | stat->current_frequency = tegra->cur_freq; |
515 | ||
516 | /* To be used by the tegra governor */ | |
517 | stat->private_data = tegra; | |
518 | ||
519 | /* The below are to be used by the other governors */ | |
520 | ||
521 | actmon_dev = &tegra->devices[MCALL]; | |
522 | ||
523 | /* Number of cycles spent on memory access */ | |
11573e91 | 524 | stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT); |
6234f380 TV |
525 | |
526 | /* The bus can be considered to be saturated way before 100% */ | |
527 | stat->busy_time *= 100 / BUS_SATURATION_RATIO; | |
528 | ||
529 | /* Number of cycles in a sampling period */ | |
530 | stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq; | |
531 | ||
11573e91 TV |
532 | stat->busy_time = min(stat->busy_time, stat->total_time); |
533 | ||
6234f380 TV |
534 | return 0; |
535 | } | |
536 | ||
11573e91 TV |
537 | static struct devfreq_dev_profile tegra_devfreq_profile = { |
538 | .polling_ms = 0, | |
539 | .target = tegra_devfreq_target, | |
540 | .get_dev_status = tegra_devfreq_get_dev_status, | |
541 | }; | |
542 | ||
543 | static int tegra_governor_get_target(struct devfreq *devfreq, | |
544 | unsigned long *freq) | |
6234f380 | 545 | { |
14de3903 | 546 | struct devfreq_dev_status *stat; |
6234f380 TV |
547 | struct tegra_devfreq *tegra; |
548 | struct tegra_devfreq_device *dev; | |
549 | unsigned long target_freq = 0; | |
550 | unsigned int i; | |
551 | int err; | |
552 | ||
14de3903 | 553 | err = devfreq_update_stats(devfreq); |
6234f380 TV |
554 | if (err) |
555 | return err; | |
556 | ||
14de3903 MH |
557 | stat = &devfreq->last_status; |
558 | ||
559 | tegra = stat->private_data; | |
6234f380 TV |
560 | |
561 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
562 | dev = &tegra->devices[i]; | |
563 | ||
564 | actmon_update_target(tegra, dev); | |
565 | ||
566 | target_freq = max(target_freq, dev->target_freq); | |
567 | } | |
568 | ||
569 | *freq = target_freq; | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
11573e91 TV |
574 | static int tegra_governor_event_handler(struct devfreq *devfreq, |
575 | unsigned int event, void *data) | |
6234f380 | 576 | { |
11573e91 TV |
577 | struct tegra_devfreq *tegra; |
578 | int ret = 0; | |
579 | ||
580 | tegra = dev_get_drvdata(devfreq->dev.parent); | |
581 | ||
582 | switch (event) { | |
583 | case DEVFREQ_GOV_START: | |
11573e91 | 584 | devfreq_monitor_start(devfreq); |
34ed5040 | 585 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
586 | break; |
587 | ||
588 | case DEVFREQ_GOV_STOP: | |
589 | tegra_actmon_disable_interrupts(tegra); | |
590 | devfreq_monitor_stop(devfreq); | |
591 | break; | |
592 | ||
593 | case DEVFREQ_GOV_SUSPEND: | |
594 | tegra_actmon_disable_interrupts(tegra); | |
595 | devfreq_monitor_suspend(devfreq); | |
596 | break; | |
597 | ||
598 | case DEVFREQ_GOV_RESUME: | |
11573e91 | 599 | devfreq_monitor_resume(devfreq); |
34ed5040 | 600 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
601 | break; |
602 | } | |
603 | ||
604 | return ret; | |
6234f380 TV |
605 | } |
606 | ||
607 | static struct devfreq_governor tegra_devfreq_governor = { | |
11573e91 TV |
608 | .name = "tegra_actmon", |
609 | .get_target_freq = tegra_governor_get_target, | |
610 | .event_handler = tegra_governor_event_handler, | |
6234f380 TV |
611 | }; |
612 | ||
6234f380 TV |
613 | static int tegra_devfreq_probe(struct platform_device *pdev) |
614 | { | |
615 | struct tegra_devfreq *tegra; | |
616 | struct tegra_devfreq_device *dev; | |
617 | struct resource *res; | |
6234f380 | 618 | unsigned int i; |
5d498b46 | 619 | unsigned long rate; |
6234f380 TV |
620 | int irq; |
621 | int err; | |
622 | ||
623 | tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); | |
624 | if (!tegra) | |
625 | return -ENOMEM; | |
626 | ||
6234f380 | 627 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6234f380 TV |
628 | |
629 | tegra->regs = devm_ioremap_resource(&pdev->dev, res); | |
11573e91 | 630 | if (IS_ERR(tegra->regs)) |
6234f380 | 631 | return PTR_ERR(tegra->regs); |
6234f380 TV |
632 | |
633 | tegra->reset = devm_reset_control_get(&pdev->dev, "actmon"); | |
634 | if (IS_ERR(tegra->reset)) { | |
635 | dev_err(&pdev->dev, "Failed to get reset\n"); | |
636 | return PTR_ERR(tegra->reset); | |
637 | } | |
638 | ||
639 | tegra->clock = devm_clk_get(&pdev->dev, "actmon"); | |
640 | if (IS_ERR(tegra->clock)) { | |
641 | dev_err(&pdev->dev, "Failed to get actmon clock\n"); | |
642 | return PTR_ERR(tegra->clock); | |
643 | } | |
644 | ||
645 | tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); | |
646 | if (IS_ERR(tegra->emc_clock)) { | |
647 | dev_err(&pdev->dev, "Failed to get emc clock\n"); | |
648 | return PTR_ERR(tegra->emc_clock); | |
649 | } | |
650 | ||
c70eea73 TV |
651 | clk_set_rate(tegra->emc_clock, ULONG_MAX); |
652 | ||
6234f380 TV |
653 | tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb; |
654 | err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); | |
655 | if (err) { | |
656 | dev_err(&pdev->dev, | |
657 | "Failed to register rate change notifier\n"); | |
658 | return err; | |
659 | } | |
660 | ||
661 | reset_control_assert(tegra->reset); | |
662 | ||
663 | err = clk_prepare_enable(tegra->clock); | |
664 | if (err) { | |
11573e91 TV |
665 | dev_err(&pdev->dev, |
666 | "Failed to prepare and enable ACTMON clock\n"); | |
6234f380 TV |
667 | return err; |
668 | } | |
669 | ||
670 | reset_control_deassert(tegra->reset); | |
671 | ||
c70eea73 | 672 | tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ; |
6234f380 TV |
673 | tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; |
674 | ||
11573e91 TV |
675 | actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1, |
676 | ACTMON_GLB_PERIOD_CTRL); | |
6234f380 TV |
677 | |
678 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
679 | dev = tegra->devices + i; | |
680 | dev->config = actmon_device_configs + i; | |
681 | dev->regs = tegra->regs + dev->config->offset; | |
11573e91 | 682 | spin_lock_init(&dev->lock); |
6234f380 | 683 | |
11573e91 | 684 | tegra_actmon_configure_device(tegra, dev); |
6234f380 TV |
685 | } |
686 | ||
5d498b46 TV |
687 | for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { |
688 | rate = clk_round_rate(tegra->emc_clock, rate); | |
689 | dev_pm_opp_add(&pdev->dev, rate, 0); | |
690 | } | |
691 | ||
11573e91 TV |
692 | irq = platform_get_irq(pdev, 0); |
693 | if (irq <= 0) { | |
694 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
695 | return -ENODEV; | |
6234f380 TV |
696 | } |
697 | ||
2da19b1a TV |
698 | platform_set_drvdata(pdev, tegra); |
699 | ||
6234f380 TV |
700 | err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr, |
701 | actmon_thread_isr, IRQF_SHARED, | |
702 | "tegra-devfreq", tegra); | |
703 | if (err) { | |
704 | dev_err(&pdev->dev, "Interrupt request failed\n"); | |
705 | return err; | |
706 | } | |
707 | ||
11573e91 TV |
708 | tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock); |
709 | tegra->devfreq = devm_devfreq_add_device(&pdev->dev, | |
710 | &tegra_devfreq_profile, | |
711 | "tegra_actmon", | |
712 | NULL); | |
713 | ||
6234f380 TV |
714 | return 0; |
715 | } | |
716 | ||
717 | static int tegra_devfreq_remove(struct platform_device *pdev) | |
718 | { | |
719 | struct tegra_devfreq *tegra = platform_get_drvdata(pdev); | |
11573e91 TV |
720 | int irq = platform_get_irq(pdev, 0); |
721 | u32 val; | |
722 | unsigned int i; | |
723 | ||
724 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
725 | val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL); | |
726 | val &= ~ACTMON_DEV_CTRL_ENB; | |
727 | device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL); | |
728 | } | |
729 | ||
730 | actmon_write_barrier(tegra); | |
731 | ||
732 | devm_free_irq(&pdev->dev, irq, tegra); | |
6234f380 TV |
733 | |
734 | clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb); | |
735 | ||
736 | clk_disable_unprepare(tegra->clock); | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
11573e91 | 741 | static const struct of_device_id tegra_devfreq_of_match[] = { |
6234f380 TV |
742 | { .compatible = "nvidia,tegra124-actmon" }, |
743 | { }, | |
744 | }; | |
745 | ||
11573e91 TV |
746 | MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match); |
747 | ||
6234f380 TV |
748 | static struct platform_driver tegra_devfreq_driver = { |
749 | .probe = tegra_devfreq_probe, | |
750 | .remove = tegra_devfreq_remove, | |
751 | .driver = { | |
11573e91 | 752 | .name = "tegra-devfreq", |
6234f380 | 753 | .of_match_table = tegra_devfreq_of_match, |
6234f380 TV |
754 | }, |
755 | }; | |
358b615f TV |
756 | |
757 | static int __init tegra_devfreq_init(void) | |
758 | { | |
759 | int ret = 0; | |
760 | ||
761 | ret = devfreq_add_governor(&tegra_devfreq_governor); | |
762 | if (ret) { | |
763 | pr_err("%s: failed to add governor: %d\n", __func__, ret); | |
764 | return ret; | |
765 | } | |
766 | ||
767 | ret = platform_driver_register(&tegra_devfreq_driver); | |
768 | if (ret) | |
769 | devfreq_remove_governor(&tegra_devfreq_governor); | |
770 | ||
771 | return ret; | |
772 | } | |
773 | module_init(tegra_devfreq_init) | |
774 | ||
775 | static void __exit tegra_devfreq_exit(void) | |
776 | { | |
777 | int ret = 0; | |
778 | ||
779 | platform_driver_unregister(&tegra_devfreq_driver); | |
780 | ||
781 | ret = devfreq_remove_governor(&tegra_devfreq_governor); | |
782 | if (ret) | |
783 | pr_err("%s: failed to remove governor: %d\n", __func__, ret); | |
784 | } | |
785 | module_exit(tegra_devfreq_exit) | |
6234f380 | 786 | |
11573e91 | 787 | MODULE_LICENSE("GPL v2"); |
6234f380 TV |
788 | MODULE_DESCRIPTION("Tegra devfreq driver"); |
789 | MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>"); |