Commit | Line | Data |
---|---|---|
c13c8260 CL |
1 | # |
2 | # DMA engine configuration | |
3 | # | |
4 | ||
2ed6dc34 | 5 | menuconfig DMADEVICES |
6d4f5879 | 6 | bool "DMA Engine support" |
04ce9ab3 | 7 | depends on HAS_DMA |
2ed6dc34 | 8 | help |
6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
10 | involving the host CPU. Currently, this framework can be | |
11 | used to offload memory copies in the network stack and | |
9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
13 | DMA Device drivers supported by the configured arch, it may | |
14 | be empty in some cases. | |
2ed6dc34 | 15 | |
6c664a89 LW |
16 | config DMADEVICES_DEBUG |
17 | bool "DMA Engine debugging" | |
18 | depends on DMADEVICES != n | |
19 | help | |
20 | This is an option for use by developers; most people should | |
21 | say N here. This enables DMA engine core and driver debugging. | |
22 | ||
23 | config DMADEVICES_VDEBUG | |
24 | bool "DMA Engine verbose debugging" | |
25 | depends on DMADEVICES_DEBUG != n | |
26 | help | |
27 | This is an option for use by developers; most people should | |
28 | say N here. This enables deeper (more verbose) debugging of | |
29 | the DMA engine core and drivers. | |
30 | ||
31 | ||
2ed6dc34 SN |
32 | if DMADEVICES |
33 | ||
34 | comment "DMA Devices" | |
35 | ||
b3c567e4 VK |
36 | config INTEL_MID_DMAC |
37 | tristate "Intel MID DMA support for Peripheral DMA controllers" | |
38 | depends on PCI && X86 | |
39 | select DMA_ENGINE | |
40 | default n | |
41 | help | |
42 | Enable support for the Intel(R) MID DMA engine present | |
43 | in Intel MID chipsets. | |
44 | ||
45 | Say Y here if you have such a chipset. | |
46 | ||
47 | If unsure, say N. | |
48 | ||
5fc6d897 | 49 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
50 | bool |
51 | ||
e8689e63 LW |
52 | config AMBA_PL08X |
53 | bool "ARM PrimeCell PL080 or PL081 support" | |
54 | depends on ARM_AMBA && EXPERIMENTAL | |
55 | select DMA_ENGINE | |
56 | help | |
57 | Platform has a PL08x DMAC device | |
58 | which can provide DMA engine support | |
59 | ||
2ed6dc34 SN |
60 | config INTEL_IOATDMA |
61 | tristate "Intel I/OAT DMA support" | |
62 | depends on PCI && X86 | |
63 | select DMA_ENGINE | |
64 | select DCA | |
7b3cc2b1 DW |
65 | select ASYNC_TX_DISABLE_PQ_VAL_DMA |
66 | select ASYNC_TX_DISABLE_XOR_VAL_DMA | |
2ed6dc34 SN |
67 | help |
68 | Enable support for the Intel(R) I/OAT DMA engine present | |
69 | in recent Intel Xeon chipsets. | |
70 | ||
71 | Say Y here if you have such a chipset. | |
72 | ||
73 | If unsure, say N. | |
74 | ||
75 | config INTEL_IOP_ADMA | |
76 | tristate "Intel IOP ADMA support" | |
77 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
2ed6dc34 | 78 | select DMA_ENGINE |
5fc6d897 | 79 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
2ed6dc34 SN |
80 | help |
81 | Enable support for the Intel(R) IOP Series RAID engines. | |
c13c8260 | 82 | |
3bfb1d20 HS |
83 | config DW_DMAC |
84 | tristate "Synopsys DesignWare AHB DMA support" | |
f44ad7e9 | 85 | depends on HAVE_CLK |
3bfb1d20 HS |
86 | select DMA_ENGINE |
87 | default y if CPU_AT32AP7000 | |
88 | help | |
89 | Support the Synopsys DesignWare AHB DMA controller. This | |
90 | can be integrated in chips such as the Atmel AT32ap7000. | |
91 | ||
dc78baa2 NF |
92 | config AT_HDMAC |
93 | tristate "Atmel AHB DMA support" | |
cd3abf98 | 94 | depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 |
dc78baa2 NF |
95 | select DMA_ENGINE |
96 | help | |
97 | Support the Atmel AHB DMA controller. This can be integrated in | |
98 | chips such as the Atmel AT91SAM9RL. | |
99 | ||
173acc7c | 100 | config FSL_DMA |
77cd62e8 TT |
101 | tristate "Freescale Elo and Elo Plus DMA support" |
102 | depends on FSL_SOC | |
173acc7c | 103 | select DMA_ENGINE |
5fc6d897 | 104 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
173acc7c | 105 | ---help--- |
77cd62e8 TT |
106 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
107 | The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
108 | Elo Plus is the DMA controller on 85xx and 86xx parts. | |
173acc7c | 109 | |
0fb6f739 PZ |
110 | config MPC512X_DMA |
111 | tristate "Freescale MPC512x built-in DMA engine support" | |
ba2eea25 | 112 | depends on PPC_MPC512x || PPC_MPC831x |
0fb6f739 PZ |
113 | select DMA_ENGINE |
114 | ---help--- | |
115 | Enable support for the Freescale MPC512x built-in DMA engine. | |
116 | ||
ff7b0479 SB |
117 | config MV_XOR |
118 | bool "Marvell XOR engine support" | |
119 | depends on PLAT_ORION | |
ff7b0479 | 120 | select DMA_ENGINE |
5fc6d897 | 121 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
ff7b0479 SB |
122 | ---help--- |
123 | Enable support for the Marvell XOR engine. | |
124 | ||
5296b56d GL |
125 | config MX3_IPU |
126 | bool "MX3x Image Processing Unit support" | |
127 | depends on ARCH_MX3 | |
128 | select DMA_ENGINE | |
129 | default y | |
130 | help | |
131 | If you plan to use the Image Processing unit in the i.MX3x, say | |
132 | Y here. If unsure, select Y. | |
133 | ||
134 | config MX3_IPU_IRQS | |
135 | int "Number of dynamically mapped interrupts for IPU" | |
136 | depends on MX3_IPU | |
137 | range 2 137 | |
138 | default 4 | |
139 | help | |
140 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
141 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
142 | number of IRQ slots and map them dynamically to specific sources. | |
143 | ||
ea76f0b3 AN |
144 | config TXX9_DMAC |
145 | tristate "Toshiba TXx9 SoC DMA support" | |
146 | depends on MACH_TX49XX || MACH_TX39XX | |
147 | select DMA_ENGINE | |
148 | help | |
149 | Support the TXx9 SoC internal DMA controller. This can be | |
150 | integrated in chips such as the Toshiba TX4927/38/39. | |
151 | ||
d8902adc NI |
152 | config SH_DMAE |
153 | tristate "Renesas SuperH DMAC support" | |
927a7c9c | 154 | depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE) |
d8902adc NI |
155 | depends on !SH_DMA_API |
156 | select DMA_ENGINE | |
157 | help | |
158 | Enable support for the Renesas SuperH DMA controllers. | |
159 | ||
61f135b9 LW |
160 | config COH901318 |
161 | bool "ST-Ericsson COH901318 DMA support" | |
162 | select DMA_ENGINE | |
163 | depends on ARCH_U300 | |
164 | help | |
165 | Enable support for ST-Ericsson COH 901 318 DMA. | |
166 | ||
8d318a50 LW |
167 | config STE_DMA40 |
168 | bool "ST-Ericsson DMA40 support" | |
169 | depends on ARCH_U8500 | |
170 | select DMA_ENGINE | |
171 | help | |
172 | Support for ST-Ericsson DMA40 controller | |
173 | ||
12458ea0 AG |
174 | config AMCC_PPC440SPE_ADMA |
175 | tristate "AMCC PPC440SPe ADMA support" | |
176 | depends on 440SPe || 440SP | |
177 | select DMA_ENGINE | |
178 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL | |
5fc6d897 | 179 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
12458ea0 AG |
180 | help |
181 | Enable support for the AMCC PPC440SPe RAID engines. | |
182 | ||
de5d4453 RR |
183 | config TIMB_DMA |
184 | tristate "Timberdale FPGA DMA support" | |
185 | depends on MFD_TIMBERDALE || HAS_IOMEM | |
186 | select DMA_ENGINE | |
187 | help | |
188 | Enable support for the Timberdale FPGA DMA engine. | |
189 | ||
12458ea0 AG |
190 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
191 | bool | |
192 | ||
b3040e40 JB |
193 | config PL330_DMA |
194 | tristate "DMA API Driver for PL330" | |
195 | select DMA_ENGINE | |
196 | depends on PL330 | |
197 | help | |
198 | Select if your platform has one or more PL330 DMACs. | |
199 | You need to provide platform specific settings via | |
200 | platform_data for a dma-pl330 device. | |
201 | ||
0c42bd0e | 202 | config PCH_DMA |
c0dfc04a | 203 | tristate "Intel EG20T PCH / OKI Semi IOH(ML7213/ML7223) DMA support" |
0c42bd0e YW |
204 | depends on PCI && X86 |
205 | select DMA_ENGINE | |
206 | help | |
2cdf2455 TM |
207 | Enable support for Intel EG20T PCH DMA engine. |
208 | ||
c0dfc04a TM |
209 | This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ |
210 | Output Hub), ML7213 and ML7223. | |
211 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is | |
212 | for MP(Media Phone) use. | |
213 | ML7213/ML7223 is companion chip for Intel Atom E6xx series. | |
214 | ML7213/ML7223 is completely compatible for Intel EG20T PCH. | |
0c42bd0e | 215 | |
1ec1e82f SH |
216 | config IMX_SDMA |
217 | tristate "i.MX SDMA support" | |
218 | depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5 | |
219 | select DMA_ENGINE | |
220 | help | |
221 | Support the i.MX SDMA engine. This engine is integrated into | |
222 | Freescale i.MX25/31/35/51 chips. | |
223 | ||
1f1846c6 SH |
224 | config IMX_DMA |
225 | tristate "i.MX DMA support" | |
5b9a4f98 | 226 | depends on IMX_HAVE_DMA_V1 |
1f1846c6 SH |
227 | select DMA_ENGINE |
228 | help | |
229 | Support the i.MX DMA engine. This engine is integrated into | |
230 | Freescale i.MX1/21/27 chips. | |
231 | ||
a580b8c5 SG |
232 | config MXS_DMA |
233 | bool "MXS DMA support" | |
234 | depends on SOC_IMX23 || SOC_IMX28 | |
235 | select DMA_ENGINE | |
236 | help | |
237 | Support the MXS DMA engine. This engine including APBH-DMA | |
238 | and APBX-DMA is integrated into Freescale i.MX23/28 chips. | |
239 | ||
760ee1c4 MW |
240 | config EP93XX_DMA |
241 | bool "Cirrus Logic EP93xx DMA support" | |
242 | depends on ARCH_EP93XX | |
243 | select DMA_ENGINE | |
244 | help | |
245 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. | |
246 | ||
c13c8260 | 247 | config DMA_ENGINE |
2ed6dc34 | 248 | bool |
c13c8260 | 249 | |
db217334 | 250 | comment "DMA Clients" |
2ed6dc34 | 251 | depends on DMA_ENGINE |
db217334 CL |
252 | |
253 | config NET_DMA | |
254 | bool "Network: TCP receive copy offload" | |
255 | depends on DMA_ENGINE && NET | |
9c402f4e | 256 | default (INTEL_IOATDMA || FSL_DMA) |
2ed6dc34 | 257 | help |
db217334 CL |
258 | This enables the use of DMA engines in the network stack to |
259 | offload receive copy-to-user operations, freeing CPU cycles. | |
9c402f4e DW |
260 | |
261 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
262 | say N. | |
db217334 | 263 | |
729b5d1b DW |
264 | config ASYNC_TX_DMA |
265 | bool "Async_tx: Offload support for the async_tx api" | |
9a8de639 | 266 | depends on DMA_ENGINE |
729b5d1b DW |
267 | help |
268 | This allows the async_tx api to take advantage of offload engines for | |
269 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
270 | a dma engine that can perform raid operations and you have enabled | |
271 | MD_RAID456 say Y. | |
272 | ||
273 | If unsure, say N. | |
274 | ||
4a776f0a HS |
275 | config DMATEST |
276 | tristate "DMA Test client" | |
277 | depends on DMA_ENGINE | |
278 | help | |
279 | Simple DMA test client. Say N unless you're debugging a | |
280 | DMA Device driver. | |
281 | ||
2ed6dc34 | 282 | endif |