Commit | Line | Data |
---|---|---|
c13c8260 CL |
1 | # |
2 | # DMA engine configuration | |
3 | # | |
4 | ||
2ed6dc34 | 5 | menuconfig DMADEVICES |
6d4f5879 | 6 | bool "DMA Engine support" |
04ce9ab3 | 7 | depends on HAS_DMA |
2ed6dc34 | 8 | help |
6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
10 | involving the host CPU. Currently, this framework can be | |
11 | used to offload memory copies in the network stack and | |
9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
13 | DMA Device drivers supported by the configured arch, it may | |
14 | be empty in some cases. | |
2ed6dc34 | 15 | |
6c664a89 LW |
16 | config DMADEVICES_DEBUG |
17 | bool "DMA Engine debugging" | |
18 | depends on DMADEVICES != n | |
19 | help | |
20 | This is an option for use by developers; most people should | |
21 | say N here. This enables DMA engine core and driver debugging. | |
22 | ||
23 | config DMADEVICES_VDEBUG | |
24 | bool "DMA Engine verbose debugging" | |
25 | depends on DMADEVICES_DEBUG != n | |
26 | help | |
27 | This is an option for use by developers; most people should | |
28 | say N here. This enables deeper (more verbose) debugging of | |
29 | the DMA engine core and drivers. | |
30 | ||
31 | ||
2ed6dc34 SN |
32 | if DMADEVICES |
33 | ||
34 | comment "DMA Devices" | |
35 | ||
95b4ecbf SY |
36 | config INTEL_MIC_X100_DMA |
37 | tristate "Intel MIC X100 DMA Driver" | |
38 | depends on 64BIT && X86 && INTEL_MIC_BUS | |
ce05b686 | 39 | select DMA_ENGINE |
95b4ecbf SY |
40 | help |
41 | This enables DMA support for the Intel Many Integrated Core | |
42 | (MIC) family of PCIe form factor coprocessor X100 devices that | |
43 | run a 64 bit Linux OS. This driver will be used by both MIC | |
44 | host and card drivers. | |
45 | ||
46 | If you are building host kernel with a MIC device or a card | |
47 | kernel for a MIC device, then say M (recommended) or Y, else | |
48 | say N. If unsure say N. | |
49 | ||
50 | More information about the Intel MIC family as well as the Linux | |
51 | OS and tools for MIC to use with this driver are available from | |
52 | <http://software.intel.com/en-us/mic-developer>. | |
53 | ||
5fc6d897 | 54 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
55 | bool |
56 | ||
e8689e63 LW |
57 | config AMBA_PL08X |
58 | bool "ARM PrimeCell PL080 or PL081 support" | |
c6a0aec9 | 59 | depends on ARM_AMBA |
e8689e63 | 60 | select DMA_ENGINE |
083be28a | 61 | select DMA_VIRTUAL_CHANNELS |
e8689e63 LW |
62 | help |
63 | Platform has a PL08x DMAC device | |
64 | which can provide DMA engine support | |
65 | ||
2ed6dc34 SN |
66 | config INTEL_IOATDMA |
67 | tristate "Intel I/OAT DMA support" | |
68 | depends on PCI && X86 | |
69 | select DMA_ENGINE | |
3cc377b9 | 70 | select DMA_ENGINE_RAID |
2ed6dc34 SN |
71 | select DCA |
72 | help | |
73 | Enable support for the Intel(R) I/OAT DMA engine present | |
74 | in recent Intel Xeon chipsets. | |
75 | ||
76 | Say Y here if you have such a chipset. | |
77 | ||
78 | If unsure, say N. | |
79 | ||
80 | config INTEL_IOP_ADMA | |
81 | tristate "Intel IOP ADMA support" | |
82 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
2ed6dc34 | 83 | select DMA_ENGINE |
5fc6d897 | 84 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
2ed6dc34 SN |
85 | help |
86 | Enable support for the Intel(R) IOP Series RAID engines. | |
c13c8260 | 87 | |
61a76496 | 88 | source "drivers/dma/dw/Kconfig" |
d5ea7b5e | 89 | |
dc78baa2 NF |
90 | config AT_HDMAC |
91 | tristate "Atmel AHB DMA support" | |
f898fed0 | 92 | depends on ARCH_AT91 |
dc78baa2 NF |
93 | select DMA_ENGINE |
94 | help | |
f898fed0 | 95 | Support the Atmel AHB DMA controller. |
dc78baa2 | 96 | |
e1f7c9ee LD |
97 | config AT_XDMAC |
98 | tristate "Atmel XDMA support" | |
6e5ae29b | 99 | depends on ARCH_AT91 |
e1f7c9ee LD |
100 | select DMA_ENGINE |
101 | help | |
102 | Support the Atmel XDMA controller. | |
103 | ||
173acc7c | 104 | config FSL_DMA |
8de7a7d9 | 105 | tristate "Freescale Elo series DMA support" |
77cd62e8 | 106 | depends on FSL_SOC |
173acc7c | 107 | select DMA_ENGINE |
5fc6d897 | 108 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
173acc7c | 109 | ---help--- |
8de7a7d9 HZ |
110 | Enable support for the Freescale Elo series DMA controllers. |
111 | The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the | |
112 | EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on | |
113 | some Txxx and Bxxx parts. | |
173acc7c | 114 | |
ad80da65 XS |
115 | config FSL_RAID |
116 | tristate "Freescale RAID engine Support" | |
117 | depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH | |
118 | select DMA_ENGINE | |
119 | select DMA_ENGINE_RAID | |
120 | ---help--- | |
121 | Enable support for Freescale RAID Engine. RAID Engine is | |
122 | available on some QorIQ SoCs (like P5020/P5040). It has | |
123 | the capability to offload memcpy, xor and pq computation | |
124 | for raid5/6. | |
125 | ||
2b49e0c5 AS |
126 | source "drivers/dma/hsu/Kconfig" |
127 | ||
0fb6f739 PZ |
128 | config MPC512X_DMA |
129 | tristate "Freescale MPC512x built-in DMA engine support" | |
ba2eea25 | 130 | depends on PPC_MPC512x || PPC_MPC831x |
0fb6f739 PZ |
131 | select DMA_ENGINE |
132 | ---help--- | |
133 | Enable support for the Freescale MPC512x built-in DMA engine. | |
134 | ||
9a322993 PDM |
135 | source "drivers/dma/bestcomm/Kconfig" |
136 | ||
ff7b0479 SB |
137 | config MV_XOR |
138 | bool "Marvell XOR engine support" | |
139 | depends on PLAT_ORION | |
ff7b0479 | 140 | select DMA_ENGINE |
3cc377b9 | 141 | select DMA_ENGINE_RAID |
5fc6d897 | 142 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
ff7b0479 SB |
143 | ---help--- |
144 | Enable support for the Marvell XOR engine. | |
145 | ||
5296b56d GL |
146 | config MX3_IPU |
147 | bool "MX3x Image Processing Unit support" | |
8e2d41f8 | 148 | depends on ARCH_MXC |
5296b56d GL |
149 | select DMA_ENGINE |
150 | default y | |
151 | help | |
152 | If you plan to use the Image Processing unit in the i.MX3x, say | |
153 | Y here. If unsure, select Y. | |
154 | ||
155 | config MX3_IPU_IRQS | |
156 | int "Number of dynamically mapped interrupts for IPU" | |
157 | depends on MX3_IPU | |
158 | range 2 137 | |
159 | default 4 | |
160 | help | |
161 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
162 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
163 | number of IRQ slots and map them dynamically to specific sources. | |
164 | ||
a57e16cf RJ |
165 | config PXA_DMA |
166 | bool "PXA DMA support" | |
167 | depends on (ARCH_MMP || ARCH_PXA) | |
168 | select DMA_ENGINE | |
169 | select DMA_VIRTUAL_CHANNELS | |
170 | help | |
171 | Support the DMA engine for PXA. It is also compatible with MMP PDMA | |
172 | platform. The internal DMA IP of all PXA variants is supported, with | |
173 | 16 to 32 channels for peripheral to memory or memory to memory | |
174 | transfers. | |
175 | ||
ea76f0b3 AN |
176 | config TXX9_DMAC |
177 | tristate "Toshiba TXx9 SoC DMA support" | |
178 | depends on MACH_TX49XX || MACH_TX39XX | |
179 | select DMA_ENGINE | |
180 | help | |
181 | Support the TXx9 SoC internal DMA controller. This can be | |
182 | integrated in chips such as the Toshiba TX4927/38/39. | |
183 | ||
ec8a1586 LD |
184 | config TEGRA20_APB_DMA |
185 | bool "NVIDIA Tegra20 APB DMA support" | |
186 | depends on ARCH_TEGRA | |
187 | select DMA_ENGINE | |
188 | help | |
189 | Support for the NVIDIA Tegra20 APB DMA controller driver. The | |
190 | DMA controller is having multiple DMA channel which can be | |
191 | configured for different peripherals like audio, UART, SPI, | |
192 | I2C etc which is in APB bus. | |
193 | This DMA controller transfers data from memory to peripheral fifo | |
194 | or vice versa. It does not support memory to memory data transfer. | |
195 | ||
ddeccb8d HS |
196 | config S3C24XX_DMAC |
197 | tristate "Samsung S3C24XX DMA support" | |
d50b9e2e | 198 | depends on ARCH_S3C24XX |
ddeccb8d HS |
199 | select DMA_ENGINE |
200 | select DMA_VIRTUAL_CHANNELS | |
201 | help | |
202 | Support for the Samsung S3C24XX DMA controller driver. The | |
203 | DMA controller is having multiple DMA channels which can be | |
204 | configured for different peripherals like audio, UART, SPI. | |
205 | The DMA controller can transfer data from memory to peripheral, | |
206 | periphal to memory, periphal to periphal and memory to memory. | |
207 | ||
189b4ee8 | 208 | source "drivers/dma/sh/Kconfig" |
d8902adc | 209 | |
61f135b9 LW |
210 | config COH901318 |
211 | bool "ST-Ericsson COH901318 DMA support" | |
212 | select DMA_ENGINE | |
213 | depends on ARCH_U300 | |
214 | help | |
215 | Enable support for ST-Ericsson COH 901 318 DMA. | |
216 | ||
8d318a50 LW |
217 | config STE_DMA40 |
218 | bool "ST-Ericsson DMA40 support" | |
219 | depends on ARCH_U8500 | |
220 | select DMA_ENGINE | |
221 | help | |
222 | Support for ST-Ericsson DMA40 controller | |
223 | ||
12458ea0 AG |
224 | config AMCC_PPC440SPE_ADMA |
225 | tristate "AMCC PPC440SPe ADMA support" | |
226 | depends on 440SPe || 440SP | |
227 | select DMA_ENGINE | |
3cc377b9 | 228 | select DMA_ENGINE_RAID |
12458ea0 | 229 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
5fc6d897 | 230 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
12458ea0 AG |
231 | help |
232 | Enable support for the AMCC PPC440SPe RAID engines. | |
233 | ||
de5d4453 RR |
234 | config TIMB_DMA |
235 | tristate "Timberdale FPGA DMA support" | |
2dda47d1 | 236 | depends on MFD_TIMBERDALE |
de5d4453 RR |
237 | select DMA_ENGINE |
238 | help | |
239 | Enable support for the Timberdale FPGA DMA engine. | |
240 | ||
ca21a146 | 241 | config SIRF_DMA |
f7d935dc BS |
242 | tristate "CSR SiRFprimaII/SiRFmarco DMA support" |
243 | depends on ARCH_SIRF | |
ca21a146 RY |
244 | select DMA_ENGINE |
245 | help | |
246 | Enable support for the CSR SiRFprimaII DMA engine. | |
247 | ||
c2dde5f8 | 248 | config TI_EDMA |
76448041 | 249 | bool "TI EDMA support" |
e7ed8b40 | 250 | depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE |
c2dde5f8 MP |
251 | select DMA_ENGINE |
252 | select DMA_VIRTUAL_CHANNELS | |
c2b9e974 | 253 | select TI_PRIV_EDMA |
c2dde5f8 MP |
254 | default n |
255 | help | |
256 | Enable support for the TI EDMA controller. This DMA | |
257 | engine is found on TI DaVinci and AM33xx parts. | |
258 | ||
a074ae38 PU |
259 | config TI_DMA_CROSSBAR |
260 | bool | |
261 | ||
12458ea0 AG |
262 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
263 | bool | |
264 | ||
b3040e40 JB |
265 | config PL330_DMA |
266 | tristate "DMA API Driver for PL330" | |
267 | select DMA_ENGINE | |
1b9bb715 | 268 | depends on ARM_AMBA |
b3040e40 JB |
269 | help |
270 | Select if your platform has one or more PL330 DMACs. | |
271 | You need to provide platform specific settings via | |
272 | platform_data for a dma-pl330 device. | |
273 | ||
0c42bd0e | 274 | config PCH_DMA |
ca7fe2db | 275 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
4828b493 | 276 | depends on PCI && (X86_32 || COMPILE_TEST) |
0c42bd0e YW |
277 | select DMA_ENGINE |
278 | help | |
2cdf2455 TM |
279 | Enable support for Intel EG20T PCH DMA engine. |
280 | ||
e79e72be | 281 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
ca7fe2db TM |
282 | Output Hub), ML7213, ML7223 and ML7831. |
283 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is | |
284 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. | |
285 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. | |
286 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. | |
0c42bd0e | 287 | |
1ec1e82f SH |
288 | config IMX_SDMA |
289 | tristate "i.MX SDMA support" | |
8e2d41f8 | 290 | depends on ARCH_MXC |
1ec1e82f SH |
291 | select DMA_ENGINE |
292 | help | |
293 | Support the i.MX SDMA engine. This engine is integrated into | |
50cf5534 | 294 | Freescale i.MX25/31/35/51/53/6 chips. |
1ec1e82f | 295 | |
1f1846c6 SH |
296 | config IMX_DMA |
297 | tristate "i.MX DMA support" | |
5b2e02e4 | 298 | depends on ARCH_MXC |
1f1846c6 SH |
299 | select DMA_ENGINE |
300 | help | |
301 | Support the i.MX DMA engine. This engine is integrated into | |
302 | Freescale i.MX1/21/27 chips. | |
303 | ||
a580b8c5 SG |
304 | config MXS_DMA |
305 | bool "MXS DMA support" | |
f5c55847 | 306 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
f5b7efcc | 307 | select STMP_DEVICE |
a580b8c5 SG |
308 | select DMA_ENGINE |
309 | help | |
310 | Support the MXS DMA engine. This engine including APBH-DMA | |
654fa249 | 311 | and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL chips. |
a580b8c5 | 312 | |
760ee1c4 MW |
313 | config EP93XX_DMA |
314 | bool "Cirrus Logic EP93xx DMA support" | |
315 | depends on ARCH_EP93XX | |
316 | select DMA_ENGINE | |
317 | help | |
318 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. | |
319 | ||
6365bead RK |
320 | config DMA_SA11X0 |
321 | tristate "SA-11x0 DMA support" | |
322 | depends on ARCH_SA1100 | |
323 | select DMA_ENGINE | |
50437bff | 324 | select DMA_VIRTUAL_CHANNELS |
6365bead RK |
325 | help |
326 | Support the DMA engine found on Intel StrongARM SA-1100 and | |
327 | SA-1110 SoCs. This DMA engine can only be used with on-chip | |
328 | devices. | |
329 | ||
c6da0ba8 ZG |
330 | config MMP_TDMA |
331 | bool "MMP Two-Channel DMA support" | |
49d57b5e | 332 | depends on ARCH_MMP |
c6da0ba8 | 333 | select DMA_ENGINE |
b9f10a10 | 334 | select MMP_SRAM |
c6da0ba8 ZG |
335 | help |
336 | Support the MMP Two-Channel DMA engine. | |
337 | This engine used for MMP Audio DMA and pxa910 SQU. | |
b9f10a10 | 338 | It needs sram driver under mach-mmp. |
c6da0ba8 ZG |
339 | |
340 | Say Y here if you enabled MMP ADMA, otherwise say N. | |
341 | ||
7bedaa55 RK |
342 | config DMA_OMAP |
343 | tristate "OMAP DMA support" | |
344 | depends on ARCH_OMAP | |
345 | select DMA_ENGINE | |
346 | select DMA_VIRTUAL_CHANNELS | |
a074ae38 | 347 | select TI_DMA_CROSSBAR if SOC_DRA7XX |
7bedaa55 | 348 | |
96286b57 FM |
349 | config DMA_BCM2835 |
350 | tristate "BCM2835 DMA engine support" | |
dd1ed372 | 351 | depends on ARCH_BCM2835 |
96286b57 FM |
352 | select DMA_ENGINE |
353 | select DMA_VIRTUAL_CHANNELS | |
354 | ||
9b3452d1 SAS |
355 | config TI_CPPI41 |
356 | tristate "AM33xx CPPI41 DMA support" | |
357 | depends on ARCH_OMAP | |
358 | select DMA_ENGINE | |
359 | help | |
360 | The Communications Port Programming Interface (CPPI) 4.1 DMA engine | |
361 | is currently used by the USB driver on AM335x platforms. | |
362 | ||
c8acd6aa ZG |
363 | config MMP_PDMA |
364 | bool "MMP PDMA support" | |
365 | depends on (ARCH_MMP || ARCH_PXA) | |
366 | select DMA_ENGINE | |
367 | help | |
8c88126b | 368 | Support the MMP PDMA engine for PXA and MMP platform. |
c8acd6aa | 369 | |
7c169a42 LPC |
370 | config DMA_JZ4740 |
371 | tristate "JZ4740 DMA support" | |
372 | depends on MACH_JZ4740 | |
373 | select DMA_ENGINE | |
374 | select DMA_VIRTUAL_CHANNELS | |
375 | ||
d894fc60 AS |
376 | config DMA_JZ4780 |
377 | tristate "JZ4780 DMA support" | |
378 | depends on MACH_JZ4780 | |
379 | select DMA_ENGINE | |
380 | select DMA_VIRTUAL_CHANNELS | |
381 | help | |
382 | This selects support for the DMA controller in Ingenic JZ4780 SoCs. | |
383 | If you have a board based on such a SoC and wish to use DMA for | |
384 | devices which can use the DMA controller, say Y or M here. | |
385 | ||
8e6152bc ZG |
386 | config K3_DMA |
387 | tristate "Hisilicon K3 DMA support" | |
388 | depends on ARCH_HI3xxx | |
389 | select DMA_ENGINE | |
390 | select DMA_VIRTUAL_CHANNELS | |
391 | help | |
392 | Support the DMA engine for Hisilicon K3 platform | |
393 | devices. | |
394 | ||
5f9e685a JJ |
395 | config MOXART_DMA |
396 | tristate "MOXART DMA support" | |
397 | depends on ARCH_MOXART | |
398 | select DMA_ENGINE | |
e803d988 | 399 | select DMA_OF |
5f9e685a JJ |
400 | select DMA_VIRTUAL_CHANNELS |
401 | help | |
402 | Enable support for the MOXA ART SoC DMA controller. | |
d6be34fb JL |
403 | |
404 | config FSL_EDMA | |
405 | tristate "Freescale eDMA engine support" | |
406 | depends on OF | |
407 | select DMA_ENGINE | |
408 | select DMA_VIRTUAL_CHANNELS | |
409 | help | |
410 | Support the Freescale eDMA engine with programmable channel | |
411 | multiplexing capability for DMA request sources(slot). | |
412 | This module can be found on Freescale Vybrid and LS-1 SoCs. | |
5f9e685a | 413 | |
9cd4360d ST |
414 | config XILINX_VDMA |
415 | tristate "Xilinx AXI VDMA Engine" | |
416 | depends on (ARCH_ZYNQ || MICROBLAZE) | |
417 | select DMA_ENGINE | |
418 | help | |
419 | Enable support for Xilinx AXI VDMA Soft IP. | |
420 | ||
421 | This engine provides high-bandwidth direct memory access | |
422 | between memory and AXI4-Stream video type target | |
423 | peripherals including peripherals which support AXI4- | |
424 | Stream Video Protocol. It has two stream interfaces/ | |
425 | channels, Memory Mapped to Stream (MM2S) and Stream to | |
426 | Memory Mapped (S2MM) for the data transfers. | |
427 | ||
55585930 MR |
428 | config DMA_SUN6I |
429 | tristate "Allwinner A31 SoCs DMA support" | |
0b04ddf8 | 430 | depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST |
a0bbe990 | 431 | depends on RESET_CONTROLLER |
55585930 MR |
432 | select DMA_ENGINE |
433 | select DMA_VIRTUAL_CHANNELS | |
434 | help | |
0b04ddf8 | 435 | Support for the DMA engine first found in Allwinner A31 SoCs. |
55585930 | 436 | |
b45b262c GL |
437 | config NBPFAXI_DMA |
438 | tristate "Renesas Type-AXI NBPF DMA support" | |
439 | select DMA_ENGINE | |
cfc6abc3 | 440 | depends on ARM || COMPILE_TEST |
b45b262c GL |
441 | help |
442 | Support for "Type-AXI" NBPF DMA IPs from Renesas | |
443 | ||
5689ba7f AB |
444 | config IMG_MDC_DMA |
445 | tristate "IMG MDC support" | |
446 | depends on MIPS || COMPILE_TEST | |
447 | depends on MFD_SYSCON | |
448 | select DMA_ENGINE | |
449 | select DMA_VIRTUAL_CHANNELS | |
450 | help | |
451 | Enable support for the IMG multi-threaded DMA controller (MDC). | |
452 | ||
9f2fd0df RPS |
453 | config XGENE_DMA |
454 | tristate "APM X-Gene DMA support" | |
80166146 | 455 | depends on ARCH_XGENE || COMPILE_TEST |
9f2fd0df RPS |
456 | select DMA_ENGINE |
457 | select DMA_ENGINE_RAID | |
458 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH | |
459 | help | |
460 | Enable support for the APM X-Gene SoC DMA engine. | |
461 | ||
c13c8260 | 462 | config DMA_ENGINE |
2ed6dc34 | 463 | bool |
c13c8260 | 464 | |
50437bff RK |
465 | config DMA_VIRTUAL_CHANNELS |
466 | tristate | |
467 | ||
1b2e98bc AS |
468 | config DMA_ACPI |
469 | def_bool y | |
470 | depends on ACPI | |
471 | ||
5fa422c9 VK |
472 | config DMA_OF |
473 | def_bool y | |
474 | depends on OF | |
2795eedf | 475 | select DMA_ENGINE |
5fa422c9 | 476 | |
db217334 | 477 | comment "DMA Clients" |
2ed6dc34 | 478 | depends on DMA_ENGINE |
db217334 | 479 | |
729b5d1b DW |
480 | config ASYNC_TX_DMA |
481 | bool "Async_tx: Offload support for the async_tx api" | |
9a8de639 | 482 | depends on DMA_ENGINE |
729b5d1b DW |
483 | help |
484 | This allows the async_tx api to take advantage of offload engines for | |
485 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
486 | a dma engine that can perform raid operations and you have enabled | |
487 | MD_RAID456 say Y. | |
488 | ||
489 | If unsure, say N. | |
490 | ||
4a776f0a HS |
491 | config DMATEST |
492 | tristate "DMA Test client" | |
493 | depends on DMA_ENGINE | |
494 | help | |
495 | Simple DMA test client. Say N unless you're debugging a | |
496 | DMA Device driver. | |
497 | ||
3cc377b9 DW |
498 | config DMA_ENGINE_RAID |
499 | bool | |
500 | ||
e7c0fe2a AG |
501 | config QCOM_BAM_DMA |
502 | tristate "QCOM BAM DMA support" | |
503 | depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) | |
504 | select DMA_ENGINE | |
505 | select DMA_VIRTUAL_CHANNELS | |
506 | ---help--- | |
507 | Enable support for the QCOM BAM DMA controller. This controller | |
508 | provides DMA capabilities for a variety of on-chip devices. | |
509 | ||
2ed6dc34 | 510 | endif |