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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
e8689e63 | 86 | #include <asm/hardware/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 | 88 | #include "dmaengine.h" |
01d8dc64 | 89 | #include "virt-dma.h" |
d2ebfb33 | 90 | |
e8689e63 LW |
91 | #define DRIVER_NAME "pl08xdmac" |
92 | ||
7703eac9 | 93 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 94 | struct pl08x_driver_data; |
7703eac9 | 95 | |
e8689e63 | 96 | /** |
94ae8522 | 97 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 98 | * @channels: the number of channels available in this variant |
94ae8522 | 99 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
100 | * @nomadik: whether the channels have Nomadik security extension bits |
101 | * that need to be checked for permission before use and some registers are | |
102 | * missing | |
e8689e63 LW |
103 | */ |
104 | struct vendor_data { | |
e8689e63 LW |
105 | u8 channels; |
106 | bool dualmaster; | |
affa115e | 107 | bool nomadik; |
e8689e63 LW |
108 | }; |
109 | ||
110 | /* | |
111 | * PL08X private data structures | |
e8b5e11d | 112 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
113 | * start & end do not - their bus bit info is in cctl. Also note that these |
114 | * are fixed 32-bit quantities. | |
e8689e63 | 115 | */ |
7cb72ad9 | 116 | struct pl08x_lli { |
e25761d7 RKAL |
117 | u32 src; |
118 | u32 dst; | |
bfddfb45 | 119 | u32 lli; |
e8689e63 LW |
120 | u32 cctl; |
121 | }; | |
122 | ||
b23f204c RK |
123 | /** |
124 | * struct pl08x_bus_data - information of source or destination | |
125 | * busses for a transfer | |
126 | * @addr: current address | |
127 | * @maxwidth: the maximum width of a transfer on this bus | |
128 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
129 | */ | |
130 | struct pl08x_bus_data { | |
131 | dma_addr_t addr; | |
132 | u8 maxwidth; | |
133 | u8 buswidth; | |
134 | }; | |
135 | ||
136 | /** | |
137 | * struct pl08x_phy_chan - holder for the physical channels | |
138 | * @id: physical index to this channel | |
139 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
140 | * @serving: the virtual channel currently being served by this physical |
141 | * channel | |
ad0de2ac RK |
142 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
143 | * world | |
b23f204c RK |
144 | */ |
145 | struct pl08x_phy_chan { | |
146 | unsigned int id; | |
147 | void __iomem *base; | |
148 | spinlock_t lock; | |
b23f204c | 149 | struct pl08x_dma_chan *serving; |
ad0de2ac | 150 | bool locked; |
b23f204c RK |
151 | }; |
152 | ||
153 | /** | |
154 | * struct pl08x_sg - structure containing data per sg | |
155 | * @src_addr: src address of sg | |
156 | * @dst_addr: dst address of sg | |
157 | * @len: transfer len in bytes | |
158 | * @node: node for txd's dsg_list | |
159 | */ | |
160 | struct pl08x_sg { | |
161 | dma_addr_t src_addr; | |
162 | dma_addr_t dst_addr; | |
163 | size_t len; | |
164 | struct list_head node; | |
165 | }; | |
166 | ||
167 | /** | |
168 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 169 | * @vd: virtual DMA descriptor |
b23f204c RK |
170 | * @node: node for txd list for channels |
171 | * @dsg_list: list of children sg's | |
b23f204c RK |
172 | * @llis_bus: DMA memory address (physical) start for the LLIs |
173 | * @llis_va: virtual memory address start for the LLIs | |
174 | * @cctl: control reg values for current txd | |
175 | * @ccfg: config reg values for current txd | |
176 | */ | |
177 | struct pl08x_txd { | |
01d8dc64 | 178 | struct virt_dma_desc vd; |
b23f204c RK |
179 | struct list_head node; |
180 | struct list_head dsg_list; | |
b23f204c RK |
181 | dma_addr_t llis_bus; |
182 | struct pl08x_lli *llis_va; | |
183 | /* Default cctl value for LLIs */ | |
184 | u32 cctl; | |
185 | /* | |
186 | * Settings to be put into the physical channel when we | |
187 | * trigger this txd. Other registers are in llis_va[0]. | |
188 | */ | |
189 | u32 ccfg; | |
190 | }; | |
191 | ||
192 | /** | |
193 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
194 | * states | |
195 | * @PL08X_CHAN_IDLE: the channel is idle | |
196 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
197 | * channel and is running a transfer on it | |
198 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
199 | * channel, but the transfer is currently paused | |
200 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
201 | * channel to become available (only pertains to memcpy channels) | |
202 | */ | |
203 | enum pl08x_dma_chan_state { | |
204 | PL08X_CHAN_IDLE, | |
205 | PL08X_CHAN_RUNNING, | |
206 | PL08X_CHAN_PAUSED, | |
207 | PL08X_CHAN_WAITING, | |
208 | }; | |
209 | ||
210 | /** | |
211 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 212 | * @vc: wrappped virtual channel |
b23f204c | 213 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
214 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc |
215 | * @name: name of channel | |
216 | * @cd: channel platform data | |
217 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c | 218 | * @pend_list: queued transactions pending on this channel |
ea160561 | 219 | * @issued_list: issued transactions for this channel |
a936e793 | 220 | * @done_list: list of completed transactions |
b23f204c RK |
221 | * @at: active transaction on this channel |
222 | * @lock: a lock for this channel data | |
223 | * @host: a pointer to the host (internal use) | |
224 | * @state: whether the channel is idle, paused, running etc | |
225 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 226 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 227 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
228 | */ |
229 | struct pl08x_dma_chan { | |
01d8dc64 | 230 | struct virt_dma_chan vc; |
b23f204c | 231 | struct pl08x_phy_chan *phychan; |
b23f204c | 232 | struct tasklet_struct tasklet; |
550ec36f | 233 | const char *name; |
b23f204c | 234 | const struct pl08x_channel_data *cd; |
ed91c13d | 235 | struct dma_slave_config cfg; |
b23f204c | 236 | struct list_head pend_list; |
ea160561 | 237 | struct list_head issued_list; |
a936e793 | 238 | struct list_head done_list; |
b23f204c RK |
239 | struct pl08x_txd *at; |
240 | spinlock_t lock; | |
241 | struct pl08x_driver_data *host; | |
242 | enum pl08x_dma_chan_state state; | |
243 | bool slave; | |
ad0de2ac | 244 | int signal; |
5e2479bd | 245 | unsigned mux_use; |
b23f204c RK |
246 | }; |
247 | ||
e8689e63 LW |
248 | /** |
249 | * struct pl08x_driver_data - the local state holder for the PL08x | |
250 | * @slave: slave engine for this instance | |
251 | * @memcpy: memcpy engine for this instance | |
252 | * @base: virtual memory base (remapped) for the PL08x | |
253 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
254 | * @vd: vendor data for this PL08x variant | |
255 | * @pd: platform data passed in from the platform/machine | |
256 | * @phy_chans: array of data for the physical channels | |
257 | * @pool: a pool for the LLI descriptors | |
258 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
259 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
260 | * fetches | |
30749cb4 | 261 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
262 | * @lock: a spinlock for this struct |
263 | */ | |
264 | struct pl08x_driver_data { | |
265 | struct dma_device slave; | |
266 | struct dma_device memcpy; | |
267 | void __iomem *base; | |
268 | struct amba_device *adev; | |
f96ca9ec | 269 | const struct vendor_data *vd; |
e8689e63 LW |
270 | struct pl08x_platform_data *pd; |
271 | struct pl08x_phy_chan *phy_chans; | |
272 | struct dma_pool *pool; | |
273 | int pool_ctr; | |
30749cb4 RKAL |
274 | u8 lli_buses; |
275 | u8 mem_buses; | |
e8689e63 LW |
276 | }; |
277 | ||
278 | /* | |
279 | * PL08X specific defines | |
280 | */ | |
281 | ||
e8689e63 LW |
282 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
283 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
284 | ||
e8b5e11d | 285 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 286 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
287 | #define PL08X_ALIGN 8 |
288 | ||
289 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
290 | { | |
01d8dc64 | 291 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
292 | } |
293 | ||
501e67e8 RKAL |
294 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
295 | { | |
01d8dc64 | 296 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
297 | } |
298 | ||
6b16c8b1 RK |
299 | /* |
300 | * Mux handling. | |
301 | * | |
302 | * This gives us the DMA request input to the PL08x primecell which the | |
303 | * peripheral described by the channel data will be routed to, possibly | |
304 | * via a board/SoC specific external MUX. One important point to note | |
305 | * here is that this does not depend on the physical channel. | |
306 | */ | |
ad0de2ac | 307 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
308 | { |
309 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
310 | int ret; | |
311 | ||
5e2479bd | 312 | if (plchan->mux_use++ == 0 && pd->get_signal) { |
6b16c8b1 | 313 | ret = pd->get_signal(plchan->cd); |
5e2479bd RK |
314 | if (ret < 0) { |
315 | plchan->mux_use = 0; | |
6b16c8b1 | 316 | return ret; |
5e2479bd | 317 | } |
6b16c8b1 | 318 | |
ad0de2ac | 319 | plchan->signal = ret; |
6b16c8b1 RK |
320 | } |
321 | return 0; | |
322 | } | |
323 | ||
324 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
325 | { | |
326 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
327 | ||
5e2479bd RK |
328 | if (plchan->signal >= 0) { |
329 | WARN_ON(plchan->mux_use == 0); | |
330 | ||
331 | if (--plchan->mux_use == 0 && pd->put_signal) { | |
332 | pd->put_signal(plchan->cd, plchan->signal); | |
333 | plchan->signal = -1; | |
334 | } | |
6b16c8b1 RK |
335 | } |
336 | } | |
337 | ||
e8689e63 LW |
338 | /* |
339 | * Physical channel handling | |
340 | */ | |
341 | ||
342 | /* Whether a certain channel is busy or not */ | |
343 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
344 | { | |
345 | unsigned int val; | |
346 | ||
347 | val = readl(ch->base + PL080_CH_CONFIG); | |
348 | return val & PL080_CONFIG_ACTIVE; | |
349 | } | |
350 | ||
351 | /* | |
352 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 353 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
354 | * been set when the LLIs were constructed. Poke them into the hardware |
355 | * and start the transfer. | |
e8689e63 | 356 | */ |
eab82533 | 357 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 358 | { |
c885bee4 | 359 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 360 | struct pl08x_phy_chan *phychan = plchan->phychan; |
eab82533 RK |
361 | struct pl08x_lli *lli; |
362 | struct pl08x_txd *txd; | |
09b3c323 | 363 | u32 val; |
c885bee4 | 364 | |
ea160561 | 365 | txd = list_first_entry(&plchan->issued_list, struct pl08x_txd, node); |
eab82533 RK |
366 | list_del(&txd->node); |
367 | ||
c885bee4 | 368 | plchan->at = txd; |
e8689e63 | 369 | |
c885bee4 RKAL |
370 | /* Wait for channel inactive */ |
371 | while (pl08x_phy_channel_busy(phychan)) | |
372 | cpu_relax(); | |
e8689e63 | 373 | |
eab82533 RK |
374 | lli = &txd->llis_va[0]; |
375 | ||
c885bee4 RKAL |
376 | dev_vdbg(&pl08x->adev->dev, |
377 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
378 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
379 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 380 | txd->ccfg); |
19524d77 RKAL |
381 | |
382 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
383 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
384 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
385 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 386 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
387 | |
388 | /* Enable the DMA channel */ | |
389 | /* Do not access config register until channel shows as disabled */ | |
390 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 391 | cpu_relax(); |
e8689e63 | 392 | |
c885bee4 RKAL |
393 | /* Do not access config register until channel shows as inactive */ |
394 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 395 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 396 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 397 | |
c885bee4 | 398 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
399 | } |
400 | ||
401 | /* | |
81796616 | 402 | * Pause the channel by setting the HALT bit. |
e8689e63 | 403 | * |
81796616 RKAL |
404 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
405 | * the FIFO can only drain if the peripheral is still requesting data. | |
406 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 407 | * |
81796616 RKAL |
408 | * For P->M transfers, disable the peripheral first to stop it filling |
409 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
410 | */ |
411 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
412 | { | |
413 | u32 val; | |
81796616 | 414 | int timeout; |
e8689e63 LW |
415 | |
416 | /* Set the HALT bit and wait for the FIFO to drain */ | |
417 | val = readl(ch->base + PL080_CH_CONFIG); | |
418 | val |= PL080_CONFIG_HALT; | |
419 | writel(val, ch->base + PL080_CH_CONFIG); | |
420 | ||
421 | /* Wait for channel inactive */ | |
81796616 RKAL |
422 | for (timeout = 1000; timeout; timeout--) { |
423 | if (!pl08x_phy_channel_busy(ch)) | |
424 | break; | |
425 | udelay(1); | |
426 | } | |
427 | if (pl08x_phy_channel_busy(ch)) | |
428 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
429 | } |
430 | ||
431 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
432 | { | |
433 | u32 val; | |
434 | ||
435 | /* Clear the HALT bit */ | |
436 | val = readl(ch->base + PL080_CH_CONFIG); | |
437 | val &= ~PL080_CONFIG_HALT; | |
438 | writel(val, ch->base + PL080_CH_CONFIG); | |
439 | } | |
440 | ||
fb526210 RKAL |
441 | /* |
442 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
443 | * clears any pending interrupt status. This should not be used for | |
444 | * an on-going transfer, but as a method of shutting down a channel | |
445 | * (eg, when it's no longer used) or terminating a transfer. | |
446 | */ | |
447 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
448 | struct pl08x_phy_chan *ch) | |
e8689e63 | 449 | { |
fb526210 | 450 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 451 | |
fb526210 RKAL |
452 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
453 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 454 | |
e8689e63 | 455 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
456 | |
457 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
458 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
459 | } |
460 | ||
461 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
462 | { | |
463 | /* The source width defines the number of bytes */ | |
464 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
465 | ||
466 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
467 | case PL080_WIDTH_8BIT: | |
468 | break; | |
469 | case PL080_WIDTH_16BIT: | |
470 | bytes *= 2; | |
471 | break; | |
472 | case PL080_WIDTH_32BIT: | |
473 | bytes *= 4; | |
474 | break; | |
475 | } | |
476 | return bytes; | |
477 | } | |
478 | ||
479 | /* The channel should be paused when calling this */ | |
480 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
481 | { | |
482 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
483 | struct pl08x_txd *txd; |
484 | unsigned long flags; | |
cace6585 | 485 | size_t bytes = 0; |
e8689e63 LW |
486 | |
487 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
488 | ch = plchan->phychan; |
489 | txd = plchan->at; | |
490 | ||
491 | /* | |
db9f136a RKAL |
492 | * Follow the LLIs to get the number of remaining |
493 | * bytes in the currently active transaction. | |
e8689e63 LW |
494 | */ |
495 | if (ch && txd) { | |
4c0df6a3 | 496 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 497 | |
db9f136a | 498 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
499 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
500 | ||
501 | if (clli) { | |
db9f136a RKAL |
502 | struct pl08x_lli *llis_va = txd->llis_va; |
503 | dma_addr_t llis_bus = txd->llis_bus; | |
504 | int index; | |
505 | ||
506 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
507 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 508 | |
db9f136a RKAL |
509 | /* |
510 | * Locate the next LLI - as this is an array, | |
511 | * it's simple maths to find. | |
512 | */ | |
513 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
514 | ||
515 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
516 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 517 | |
e8689e63 | 518 | /* |
e8b5e11d | 519 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 520 | */ |
db9f136a RKAL |
521 | if (!llis_va[index].lli) |
522 | break; | |
e8689e63 LW |
523 | } |
524 | } | |
525 | } | |
526 | ||
527 | /* Sum up all queued transactions */ | |
ea160561 RK |
528 | if (!list_empty(&plchan->issued_list)) { |
529 | struct pl08x_txd *txdi; | |
530 | list_for_each_entry(txdi, &plchan->issued_list, node) { | |
531 | struct pl08x_sg *dsg; | |
532 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
533 | bytes += dsg->len; | |
534 | } | |
535 | } | |
536 | ||
15c17232 | 537 | if (!list_empty(&plchan->pend_list)) { |
db9f136a | 538 | struct pl08x_txd *txdi; |
15c17232 | 539 | list_for_each_entry(txdi, &plchan->pend_list, node) { |
b7f69d9d VK |
540 | struct pl08x_sg *dsg; |
541 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
542 | bytes += dsg->len; | |
e8689e63 | 543 | } |
e8689e63 LW |
544 | } |
545 | ||
546 | spin_unlock_irqrestore(&plchan->lock, flags); | |
547 | ||
548 | return bytes; | |
549 | } | |
550 | ||
551 | /* | |
552 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
553 | * |
554 | * Try to locate a physical channel to be used for this transfer. If all | |
555 | * are taken return NULL and the requester will have to cope by using | |
556 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
557 | */ |
558 | static struct pl08x_phy_chan * | |
559 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
560 | struct pl08x_dma_chan *virt_chan) | |
561 | { | |
562 | struct pl08x_phy_chan *ch = NULL; | |
563 | unsigned long flags; | |
564 | int i; | |
565 | ||
e8689e63 LW |
566 | for (i = 0; i < pl08x->vd->channels; i++) { |
567 | ch = &pl08x->phy_chans[i]; | |
568 | ||
569 | spin_lock_irqsave(&ch->lock, flags); | |
570 | ||
affa115e | 571 | if (!ch->locked && !ch->serving) { |
e8689e63 | 572 | ch->serving = virt_chan; |
e8689e63 LW |
573 | spin_unlock_irqrestore(&ch->lock, flags); |
574 | break; | |
575 | } | |
576 | ||
577 | spin_unlock_irqrestore(&ch->lock, flags); | |
578 | } | |
579 | ||
580 | if (i == pl08x->vd->channels) { | |
581 | /* No physical channel available, cope with it */ | |
582 | return NULL; | |
583 | } | |
584 | ||
585 | return ch; | |
586 | } | |
587 | ||
a5a488db | 588 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
589 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
590 | struct pl08x_phy_chan *ch) | |
591 | { | |
a5a488db RK |
592 | ch->serving = NULL; |
593 | } | |
e8689e63 | 594 | |
a5a488db RK |
595 | /* |
596 | * Try to allocate a physical channel. When successful, assign it to | |
597 | * this virtual channel, and initiate the next descriptor. The | |
598 | * virtual channel lock must be held at this point. | |
599 | */ | |
600 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
601 | { | |
602 | struct pl08x_driver_data *pl08x = plchan->host; | |
603 | struct pl08x_phy_chan *ch; | |
fb526210 | 604 | |
a5a488db RK |
605 | ch = pl08x_get_phy_channel(pl08x, plchan); |
606 | if (!ch) { | |
607 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
608 | plchan->state = PL08X_CHAN_WAITING; | |
609 | return; | |
610 | } | |
e8689e63 | 611 | |
a5a488db RK |
612 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
613 | ch->id, plchan->name); | |
614 | ||
615 | plchan->phychan = ch; | |
616 | plchan->state = PL08X_CHAN_RUNNING; | |
617 | pl08x_start_next_txd(plchan); | |
618 | } | |
619 | ||
620 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
621 | struct pl08x_dma_chan *plchan) | |
622 | { | |
623 | struct pl08x_driver_data *pl08x = plchan->host; | |
624 | ||
625 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
626 | ch->id, plchan->name); | |
627 | ||
628 | /* | |
629 | * We do this without taking the lock; we're really only concerned | |
630 | * about whether this pointer is NULL or not, and we're guaranteed | |
631 | * that this will only be called when it _already_ is non-NULL. | |
632 | */ | |
633 | ch->serving = plchan; | |
634 | plchan->phychan = ch; | |
635 | plchan->state = PL08X_CHAN_RUNNING; | |
636 | pl08x_start_next_txd(plchan); | |
637 | } | |
638 | ||
639 | /* | |
640 | * Free a physical DMA channel, potentially reallocating it to another | |
641 | * virtual channel if we have any pending. | |
642 | */ | |
643 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
644 | { | |
645 | struct pl08x_driver_data *pl08x = plchan->host; | |
646 | struct pl08x_dma_chan *p, *next; | |
647 | ||
648 | retry: | |
649 | next = NULL; | |
650 | ||
651 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 652 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
653 | if (p->state == PL08X_CHAN_WAITING) { |
654 | next = p; | |
655 | break; | |
656 | } | |
657 | ||
658 | if (!next) { | |
01d8dc64 | 659 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
660 | if (p->state == PL08X_CHAN_WAITING) { |
661 | next = p; | |
662 | break; | |
663 | } | |
664 | } | |
665 | ||
666 | /* Ensure that the physical channel is stopped */ | |
667 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
668 | ||
669 | if (next) { | |
670 | bool success; | |
671 | ||
672 | /* | |
673 | * Eww. We know this isn't going to deadlock | |
674 | * but lockdep probably doesn't. | |
675 | */ | |
676 | spin_lock(&next->lock); | |
677 | /* Re-check the state now that we have the lock */ | |
678 | success = next->state == PL08X_CHAN_WAITING; | |
679 | if (success) | |
680 | pl08x_phy_reassign_start(plchan->phychan, next); | |
681 | spin_unlock(&next->lock); | |
682 | ||
683 | /* If the state changed, try to find another channel */ | |
684 | if (!success) | |
685 | goto retry; | |
686 | } else { | |
687 | /* No more jobs, so free up the physical channel */ | |
688 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
689 | } | |
690 | ||
691 | plchan->phychan = NULL; | |
692 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
693 | } |
694 | ||
695 | /* | |
696 | * LLI handling | |
697 | */ | |
698 | ||
699 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
700 | { | |
701 | switch (coded) { | |
702 | case PL080_WIDTH_8BIT: | |
703 | return 1; | |
704 | case PL080_WIDTH_16BIT: | |
705 | return 2; | |
706 | case PL080_WIDTH_32BIT: | |
707 | return 4; | |
708 | default: | |
709 | break; | |
710 | } | |
711 | BUG(); | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 716 | size_t tsize) |
e8689e63 LW |
717 | { |
718 | u32 retbits = cctl; | |
719 | ||
e8b5e11d | 720 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
721 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
722 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
723 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
724 | ||
725 | /* Then set the bits according to the parameters */ | |
726 | switch (srcwidth) { | |
727 | case 1: | |
728 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
729 | break; | |
730 | case 2: | |
731 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
732 | break; | |
733 | case 4: | |
734 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
735 | break; | |
736 | default: | |
737 | BUG(); | |
738 | break; | |
739 | } | |
740 | ||
741 | switch (dstwidth) { | |
742 | case 1: | |
743 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
744 | break; | |
745 | case 2: | |
746 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
747 | break; | |
748 | case 4: | |
749 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
750 | break; | |
751 | default: | |
752 | BUG(); | |
753 | break; | |
754 | } | |
755 | ||
756 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
757 | return retbits; | |
758 | } | |
759 | ||
542361f8 RKAL |
760 | struct pl08x_lli_build_data { |
761 | struct pl08x_txd *txd; | |
542361f8 RKAL |
762 | struct pl08x_bus_data srcbus; |
763 | struct pl08x_bus_data dstbus; | |
764 | size_t remainder; | |
25c94f7f | 765 | u32 lli_bus; |
542361f8 RKAL |
766 | }; |
767 | ||
e8689e63 | 768 | /* |
0532e6fc VK |
769 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
770 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
771 | * masters address with width requirements of transfer (by sending few byte by | |
772 | * byte data), slave is still not aligned, then its width will be reduced to | |
773 | * BYTE. | |
774 | * - prefers the destination bus if both available | |
036f05fd | 775 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 776 | */ |
542361f8 RKAL |
777 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
778 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
779 | { |
780 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
781 | *mbus = &bd->dstbus; |
782 | *sbus = &bd->srcbus; | |
036f05fd VK |
783 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
784 | *mbus = &bd->srcbus; | |
785 | *sbus = &bd->dstbus; | |
e8689e63 | 786 | } else { |
036f05fd | 787 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
788 | *mbus = &bd->dstbus; |
789 | *sbus = &bd->srcbus; | |
036f05fd | 790 | } else { |
542361f8 RKAL |
791 | *mbus = &bd->srcbus; |
792 | *sbus = &bd->dstbus; | |
e8689e63 LW |
793 | } |
794 | } | |
795 | } | |
796 | ||
797 | /* | |
94ae8522 | 798 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 799 | */ |
542361f8 RKAL |
800 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
801 | int num_llis, int len, u32 cctl) | |
e8689e63 | 802 | { |
542361f8 RKAL |
803 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
804 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
805 | |
806 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
807 | ||
30749cb4 | 808 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
809 | llis_va[num_llis].src = bd->srcbus.addr; |
810 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
811 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
812 | sizeof(struct pl08x_lli); | |
25c94f7f | 813 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
814 | |
815 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 816 | bd->srcbus.addr += len; |
e8689e63 | 817 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 818 | bd->dstbus.addr += len; |
e8689e63 | 819 | |
542361f8 | 820 | BUG_ON(bd->remainder < len); |
cace6585 | 821 | |
542361f8 | 822 | bd->remainder -= len; |
e8689e63 LW |
823 | } |
824 | ||
03af500f VK |
825 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
826 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 827 | { |
03af500f VK |
828 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
829 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
830 | (*total_bytes) += len; | |
e8689e63 LW |
831 | } |
832 | ||
833 | /* | |
834 | * This fills in the table of LLIs for the transfer descriptor | |
835 | * Note that we assume we never have to change the burst sizes | |
836 | * Return 0 for error | |
837 | */ | |
838 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
839 | struct pl08x_txd *txd) | |
840 | { | |
e8689e63 | 841 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 842 | struct pl08x_lli_build_data bd; |
e8689e63 | 843 | int num_llis = 0; |
03af500f | 844 | u32 cctl, early_bytes = 0; |
b7f69d9d | 845 | size_t max_bytes_per_lli, total_bytes; |
7cb72ad9 | 846 | struct pl08x_lli *llis_va; |
b7f69d9d | 847 | struct pl08x_sg *dsg; |
e8689e63 | 848 | |
3e27ee84 | 849 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
850 | if (!txd->llis_va) { |
851 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
852 | return 0; | |
853 | } | |
854 | ||
855 | pl08x->pool_ctr++; | |
856 | ||
542361f8 | 857 | bd.txd = txd; |
25c94f7f | 858 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 859 | cctl = txd->cctl; |
542361f8 | 860 | |
e8689e63 | 861 | /* Find maximum width of the source bus */ |
542361f8 | 862 | bd.srcbus.maxwidth = |
e8689e63 LW |
863 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
864 | PL080_CONTROL_SWIDTH_SHIFT); | |
865 | ||
866 | /* Find maximum width of the destination bus */ | |
542361f8 | 867 | bd.dstbus.maxwidth = |
e8689e63 LW |
868 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
869 | PL080_CONTROL_DWIDTH_SHIFT); | |
870 | ||
b7f69d9d VK |
871 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
872 | total_bytes = 0; | |
873 | cctl = txd->cctl; | |
e8689e63 | 874 | |
b7f69d9d VK |
875 | bd.srcbus.addr = dsg->src_addr; |
876 | bd.dstbus.addr = dsg->dst_addr; | |
877 | bd.remainder = dsg->len; | |
878 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
879 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 880 | |
b7f69d9d | 881 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 882 | |
b7f69d9d VK |
883 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
884 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
885 | bd.srcbus.buswidth, | |
886 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
887 | bd.dstbus.buswidth, | |
888 | bd.remainder); | |
889 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
890 | mbus == &bd.srcbus ? "src" : "dst", | |
891 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 892 | |
b7f69d9d VK |
893 | /* |
894 | * Zero length is only allowed if all these requirements are | |
895 | * met: | |
896 | * - flow controller is peripheral. | |
897 | * - src.addr is aligned to src.width | |
898 | * - dst.addr is aligned to dst.width | |
899 | * | |
900 | * sg_len == 1 should be true, as there can be two cases here: | |
901 | * | |
902 | * - Memory addresses are contiguous and are not scattered. | |
903 | * Here, Only one sg will be passed by user driver, with | |
904 | * memory address and zero length. We pass this to controller | |
905 | * and after the transfer it will receive the last burst | |
906 | * request from peripheral and so transfer finishes. | |
907 | * | |
908 | * - Memory addresses are scattered and are not contiguous. | |
909 | * Here, Obviously as DMA controller doesn't know when a lli's | |
910 | * transfer gets over, it can't load next lli. So in this | |
911 | * case, there has to be an assumption that only one lli is | |
912 | * supported. Thus, we can't have scattered addresses. | |
913 | */ | |
914 | if (!bd.remainder) { | |
915 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
916 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
917 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 918 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
919 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
920 | __func__); | |
921 | return 0; | |
922 | } | |
0a235657 | 923 | |
b7f69d9d | 924 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 925 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
926 | dev_err(&pl08x->adev->dev, |
927 | "%s src & dst address must be aligned to src" | |
928 | " & dst width if peripheral is flow controller", | |
929 | __func__); | |
930 | return 0; | |
931 | } | |
03af500f | 932 | |
b7f69d9d VK |
933 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
934 | bd.dstbus.buswidth, 0); | |
935 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
936 | break; | |
937 | } | |
e8689e63 LW |
938 | |
939 | /* | |
b7f69d9d VK |
940 | * Send byte by byte for following cases |
941 | * - Less than a bus width available | |
942 | * - until master bus is aligned | |
e8689e63 | 943 | */ |
b7f69d9d VK |
944 | if (bd.remainder < mbus->buswidth) |
945 | early_bytes = bd.remainder; | |
946 | else if ((mbus->addr) % (mbus->buswidth)) { | |
947 | early_bytes = mbus->buswidth - (mbus->addr) % | |
948 | (mbus->buswidth); | |
949 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
950 | early_bytes = bd.remainder; | |
951 | } | |
e8689e63 | 952 | |
b7f69d9d VK |
953 | if (early_bytes) { |
954 | dev_vdbg(&pl08x->adev->dev, | |
955 | "%s byte width LLIs (remain 0x%08x)\n", | |
956 | __func__, bd.remainder); | |
957 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
958 | &total_bytes); | |
e8689e63 LW |
959 | } |
960 | ||
b7f69d9d VK |
961 | if (bd.remainder) { |
962 | /* | |
963 | * Master now aligned | |
964 | * - if slave is not then we must set its width down | |
965 | */ | |
966 | if (sbus->addr % sbus->buswidth) { | |
967 | dev_dbg(&pl08x->adev->dev, | |
968 | "%s set down bus width to one byte\n", | |
969 | __func__); | |
fa6a940b | 970 | |
b7f69d9d VK |
971 | sbus->buswidth = 1; |
972 | } | |
e8689e63 LW |
973 | |
974 | /* | |
b7f69d9d VK |
975 | * Bytes transferred = tsize * src width, not |
976 | * MIN(buswidths) | |
e8689e63 | 977 | */ |
b7f69d9d VK |
978 | max_bytes_per_lli = bd.srcbus.buswidth * |
979 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
980 | dev_vdbg(&pl08x->adev->dev, | |
981 | "%s max bytes per lli = %zu\n", | |
982 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
983 | |
984 | /* | |
b7f69d9d VK |
985 | * Make largest possible LLIs until less than one bus |
986 | * width left | |
e8689e63 | 987 | */ |
b7f69d9d VK |
988 | while (bd.remainder > (mbus->buswidth - 1)) { |
989 | size_t lli_len, tsize, width; | |
e8689e63 | 990 | |
b7f69d9d VK |
991 | /* |
992 | * If enough left try to send max possible, | |
993 | * otherwise try to send the remainder | |
994 | */ | |
995 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 996 | |
b7f69d9d VK |
997 | /* |
998 | * Check against maximum bus alignment: | |
999 | * Calculate actual transfer size in relation to | |
1000 | * bus width an get a maximum remainder of the | |
1001 | * highest bus width - 1 | |
1002 | */ | |
1003 | width = max(mbus->buswidth, sbus->buswidth); | |
1004 | lli_len = (lli_len / width) * width; | |
1005 | tsize = lli_len / bd.srcbus.buswidth; | |
1006 | ||
1007 | dev_vdbg(&pl08x->adev->dev, | |
1008 | "%s fill lli with single lli chunk of " | |
1009 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1010 | __func__, lli_len, bd.remainder); | |
1011 | ||
1012 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 1013 | bd.dstbus.buswidth, tsize); |
b7f69d9d VK |
1014 | pl08x_fill_lli_for_desc(&bd, num_llis++, |
1015 | lli_len, cctl); | |
1016 | total_bytes += lli_len; | |
1017 | } | |
e8689e63 | 1018 | |
b7f69d9d VK |
1019 | /* |
1020 | * Send any odd bytes | |
1021 | */ | |
1022 | if (bd.remainder) { | |
1023 | dev_vdbg(&pl08x->adev->dev, | |
1024 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1025 | __func__, bd.remainder); | |
1026 | prep_byte_width_lli(&bd, &cctl, bd.remainder, | |
1027 | num_llis++, &total_bytes); | |
1028 | } | |
e8689e63 | 1029 | } |
16a2e7d3 | 1030 | |
b7f69d9d VK |
1031 | if (total_bytes != dsg->len) { |
1032 | dev_err(&pl08x->adev->dev, | |
1033 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1034 | __func__, total_bytes, dsg->len); | |
1035 | return 0; | |
1036 | } | |
e8689e63 | 1037 | |
b7f69d9d VK |
1038 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1039 | dev_err(&pl08x->adev->dev, | |
1040 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
1041 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
1042 | return 0; | |
1043 | } | |
e8689e63 | 1044 | } |
b58b6b5b RKAL |
1045 | |
1046 | llis_va = txd->llis_va; | |
94ae8522 | 1047 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 1048 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 1049 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 1050 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1051 | |
e8689e63 LW |
1052 | #ifdef VERBOSE_DEBUG |
1053 | { | |
1054 | int i; | |
1055 | ||
fc74eb79 RKAL |
1056 | dev_vdbg(&pl08x->adev->dev, |
1057 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
1058 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
1059 | for (i = 0; i < num_llis; i++) { |
1060 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
1061 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
1062 | i, &llis_va[i], llis_va[i].src, | |
1063 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
1064 | ); |
1065 | } | |
1066 | } | |
1067 | #endif | |
1068 | ||
1069 | return num_llis; | |
1070 | } | |
1071 | ||
1072 | /* You should call this with the struct pl08x lock held */ | |
1073 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
1074 | struct pl08x_txd *txd) | |
1075 | { | |
b7f69d9d VK |
1076 | struct pl08x_sg *dsg, *_dsg; |
1077 | ||
e8689e63 | 1078 | /* Free the LLI */ |
c1205646 VK |
1079 | if (txd->llis_va) |
1080 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 LW |
1081 | |
1082 | pl08x->pool_ctr--; | |
1083 | ||
b7f69d9d VK |
1084 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1085 | list_del(&dsg->node); | |
1086 | kfree(dsg); | |
1087 | } | |
1088 | ||
e8689e63 LW |
1089 | kfree(txd); |
1090 | } | |
1091 | ||
1092 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
1093 | struct pl08x_dma_chan *plchan) | |
1094 | { | |
ea160561 RK |
1095 | LIST_HEAD(head); |
1096 | struct pl08x_txd *txd; | |
e8689e63 | 1097 | |
ea160561 RK |
1098 | list_splice_tail_init(&plchan->issued_list, &head); |
1099 | list_splice_tail_init(&plchan->pend_list, &head); | |
1100 | ||
1101 | while (!list_empty(&head)) { | |
1102 | txd = list_first_entry(&head, struct pl08x_txd, node); | |
1103 | pl08x_release_mux(plchan); | |
1104 | list_del(&txd->node); | |
1105 | pl08x_free_txd(pl08x, txd); | |
e8689e63 LW |
1106 | } |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * The DMA ENGINE API | |
1111 | */ | |
1112 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1113 | { | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1118 | { | |
1119 | } | |
1120 | ||
e8689e63 LW |
1121 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
1122 | { | |
1123 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
501e67e8 | 1124 | struct pl08x_txd *txd = to_pl08x_txd(tx); |
c370e594 | 1125 | unsigned long flags; |
884485e1 | 1126 | dma_cookie_t cookie; |
c370e594 RKAL |
1127 | |
1128 | spin_lock_irqsave(&plchan->lock, flags); | |
884485e1 | 1129 | cookie = dma_cookie_assign(tx); |
501e67e8 RKAL |
1130 | |
1131 | /* Put this onto the pending list */ | |
1132 | list_add_tail(&txd->node, &plchan->pend_list); | |
c370e594 | 1133 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 | 1134 | |
884485e1 | 1135 | return cookie; |
e8689e63 LW |
1136 | } |
1137 | ||
1138 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
1139 | struct dma_chan *chan, unsigned long flags) | |
1140 | { | |
1141 | struct dma_async_tx_descriptor *retval = NULL; | |
1142 | ||
1143 | return retval; | |
1144 | } | |
1145 | ||
1146 | /* | |
94ae8522 RKAL |
1147 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1148 | * If slaves are relying on interrupts to signal completion this function | |
1149 | * must not be called with interrupts disabled. | |
e8689e63 | 1150 | */ |
3e27ee84 VK |
1151 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1152 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1153 | { |
1154 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 | 1155 | enum dma_status ret; |
e8689e63 | 1156 | |
96a2af41 RKAL |
1157 | ret = dma_cookie_status(chan, cookie, txstate); |
1158 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1159 | return ret; |
e8689e63 | 1160 | |
e8689e63 LW |
1161 | /* |
1162 | * This cookie not complete yet | |
96a2af41 | 1163 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1164 | */ |
96a2af41 | 1165 | dma_set_residue(txstate, pl08x_getbytes_chan(plchan)); |
e8689e63 LW |
1166 | |
1167 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1168 | return DMA_PAUSED; | |
1169 | ||
1170 | /* Whether waiting or running, we're in progress */ | |
1171 | return DMA_IN_PROGRESS; | |
1172 | } | |
1173 | ||
1174 | /* PrimeCell DMA extension */ | |
1175 | struct burst_table { | |
760596c6 | 1176 | u32 burstwords; |
e8689e63 LW |
1177 | u32 reg; |
1178 | }; | |
1179 | ||
1180 | static const struct burst_table burst_sizes[] = { | |
1181 | { | |
1182 | .burstwords = 256, | |
760596c6 | 1183 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1184 | }, |
1185 | { | |
1186 | .burstwords = 128, | |
760596c6 | 1187 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1188 | }, |
1189 | { | |
1190 | .burstwords = 64, | |
760596c6 | 1191 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1192 | }, |
1193 | { | |
1194 | .burstwords = 32, | |
760596c6 | 1195 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1196 | }, |
1197 | { | |
1198 | .burstwords = 16, | |
760596c6 | 1199 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1200 | }, |
1201 | { | |
1202 | .burstwords = 8, | |
760596c6 | 1203 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1204 | }, |
1205 | { | |
1206 | .burstwords = 4, | |
760596c6 | 1207 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1208 | }, |
1209 | { | |
760596c6 RKAL |
1210 | .burstwords = 0, |
1211 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1212 | }, |
1213 | }; | |
1214 | ||
121c8476 RKAL |
1215 | /* |
1216 | * Given the source and destination available bus masks, select which | |
1217 | * will be routed to each port. We try to have source and destination | |
1218 | * on separate ports, but always respect the allowable settings. | |
1219 | */ | |
1220 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1221 | { | |
1222 | u32 cctl = 0; | |
1223 | ||
1224 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1225 | cctl |= PL080_CONTROL_DST_AHB2; | |
1226 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1227 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1228 | ||
1229 | return cctl; | |
1230 | } | |
1231 | ||
f14c426c RKAL |
1232 | static u32 pl08x_cctl(u32 cctl) |
1233 | { | |
1234 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1235 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1236 | PL080_CONTROL_PROT_MASK); | |
1237 | ||
1238 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1239 | return cctl | PL080_CONTROL_PROT_SYS; | |
1240 | } | |
1241 | ||
aa88cdaa RKAL |
1242 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1243 | { | |
1244 | switch (width) { | |
1245 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1246 | return PL080_WIDTH_8BIT; | |
1247 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1248 | return PL080_WIDTH_16BIT; | |
1249 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1250 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1251 | default: |
1252 | return ~0; | |
aa88cdaa | 1253 | } |
aa88cdaa RKAL |
1254 | } |
1255 | ||
760596c6 RKAL |
1256 | static u32 pl08x_burst(u32 maxburst) |
1257 | { | |
1258 | int i; | |
1259 | ||
1260 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1261 | if (burst_sizes[i].burstwords <= maxburst) | |
1262 | break; | |
1263 | ||
1264 | return burst_sizes[i].reg; | |
1265 | } | |
1266 | ||
9862ba17 RK |
1267 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1268 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1269 | { | |
1270 | u32 width, burst, cctl = 0; | |
1271 | ||
1272 | width = pl08x_width(addr_width); | |
1273 | if (width == ~0) | |
1274 | return ~0; | |
1275 | ||
1276 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1277 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1278 | ||
1279 | /* | |
1280 | * If this channel will only request single transfers, set this | |
1281 | * down to ONE element. Also select one element if no maxburst | |
1282 | * is specified. | |
1283 | */ | |
1284 | if (plchan->cd->single) | |
1285 | maxburst = 1; | |
1286 | ||
1287 | burst = pl08x_burst(maxburst); | |
1288 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1289 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1290 | ||
1291 | return pl08x_cctl(cctl); | |
1292 | } | |
1293 | ||
f0fd9446 RKAL |
1294 | static int dma_set_runtime_config(struct dma_chan *chan, |
1295 | struct dma_slave_config *config) | |
e8689e63 LW |
1296 | { |
1297 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
b7f75865 RKAL |
1298 | |
1299 | if (!plchan->slave) | |
1300 | return -EINVAL; | |
e8689e63 | 1301 | |
dc8d5f8d RK |
1302 | /* Reject definitely invalid configurations */ |
1303 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1304 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1305 | return -EINVAL; |
e8689e63 | 1306 | |
ed91c13d RK |
1307 | plchan->cfg = *config; |
1308 | ||
f0fd9446 | 1309 | return 0; |
e8689e63 LW |
1310 | } |
1311 | ||
1312 | /* | |
1313 | * Slave transactions callback to the slave device to allow | |
1314 | * synchronization of slave DMA signals with the DMAC enable | |
1315 | */ | |
1316 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1317 | { | |
1318 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1319 | unsigned long flags; |
1320 | ||
1321 | spin_lock_irqsave(&plchan->lock, flags); | |
ea160561 | 1322 | list_splice_tail_init(&plchan->pend_list, &plchan->issued_list); |
ea160561 | 1323 | if (!list_empty(&plchan->issued_list)) { |
a5a488db RK |
1324 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1325 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1326 | } |
e8689e63 LW |
1327 | spin_unlock_irqrestore(&plchan->lock, flags); |
1328 | } | |
1329 | ||
1330 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1331 | struct pl08x_txd *txd) | |
1332 | { | |
e8689e63 | 1333 | struct pl08x_driver_data *pl08x = plchan->host; |
a5a488db | 1334 | int num_llis; |
e8689e63 LW |
1335 | |
1336 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 | 1337 | if (!num_llis) { |
a5a488db RK |
1338 | unsigned long flags; |
1339 | ||
57001a60 VK |
1340 | spin_lock_irqsave(&plchan->lock, flags); |
1341 | pl08x_free_txd(pl08x, txd); | |
1342 | spin_unlock_irqrestore(&plchan->lock, flags); | |
a5a488db | 1343 | |
e8689e63 | 1344 | return -EINVAL; |
dafa7317 | 1345 | } |
e8689e63 LW |
1346 | return 0; |
1347 | } | |
1348 | ||
c0428794 RKAL |
1349 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, |
1350 | unsigned long flags) | |
ac3cd20d | 1351 | { |
b201c111 | 1352 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1353 | |
1354 | if (txd) { | |
01d8dc64 RK |
1355 | dma_async_tx_descriptor_init(&txd->vd.tx, &plchan->vc.chan); |
1356 | txd->vd.tx.flags = flags; | |
1357 | txd->vd.tx.tx_submit = pl08x_tx_submit; | |
ac3cd20d | 1358 | INIT_LIST_HEAD(&txd->node); |
b7f69d9d | 1359 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1360 | |
1361 | /* Always enable error and terminal interrupts */ | |
1362 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1363 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1364 | } |
1365 | return txd; | |
1366 | } | |
1367 | ||
e8689e63 LW |
1368 | /* |
1369 | * Initialize a descriptor to be used by memcpy submit | |
1370 | */ | |
1371 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1372 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1373 | size_t len, unsigned long flags) | |
1374 | { | |
1375 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1376 | struct pl08x_driver_data *pl08x = plchan->host; | |
1377 | struct pl08x_txd *txd; | |
b7f69d9d | 1378 | struct pl08x_sg *dsg; |
e8689e63 LW |
1379 | int ret; |
1380 | ||
c0428794 | 1381 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1382 | if (!txd) { |
1383 | dev_err(&pl08x->adev->dev, | |
1384 | "%s no memory for descriptor\n", __func__); | |
1385 | return NULL; | |
1386 | } | |
1387 | ||
b7f69d9d VK |
1388 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1389 | if (!dsg) { | |
1390 | pl08x_free_txd(pl08x, txd); | |
1391 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1392 | __func__); | |
1393 | return NULL; | |
1394 | } | |
1395 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1396 | ||
b7f69d9d VK |
1397 | dsg->src_addr = src; |
1398 | dsg->dst_addr = dest; | |
1399 | dsg->len = len; | |
e8689e63 LW |
1400 | |
1401 | /* Set platform data for m2m */ | |
4983a04f | 1402 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1403 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1404 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1405 | |
e8689e63 | 1406 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1407 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1408 | |
c7da9a56 | 1409 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1410 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1411 | pl08x->mem_buses); | |
e8689e63 | 1412 | |
e8689e63 LW |
1413 | ret = pl08x_prep_channel_resources(plchan, txd); |
1414 | if (ret) | |
1415 | return NULL; | |
e8689e63 | 1416 | |
01d8dc64 | 1417 | return &txd->vd.tx; |
e8689e63 LW |
1418 | } |
1419 | ||
3e2a037c | 1420 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1421 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1422 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1423 | unsigned long flags, void *context) |
e8689e63 LW |
1424 | { |
1425 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1426 | struct pl08x_driver_data *pl08x = plchan->host; | |
1427 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1428 | struct pl08x_sg *dsg; |
1429 | struct scatterlist *sg; | |
dc8d5f8d | 1430 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1431 | dma_addr_t slave_addr; |
0a235657 | 1432 | int ret, tmp; |
409ec8db | 1433 | u8 src_buses, dst_buses; |
dc8d5f8d | 1434 | u32 maxburst, cctl; |
e8689e63 | 1435 | |
e8689e63 | 1436 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1437 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1438 | |
c0428794 | 1439 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1440 | if (!txd) { |
1441 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1442 | return NULL; | |
1443 | } | |
1444 | ||
e8689e63 LW |
1445 | /* |
1446 | * Set up addresses, the PrimeCell configured address | |
1447 | * will take precedence since this may configure the | |
1448 | * channel target address dynamically at runtime. | |
1449 | */ | |
db8196df | 1450 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1451 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1452 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1453 | addr_width = plchan->cfg.dst_addr_width; |
1454 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1455 | src_buses = pl08x->mem_buses; |
1456 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1457 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1458 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1459 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1460 | addr_width = plchan->cfg.src_addr_width; |
1461 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1462 | src_buses = plchan->cd->periph_buses; |
1463 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1464 | } else { |
b7f69d9d | 1465 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1466 | dev_err(&pl08x->adev->dev, |
1467 | "%s direction unsupported\n", __func__); | |
1468 | return NULL; | |
1469 | } | |
e8689e63 | 1470 | |
dc8d5f8d | 1471 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1472 | if (cctl == ~0) { |
1473 | pl08x_free_txd(pl08x, txd); | |
1474 | dev_err(&pl08x->adev->dev, | |
1475 | "DMA slave configuration botched?\n"); | |
1476 | return NULL; | |
1477 | } | |
1478 | ||
409ec8db RK |
1479 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1480 | ||
95442b22 | 1481 | if (plchan->cfg.device_fc) |
db8196df | 1482 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1483 | PL080_FLOW_PER2MEM_PER; |
1484 | else | |
db8196df | 1485 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1486 | PL080_FLOW_PER2MEM; |
1487 | ||
1488 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1489 | ||
c48d4963 RK |
1490 | ret = pl08x_request_mux(plchan); |
1491 | if (ret < 0) { | |
1492 | pl08x_free_txd(pl08x, txd); | |
1493 | dev_dbg(&pl08x->adev->dev, | |
1494 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1495 | plchan->name); | |
1496 | return NULL; | |
1497 | } | |
1498 | ||
1499 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1500 | plchan->signal, plchan->name); | |
1501 | ||
1502 | /* Assign the flow control signal to this channel */ | |
1503 | if (direction == DMA_MEM_TO_DEV) | |
1504 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1505 | else | |
1506 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1507 | ||
b7f69d9d VK |
1508 | for_each_sg(sgl, sg, sg_len, tmp) { |
1509 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1510 | if (!dsg) { | |
c48d4963 | 1511 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1512 | pl08x_free_txd(pl08x, txd); |
1513 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1514 | __func__); | |
1515 | return NULL; | |
1516 | } | |
1517 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1518 | ||
1519 | dsg->len = sg_dma_len(sg); | |
db8196df | 1520 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1521 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1522 | dsg->dst_addr = slave_addr; |
1523 | } else { | |
1524 | dsg->src_addr = slave_addr; | |
cbb796cc | 1525 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1526 | } |
1527 | } | |
1528 | ||
e8689e63 LW |
1529 | ret = pl08x_prep_channel_resources(plchan, txd); |
1530 | if (ret) | |
1531 | return NULL; | |
e8689e63 | 1532 | |
01d8dc64 | 1533 | return &txd->vd.tx; |
e8689e63 LW |
1534 | } |
1535 | ||
1536 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1537 | unsigned long arg) | |
1538 | { | |
1539 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1540 | struct pl08x_driver_data *pl08x = plchan->host; | |
1541 | unsigned long flags; | |
1542 | int ret = 0; | |
1543 | ||
1544 | /* Controls applicable to inactive channels */ | |
1545 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1546 | return dma_set_runtime_config(chan, |
1547 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1548 | } |
1549 | ||
1550 | /* | |
1551 | * Anything succeeds on channels with no physical allocation and | |
1552 | * no queued transfers. | |
1553 | */ | |
1554 | spin_lock_irqsave(&plchan->lock, flags); | |
1555 | if (!plchan->phychan && !plchan->at) { | |
1556 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | switch (cmd) { | |
1561 | case DMA_TERMINATE_ALL: | |
1562 | plchan->state = PL08X_CHAN_IDLE; | |
1563 | ||
1564 | if (plchan->phychan) { | |
e8689e63 LW |
1565 | /* |
1566 | * Mark physical channel as free and free any slave | |
1567 | * signal | |
1568 | */ | |
a5a488db | 1569 | pl08x_phy_free(plchan); |
e8689e63 | 1570 | } |
e8689e63 LW |
1571 | /* Dequeue jobs and free LLIs */ |
1572 | if (plchan->at) { | |
c48d4963 RK |
1573 | /* Killing this one off, release its mux */ |
1574 | pl08x_release_mux(plchan); | |
e8689e63 LW |
1575 | pl08x_free_txd(pl08x, plchan->at); |
1576 | plchan->at = NULL; | |
1577 | } | |
1578 | /* Dequeue jobs not yet fired as well */ | |
1579 | pl08x_free_txd_list(pl08x, plchan); | |
1580 | break; | |
1581 | case DMA_PAUSE: | |
1582 | pl08x_pause_phy_chan(plchan->phychan); | |
1583 | plchan->state = PL08X_CHAN_PAUSED; | |
1584 | break; | |
1585 | case DMA_RESUME: | |
1586 | pl08x_resume_phy_chan(plchan->phychan); | |
1587 | plchan->state = PL08X_CHAN_RUNNING; | |
1588 | break; | |
1589 | default: | |
1590 | /* Unknown command */ | |
1591 | ret = -ENXIO; | |
1592 | break; | |
1593 | } | |
1594 | ||
1595 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1596 | ||
1597 | return ret; | |
1598 | } | |
1599 | ||
1600 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1601 | { | |
7703eac9 | 1602 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1603 | char *name = chan_id; |
1604 | ||
7703eac9 RKAL |
1605 | /* Reject channels for devices not bound to this driver */ |
1606 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1607 | return false; | |
1608 | ||
1609 | plchan = to_pl08x_chan(chan); | |
1610 | ||
e8689e63 LW |
1611 | /* Check that the channel is not taken! */ |
1612 | if (!strcmp(plchan->name, name)) | |
1613 | return true; | |
1614 | ||
1615 | return false; | |
1616 | } | |
1617 | ||
1618 | /* | |
1619 | * Just check that the device is there and active | |
94ae8522 RKAL |
1620 | * TODO: turn this bit on/off depending on the number of physical channels |
1621 | * actually used, if it is zero... well shut it off. That will save some | |
1622 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1623 | */ |
1624 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1625 | { | |
affa115e LW |
1626 | /* The Nomadik variant does not have the config register */ |
1627 | if (pl08x->vd->nomadik) | |
1628 | return; | |
48a59ef3 | 1629 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1630 | } |
1631 | ||
3d992e1a RKAL |
1632 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1633 | { | |
01d8dc64 | 1634 | struct device *dev = txd->vd.tx.chan->device->dev; |
b7f69d9d | 1635 | struct pl08x_sg *dsg; |
3d992e1a | 1636 | |
01d8dc64 RK |
1637 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { |
1638 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
b7f69d9d VK |
1639 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1640 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1641 | DMA_TO_DEVICE); | |
1642 | else { | |
1643 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1644 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1645 | DMA_TO_DEVICE); | |
1646 | } | |
3d992e1a | 1647 | } |
01d8dc64 RK |
1648 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { |
1649 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
b7f69d9d VK |
1650 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1651 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1652 | DMA_FROM_DEVICE); | |
3d992e1a | 1653 | else |
b7f69d9d VK |
1654 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1655 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1656 | DMA_FROM_DEVICE); | |
3d992e1a RKAL |
1657 | } |
1658 | } | |
1659 | ||
e8689e63 LW |
1660 | static void pl08x_tasklet(unsigned long data) |
1661 | { | |
1662 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1663 | struct pl08x_driver_data *pl08x = plchan->host; |
bf072af4 | 1664 | unsigned long flags; |
a936e793 | 1665 | LIST_HEAD(head); |
e8689e63 | 1666 | |
bf072af4 | 1667 | spin_lock_irqsave(&plchan->lock, flags); |
a936e793 | 1668 | list_splice_tail_init(&plchan->done_list, &head); |
bf072af4 | 1669 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 | 1670 | |
a936e793 RK |
1671 | while (!list_empty(&head)) { |
1672 | struct pl08x_txd *txd = list_first_entry(&head, | |
1673 | struct pl08x_txd, node); | |
01d8dc64 RK |
1674 | dma_async_tx_callback callback = txd->vd.tx.callback; |
1675 | void *callback_param = txd->vd.tx.callback_param; | |
3d992e1a | 1676 | |
a936e793 RK |
1677 | list_del(&txd->node); |
1678 | ||
3d992e1a RKAL |
1679 | /* Don't try to unmap buffers on slave channels */ |
1680 | if (!plchan->slave) | |
1681 | pl08x_unmap_buffers(txd); | |
1682 | ||
1683 | /* Free the descriptor */ | |
1684 | spin_lock_irqsave(&plchan->lock, flags); | |
1685 | pl08x_free_txd(pl08x, txd); | |
1686 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1687 | ||
1688 | /* Callback to signal completion */ | |
1689 | if (callback) | |
1690 | callback(callback_param); | |
1691 | } | |
e8689e63 LW |
1692 | } |
1693 | ||
1694 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1695 | { | |
1696 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1697 | u32 mask = 0, err, tc, i; |
1698 | ||
1699 | /* check & clear - ERR & TC interrupts */ | |
1700 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1701 | if (err) { | |
1702 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1703 | __func__, err); | |
1704 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1705 | } |
d29bf019 | 1706 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1707 | if (tc) |
1708 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1709 | ||
1710 | if (!err && !tc) | |
1711 | return IRQ_NONE; | |
1712 | ||
e8689e63 | 1713 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1714 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1715 | /* Locate physical channel */ |
1716 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1717 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1718 | struct pl08x_txd *tx; |
e8689e63 | 1719 | |
28da2836 VK |
1720 | if (!plchan) { |
1721 | dev_err(&pl08x->adev->dev, | |
1722 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1723 | __func__, i); | |
1724 | continue; | |
1725 | } | |
1726 | ||
a936e793 RK |
1727 | spin_lock(&plchan->lock); |
1728 | tx = plchan->at; | |
1729 | if (tx) { | |
1730 | plchan->at = NULL; | |
c48d4963 RK |
1731 | /* |
1732 | * This descriptor is done, release its mux | |
1733 | * reservation. | |
1734 | */ | |
1735 | pl08x_release_mux(plchan); | |
01d8dc64 | 1736 | dma_cookie_complete(&tx->vd.tx); |
a936e793 | 1737 | list_add_tail(&tx->node, &plchan->done_list); |
c33b644c | 1738 | |
a5a488db RK |
1739 | /* |
1740 | * And start the next descriptor (if any), | |
1741 | * otherwise free this channel. | |
1742 | */ | |
c33b644c RK |
1743 | if (!list_empty(&plchan->issued_list)) |
1744 | pl08x_start_next_txd(plchan); | |
a5a488db RK |
1745 | else |
1746 | pl08x_phy_free(plchan); | |
a936e793 RK |
1747 | } |
1748 | spin_unlock(&plchan->lock); | |
1749 | ||
e8689e63 LW |
1750 | /* Schedule tasklet on this channel */ |
1751 | tasklet_schedule(&plchan->tasklet); | |
e8689e63 LW |
1752 | mask |= (1 << i); |
1753 | } | |
1754 | } | |
e8689e63 LW |
1755 | |
1756 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1757 | } | |
1758 | ||
121c8476 RKAL |
1759 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1760 | { | |
121c8476 RKAL |
1761 | chan->slave = true; |
1762 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1763 | chan->cfg.src_addr = chan->cd->addr; |
1764 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1765 | } |
1766 | ||
e8689e63 LW |
1767 | /* |
1768 | * Initialise the DMAC memcpy/slave channels. | |
1769 | * Make a local wrapper to hold required data | |
1770 | */ | |
1771 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1772 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1773 | { |
1774 | struct pl08x_dma_chan *chan; | |
1775 | int i; | |
1776 | ||
1777 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1778 | |
e8689e63 LW |
1779 | /* |
1780 | * Register as many many memcpy as we have physical channels, | |
1781 | * we won't always be able to use all but the code will have | |
1782 | * to cope with that situation. | |
1783 | */ | |
1784 | for (i = 0; i < channels; i++) { | |
b201c111 | 1785 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1786 | if (!chan) { |
1787 | dev_err(&pl08x->adev->dev, | |
1788 | "%s no memory for channel\n", __func__); | |
1789 | return -ENOMEM; | |
1790 | } | |
1791 | ||
1792 | chan->host = pl08x; | |
1793 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1794 | chan->signal = -1; |
e8689e63 LW |
1795 | |
1796 | if (slave) { | |
e8689e63 | 1797 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1798 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1799 | } else { |
1800 | chan->cd = &pl08x->pd->memcpy_channel; | |
1801 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1802 | if (!chan->name) { | |
1803 | kfree(chan); | |
1804 | return -ENOMEM; | |
1805 | } | |
1806 | } | |
175a5e61 | 1807 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1808 | "initialize virtual channel \"%s\"\n", |
1809 | chan->name); | |
1810 | ||
01d8dc64 RK |
1811 | chan->vc.chan.device = dmadev; |
1812 | dma_cookie_init(&chan->vc.chan); | |
e8689e63 LW |
1813 | |
1814 | spin_lock_init(&chan->lock); | |
15c17232 | 1815 | INIT_LIST_HEAD(&chan->pend_list); |
ea160561 | 1816 | INIT_LIST_HEAD(&chan->issued_list); |
a936e793 | 1817 | INIT_LIST_HEAD(&chan->done_list); |
e8689e63 LW |
1818 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1819 | (unsigned long) chan); | |
1820 | ||
01d8dc64 | 1821 | list_add_tail(&chan->vc.chan.device_node, &dmadev->channels); |
e8689e63 LW |
1822 | } |
1823 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1824 | i, slave ? "slave" : "memcpy"); | |
1825 | return i; | |
1826 | } | |
1827 | ||
1828 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1829 | { | |
1830 | struct pl08x_dma_chan *chan = NULL; | |
1831 | struct pl08x_dma_chan *next; | |
1832 | ||
1833 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1834 | next, &dmadev->channels, vc.chan.device_node) { |
1835 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1836 | kfree(chan); |
1837 | } | |
1838 | } | |
1839 | ||
1840 | #ifdef CONFIG_DEBUG_FS | |
1841 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1842 | { | |
1843 | switch (state) { | |
1844 | case PL08X_CHAN_IDLE: | |
1845 | return "idle"; | |
1846 | case PL08X_CHAN_RUNNING: | |
1847 | return "running"; | |
1848 | case PL08X_CHAN_PAUSED: | |
1849 | return "paused"; | |
1850 | case PL08X_CHAN_WAITING: | |
1851 | return "waiting"; | |
1852 | default: | |
1853 | break; | |
1854 | } | |
1855 | return "UNKNOWN STATE"; | |
1856 | } | |
1857 | ||
1858 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1859 | { | |
1860 | struct pl08x_driver_data *pl08x = s->private; | |
1861 | struct pl08x_dma_chan *chan; | |
1862 | struct pl08x_phy_chan *ch; | |
1863 | unsigned long flags; | |
1864 | int i; | |
1865 | ||
1866 | seq_printf(s, "PL08x physical channels:\n"); | |
1867 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1868 | seq_printf(s, "--------\t-----\n"); | |
1869 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1870 | struct pl08x_dma_chan *virt_chan; | |
1871 | ||
1872 | ch = &pl08x->phy_chans[i]; | |
1873 | ||
1874 | spin_lock_irqsave(&ch->lock, flags); | |
1875 | virt_chan = ch->serving; | |
1876 | ||
affa115e LW |
1877 | seq_printf(s, "%d\t\t%s%s\n", |
1878 | ch->id, | |
1879 | virt_chan ? virt_chan->name : "(none)", | |
1880 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1881 | |
1882 | spin_unlock_irqrestore(&ch->lock, flags); | |
1883 | } | |
1884 | ||
1885 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1886 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1887 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1888 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1889 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1890 | pl08x_state_str(chan->state)); |
1891 | } | |
1892 | ||
1893 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1894 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1895 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1896 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1897 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1898 | pl08x_state_str(chan->state)); |
1899 | } | |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | ||
1904 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1905 | { | |
1906 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1907 | } | |
1908 | ||
1909 | static const struct file_operations pl08x_debugfs_operations = { | |
1910 | .open = pl08x_debugfs_open, | |
1911 | .read = seq_read, | |
1912 | .llseek = seq_lseek, | |
1913 | .release = single_release, | |
1914 | }; | |
1915 | ||
1916 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1917 | { | |
1918 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1919 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1920 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1921 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1922 | } |
1923 | ||
1924 | #else | |
1925 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1926 | { | |
1927 | } | |
1928 | #endif | |
1929 | ||
aa25afad | 1930 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1931 | { |
1932 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1933 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1934 | int ret = 0; |
1935 | int i; | |
1936 | ||
1937 | ret = amba_request_regions(adev, NULL); | |
1938 | if (ret) | |
1939 | return ret; | |
1940 | ||
1941 | /* Create the driver state holder */ | |
b201c111 | 1942 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1943 | if (!pl08x) { |
1944 | ret = -ENOMEM; | |
1945 | goto out_no_pl08x; | |
1946 | } | |
1947 | ||
1948 | /* Initialize memcpy engine */ | |
1949 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1950 | pl08x->memcpy.dev = &adev->dev; | |
1951 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1952 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1953 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1954 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1955 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1956 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1957 | pl08x->memcpy.device_control = pl08x_control; | |
1958 | ||
1959 | /* Initialize slave engine */ | |
1960 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1961 | pl08x->slave.dev = &adev->dev; | |
1962 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1963 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1964 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1965 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1966 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1967 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1968 | pl08x->slave.device_control = pl08x_control; | |
1969 | ||
1970 | /* Get the platform data */ | |
1971 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1972 | if (!pl08x->pd) { | |
1973 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1974 | goto out_no_platdata; | |
1975 | } | |
1976 | ||
1977 | /* Assign useful pointers to the driver state */ | |
1978 | pl08x->adev = adev; | |
1979 | pl08x->vd = vd; | |
1980 | ||
30749cb4 RKAL |
1981 | /* By default, AHB1 only. If dualmaster, from platform */ |
1982 | pl08x->lli_buses = PL08X_AHB1; | |
1983 | pl08x->mem_buses = PL08X_AHB1; | |
1984 | if (pl08x->vd->dualmaster) { | |
1985 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1986 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1987 | } | |
1988 | ||
e8689e63 LW |
1989 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1990 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1991 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1992 | if (!pl08x->pool) { | |
1993 | ret = -ENOMEM; | |
1994 | goto out_no_lli_pool; | |
1995 | } | |
1996 | ||
e8689e63 LW |
1997 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
1998 | if (!pl08x->base) { | |
1999 | ret = -ENOMEM; | |
2000 | goto out_no_ioremap; | |
2001 | } | |
2002 | ||
2003 | /* Turn on the PL08x */ | |
2004 | pl08x_ensure_on(pl08x); | |
2005 | ||
94ae8522 | 2006 | /* Attach the interrupt handler */ |
e8689e63 LW |
2007 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
2008 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
2009 | ||
2010 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 2011 | DRIVER_NAME, pl08x); |
e8689e63 LW |
2012 | if (ret) { |
2013 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2014 | __func__, adev->irq[0]); | |
2015 | goto out_no_irq; | |
2016 | } | |
2017 | ||
2018 | /* Initialize physical channels */ | |
affa115e | 2019 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2020 | GFP_KERNEL); |
2021 | if (!pl08x->phy_chans) { | |
2022 | dev_err(&adev->dev, "%s failed to allocate " | |
2023 | "physical channel holders\n", | |
2024 | __func__); | |
2025 | goto out_no_phychans; | |
2026 | } | |
2027 | ||
2028 | for (i = 0; i < vd->channels; i++) { | |
2029 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2030 | ||
2031 | ch->id = i; | |
2032 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
2033 | spin_lock_init(&ch->lock); | |
affa115e LW |
2034 | |
2035 | /* | |
2036 | * Nomadik variants can have channels that are locked | |
2037 | * down for the secure world only. Lock up these channels | |
2038 | * by perpetually serving a dummy virtual channel. | |
2039 | */ | |
2040 | if (vd->nomadik) { | |
2041 | u32 val; | |
2042 | ||
2043 | val = readl(ch->base + PL080_CH_CONFIG); | |
2044 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { | |
2045 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2046 | ch->locked = true; | |
2047 | } | |
2048 | } | |
2049 | ||
175a5e61 VK |
2050 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2051 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2052 | } |
2053 | ||
2054 | /* Register as many memcpy channels as there are physical channels */ | |
2055 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2056 | pl08x->vd->channels, false); | |
2057 | if (ret <= 0) { | |
2058 | dev_warn(&pl08x->adev->dev, | |
2059 | "%s failed to enumerate memcpy channels - %d\n", | |
2060 | __func__, ret); | |
2061 | goto out_no_memcpy; | |
2062 | } | |
2063 | pl08x->memcpy.chancnt = ret; | |
2064 | ||
2065 | /* Register slave channels */ | |
2066 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2067 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2068 | if (ret <= 0) { |
2069 | dev_warn(&pl08x->adev->dev, | |
2070 | "%s failed to enumerate slave channels - %d\n", | |
2071 | __func__, ret); | |
2072 | goto out_no_slave; | |
2073 | } | |
2074 | pl08x->slave.chancnt = ret; | |
2075 | ||
2076 | ret = dma_async_device_register(&pl08x->memcpy); | |
2077 | if (ret) { | |
2078 | dev_warn(&pl08x->adev->dev, | |
2079 | "%s failed to register memcpy as an async device - %d\n", | |
2080 | __func__, ret); | |
2081 | goto out_no_memcpy_reg; | |
2082 | } | |
2083 | ||
2084 | ret = dma_async_device_register(&pl08x->slave); | |
2085 | if (ret) { | |
2086 | dev_warn(&pl08x->adev->dev, | |
2087 | "%s failed to register slave as an async device - %d\n", | |
2088 | __func__, ret); | |
2089 | goto out_no_slave_reg; | |
2090 | } | |
2091 | ||
2092 | amba_set_drvdata(adev, pl08x); | |
2093 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2094 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2095 | amba_part(adev), amba_rev(adev), | |
2096 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b | 2097 | |
e8689e63 LW |
2098 | return 0; |
2099 | ||
2100 | out_no_slave_reg: | |
2101 | dma_async_device_unregister(&pl08x->memcpy); | |
2102 | out_no_memcpy_reg: | |
2103 | pl08x_free_virtual_channels(&pl08x->slave); | |
2104 | out_no_slave: | |
2105 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2106 | out_no_memcpy: | |
2107 | kfree(pl08x->phy_chans); | |
2108 | out_no_phychans: | |
2109 | free_irq(adev->irq[0], pl08x); | |
2110 | out_no_irq: | |
2111 | iounmap(pl08x->base); | |
2112 | out_no_ioremap: | |
2113 | dma_pool_destroy(pl08x->pool); | |
2114 | out_no_lli_pool: | |
2115 | out_no_platdata: | |
2116 | kfree(pl08x); | |
2117 | out_no_pl08x: | |
2118 | amba_release_regions(adev); | |
2119 | return ret; | |
2120 | } | |
2121 | ||
2122 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2123 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2124 | .channels = 8, |
2125 | .dualmaster = true, | |
2126 | }; | |
2127 | ||
affa115e LW |
2128 | static struct vendor_data vendor_nomadik = { |
2129 | .channels = 8, | |
2130 | .dualmaster = true, | |
2131 | .nomadik = true, | |
2132 | }; | |
2133 | ||
e8689e63 | 2134 | static struct vendor_data vendor_pl081 = { |
e8689e63 LW |
2135 | .channels = 2, |
2136 | .dualmaster = false, | |
2137 | }; | |
2138 | ||
2139 | static struct amba_id pl08x_ids[] = { | |
2140 | /* PL080 */ | |
2141 | { | |
2142 | .id = 0x00041080, | |
2143 | .mask = 0x000fffff, | |
2144 | .data = &vendor_pl080, | |
2145 | }, | |
2146 | /* PL081 */ | |
2147 | { | |
2148 | .id = 0x00041081, | |
2149 | .mask = 0x000fffff, | |
2150 | .data = &vendor_pl081, | |
2151 | }, | |
2152 | /* Nomadik 8815 PL080 variant */ | |
2153 | { | |
affa115e | 2154 | .id = 0x00280080, |
e8689e63 | 2155 | .mask = 0x00ffffff, |
affa115e | 2156 | .data = &vendor_nomadik, |
e8689e63 LW |
2157 | }, |
2158 | { 0, 0 }, | |
2159 | }; | |
2160 | ||
037566df DM |
2161 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2162 | ||
e8689e63 LW |
2163 | static struct amba_driver pl08x_amba_driver = { |
2164 | .drv.name = DRIVER_NAME, | |
2165 | .id_table = pl08x_ids, | |
2166 | .probe = pl08x_probe, | |
2167 | }; | |
2168 | ||
2169 | static int __init pl08x_init(void) | |
2170 | { | |
2171 | int retval; | |
2172 | retval = amba_driver_register(&pl08x_amba_driver); | |
2173 | if (retval) | |
2174 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2175 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2176 | retval); |
2177 | return retval; | |
2178 | } | |
2179 | subsys_initcall(pl08x_init); |