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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
e8689e63 | 86 | #include <asm/hardware/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 | 88 | #include "dmaengine.h" |
01d8dc64 | 89 | #include "virt-dma.h" |
d2ebfb33 | 90 | |
e8689e63 LW |
91 | #define DRIVER_NAME "pl08xdmac" |
92 | ||
7703eac9 | 93 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 94 | struct pl08x_driver_data; |
7703eac9 | 95 | |
e8689e63 | 96 | /** |
94ae8522 | 97 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 98 | * @channels: the number of channels available in this variant |
94ae8522 | 99 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
100 | * @nomadik: whether the channels have Nomadik security extension bits |
101 | * that need to be checked for permission before use and some registers are | |
102 | * missing | |
e8689e63 LW |
103 | */ |
104 | struct vendor_data { | |
e8689e63 LW |
105 | u8 channels; |
106 | bool dualmaster; | |
affa115e | 107 | bool nomadik; |
e8689e63 LW |
108 | }; |
109 | ||
110 | /* | |
111 | * PL08X private data structures | |
e8b5e11d | 112 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
113 | * start & end do not - their bus bit info is in cctl. Also note that these |
114 | * are fixed 32-bit quantities. | |
e8689e63 | 115 | */ |
7cb72ad9 | 116 | struct pl08x_lli { |
e25761d7 RKAL |
117 | u32 src; |
118 | u32 dst; | |
bfddfb45 | 119 | u32 lli; |
e8689e63 LW |
120 | u32 cctl; |
121 | }; | |
122 | ||
b23f204c RK |
123 | /** |
124 | * struct pl08x_bus_data - information of source or destination | |
125 | * busses for a transfer | |
126 | * @addr: current address | |
127 | * @maxwidth: the maximum width of a transfer on this bus | |
128 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
129 | */ | |
130 | struct pl08x_bus_data { | |
131 | dma_addr_t addr; | |
132 | u8 maxwidth; | |
133 | u8 buswidth; | |
134 | }; | |
135 | ||
136 | /** | |
137 | * struct pl08x_phy_chan - holder for the physical channels | |
138 | * @id: physical index to this channel | |
139 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
140 | * @serving: the virtual channel currently being served by this physical |
141 | * channel | |
ad0de2ac RK |
142 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
143 | * world | |
b23f204c RK |
144 | */ |
145 | struct pl08x_phy_chan { | |
146 | unsigned int id; | |
147 | void __iomem *base; | |
148 | spinlock_t lock; | |
b23f204c | 149 | struct pl08x_dma_chan *serving; |
ad0de2ac | 150 | bool locked; |
b23f204c RK |
151 | }; |
152 | ||
153 | /** | |
154 | * struct pl08x_sg - structure containing data per sg | |
155 | * @src_addr: src address of sg | |
156 | * @dst_addr: dst address of sg | |
157 | * @len: transfer len in bytes | |
158 | * @node: node for txd's dsg_list | |
159 | */ | |
160 | struct pl08x_sg { | |
161 | dma_addr_t src_addr; | |
162 | dma_addr_t dst_addr; | |
163 | size_t len; | |
164 | struct list_head node; | |
165 | }; | |
166 | ||
167 | /** | |
168 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 169 | * @vd: virtual DMA descriptor |
b23f204c RK |
170 | * @node: node for txd list for channels |
171 | * @dsg_list: list of children sg's | |
b23f204c RK |
172 | * @llis_bus: DMA memory address (physical) start for the LLIs |
173 | * @llis_va: virtual memory address start for the LLIs | |
174 | * @cctl: control reg values for current txd | |
175 | * @ccfg: config reg values for current txd | |
176 | */ | |
177 | struct pl08x_txd { | |
01d8dc64 | 178 | struct virt_dma_desc vd; |
b23f204c RK |
179 | struct list_head node; |
180 | struct list_head dsg_list; | |
b23f204c RK |
181 | dma_addr_t llis_bus; |
182 | struct pl08x_lli *llis_va; | |
183 | /* Default cctl value for LLIs */ | |
184 | u32 cctl; | |
185 | /* | |
186 | * Settings to be put into the physical channel when we | |
187 | * trigger this txd. Other registers are in llis_va[0]. | |
188 | */ | |
189 | u32 ccfg; | |
190 | }; | |
191 | ||
192 | /** | |
193 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
194 | * states | |
195 | * @PL08X_CHAN_IDLE: the channel is idle | |
196 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
197 | * channel and is running a transfer on it | |
198 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
199 | * channel, but the transfer is currently paused | |
200 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
201 | * channel to become available (only pertains to memcpy channels) | |
202 | */ | |
203 | enum pl08x_dma_chan_state { | |
204 | PL08X_CHAN_IDLE, | |
205 | PL08X_CHAN_RUNNING, | |
206 | PL08X_CHAN_PAUSED, | |
207 | PL08X_CHAN_WAITING, | |
208 | }; | |
209 | ||
210 | /** | |
211 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 212 | * @vc: wrappped virtual channel |
b23f204c | 213 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
214 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc |
215 | * @name: name of channel | |
216 | * @cd: channel platform data | |
217 | * @runtime_addr: address for RX/TX according to the runtime config | |
a936e793 | 218 | * @done_list: list of completed transactions |
b23f204c RK |
219 | * @at: active transaction on this channel |
220 | * @lock: a lock for this channel data | |
221 | * @host: a pointer to the host (internal use) | |
222 | * @state: whether the channel is idle, paused, running etc | |
223 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 224 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 225 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
226 | */ |
227 | struct pl08x_dma_chan { | |
01d8dc64 | 228 | struct virt_dma_chan vc; |
b23f204c | 229 | struct pl08x_phy_chan *phychan; |
b23f204c | 230 | struct tasklet_struct tasklet; |
550ec36f | 231 | const char *name; |
b23f204c | 232 | const struct pl08x_channel_data *cd; |
ed91c13d | 233 | struct dma_slave_config cfg; |
a936e793 | 234 | struct list_head done_list; |
b23f204c | 235 | struct pl08x_txd *at; |
b23f204c RK |
236 | struct pl08x_driver_data *host; |
237 | enum pl08x_dma_chan_state state; | |
238 | bool slave; | |
ad0de2ac | 239 | int signal; |
5e2479bd | 240 | unsigned mux_use; |
b23f204c RK |
241 | }; |
242 | ||
e8689e63 LW |
243 | /** |
244 | * struct pl08x_driver_data - the local state holder for the PL08x | |
245 | * @slave: slave engine for this instance | |
246 | * @memcpy: memcpy engine for this instance | |
247 | * @base: virtual memory base (remapped) for the PL08x | |
248 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
249 | * @vd: vendor data for this PL08x variant | |
250 | * @pd: platform data passed in from the platform/machine | |
251 | * @phy_chans: array of data for the physical channels | |
252 | * @pool: a pool for the LLI descriptors | |
253 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
254 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
255 | * fetches | |
30749cb4 | 256 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
257 | * @lock: a spinlock for this struct |
258 | */ | |
259 | struct pl08x_driver_data { | |
260 | struct dma_device slave; | |
261 | struct dma_device memcpy; | |
262 | void __iomem *base; | |
263 | struct amba_device *adev; | |
f96ca9ec | 264 | const struct vendor_data *vd; |
e8689e63 LW |
265 | struct pl08x_platform_data *pd; |
266 | struct pl08x_phy_chan *phy_chans; | |
267 | struct dma_pool *pool; | |
268 | int pool_ctr; | |
30749cb4 RKAL |
269 | u8 lli_buses; |
270 | u8 mem_buses; | |
e8689e63 LW |
271 | }; |
272 | ||
273 | /* | |
274 | * PL08X specific defines | |
275 | */ | |
276 | ||
e8689e63 LW |
277 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
278 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
279 | ||
e8b5e11d | 280 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 281 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
282 | #define PL08X_ALIGN 8 |
283 | ||
284 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
285 | { | |
01d8dc64 | 286 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
287 | } |
288 | ||
501e67e8 RKAL |
289 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
290 | { | |
01d8dc64 | 291 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
292 | } |
293 | ||
6b16c8b1 RK |
294 | /* |
295 | * Mux handling. | |
296 | * | |
297 | * This gives us the DMA request input to the PL08x primecell which the | |
298 | * peripheral described by the channel data will be routed to, possibly | |
299 | * via a board/SoC specific external MUX. One important point to note | |
300 | * here is that this does not depend on the physical channel. | |
301 | */ | |
ad0de2ac | 302 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
303 | { |
304 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
305 | int ret; | |
306 | ||
5e2479bd | 307 | if (plchan->mux_use++ == 0 && pd->get_signal) { |
6b16c8b1 | 308 | ret = pd->get_signal(plchan->cd); |
5e2479bd RK |
309 | if (ret < 0) { |
310 | plchan->mux_use = 0; | |
6b16c8b1 | 311 | return ret; |
5e2479bd | 312 | } |
6b16c8b1 | 313 | |
ad0de2ac | 314 | plchan->signal = ret; |
6b16c8b1 RK |
315 | } |
316 | return 0; | |
317 | } | |
318 | ||
319 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
320 | { | |
321 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
322 | ||
5e2479bd RK |
323 | if (plchan->signal >= 0) { |
324 | WARN_ON(plchan->mux_use == 0); | |
325 | ||
326 | if (--plchan->mux_use == 0 && pd->put_signal) { | |
327 | pd->put_signal(plchan->cd, plchan->signal); | |
328 | plchan->signal = -1; | |
329 | } | |
6b16c8b1 RK |
330 | } |
331 | } | |
332 | ||
e8689e63 LW |
333 | /* |
334 | * Physical channel handling | |
335 | */ | |
336 | ||
337 | /* Whether a certain channel is busy or not */ | |
338 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
339 | { | |
340 | unsigned int val; | |
341 | ||
342 | val = readl(ch->base + PL080_CH_CONFIG); | |
343 | return val & PL080_CONFIG_ACTIVE; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 348 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
349 | * been set when the LLIs were constructed. Poke them into the hardware |
350 | * and start the transfer. | |
e8689e63 | 351 | */ |
eab82533 | 352 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 353 | { |
c885bee4 | 354 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 355 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
356 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
357 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
eab82533 | 358 | struct pl08x_lli *lli; |
09b3c323 | 359 | u32 val; |
c885bee4 | 360 | |
879f127b | 361 | list_del(&txd->vd.node); |
eab82533 | 362 | |
c885bee4 | 363 | plchan->at = txd; |
e8689e63 | 364 | |
c885bee4 RKAL |
365 | /* Wait for channel inactive */ |
366 | while (pl08x_phy_channel_busy(phychan)) | |
367 | cpu_relax(); | |
e8689e63 | 368 | |
eab82533 RK |
369 | lli = &txd->llis_va[0]; |
370 | ||
c885bee4 RKAL |
371 | dev_vdbg(&pl08x->adev->dev, |
372 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
373 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
374 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 375 | txd->ccfg); |
19524d77 RKAL |
376 | |
377 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
378 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
379 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
380 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 381 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
382 | |
383 | /* Enable the DMA channel */ | |
384 | /* Do not access config register until channel shows as disabled */ | |
385 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 386 | cpu_relax(); |
e8689e63 | 387 | |
c885bee4 RKAL |
388 | /* Do not access config register until channel shows as inactive */ |
389 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 390 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 391 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 392 | |
c885bee4 | 393 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
394 | } |
395 | ||
396 | /* | |
81796616 | 397 | * Pause the channel by setting the HALT bit. |
e8689e63 | 398 | * |
81796616 RKAL |
399 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
400 | * the FIFO can only drain if the peripheral is still requesting data. | |
401 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 402 | * |
81796616 RKAL |
403 | * For P->M transfers, disable the peripheral first to stop it filling |
404 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
405 | */ |
406 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
407 | { | |
408 | u32 val; | |
81796616 | 409 | int timeout; |
e8689e63 LW |
410 | |
411 | /* Set the HALT bit and wait for the FIFO to drain */ | |
412 | val = readl(ch->base + PL080_CH_CONFIG); | |
413 | val |= PL080_CONFIG_HALT; | |
414 | writel(val, ch->base + PL080_CH_CONFIG); | |
415 | ||
416 | /* Wait for channel inactive */ | |
81796616 RKAL |
417 | for (timeout = 1000; timeout; timeout--) { |
418 | if (!pl08x_phy_channel_busy(ch)) | |
419 | break; | |
420 | udelay(1); | |
421 | } | |
422 | if (pl08x_phy_channel_busy(ch)) | |
423 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
424 | } |
425 | ||
426 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
427 | { | |
428 | u32 val; | |
429 | ||
430 | /* Clear the HALT bit */ | |
431 | val = readl(ch->base + PL080_CH_CONFIG); | |
432 | val &= ~PL080_CONFIG_HALT; | |
433 | writel(val, ch->base + PL080_CH_CONFIG); | |
434 | } | |
435 | ||
fb526210 RKAL |
436 | /* |
437 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
438 | * clears any pending interrupt status. This should not be used for | |
439 | * an on-going transfer, but as a method of shutting down a channel | |
440 | * (eg, when it's no longer used) or terminating a transfer. | |
441 | */ | |
442 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
443 | struct pl08x_phy_chan *ch) | |
e8689e63 | 444 | { |
fb526210 | 445 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 446 | |
fb526210 RKAL |
447 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
448 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 449 | |
e8689e63 | 450 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
451 | |
452 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
453 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
454 | } |
455 | ||
456 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
457 | { | |
458 | /* The source width defines the number of bytes */ | |
459 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
460 | ||
461 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
462 | case PL080_WIDTH_8BIT: | |
463 | break; | |
464 | case PL080_WIDTH_16BIT: | |
465 | bytes *= 2; | |
466 | break; | |
467 | case PL080_WIDTH_32BIT: | |
468 | bytes *= 4; | |
469 | break; | |
470 | } | |
471 | return bytes; | |
472 | } | |
473 | ||
474 | /* The channel should be paused when calling this */ | |
475 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
476 | { | |
477 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
478 | struct pl08x_txd *txd; |
479 | unsigned long flags; | |
cace6585 | 480 | size_t bytes = 0; |
e8689e63 | 481 | |
083be28a | 482 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 LW |
483 | ch = plchan->phychan; |
484 | txd = plchan->at; | |
485 | ||
486 | /* | |
db9f136a RKAL |
487 | * Follow the LLIs to get the number of remaining |
488 | * bytes in the currently active transaction. | |
e8689e63 LW |
489 | */ |
490 | if (ch && txd) { | |
4c0df6a3 | 491 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 492 | |
db9f136a | 493 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
494 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
495 | ||
496 | if (clli) { | |
db9f136a RKAL |
497 | struct pl08x_lli *llis_va = txd->llis_va; |
498 | dma_addr_t llis_bus = txd->llis_bus; | |
499 | int index; | |
500 | ||
501 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
502 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 503 | |
db9f136a RKAL |
504 | /* |
505 | * Locate the next LLI - as this is an array, | |
506 | * it's simple maths to find. | |
507 | */ | |
508 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
509 | ||
510 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
511 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 512 | |
e8689e63 | 513 | /* |
e8b5e11d | 514 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 515 | */ |
db9f136a RKAL |
516 | if (!llis_va[index].lli) |
517 | break; | |
e8689e63 LW |
518 | } |
519 | } | |
520 | } | |
521 | ||
522 | /* Sum up all queued transactions */ | |
879f127b | 523 | if (!list_empty(&plchan->vc.desc_issued)) { |
ea160561 | 524 | struct pl08x_txd *txdi; |
879f127b | 525 | list_for_each_entry(txdi, &plchan->vc.desc_issued, vd.node) { |
ea160561 RK |
526 | struct pl08x_sg *dsg; |
527 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
528 | bytes += dsg->len; | |
529 | } | |
530 | } | |
531 | ||
879f127b | 532 | if (!list_empty(&plchan->vc.desc_submitted)) { |
db9f136a | 533 | struct pl08x_txd *txdi; |
879f127b | 534 | list_for_each_entry(txdi, &plchan->vc.desc_submitted, vd.node) { |
b7f69d9d VK |
535 | struct pl08x_sg *dsg; |
536 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
537 | bytes += dsg->len; | |
e8689e63 | 538 | } |
e8689e63 LW |
539 | } |
540 | ||
083be28a | 541 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
542 | |
543 | return bytes; | |
544 | } | |
545 | ||
546 | /* | |
547 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
548 | * |
549 | * Try to locate a physical channel to be used for this transfer. If all | |
550 | * are taken return NULL and the requester will have to cope by using | |
551 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
552 | */ |
553 | static struct pl08x_phy_chan * | |
554 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
555 | struct pl08x_dma_chan *virt_chan) | |
556 | { | |
557 | struct pl08x_phy_chan *ch = NULL; | |
558 | unsigned long flags; | |
559 | int i; | |
560 | ||
e8689e63 LW |
561 | for (i = 0; i < pl08x->vd->channels; i++) { |
562 | ch = &pl08x->phy_chans[i]; | |
563 | ||
564 | spin_lock_irqsave(&ch->lock, flags); | |
565 | ||
affa115e | 566 | if (!ch->locked && !ch->serving) { |
e8689e63 | 567 | ch->serving = virt_chan; |
e8689e63 LW |
568 | spin_unlock_irqrestore(&ch->lock, flags); |
569 | break; | |
570 | } | |
571 | ||
572 | spin_unlock_irqrestore(&ch->lock, flags); | |
573 | } | |
574 | ||
575 | if (i == pl08x->vd->channels) { | |
576 | /* No physical channel available, cope with it */ | |
577 | return NULL; | |
578 | } | |
579 | ||
580 | return ch; | |
581 | } | |
582 | ||
a5a488db | 583 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
584 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
585 | struct pl08x_phy_chan *ch) | |
586 | { | |
a5a488db RK |
587 | ch->serving = NULL; |
588 | } | |
e8689e63 | 589 | |
a5a488db RK |
590 | /* |
591 | * Try to allocate a physical channel. When successful, assign it to | |
592 | * this virtual channel, and initiate the next descriptor. The | |
593 | * virtual channel lock must be held at this point. | |
594 | */ | |
595 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
596 | { | |
597 | struct pl08x_driver_data *pl08x = plchan->host; | |
598 | struct pl08x_phy_chan *ch; | |
fb526210 | 599 | |
a5a488db RK |
600 | ch = pl08x_get_phy_channel(pl08x, plchan); |
601 | if (!ch) { | |
602 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
603 | plchan->state = PL08X_CHAN_WAITING; | |
604 | return; | |
605 | } | |
e8689e63 | 606 | |
a5a488db RK |
607 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
608 | ch->id, plchan->name); | |
609 | ||
610 | plchan->phychan = ch; | |
611 | plchan->state = PL08X_CHAN_RUNNING; | |
612 | pl08x_start_next_txd(plchan); | |
613 | } | |
614 | ||
615 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
616 | struct pl08x_dma_chan *plchan) | |
617 | { | |
618 | struct pl08x_driver_data *pl08x = plchan->host; | |
619 | ||
620 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
621 | ch->id, plchan->name); | |
622 | ||
623 | /* | |
624 | * We do this without taking the lock; we're really only concerned | |
625 | * about whether this pointer is NULL or not, and we're guaranteed | |
626 | * that this will only be called when it _already_ is non-NULL. | |
627 | */ | |
628 | ch->serving = plchan; | |
629 | plchan->phychan = ch; | |
630 | plchan->state = PL08X_CHAN_RUNNING; | |
631 | pl08x_start_next_txd(plchan); | |
632 | } | |
633 | ||
634 | /* | |
635 | * Free a physical DMA channel, potentially reallocating it to another | |
636 | * virtual channel if we have any pending. | |
637 | */ | |
638 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
639 | { | |
640 | struct pl08x_driver_data *pl08x = plchan->host; | |
641 | struct pl08x_dma_chan *p, *next; | |
642 | ||
643 | retry: | |
644 | next = NULL; | |
645 | ||
646 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 647 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
648 | if (p->state == PL08X_CHAN_WAITING) { |
649 | next = p; | |
650 | break; | |
651 | } | |
652 | ||
653 | if (!next) { | |
01d8dc64 | 654 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
655 | if (p->state == PL08X_CHAN_WAITING) { |
656 | next = p; | |
657 | break; | |
658 | } | |
659 | } | |
660 | ||
661 | /* Ensure that the physical channel is stopped */ | |
662 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
663 | ||
664 | if (next) { | |
665 | bool success; | |
666 | ||
667 | /* | |
668 | * Eww. We know this isn't going to deadlock | |
669 | * but lockdep probably doesn't. | |
670 | */ | |
083be28a | 671 | spin_lock(&next->vc.lock); |
a5a488db RK |
672 | /* Re-check the state now that we have the lock */ |
673 | success = next->state == PL08X_CHAN_WAITING; | |
674 | if (success) | |
675 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 676 | spin_unlock(&next->vc.lock); |
a5a488db RK |
677 | |
678 | /* If the state changed, try to find another channel */ | |
679 | if (!success) | |
680 | goto retry; | |
681 | } else { | |
682 | /* No more jobs, so free up the physical channel */ | |
683 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
684 | } | |
685 | ||
686 | plchan->phychan = NULL; | |
687 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
688 | } |
689 | ||
690 | /* | |
691 | * LLI handling | |
692 | */ | |
693 | ||
694 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
695 | { | |
696 | switch (coded) { | |
697 | case PL080_WIDTH_8BIT: | |
698 | return 1; | |
699 | case PL080_WIDTH_16BIT: | |
700 | return 2; | |
701 | case PL080_WIDTH_32BIT: | |
702 | return 4; | |
703 | default: | |
704 | break; | |
705 | } | |
706 | BUG(); | |
707 | return 0; | |
708 | } | |
709 | ||
710 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 711 | size_t tsize) |
e8689e63 LW |
712 | { |
713 | u32 retbits = cctl; | |
714 | ||
e8b5e11d | 715 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
716 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
717 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
718 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
719 | ||
720 | /* Then set the bits according to the parameters */ | |
721 | switch (srcwidth) { | |
722 | case 1: | |
723 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
724 | break; | |
725 | case 2: | |
726 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
727 | break; | |
728 | case 4: | |
729 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
730 | break; | |
731 | default: | |
732 | BUG(); | |
733 | break; | |
734 | } | |
735 | ||
736 | switch (dstwidth) { | |
737 | case 1: | |
738 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
739 | break; | |
740 | case 2: | |
741 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
742 | break; | |
743 | case 4: | |
744 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
745 | break; | |
746 | default: | |
747 | BUG(); | |
748 | break; | |
749 | } | |
750 | ||
751 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
752 | return retbits; | |
753 | } | |
754 | ||
542361f8 RKAL |
755 | struct pl08x_lli_build_data { |
756 | struct pl08x_txd *txd; | |
542361f8 RKAL |
757 | struct pl08x_bus_data srcbus; |
758 | struct pl08x_bus_data dstbus; | |
759 | size_t remainder; | |
25c94f7f | 760 | u32 lli_bus; |
542361f8 RKAL |
761 | }; |
762 | ||
e8689e63 | 763 | /* |
0532e6fc VK |
764 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
765 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
766 | * masters address with width requirements of transfer (by sending few byte by | |
767 | * byte data), slave is still not aligned, then its width will be reduced to | |
768 | * BYTE. | |
769 | * - prefers the destination bus if both available | |
036f05fd | 770 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 771 | */ |
542361f8 RKAL |
772 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
773 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
774 | { |
775 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
776 | *mbus = &bd->dstbus; |
777 | *sbus = &bd->srcbus; | |
036f05fd VK |
778 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
779 | *mbus = &bd->srcbus; | |
780 | *sbus = &bd->dstbus; | |
e8689e63 | 781 | } else { |
036f05fd | 782 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
783 | *mbus = &bd->dstbus; |
784 | *sbus = &bd->srcbus; | |
036f05fd | 785 | } else { |
542361f8 RKAL |
786 | *mbus = &bd->srcbus; |
787 | *sbus = &bd->dstbus; | |
e8689e63 LW |
788 | } |
789 | } | |
790 | } | |
791 | ||
792 | /* | |
94ae8522 | 793 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 794 | */ |
542361f8 RKAL |
795 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
796 | int num_llis, int len, u32 cctl) | |
e8689e63 | 797 | { |
542361f8 RKAL |
798 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
799 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
800 | |
801 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
802 | ||
30749cb4 | 803 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
804 | llis_va[num_llis].src = bd->srcbus.addr; |
805 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
806 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
807 | sizeof(struct pl08x_lli); | |
25c94f7f | 808 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
809 | |
810 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 811 | bd->srcbus.addr += len; |
e8689e63 | 812 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 813 | bd->dstbus.addr += len; |
e8689e63 | 814 | |
542361f8 | 815 | BUG_ON(bd->remainder < len); |
cace6585 | 816 | |
542361f8 | 817 | bd->remainder -= len; |
e8689e63 LW |
818 | } |
819 | ||
03af500f VK |
820 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
821 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 822 | { |
03af500f VK |
823 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
824 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
825 | (*total_bytes) += len; | |
e8689e63 LW |
826 | } |
827 | ||
828 | /* | |
829 | * This fills in the table of LLIs for the transfer descriptor | |
830 | * Note that we assume we never have to change the burst sizes | |
831 | * Return 0 for error | |
832 | */ | |
833 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
834 | struct pl08x_txd *txd) | |
835 | { | |
e8689e63 | 836 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 837 | struct pl08x_lli_build_data bd; |
e8689e63 | 838 | int num_llis = 0; |
03af500f | 839 | u32 cctl, early_bytes = 0; |
b7f69d9d | 840 | size_t max_bytes_per_lli, total_bytes; |
7cb72ad9 | 841 | struct pl08x_lli *llis_va; |
b7f69d9d | 842 | struct pl08x_sg *dsg; |
e8689e63 | 843 | |
3e27ee84 | 844 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
845 | if (!txd->llis_va) { |
846 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
847 | return 0; | |
848 | } | |
849 | ||
850 | pl08x->pool_ctr++; | |
851 | ||
542361f8 | 852 | bd.txd = txd; |
25c94f7f | 853 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 854 | cctl = txd->cctl; |
542361f8 | 855 | |
e8689e63 | 856 | /* Find maximum width of the source bus */ |
542361f8 | 857 | bd.srcbus.maxwidth = |
e8689e63 LW |
858 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
859 | PL080_CONTROL_SWIDTH_SHIFT); | |
860 | ||
861 | /* Find maximum width of the destination bus */ | |
542361f8 | 862 | bd.dstbus.maxwidth = |
e8689e63 LW |
863 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
864 | PL080_CONTROL_DWIDTH_SHIFT); | |
865 | ||
b7f69d9d VK |
866 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
867 | total_bytes = 0; | |
868 | cctl = txd->cctl; | |
e8689e63 | 869 | |
b7f69d9d VK |
870 | bd.srcbus.addr = dsg->src_addr; |
871 | bd.dstbus.addr = dsg->dst_addr; | |
872 | bd.remainder = dsg->len; | |
873 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
874 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 875 | |
b7f69d9d | 876 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 877 | |
b7f69d9d VK |
878 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
879 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
880 | bd.srcbus.buswidth, | |
881 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
882 | bd.dstbus.buswidth, | |
883 | bd.remainder); | |
884 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
885 | mbus == &bd.srcbus ? "src" : "dst", | |
886 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 887 | |
b7f69d9d VK |
888 | /* |
889 | * Zero length is only allowed if all these requirements are | |
890 | * met: | |
891 | * - flow controller is peripheral. | |
892 | * - src.addr is aligned to src.width | |
893 | * - dst.addr is aligned to dst.width | |
894 | * | |
895 | * sg_len == 1 should be true, as there can be two cases here: | |
896 | * | |
897 | * - Memory addresses are contiguous and are not scattered. | |
898 | * Here, Only one sg will be passed by user driver, with | |
899 | * memory address and zero length. We pass this to controller | |
900 | * and after the transfer it will receive the last burst | |
901 | * request from peripheral and so transfer finishes. | |
902 | * | |
903 | * - Memory addresses are scattered and are not contiguous. | |
904 | * Here, Obviously as DMA controller doesn't know when a lli's | |
905 | * transfer gets over, it can't load next lli. So in this | |
906 | * case, there has to be an assumption that only one lli is | |
907 | * supported. Thus, we can't have scattered addresses. | |
908 | */ | |
909 | if (!bd.remainder) { | |
910 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
911 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
912 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 913 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
914 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
915 | __func__); | |
916 | return 0; | |
917 | } | |
0a235657 | 918 | |
b7f69d9d | 919 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 920 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
921 | dev_err(&pl08x->adev->dev, |
922 | "%s src & dst address must be aligned to src" | |
923 | " & dst width if peripheral is flow controller", | |
924 | __func__); | |
925 | return 0; | |
926 | } | |
03af500f | 927 | |
b7f69d9d VK |
928 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
929 | bd.dstbus.buswidth, 0); | |
930 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
931 | break; | |
932 | } | |
e8689e63 LW |
933 | |
934 | /* | |
b7f69d9d VK |
935 | * Send byte by byte for following cases |
936 | * - Less than a bus width available | |
937 | * - until master bus is aligned | |
e8689e63 | 938 | */ |
b7f69d9d VK |
939 | if (bd.remainder < mbus->buswidth) |
940 | early_bytes = bd.remainder; | |
941 | else if ((mbus->addr) % (mbus->buswidth)) { | |
942 | early_bytes = mbus->buswidth - (mbus->addr) % | |
943 | (mbus->buswidth); | |
944 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
945 | early_bytes = bd.remainder; | |
946 | } | |
e8689e63 | 947 | |
b7f69d9d VK |
948 | if (early_bytes) { |
949 | dev_vdbg(&pl08x->adev->dev, | |
950 | "%s byte width LLIs (remain 0x%08x)\n", | |
951 | __func__, bd.remainder); | |
952 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
953 | &total_bytes); | |
e8689e63 LW |
954 | } |
955 | ||
b7f69d9d VK |
956 | if (bd.remainder) { |
957 | /* | |
958 | * Master now aligned | |
959 | * - if slave is not then we must set its width down | |
960 | */ | |
961 | if (sbus->addr % sbus->buswidth) { | |
962 | dev_dbg(&pl08x->adev->dev, | |
963 | "%s set down bus width to one byte\n", | |
964 | __func__); | |
fa6a940b | 965 | |
b7f69d9d VK |
966 | sbus->buswidth = 1; |
967 | } | |
e8689e63 LW |
968 | |
969 | /* | |
b7f69d9d VK |
970 | * Bytes transferred = tsize * src width, not |
971 | * MIN(buswidths) | |
e8689e63 | 972 | */ |
b7f69d9d VK |
973 | max_bytes_per_lli = bd.srcbus.buswidth * |
974 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
975 | dev_vdbg(&pl08x->adev->dev, | |
976 | "%s max bytes per lli = %zu\n", | |
977 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
978 | |
979 | /* | |
b7f69d9d VK |
980 | * Make largest possible LLIs until less than one bus |
981 | * width left | |
e8689e63 | 982 | */ |
b7f69d9d VK |
983 | while (bd.remainder > (mbus->buswidth - 1)) { |
984 | size_t lli_len, tsize, width; | |
e8689e63 | 985 | |
b7f69d9d VK |
986 | /* |
987 | * If enough left try to send max possible, | |
988 | * otherwise try to send the remainder | |
989 | */ | |
990 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 991 | |
b7f69d9d VK |
992 | /* |
993 | * Check against maximum bus alignment: | |
994 | * Calculate actual transfer size in relation to | |
995 | * bus width an get a maximum remainder of the | |
996 | * highest bus width - 1 | |
997 | */ | |
998 | width = max(mbus->buswidth, sbus->buswidth); | |
999 | lli_len = (lli_len / width) * width; | |
1000 | tsize = lli_len / bd.srcbus.buswidth; | |
1001 | ||
1002 | dev_vdbg(&pl08x->adev->dev, | |
1003 | "%s fill lli with single lli chunk of " | |
1004 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1005 | __func__, lli_len, bd.remainder); | |
1006 | ||
1007 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 1008 | bd.dstbus.buswidth, tsize); |
b7f69d9d VK |
1009 | pl08x_fill_lli_for_desc(&bd, num_llis++, |
1010 | lli_len, cctl); | |
1011 | total_bytes += lli_len; | |
1012 | } | |
e8689e63 | 1013 | |
b7f69d9d VK |
1014 | /* |
1015 | * Send any odd bytes | |
1016 | */ | |
1017 | if (bd.remainder) { | |
1018 | dev_vdbg(&pl08x->adev->dev, | |
1019 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1020 | __func__, bd.remainder); | |
1021 | prep_byte_width_lli(&bd, &cctl, bd.remainder, | |
1022 | num_llis++, &total_bytes); | |
1023 | } | |
e8689e63 | 1024 | } |
16a2e7d3 | 1025 | |
b7f69d9d VK |
1026 | if (total_bytes != dsg->len) { |
1027 | dev_err(&pl08x->adev->dev, | |
1028 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1029 | __func__, total_bytes, dsg->len); | |
1030 | return 0; | |
1031 | } | |
e8689e63 | 1032 | |
b7f69d9d VK |
1033 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1034 | dev_err(&pl08x->adev->dev, | |
1035 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
1036 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
1037 | return 0; | |
1038 | } | |
e8689e63 | 1039 | } |
b58b6b5b RKAL |
1040 | |
1041 | llis_va = txd->llis_va; | |
94ae8522 | 1042 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 1043 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 1044 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 1045 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1046 | |
e8689e63 LW |
1047 | #ifdef VERBOSE_DEBUG |
1048 | { | |
1049 | int i; | |
1050 | ||
fc74eb79 RKAL |
1051 | dev_vdbg(&pl08x->adev->dev, |
1052 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
1053 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
1054 | for (i = 0; i < num_llis; i++) { |
1055 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
1056 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
1057 | i, &llis_va[i], llis_va[i].src, | |
1058 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
1059 | ); |
1060 | } | |
1061 | } | |
1062 | #endif | |
1063 | ||
1064 | return num_llis; | |
1065 | } | |
1066 | ||
1067 | /* You should call this with the struct pl08x lock held */ | |
1068 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
1069 | struct pl08x_txd *txd) | |
1070 | { | |
b7f69d9d VK |
1071 | struct pl08x_sg *dsg, *_dsg; |
1072 | ||
e8689e63 | 1073 | /* Free the LLI */ |
c1205646 VK |
1074 | if (txd->llis_va) |
1075 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 LW |
1076 | |
1077 | pl08x->pool_ctr--; | |
1078 | ||
b7f69d9d VK |
1079 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1080 | list_del(&dsg->node); | |
1081 | kfree(dsg); | |
1082 | } | |
1083 | ||
e8689e63 LW |
1084 | kfree(txd); |
1085 | } | |
1086 | ||
1087 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
1088 | struct pl08x_dma_chan *plchan) | |
1089 | { | |
ea160561 RK |
1090 | LIST_HEAD(head); |
1091 | struct pl08x_txd *txd; | |
e8689e63 | 1092 | |
879f127b | 1093 | vchan_get_all_descriptors(&plchan->vc, &head); |
ea160561 RK |
1094 | |
1095 | while (!list_empty(&head)) { | |
879f127b | 1096 | txd = list_first_entry(&head, struct pl08x_txd, vd.node); |
ea160561 | 1097 | pl08x_release_mux(plchan); |
879f127b | 1098 | list_del(&txd->vd.node); |
ea160561 | 1099 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1100 | } |
1101 | } | |
1102 | ||
1103 | /* | |
1104 | * The DMA ENGINE API | |
1105 | */ | |
1106 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1107 | { | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1112 | { | |
1113 | } | |
1114 | ||
e8689e63 LW |
1115 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1116 | struct dma_chan *chan, unsigned long flags) | |
1117 | { | |
1118 | struct dma_async_tx_descriptor *retval = NULL; | |
1119 | ||
1120 | return retval; | |
1121 | } | |
1122 | ||
1123 | /* | |
94ae8522 RKAL |
1124 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1125 | * If slaves are relying on interrupts to signal completion this function | |
1126 | * must not be called with interrupts disabled. | |
e8689e63 | 1127 | */ |
3e27ee84 VK |
1128 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1129 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1130 | { |
1131 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 | 1132 | enum dma_status ret; |
e8689e63 | 1133 | |
96a2af41 RKAL |
1134 | ret = dma_cookie_status(chan, cookie, txstate); |
1135 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1136 | return ret; |
e8689e63 | 1137 | |
e8689e63 LW |
1138 | /* |
1139 | * This cookie not complete yet | |
96a2af41 | 1140 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1141 | */ |
96a2af41 | 1142 | dma_set_residue(txstate, pl08x_getbytes_chan(plchan)); |
e8689e63 LW |
1143 | |
1144 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1145 | return DMA_PAUSED; | |
1146 | ||
1147 | /* Whether waiting or running, we're in progress */ | |
1148 | return DMA_IN_PROGRESS; | |
1149 | } | |
1150 | ||
1151 | /* PrimeCell DMA extension */ | |
1152 | struct burst_table { | |
760596c6 | 1153 | u32 burstwords; |
e8689e63 LW |
1154 | u32 reg; |
1155 | }; | |
1156 | ||
1157 | static const struct burst_table burst_sizes[] = { | |
1158 | { | |
1159 | .burstwords = 256, | |
760596c6 | 1160 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1161 | }, |
1162 | { | |
1163 | .burstwords = 128, | |
760596c6 | 1164 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1165 | }, |
1166 | { | |
1167 | .burstwords = 64, | |
760596c6 | 1168 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1169 | }, |
1170 | { | |
1171 | .burstwords = 32, | |
760596c6 | 1172 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1173 | }, |
1174 | { | |
1175 | .burstwords = 16, | |
760596c6 | 1176 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1177 | }, |
1178 | { | |
1179 | .burstwords = 8, | |
760596c6 | 1180 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1181 | }, |
1182 | { | |
1183 | .burstwords = 4, | |
760596c6 | 1184 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1185 | }, |
1186 | { | |
760596c6 RKAL |
1187 | .burstwords = 0, |
1188 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1189 | }, |
1190 | }; | |
1191 | ||
121c8476 RKAL |
1192 | /* |
1193 | * Given the source and destination available bus masks, select which | |
1194 | * will be routed to each port. We try to have source and destination | |
1195 | * on separate ports, but always respect the allowable settings. | |
1196 | */ | |
1197 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1198 | { | |
1199 | u32 cctl = 0; | |
1200 | ||
1201 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1202 | cctl |= PL080_CONTROL_DST_AHB2; | |
1203 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1204 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1205 | ||
1206 | return cctl; | |
1207 | } | |
1208 | ||
f14c426c RKAL |
1209 | static u32 pl08x_cctl(u32 cctl) |
1210 | { | |
1211 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1212 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1213 | PL080_CONTROL_PROT_MASK); | |
1214 | ||
1215 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1216 | return cctl | PL080_CONTROL_PROT_SYS; | |
1217 | } | |
1218 | ||
aa88cdaa RKAL |
1219 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1220 | { | |
1221 | switch (width) { | |
1222 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1223 | return PL080_WIDTH_8BIT; | |
1224 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1225 | return PL080_WIDTH_16BIT; | |
1226 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1227 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1228 | default: |
1229 | return ~0; | |
aa88cdaa | 1230 | } |
aa88cdaa RKAL |
1231 | } |
1232 | ||
760596c6 RKAL |
1233 | static u32 pl08x_burst(u32 maxburst) |
1234 | { | |
1235 | int i; | |
1236 | ||
1237 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1238 | if (burst_sizes[i].burstwords <= maxburst) | |
1239 | break; | |
1240 | ||
1241 | return burst_sizes[i].reg; | |
1242 | } | |
1243 | ||
9862ba17 RK |
1244 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1245 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1246 | { | |
1247 | u32 width, burst, cctl = 0; | |
1248 | ||
1249 | width = pl08x_width(addr_width); | |
1250 | if (width == ~0) | |
1251 | return ~0; | |
1252 | ||
1253 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1254 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1255 | ||
1256 | /* | |
1257 | * If this channel will only request single transfers, set this | |
1258 | * down to ONE element. Also select one element if no maxburst | |
1259 | * is specified. | |
1260 | */ | |
1261 | if (plchan->cd->single) | |
1262 | maxburst = 1; | |
1263 | ||
1264 | burst = pl08x_burst(maxburst); | |
1265 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1266 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1267 | ||
1268 | return pl08x_cctl(cctl); | |
1269 | } | |
1270 | ||
f0fd9446 RKAL |
1271 | static int dma_set_runtime_config(struct dma_chan *chan, |
1272 | struct dma_slave_config *config) | |
e8689e63 LW |
1273 | { |
1274 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
b7f75865 RKAL |
1275 | |
1276 | if (!plchan->slave) | |
1277 | return -EINVAL; | |
e8689e63 | 1278 | |
dc8d5f8d RK |
1279 | /* Reject definitely invalid configurations */ |
1280 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1281 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1282 | return -EINVAL; |
e8689e63 | 1283 | |
ed91c13d RK |
1284 | plchan->cfg = *config; |
1285 | ||
f0fd9446 | 1286 | return 0; |
e8689e63 LW |
1287 | } |
1288 | ||
1289 | /* | |
1290 | * Slave transactions callback to the slave device to allow | |
1291 | * synchronization of slave DMA signals with the DMAC enable | |
1292 | */ | |
1293 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1294 | { | |
1295 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1296 | unsigned long flags; |
1297 | ||
083be28a | 1298 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1299 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1300 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1301 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1302 | } |
083be28a | 1303 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1304 | } |
1305 | ||
1306 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1307 | struct pl08x_txd *txd) | |
1308 | { | |
e8689e63 | 1309 | struct pl08x_driver_data *pl08x = plchan->host; |
a5a488db | 1310 | int num_llis; |
e8689e63 LW |
1311 | |
1312 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 | 1313 | if (!num_llis) { |
a5a488db RK |
1314 | unsigned long flags; |
1315 | ||
083be28a | 1316 | spin_lock_irqsave(&plchan->vc.lock, flags); |
57001a60 | 1317 | pl08x_free_txd(pl08x, txd); |
083be28a | 1318 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
a5a488db | 1319 | |
e8689e63 | 1320 | return -EINVAL; |
dafa7317 | 1321 | } |
e8689e63 LW |
1322 | return 0; |
1323 | } | |
1324 | ||
879f127b | 1325 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1326 | { |
b201c111 | 1327 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1328 | |
1329 | if (txd) { | |
b7f69d9d | 1330 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1331 | |
1332 | /* Always enable error and terminal interrupts */ | |
1333 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1334 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1335 | } |
1336 | return txd; | |
1337 | } | |
1338 | ||
e8689e63 LW |
1339 | /* |
1340 | * Initialize a descriptor to be used by memcpy submit | |
1341 | */ | |
1342 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1343 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1344 | size_t len, unsigned long flags) | |
1345 | { | |
1346 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1347 | struct pl08x_driver_data *pl08x = plchan->host; | |
1348 | struct pl08x_txd *txd; | |
b7f69d9d | 1349 | struct pl08x_sg *dsg; |
e8689e63 LW |
1350 | int ret; |
1351 | ||
879f127b | 1352 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1353 | if (!txd) { |
1354 | dev_err(&pl08x->adev->dev, | |
1355 | "%s no memory for descriptor\n", __func__); | |
1356 | return NULL; | |
1357 | } | |
1358 | ||
b7f69d9d VK |
1359 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1360 | if (!dsg) { | |
1361 | pl08x_free_txd(pl08x, txd); | |
1362 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1363 | __func__); | |
1364 | return NULL; | |
1365 | } | |
1366 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1367 | ||
b7f69d9d VK |
1368 | dsg->src_addr = src; |
1369 | dsg->dst_addr = dest; | |
1370 | dsg->len = len; | |
e8689e63 LW |
1371 | |
1372 | /* Set platform data for m2m */ | |
4983a04f | 1373 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1374 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1375 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1376 | |
e8689e63 | 1377 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1378 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1379 | |
c7da9a56 | 1380 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1381 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1382 | pl08x->mem_buses); | |
e8689e63 | 1383 | |
e8689e63 LW |
1384 | ret = pl08x_prep_channel_resources(plchan, txd); |
1385 | if (ret) | |
1386 | return NULL; | |
e8689e63 | 1387 | |
879f127b | 1388 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1389 | } |
1390 | ||
3e2a037c | 1391 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1392 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1393 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1394 | unsigned long flags, void *context) |
e8689e63 LW |
1395 | { |
1396 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1397 | struct pl08x_driver_data *pl08x = plchan->host; | |
1398 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1399 | struct pl08x_sg *dsg; |
1400 | struct scatterlist *sg; | |
dc8d5f8d | 1401 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1402 | dma_addr_t slave_addr; |
0a235657 | 1403 | int ret, tmp; |
409ec8db | 1404 | u8 src_buses, dst_buses; |
dc8d5f8d | 1405 | u32 maxburst, cctl; |
e8689e63 | 1406 | |
e8689e63 | 1407 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1408 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1409 | |
879f127b | 1410 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1411 | if (!txd) { |
1412 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1413 | return NULL; | |
1414 | } | |
1415 | ||
e8689e63 LW |
1416 | /* |
1417 | * Set up addresses, the PrimeCell configured address | |
1418 | * will take precedence since this may configure the | |
1419 | * channel target address dynamically at runtime. | |
1420 | */ | |
db8196df | 1421 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1422 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1423 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1424 | addr_width = plchan->cfg.dst_addr_width; |
1425 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1426 | src_buses = pl08x->mem_buses; |
1427 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1428 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1429 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1430 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1431 | addr_width = plchan->cfg.src_addr_width; |
1432 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1433 | src_buses = plchan->cd->periph_buses; |
1434 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1435 | } else { |
b7f69d9d | 1436 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1437 | dev_err(&pl08x->adev->dev, |
1438 | "%s direction unsupported\n", __func__); | |
1439 | return NULL; | |
1440 | } | |
e8689e63 | 1441 | |
dc8d5f8d | 1442 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1443 | if (cctl == ~0) { |
1444 | pl08x_free_txd(pl08x, txd); | |
1445 | dev_err(&pl08x->adev->dev, | |
1446 | "DMA slave configuration botched?\n"); | |
1447 | return NULL; | |
1448 | } | |
1449 | ||
409ec8db RK |
1450 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1451 | ||
95442b22 | 1452 | if (plchan->cfg.device_fc) |
db8196df | 1453 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1454 | PL080_FLOW_PER2MEM_PER; |
1455 | else | |
db8196df | 1456 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1457 | PL080_FLOW_PER2MEM; |
1458 | ||
1459 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1460 | ||
c48d4963 RK |
1461 | ret = pl08x_request_mux(plchan); |
1462 | if (ret < 0) { | |
1463 | pl08x_free_txd(pl08x, txd); | |
1464 | dev_dbg(&pl08x->adev->dev, | |
1465 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1466 | plchan->name); | |
1467 | return NULL; | |
1468 | } | |
1469 | ||
1470 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1471 | plchan->signal, plchan->name); | |
1472 | ||
1473 | /* Assign the flow control signal to this channel */ | |
1474 | if (direction == DMA_MEM_TO_DEV) | |
1475 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1476 | else | |
1477 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1478 | ||
b7f69d9d VK |
1479 | for_each_sg(sgl, sg, sg_len, tmp) { |
1480 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1481 | if (!dsg) { | |
c48d4963 | 1482 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1483 | pl08x_free_txd(pl08x, txd); |
1484 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1485 | __func__); | |
1486 | return NULL; | |
1487 | } | |
1488 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1489 | ||
1490 | dsg->len = sg_dma_len(sg); | |
db8196df | 1491 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1492 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1493 | dsg->dst_addr = slave_addr; |
1494 | } else { | |
1495 | dsg->src_addr = slave_addr; | |
cbb796cc | 1496 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1497 | } |
1498 | } | |
1499 | ||
e8689e63 LW |
1500 | ret = pl08x_prep_channel_resources(plchan, txd); |
1501 | if (ret) | |
1502 | return NULL; | |
e8689e63 | 1503 | |
879f127b | 1504 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1505 | } |
1506 | ||
1507 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1508 | unsigned long arg) | |
1509 | { | |
1510 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1511 | struct pl08x_driver_data *pl08x = plchan->host; | |
1512 | unsigned long flags; | |
1513 | int ret = 0; | |
1514 | ||
1515 | /* Controls applicable to inactive channels */ | |
1516 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1517 | return dma_set_runtime_config(chan, |
1518 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1519 | } |
1520 | ||
1521 | /* | |
1522 | * Anything succeeds on channels with no physical allocation and | |
1523 | * no queued transfers. | |
1524 | */ | |
083be28a | 1525 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1526 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1527 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1528 | return 0; |
1529 | } | |
1530 | ||
1531 | switch (cmd) { | |
1532 | case DMA_TERMINATE_ALL: | |
1533 | plchan->state = PL08X_CHAN_IDLE; | |
1534 | ||
1535 | if (plchan->phychan) { | |
e8689e63 LW |
1536 | /* |
1537 | * Mark physical channel as free and free any slave | |
1538 | * signal | |
1539 | */ | |
a5a488db | 1540 | pl08x_phy_free(plchan); |
e8689e63 | 1541 | } |
e8689e63 LW |
1542 | /* Dequeue jobs and free LLIs */ |
1543 | if (plchan->at) { | |
c48d4963 RK |
1544 | /* Killing this one off, release its mux */ |
1545 | pl08x_release_mux(plchan); | |
e8689e63 LW |
1546 | pl08x_free_txd(pl08x, plchan->at); |
1547 | plchan->at = NULL; | |
1548 | } | |
1549 | /* Dequeue jobs not yet fired as well */ | |
1550 | pl08x_free_txd_list(pl08x, plchan); | |
1551 | break; | |
1552 | case DMA_PAUSE: | |
1553 | pl08x_pause_phy_chan(plchan->phychan); | |
1554 | plchan->state = PL08X_CHAN_PAUSED; | |
1555 | break; | |
1556 | case DMA_RESUME: | |
1557 | pl08x_resume_phy_chan(plchan->phychan); | |
1558 | plchan->state = PL08X_CHAN_RUNNING; | |
1559 | break; | |
1560 | default: | |
1561 | /* Unknown command */ | |
1562 | ret = -ENXIO; | |
1563 | break; | |
1564 | } | |
1565 | ||
083be28a | 1566 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1567 | |
1568 | return ret; | |
1569 | } | |
1570 | ||
1571 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1572 | { | |
7703eac9 | 1573 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1574 | char *name = chan_id; |
1575 | ||
7703eac9 RKAL |
1576 | /* Reject channels for devices not bound to this driver */ |
1577 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1578 | return false; | |
1579 | ||
1580 | plchan = to_pl08x_chan(chan); | |
1581 | ||
e8689e63 LW |
1582 | /* Check that the channel is not taken! */ |
1583 | if (!strcmp(plchan->name, name)) | |
1584 | return true; | |
1585 | ||
1586 | return false; | |
1587 | } | |
1588 | ||
1589 | /* | |
1590 | * Just check that the device is there and active | |
94ae8522 RKAL |
1591 | * TODO: turn this bit on/off depending on the number of physical channels |
1592 | * actually used, if it is zero... well shut it off. That will save some | |
1593 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1594 | */ |
1595 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1596 | { | |
affa115e LW |
1597 | /* The Nomadik variant does not have the config register */ |
1598 | if (pl08x->vd->nomadik) | |
1599 | return; | |
48a59ef3 | 1600 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1601 | } |
1602 | ||
3d992e1a RKAL |
1603 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1604 | { | |
01d8dc64 | 1605 | struct device *dev = txd->vd.tx.chan->device->dev; |
b7f69d9d | 1606 | struct pl08x_sg *dsg; |
3d992e1a | 1607 | |
01d8dc64 RK |
1608 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { |
1609 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
b7f69d9d VK |
1610 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1611 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1612 | DMA_TO_DEVICE); | |
1613 | else { | |
1614 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1615 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1616 | DMA_TO_DEVICE); | |
1617 | } | |
3d992e1a | 1618 | } |
01d8dc64 RK |
1619 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { |
1620 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
b7f69d9d VK |
1621 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1622 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1623 | DMA_FROM_DEVICE); | |
3d992e1a | 1624 | else |
b7f69d9d VK |
1625 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1626 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1627 | DMA_FROM_DEVICE); | |
3d992e1a RKAL |
1628 | } |
1629 | } | |
1630 | ||
e8689e63 LW |
1631 | static void pl08x_tasklet(unsigned long data) |
1632 | { | |
1633 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1634 | struct pl08x_driver_data *pl08x = plchan->host; |
bf072af4 | 1635 | unsigned long flags; |
a936e793 | 1636 | LIST_HEAD(head); |
e8689e63 | 1637 | |
083be28a | 1638 | spin_lock_irqsave(&plchan->vc.lock, flags); |
a936e793 | 1639 | list_splice_tail_init(&plchan->done_list, &head); |
083be28a | 1640 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
858c21c0 | 1641 | |
a936e793 RK |
1642 | while (!list_empty(&head)) { |
1643 | struct pl08x_txd *txd = list_first_entry(&head, | |
1644 | struct pl08x_txd, node); | |
01d8dc64 RK |
1645 | dma_async_tx_callback callback = txd->vd.tx.callback; |
1646 | void *callback_param = txd->vd.tx.callback_param; | |
3d992e1a | 1647 | |
a936e793 RK |
1648 | list_del(&txd->node); |
1649 | ||
3d992e1a RKAL |
1650 | /* Don't try to unmap buffers on slave channels */ |
1651 | if (!plchan->slave) | |
1652 | pl08x_unmap_buffers(txd); | |
1653 | ||
1654 | /* Free the descriptor */ | |
083be28a | 1655 | spin_lock_irqsave(&plchan->vc.lock, flags); |
3d992e1a | 1656 | pl08x_free_txd(pl08x, txd); |
083be28a | 1657 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
3d992e1a RKAL |
1658 | |
1659 | /* Callback to signal completion */ | |
1660 | if (callback) | |
1661 | callback(callback_param); | |
1662 | } | |
e8689e63 LW |
1663 | } |
1664 | ||
1665 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1666 | { | |
1667 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1668 | u32 mask = 0, err, tc, i; |
1669 | ||
1670 | /* check & clear - ERR & TC interrupts */ | |
1671 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1672 | if (err) { | |
1673 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1674 | __func__, err); | |
1675 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1676 | } |
d29bf019 | 1677 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1678 | if (tc) |
1679 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1680 | ||
1681 | if (!err && !tc) | |
1682 | return IRQ_NONE; | |
1683 | ||
e8689e63 | 1684 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1685 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1686 | /* Locate physical channel */ |
1687 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1688 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1689 | struct pl08x_txd *tx; |
e8689e63 | 1690 | |
28da2836 VK |
1691 | if (!plchan) { |
1692 | dev_err(&pl08x->adev->dev, | |
1693 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1694 | __func__, i); | |
1695 | continue; | |
1696 | } | |
1697 | ||
083be28a | 1698 | spin_lock(&plchan->vc.lock); |
a936e793 RK |
1699 | tx = plchan->at; |
1700 | if (tx) { | |
1701 | plchan->at = NULL; | |
c48d4963 RK |
1702 | /* |
1703 | * This descriptor is done, release its mux | |
1704 | * reservation. | |
1705 | */ | |
1706 | pl08x_release_mux(plchan); | |
01d8dc64 | 1707 | dma_cookie_complete(&tx->vd.tx); |
a936e793 | 1708 | list_add_tail(&tx->node, &plchan->done_list); |
c33b644c | 1709 | |
a5a488db RK |
1710 | /* |
1711 | * And start the next descriptor (if any), | |
1712 | * otherwise free this channel. | |
1713 | */ | |
879f127b | 1714 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1715 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1716 | else |
1717 | pl08x_phy_free(plchan); | |
a936e793 | 1718 | } |
083be28a | 1719 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1720 | |
e8689e63 LW |
1721 | /* Schedule tasklet on this channel */ |
1722 | tasklet_schedule(&plchan->tasklet); | |
e8689e63 LW |
1723 | mask |= (1 << i); |
1724 | } | |
1725 | } | |
e8689e63 LW |
1726 | |
1727 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1728 | } | |
1729 | ||
121c8476 RKAL |
1730 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1731 | { | |
121c8476 RKAL |
1732 | chan->slave = true; |
1733 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1734 | chan->cfg.src_addr = chan->cd->addr; |
1735 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1736 | } |
1737 | ||
e8689e63 LW |
1738 | /* |
1739 | * Initialise the DMAC memcpy/slave channels. | |
1740 | * Make a local wrapper to hold required data | |
1741 | */ | |
1742 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1743 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1744 | { |
1745 | struct pl08x_dma_chan *chan; | |
1746 | int i; | |
1747 | ||
1748 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1749 | |
e8689e63 LW |
1750 | /* |
1751 | * Register as many many memcpy as we have physical channels, | |
1752 | * we won't always be able to use all but the code will have | |
1753 | * to cope with that situation. | |
1754 | */ | |
1755 | for (i = 0; i < channels; i++) { | |
b201c111 | 1756 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1757 | if (!chan) { |
1758 | dev_err(&pl08x->adev->dev, | |
1759 | "%s no memory for channel\n", __func__); | |
1760 | return -ENOMEM; | |
1761 | } | |
1762 | ||
1763 | chan->host = pl08x; | |
1764 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1765 | chan->signal = -1; |
e8689e63 LW |
1766 | |
1767 | if (slave) { | |
e8689e63 | 1768 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1769 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1770 | } else { |
1771 | chan->cd = &pl08x->pd->memcpy_channel; | |
1772 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1773 | if (!chan->name) { | |
1774 | kfree(chan); | |
1775 | return -ENOMEM; | |
1776 | } | |
1777 | } | |
175a5e61 | 1778 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1779 | "initialize virtual channel \"%s\"\n", |
1780 | chan->name); | |
1781 | ||
a936e793 | 1782 | INIT_LIST_HEAD(&chan->done_list); |
e8689e63 LW |
1783 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1784 | (unsigned long) chan); | |
1785 | ||
083be28a | 1786 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1787 | } |
1788 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1789 | i, slave ? "slave" : "memcpy"); | |
1790 | return i; | |
1791 | } | |
1792 | ||
1793 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1794 | { | |
1795 | struct pl08x_dma_chan *chan = NULL; | |
1796 | struct pl08x_dma_chan *next; | |
1797 | ||
1798 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1799 | next, &dmadev->channels, vc.chan.device_node) { |
1800 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1801 | kfree(chan); |
1802 | } | |
1803 | } | |
1804 | ||
1805 | #ifdef CONFIG_DEBUG_FS | |
1806 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1807 | { | |
1808 | switch (state) { | |
1809 | case PL08X_CHAN_IDLE: | |
1810 | return "idle"; | |
1811 | case PL08X_CHAN_RUNNING: | |
1812 | return "running"; | |
1813 | case PL08X_CHAN_PAUSED: | |
1814 | return "paused"; | |
1815 | case PL08X_CHAN_WAITING: | |
1816 | return "waiting"; | |
1817 | default: | |
1818 | break; | |
1819 | } | |
1820 | return "UNKNOWN STATE"; | |
1821 | } | |
1822 | ||
1823 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1824 | { | |
1825 | struct pl08x_driver_data *pl08x = s->private; | |
1826 | struct pl08x_dma_chan *chan; | |
1827 | struct pl08x_phy_chan *ch; | |
1828 | unsigned long flags; | |
1829 | int i; | |
1830 | ||
1831 | seq_printf(s, "PL08x physical channels:\n"); | |
1832 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1833 | seq_printf(s, "--------\t-----\n"); | |
1834 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1835 | struct pl08x_dma_chan *virt_chan; | |
1836 | ||
1837 | ch = &pl08x->phy_chans[i]; | |
1838 | ||
1839 | spin_lock_irqsave(&ch->lock, flags); | |
1840 | virt_chan = ch->serving; | |
1841 | ||
affa115e LW |
1842 | seq_printf(s, "%d\t\t%s%s\n", |
1843 | ch->id, | |
1844 | virt_chan ? virt_chan->name : "(none)", | |
1845 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1846 | |
1847 | spin_unlock_irqrestore(&ch->lock, flags); | |
1848 | } | |
1849 | ||
1850 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1851 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1852 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1853 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1854 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1855 | pl08x_state_str(chan->state)); |
1856 | } | |
1857 | ||
1858 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1859 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1860 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1861 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1862 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1863 | pl08x_state_str(chan->state)); |
1864 | } | |
1865 | ||
1866 | return 0; | |
1867 | } | |
1868 | ||
1869 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1870 | { | |
1871 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1872 | } | |
1873 | ||
1874 | static const struct file_operations pl08x_debugfs_operations = { | |
1875 | .open = pl08x_debugfs_open, | |
1876 | .read = seq_read, | |
1877 | .llseek = seq_lseek, | |
1878 | .release = single_release, | |
1879 | }; | |
1880 | ||
1881 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1882 | { | |
1883 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1884 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1885 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1886 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1887 | } |
1888 | ||
1889 | #else | |
1890 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1891 | { | |
1892 | } | |
1893 | #endif | |
1894 | ||
aa25afad | 1895 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1896 | { |
1897 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1898 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1899 | int ret = 0; |
1900 | int i; | |
1901 | ||
1902 | ret = amba_request_regions(adev, NULL); | |
1903 | if (ret) | |
1904 | return ret; | |
1905 | ||
1906 | /* Create the driver state holder */ | |
b201c111 | 1907 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1908 | if (!pl08x) { |
1909 | ret = -ENOMEM; | |
1910 | goto out_no_pl08x; | |
1911 | } | |
1912 | ||
1913 | /* Initialize memcpy engine */ | |
1914 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1915 | pl08x->memcpy.dev = &adev->dev; | |
1916 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1917 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1918 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1919 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1920 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1921 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1922 | pl08x->memcpy.device_control = pl08x_control; | |
1923 | ||
1924 | /* Initialize slave engine */ | |
1925 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1926 | pl08x->slave.dev = &adev->dev; | |
1927 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1928 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1929 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1930 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1931 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1932 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1933 | pl08x->slave.device_control = pl08x_control; | |
1934 | ||
1935 | /* Get the platform data */ | |
1936 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1937 | if (!pl08x->pd) { | |
1938 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1939 | goto out_no_platdata; | |
1940 | } | |
1941 | ||
1942 | /* Assign useful pointers to the driver state */ | |
1943 | pl08x->adev = adev; | |
1944 | pl08x->vd = vd; | |
1945 | ||
30749cb4 RKAL |
1946 | /* By default, AHB1 only. If dualmaster, from platform */ |
1947 | pl08x->lli_buses = PL08X_AHB1; | |
1948 | pl08x->mem_buses = PL08X_AHB1; | |
1949 | if (pl08x->vd->dualmaster) { | |
1950 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1951 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1952 | } | |
1953 | ||
e8689e63 LW |
1954 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1955 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1956 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1957 | if (!pl08x->pool) { | |
1958 | ret = -ENOMEM; | |
1959 | goto out_no_lli_pool; | |
1960 | } | |
1961 | ||
e8689e63 LW |
1962 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
1963 | if (!pl08x->base) { | |
1964 | ret = -ENOMEM; | |
1965 | goto out_no_ioremap; | |
1966 | } | |
1967 | ||
1968 | /* Turn on the PL08x */ | |
1969 | pl08x_ensure_on(pl08x); | |
1970 | ||
94ae8522 | 1971 | /* Attach the interrupt handler */ |
e8689e63 LW |
1972 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1973 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1974 | ||
1975 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1976 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1977 | if (ret) { |
1978 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1979 | __func__, adev->irq[0]); | |
1980 | goto out_no_irq; | |
1981 | } | |
1982 | ||
1983 | /* Initialize physical channels */ | |
affa115e | 1984 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1985 | GFP_KERNEL); |
1986 | if (!pl08x->phy_chans) { | |
1987 | dev_err(&adev->dev, "%s failed to allocate " | |
1988 | "physical channel holders\n", | |
1989 | __func__); | |
1990 | goto out_no_phychans; | |
1991 | } | |
1992 | ||
1993 | for (i = 0; i < vd->channels; i++) { | |
1994 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1995 | ||
1996 | ch->id = i; | |
1997 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1998 | spin_lock_init(&ch->lock); | |
affa115e LW |
1999 | |
2000 | /* | |
2001 | * Nomadik variants can have channels that are locked | |
2002 | * down for the secure world only. Lock up these channels | |
2003 | * by perpetually serving a dummy virtual channel. | |
2004 | */ | |
2005 | if (vd->nomadik) { | |
2006 | u32 val; | |
2007 | ||
2008 | val = readl(ch->base + PL080_CH_CONFIG); | |
2009 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { | |
2010 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2011 | ch->locked = true; | |
2012 | } | |
2013 | } | |
2014 | ||
175a5e61 VK |
2015 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2016 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2017 | } |
2018 | ||
2019 | /* Register as many memcpy channels as there are physical channels */ | |
2020 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2021 | pl08x->vd->channels, false); | |
2022 | if (ret <= 0) { | |
2023 | dev_warn(&pl08x->adev->dev, | |
2024 | "%s failed to enumerate memcpy channels - %d\n", | |
2025 | __func__, ret); | |
2026 | goto out_no_memcpy; | |
2027 | } | |
2028 | pl08x->memcpy.chancnt = ret; | |
2029 | ||
2030 | /* Register slave channels */ | |
2031 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2032 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2033 | if (ret <= 0) { |
2034 | dev_warn(&pl08x->adev->dev, | |
2035 | "%s failed to enumerate slave channels - %d\n", | |
2036 | __func__, ret); | |
2037 | goto out_no_slave; | |
2038 | } | |
2039 | pl08x->slave.chancnt = ret; | |
2040 | ||
2041 | ret = dma_async_device_register(&pl08x->memcpy); | |
2042 | if (ret) { | |
2043 | dev_warn(&pl08x->adev->dev, | |
2044 | "%s failed to register memcpy as an async device - %d\n", | |
2045 | __func__, ret); | |
2046 | goto out_no_memcpy_reg; | |
2047 | } | |
2048 | ||
2049 | ret = dma_async_device_register(&pl08x->slave); | |
2050 | if (ret) { | |
2051 | dev_warn(&pl08x->adev->dev, | |
2052 | "%s failed to register slave as an async device - %d\n", | |
2053 | __func__, ret); | |
2054 | goto out_no_slave_reg; | |
2055 | } | |
2056 | ||
2057 | amba_set_drvdata(adev, pl08x); | |
2058 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2059 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2060 | amba_part(adev), amba_rev(adev), | |
2061 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b | 2062 | |
e8689e63 LW |
2063 | return 0; |
2064 | ||
2065 | out_no_slave_reg: | |
2066 | dma_async_device_unregister(&pl08x->memcpy); | |
2067 | out_no_memcpy_reg: | |
2068 | pl08x_free_virtual_channels(&pl08x->slave); | |
2069 | out_no_slave: | |
2070 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2071 | out_no_memcpy: | |
2072 | kfree(pl08x->phy_chans); | |
2073 | out_no_phychans: | |
2074 | free_irq(adev->irq[0], pl08x); | |
2075 | out_no_irq: | |
2076 | iounmap(pl08x->base); | |
2077 | out_no_ioremap: | |
2078 | dma_pool_destroy(pl08x->pool); | |
2079 | out_no_lli_pool: | |
2080 | out_no_platdata: | |
2081 | kfree(pl08x); | |
2082 | out_no_pl08x: | |
2083 | amba_release_regions(adev); | |
2084 | return ret; | |
2085 | } | |
2086 | ||
2087 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2088 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2089 | .channels = 8, |
2090 | .dualmaster = true, | |
2091 | }; | |
2092 | ||
affa115e LW |
2093 | static struct vendor_data vendor_nomadik = { |
2094 | .channels = 8, | |
2095 | .dualmaster = true, | |
2096 | .nomadik = true, | |
2097 | }; | |
2098 | ||
e8689e63 | 2099 | static struct vendor_data vendor_pl081 = { |
e8689e63 LW |
2100 | .channels = 2, |
2101 | .dualmaster = false, | |
2102 | }; | |
2103 | ||
2104 | static struct amba_id pl08x_ids[] = { | |
2105 | /* PL080 */ | |
2106 | { | |
2107 | .id = 0x00041080, | |
2108 | .mask = 0x000fffff, | |
2109 | .data = &vendor_pl080, | |
2110 | }, | |
2111 | /* PL081 */ | |
2112 | { | |
2113 | .id = 0x00041081, | |
2114 | .mask = 0x000fffff, | |
2115 | .data = &vendor_pl081, | |
2116 | }, | |
2117 | /* Nomadik 8815 PL080 variant */ | |
2118 | { | |
affa115e | 2119 | .id = 0x00280080, |
e8689e63 | 2120 | .mask = 0x00ffffff, |
affa115e | 2121 | .data = &vendor_nomadik, |
e8689e63 LW |
2122 | }, |
2123 | { 0, 0 }, | |
2124 | }; | |
2125 | ||
037566df DM |
2126 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2127 | ||
e8689e63 LW |
2128 | static struct amba_driver pl08x_amba_driver = { |
2129 | .drv.name = DRIVER_NAME, | |
2130 | .id_table = pl08x_ids, | |
2131 | .probe = pl08x_probe, | |
2132 | }; | |
2133 | ||
2134 | static int __init pl08x_init(void) | |
2135 | { | |
2136 | int retval; | |
2137 | retval = amba_driver_register(&pl08x_amba_driver); | |
2138 | if (retval) | |
2139 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2140 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2141 | retval); |
2142 | return retval; | |
2143 | } | |
2144 | subsys_initcall(pl08x_init); |