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ARM: PL08x: consolidate common txd initialization
[deliverable/linux.git] / drivers / dma / amba-pl08x.c
CommitLineData
e8689e63
LW		 1/*
2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
4 *
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 *
e8b5e11d 22 * The full GNU General Public License is in this distribution in the
e8689e63
LW		 23 * file called COPYING.
24 *
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
27 *
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
29 * any channel.
30 *
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
36 *
37 * The PL080 has a dual bus master, PL081 has a single master.
38 *
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
41 * Until no data left
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
44 * Clear burst request
45 * Raise terminal count interrupt
46 *
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
50 *
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
53 *
54 * ASSUMES default (little) endianness for DMA transfers
55 *
9dc2c200
RKAL		 56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
62 * are ignored.
63 *
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
68 *
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
e8689e63
LW		 73 *
74 * Global TODO:
75 * - Break out common code from arch/arm/mach-s3c64xx and share
76 */
77#include <linux/device.h>
78#include <linux/init.h>
79#include <linux/module.h>
e8689e63
LW		 80#include <linux/interrupt.h>
81#include <linux/slab.h>
82#include <linux/dmapool.h>
e8689e63 83#include <linux/dmaengine.h>
730404ac 84#include <linux/amba/bus.h>
e8689e63
LW		 85#include <linux/amba/pl08x.h>
86#include <linux/debugfs.h>
87#include <linux/seq_file.h>
88
89#include <asm/hardware/pl080.h>
e8689e63
LW		 90
91#define DRIVER_NAME "pl08xdmac"
92
93/**
94 * struct vendor_data - vendor-specific config parameters
e8b5e11d 95 * for PL08x derivatives
e8689e63
LW		 96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
98 * or not.
99 */
100struct vendor_data {
e8689e63
LW		 101 u8 channels;
102 bool dualmaster;
103};
104
105/*
106 * PL08X private data structures
e8b5e11d
RKAL		 107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl.
e8689e63 109 */
7cb72ad9 110struct pl08x_lli {
e8689e63
LW		 111 dma_addr_t src;
112 dma_addr_t dst;
113 dma_addr_t next;
114 u32 cctl;
115};
116
117/**
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lock: a spinlock for this struct
129 */
130struct pl08x_driver_data {
131 struct dma_device slave;
132 struct dma_device memcpy;
133 void __iomem *base;
134 struct amba_device *adev;
f96ca9ec 135 const struct vendor_data *vd;
e8689e63
LW		 136 struct pl08x_platform_data *pd;
137 struct pl08x_phy_chan *phy_chans;
138 struct dma_pool *pool;
139 int pool_ctr;
140 spinlock_t lock;
141};
142
143/*
144 * PL08X specific defines
145 */
146
147/*
148 * Memory boundaries: the manual for PL08x says that the controller
149 * cannot read past a 1KiB boundary, so these defines are used to
150 * create transfer LLIs that do not cross such boundaries.
151 */
152#define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
153#define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
154
155/* Minimum period between work queue runs */
156#define PL08X_WQ_PERIODMIN 20
157
158/* Size (bytes) of each LLI buffer allocated for one transfer */
159# define PL08X_LLI_TSFR_SIZE 0x2000
160
e8b5e11d 161/* Maximum times we call dma_pool_alloc on this pool without freeing */
e8689e63 162#define PL08X_MAX_ALLOCS 0x40
7cb72ad9 163#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
e8689e63
LW		 164#define PL08X_ALIGN 8
165
166static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
167{
168 return container_of(chan, struct pl08x_dma_chan, chan);
169}
170
171/*
172 * Physical channel handling
173 */
174
175/* Whether a certain channel is busy or not */
176static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
177{
178 unsigned int val;
179
180 val = readl(ch->base + PL080_CH_CONFIG);
181 return val & PL080_CONFIG_ACTIVE;
182}
183
184/*
185 * Set the initial DMA register values i.e. those for the first LLI
e8b5e11d 186 * The next LLI pointer and the configuration interrupt bit have
e8689e63
LW		 187 * been set when the LLIs were constructed
188 */
189static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
190 struct pl08x_phy_chan *ch)
191{
192 /* Wait for channel inactive */
193 while (pl08x_phy_channel_busy(ch))
194 ;
195
196 dev_vdbg(&pl08x->adev->dev,
9c132992
RKAL		 197 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
198 "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
e8689e63
LW		 199 ch->id,
200 ch->csrc,
201 ch->cdst,
202 ch->cctl,
203 ch->clli,
204 ch->ccfg);
205
206 writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
207 writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
208 writel(ch->clli, ch->base + PL080_CH_LLI);
209 writel(ch->cctl, ch->base + PL080_CH_CONTROL);
210 writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
211}
212
213static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
214{
215 struct pl08x_channel_data *cd = plchan->cd;
216 struct pl08x_phy_chan *phychan = plchan->phychan;
217 struct pl08x_txd *txd = plchan->at;
218
219 /* Copy the basic control register calculated at transfer config */
220 phychan->csrc = txd->csrc;
221 phychan->cdst = txd->cdst;
222 phychan->clli = txd->clli;
223 phychan->cctl = txd->cctl;
224
225 /* Assign the signal to the proper control registers */
226 phychan->ccfg = cd->ccfg;
227 phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
228 phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
229 /* If it wasn't set from AMBA, ignore it */
230 if (txd->direction == DMA_TO_DEVICE)
231 /* Select signal as destination */
232 phychan->ccfg |=
233 (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
234 else if (txd->direction == DMA_FROM_DEVICE)
235 /* Select signal as source */
236 phychan->ccfg |=
237 (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
238 /* Always enable error interrupts */
239 phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
240 /* Always enable terminal interrupts */
241 phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
242}
243
244/*
245 * Enable the DMA channel
246 * Assumes all other configuration bits have been set
247 * as desired before this code is called
248 */
249static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
250 struct pl08x_phy_chan *ch)
251{
252 u32 val;
253
254 /*
255 * Do not access config register until channel shows as disabled
256 */
257 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
258 ;
259
260 /*
261 * Do not access config register until channel shows as inactive
262 */
263 val = readl(ch->base + PL080_CH_CONFIG);
264 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
265 val = readl(ch->base + PL080_CH_CONFIG);
266
267 writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
268}
269
270/*
271 * Overall DMAC remains enabled always.
272 *
273 * Disabling individual channels could lose data.
274 *
275 * Disable the peripheral DMA after disabling the DMAC
276 * in order to allow the DMAC FIFO to drain, and
277 * hence allow the channel to show inactive
278 *
279 */
280static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
281{
282 u32 val;
283
284 /* Set the HALT bit and wait for the FIFO to drain */
285 val = readl(ch->base + PL080_CH_CONFIG);
286 val |= PL080_CONFIG_HALT;
287 writel(val, ch->base + PL080_CH_CONFIG);
288
289 /* Wait for channel inactive */
290 while (pl08x_phy_channel_busy(ch))
291 ;
292}
293
294static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
295{
296 u32 val;
297
298 /* Clear the HALT bit */
299 val = readl(ch->base + PL080_CH_CONFIG);
300 val &= ~PL080_CONFIG_HALT;
301 writel(val, ch->base + PL080_CH_CONFIG);
302}
303
304
305/* Stops the channel */
306static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
307{
308 u32 val;
309
310 pl08x_pause_phy_chan(ch);
311
312 /* Disable channel */
313 val = readl(ch->base + PL080_CH_CONFIG);
314 val &= ~PL080_CONFIG_ENABLE;
315 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
316 val &= ~PL080_CONFIG_TC_IRQ_MASK;
317 writel(val, ch->base + PL080_CH_CONFIG);
318}
319
320static inline u32 get_bytes_in_cctl(u32 cctl)
321{
322 /* The source width defines the number of bytes */
323 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
324
325 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
326 case PL080_WIDTH_8BIT:
327 break;
328 case PL080_WIDTH_16BIT:
329 bytes *= 2;
330 break;
331 case PL080_WIDTH_32BIT:
332 bytes *= 4;
333 break;
334 }
335 return bytes;
336}
337
338/* The channel should be paused when calling this */
339static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
340{
341 struct pl08x_phy_chan *ch;
342 struct pl08x_txd *txdi = NULL;
343 struct pl08x_txd *txd;
344 unsigned long flags;
345 u32 bytes = 0;
346
347 spin_lock_irqsave(&plchan->lock, flags);
348
349 ch = plchan->phychan;
350 txd = plchan->at;
351
352 /*
353 * Next follow the LLIs to get the number of pending bytes in the
354 * currently active transaction.
355 */
356 if (ch && txd) {
7cb72ad9
RKAL		 357 struct pl08x_lli *llis_va = txd->llis_va;
358 struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
e8689e63
LW		 359 u32 clli = readl(ch->base + PL080_CH_LLI);
360
361 /* First get the bytes in the current active LLI */
362 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
363
364 if (clli) {
365 int i = 0;
366
367 /* Forward to the LLI pointed to by clli */
368 while ((clli != (u32) &(llis_bus[i])) &&
369 (i < MAX_NUM_TSFR_LLIS))
370 i++;
371
372 while (clli) {
373 bytes += get_bytes_in_cctl(llis_va[i].cctl);
374 /*
e8b5e11d 375 * A LLI pointer of 0 terminates the LLI list
e8689e63
LW		 376 */
377 clli = llis_va[i].next;
378 i++;
379 }
380 }
381 }
382
383 /* Sum up all queued transactions */
384 if (!list_empty(&plchan->desc_list)) {
385 list_for_each_entry(txdi, &plchan->desc_list, node) {
386 bytes += txdi->len;
387 }
388
389 }
390
391 spin_unlock_irqrestore(&plchan->lock, flags);
392
393 return bytes;
394}
395
396/*
397 * Allocate a physical channel for a virtual channel
398 */
399static struct pl08x_phy_chan *
400pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
401 struct pl08x_dma_chan *virt_chan)
402{
403 struct pl08x_phy_chan *ch = NULL;
404 unsigned long flags;
405 int i;
406
407 /*
408 * Try to locate a physical channel to be used for
409 * this transfer. If all are taken return NULL and
410 * the requester will have to cope by using some fallback
411 * PIO mode or retrying later.
412 */
413 for (i = 0; i < pl08x->vd->channels; i++) {
414 ch = &pl08x->phy_chans[i];
415
416 spin_lock_irqsave(&ch->lock, flags);
417
418 if (!ch->serving) {
419 ch->serving = virt_chan;
420 ch->signal = -1;
421 spin_unlock_irqrestore(&ch->lock, flags);
422 break;
423 }
424
425 spin_unlock_irqrestore(&ch->lock, flags);
426 }
427
428 if (i == pl08x->vd->channels) {
429 /* No physical channel available, cope with it */
430 return NULL;
431 }
432
433 return ch;
434}
435
436static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
437 struct pl08x_phy_chan *ch)
438{
439 unsigned long flags;
440
441 /* Stop the channel and clear its interrupts */
442 pl08x_stop_phy_chan(ch);
443 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
444 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
445
446 /* Mark it as free */
447 spin_lock_irqsave(&ch->lock, flags);
448 ch->serving = NULL;
449 spin_unlock_irqrestore(&ch->lock, flags);
450}
451
452/*
453 * LLI handling
454 */
455
456static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
457{
458 switch (coded) {
459 case PL080_WIDTH_8BIT:
460 return 1;
461 case PL080_WIDTH_16BIT:
462 return 2;
463 case PL080_WIDTH_32BIT:
464 return 4;
465 default:
466 break;
467 }
468 BUG();
469 return 0;
470}
471
472static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
473 u32 tsize)
474{
475 u32 retbits = cctl;
476
e8b5e11d 477 /* Remove all src, dst and transfer size bits */
e8689e63
LW		 478 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
479 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
480 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
481
482 /* Then set the bits according to the parameters */
483 switch (srcwidth) {
484 case 1:
485 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
486 break;
487 case 2:
488 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
489 break;
490 case 4:
491 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
492 break;
493 default:
494 BUG();
495 break;
496 }
497
498 switch (dstwidth) {
499 case 1:
500 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
501 break;
502 case 2:
503 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
504 break;
505 case 4:
506 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
507 break;
508 default:
509 BUG();
510 break;
511 }
512
513 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
514 return retbits;
515}
516
517/*
518 * Autoselect a master bus to use for the transfer
519 * this prefers the destination bus if both available
520 * if fixed address on one bus the other will be chosen
521 */
3e2a037c 522static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
e8689e63
LW		 523 struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
524 struct pl08x_bus_data **sbus, u32 cctl)
525{
526 if (!(cctl & PL080_CONTROL_DST_INCR)) {
527 *mbus = src_bus;
528 *sbus = dst_bus;
529 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
530 *mbus = dst_bus;
531 *sbus = src_bus;
532 } else {
533 if (dst_bus->buswidth == 4) {
534 *mbus = dst_bus;
535 *sbus = src_bus;
536 } else if (src_bus->buswidth == 4) {
537 *mbus = src_bus;
538 *sbus = dst_bus;
539 } else if (dst_bus->buswidth == 2) {
540 *mbus = dst_bus;
541 *sbus = src_bus;
542 } else if (src_bus->buswidth == 2) {
543 *mbus = src_bus;
544 *sbus = dst_bus;
545 } else {
546 /* src_bus->buswidth == 1 */
547 *mbus = dst_bus;
548 *sbus = src_bus;
549 }
550 }
551}
552
553/*
554 * Fills in one LLI for a certain transfer descriptor
555 * and advance the counter
556 */
3e2a037c 557static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
e8689e63
LW		 558 struct pl08x_txd *txd, int num_llis, int len,
559 u32 cctl, u32 *remainder)
560{
7cb72ad9
RKAL		 561 struct pl08x_lli *llis_va = txd->llis_va;
562 struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
e8689e63
LW		 563
564 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
565
566 llis_va[num_llis].cctl = cctl;
567 llis_va[num_llis].src = txd->srcbus.addr;
568 llis_va[num_llis].dst = txd->dstbus.addr;
569
570 /*
571 * On versions with dual masters, you can optionally AND on
572 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
573 * in new LLIs with that controller, but we always try to
574 * choose AHB1 to point into memory. The idea is to have AHB2
575 * fixed on the peripheral and AHB1 messing around in the
576 * memory. So we don't manipulate this bit currently.
577 */
578
579 llis_va[num_llis].next =
580 (dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
581
582 if (cctl & PL080_CONTROL_SRC_INCR)
583 txd->srcbus.addr += len;
584 if (cctl & PL080_CONTROL_DST_INCR)
585 txd->dstbus.addr += len;
586
587 *remainder -= len;
588
589 return num_llis + 1;
590}
591
592/*
593 * Return number of bytes to fill to boundary, or len
594 */
595static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
596{
597 u32 boundary;
598
599 boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
600 << PL08X_BOUNDARY_SHIFT;
601
602 if (boundary < addr + len)
603 return boundary - addr;
604 else
605 return len;
606}
607
608/*
609 * This fills in the table of LLIs for the transfer descriptor
610 * Note that we assume we never have to change the burst sizes
611 * Return 0 for error
612 */
613static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
614 struct pl08x_txd *txd)
615{
616 struct pl08x_channel_data *cd = txd->cd;
617 struct pl08x_bus_data *mbus, *sbus;
618 u32 remainder;
619 int num_llis = 0;
620 u32 cctl;
621 int max_bytes_per_lli;
622 int total_bytes = 0;
7cb72ad9
RKAL		 623 struct pl08x_lli *llis_va;
624 struct pl08x_lli *llis_bus;
e8689e63 625
e8689e63
LW		 626 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
627 &txd->llis_bus);
628 if (!txd->llis_va) {
629 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
630 return 0;
631 }
632
633 pl08x->pool_ctr++;
634
635 /*
636 * Initialize bus values for this transfer
637 * from the passed optimal values
638 */
639 if (!cd) {
640 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
641 return 0;
642 }
643
644 /* Get the default CCTL from the platform data */
645 cctl = cd->cctl;
646
647 /*
648 * On the PL080 we have two bus masters and we
649 * should select one for source and one for
650 * destination. We try to use AHB2 for the
651 * bus which does not increment (typically the
652 * peripheral) else we just choose something.
653 */
654 cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
655 if (pl08x->vd->dualmaster) {
656 if (cctl & PL080_CONTROL_SRC_INCR)
657 /* Source increments, use AHB2 for destination */
658 cctl |= PL080_CONTROL_DST_AHB2;
659 else if (cctl & PL080_CONTROL_DST_INCR)
660 /* Destination increments, use AHB2 for source */
661 cctl |= PL080_CONTROL_SRC_AHB2;
662 else
663 /* Just pick something, source AHB1 dest AHB2 */
664 cctl |= PL080_CONTROL_DST_AHB2;
665 }
666
667 /* Find maximum width of the source bus */
668 txd->srcbus.maxwidth =
669 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
670 PL080_CONTROL_SWIDTH_SHIFT);
671
672 /* Find maximum width of the destination bus */
673 txd->dstbus.maxwidth =
674 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
675 PL080_CONTROL_DWIDTH_SHIFT);
676
677 /* Set up the bus widths to the maximum */
678 txd->srcbus.buswidth = txd->srcbus.maxwidth;
679 txd->dstbus.buswidth = txd->dstbus.maxwidth;
680 dev_vdbg(&pl08x->adev->dev,
681 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
682 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
683
684
685 /*
686 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
687 */
688 max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
689 PL080_CONTROL_TRANSFER_SIZE_MASK;
690 dev_vdbg(&pl08x->adev->dev,
691 "%s max bytes per lli = %d\n",
692 __func__, max_bytes_per_lli);
693
694 /* We need to count this down to zero */
695 remainder = txd->len;
696 dev_vdbg(&pl08x->adev->dev,
697 "%s remainder = %d\n",
698 __func__, remainder);
699
700 /*
701 * Choose bus to align to
702 * - prefers destination bus if both available
703 * - if fixed address on one bus chooses other
e8b5e11d 704 * - modifies cctl to choose an appropriate master
e8689e63
LW		 705 */
706 pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
707 &mbus, &sbus, cctl);
708
709
710 /*
711 * The lowest bit of the LLI register
712 * is also used to indicate which master to
713 * use for reading the LLIs.
714 */
715
716 if (txd->len < mbus->buswidth) {
717 /*
718 * Less than a bus width available
719 * - send as single bytes
720 */
721 while (remainder) {
722 dev_vdbg(&pl08x->adev->dev,
723 "%s single byte LLIs for a transfer of "
9c132992 724 "less than a bus width (remain 0x%08x)\n",
e8689e63
LW		 725 __func__, remainder);
726 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
727 num_llis =
728 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
729 cctl, &remainder);
730 total_bytes++;
731 }
732 } else {
733 /*
734 * Make one byte LLIs until master bus is aligned
735 * - slave will then be aligned also
736 */
737 while ((mbus->addr) % (mbus->buswidth)) {
738 dev_vdbg(&pl08x->adev->dev,
739 "%s adjustment lli for less than bus width "
9c132992 740 "(remain 0x%08x)\n",
e8689e63
LW		 741 __func__, remainder);
742 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
743 num_llis = pl08x_fill_lli_for_desc
744 (pl08x, txd, num_llis, 1, cctl, &remainder);
745 total_bytes++;
746 }
747
748 /*
749 * Master now aligned
750 * - if slave is not then we must set its width down
751 */
752 if (sbus->addr % sbus->buswidth) {
753 dev_dbg(&pl08x->adev->dev,
754 "%s set down bus width to one byte\n",
755 __func__);
756
757 sbus->buswidth = 1;
758 }
759
760 /*
761 * Make largest possible LLIs until less than one bus
762 * width left
763 */
764 while (remainder > (mbus->buswidth - 1)) {
765 int lli_len, target_len;
766 int tsize;
767 int odd_bytes;
768
769 /*
770 * If enough left try to send max possible,
771 * otherwise try to send the remainder
772 */
773 target_len = remainder;
774 if (remainder > max_bytes_per_lli)
775 target_len = max_bytes_per_lli;
776
777 /*
e8b5e11d 778 * Set bus lengths for incrementing buses
e8689e63
LW		 779 * to number of bytes which fill to next memory
780 * boundary
781 */
782 if (cctl & PL080_CONTROL_SRC_INCR)
783 txd->srcbus.fill_bytes =
784 pl08x_pre_boundary(
785 txd->srcbus.addr,
786 remainder);
787 else
788 txd->srcbus.fill_bytes =
789 max_bytes_per_lli;
790
791 if (cctl & PL080_CONTROL_DST_INCR)
792 txd->dstbus.fill_bytes =
793 pl08x_pre_boundary(
794 txd->dstbus.addr,
795 remainder);
796 else
797 txd->dstbus.fill_bytes =
798 max_bytes_per_lli;
799
800 /*
801 * Find the nearest
802 */
803 lli_len = min(txd->srcbus.fill_bytes,
804 txd->dstbus.fill_bytes);
805
806 BUG_ON(lli_len > remainder);
807
808 if (lli_len <= 0) {
809 dev_err(&pl08x->adev->dev,
810 "%s lli_len is %d, <= 0\n",
811 __func__, lli_len);
812 return 0;
813 }
814
815 if (lli_len == target_len) {
816 /*
817 * Can send what we wanted
818 */
819 /*
820 * Maintain alignment
821 */
822 lli_len = (lli_len/mbus->buswidth) *
823 mbus->buswidth;
824 odd_bytes = 0;
825 } else {
826 /*
827 * So now we know how many bytes to transfer
828 * to get to the nearest boundary
e8b5e11d 829 * The next LLI will past the boundary
e8689e63
LW		 830 * - however we may be working to a boundary
831 * on the slave bus
832 * We need to ensure the master stays aligned
833 */
834 odd_bytes = lli_len % mbus->buswidth;
835 /*
836 * - and that we are working in multiples
837 * of the bus widths
838 */
839 lli_len -= odd_bytes;
840
841 }
842
843 if (lli_len) {
844 /*
845 * Check against minimum bus alignment:
846 * Calculate actual transfer size in relation
847 * to bus width an get a maximum remainder of
848 * the smallest bus width - 1
849 */
850 /* FIXME: use round_down()? */
851 tsize = lli_len / min(mbus->buswidth,
852 sbus->buswidth);
853 lli_len = tsize * min(mbus->buswidth,
854 sbus->buswidth);
855
856 if (target_len != lli_len) {
857 dev_vdbg(&pl08x->adev->dev,
9c132992 858 "%s can't send what we want. Desired 0x%08x, lli of 0x%08x bytes in txd of 0x%08x\n",
e8689e63
LW		 859 __func__, target_len, lli_len, txd->len);
860 }
861
862 cctl = pl08x_cctl_bits(cctl,
863 txd->srcbus.buswidth,
864 txd->dstbus.buswidth,
865 tsize);
866
867 dev_vdbg(&pl08x->adev->dev,
9c132992 868 "%s fill lli with single lli chunk of size 0x%08x (remainder 0x%08x)\n",
e8689e63
LW		 869 __func__, lli_len, remainder);
870 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
871 num_llis, lli_len, cctl,
872 &remainder);
873 total_bytes += lli_len;
874 }
875
876
877 if (odd_bytes) {
878 /*
879 * Creep past the boundary,
880 * maintaining master alignment
881 */
882 int j;
883 for (j = 0; (j < mbus->buswidth)
884 && (remainder); j++) {
885 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
886 dev_vdbg(&pl08x->adev->dev,
9c132992 887 "%s align with boundary, single byte (remain 0x%08x)\n",
e8689e63
LW		 888 __func__, remainder);
889 num_llis =
890 pl08x_fill_lli_for_desc(pl08x,
891 txd, num_llis, 1,
892 cctl, &remainder);
893 total_bytes++;
894 }
895 }
896 }
897
898 /*
899 * Send any odd bytes
900 */
901 if (remainder < 0) {
902 dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
903 __func__, remainder);
904 return 0;
905 }
906
907 while (remainder) {
908 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
909 dev_vdbg(&pl08x->adev->dev,
e8b5e11d 910 "%s align with boundary, single odd byte (remain %d)\n",
e8689e63
LW		 911 __func__, remainder);
912 num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
913 1, cctl, &remainder);
914 total_bytes++;
915 }
916 }
917 if (total_bytes != txd->len) {
918 dev_err(&pl08x->adev->dev,
919 "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
920 __func__, total_bytes, txd->len);
921 return 0;
922 }
923
924 if (num_llis >= MAX_NUM_TSFR_LLIS) {
925 dev_err(&pl08x->adev->dev,
926 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
927 __func__, (u32) MAX_NUM_TSFR_LLIS);
928 return 0;
929 }
b58b6b5b
RKAL		 930
931 llis_va = txd->llis_va;
e8689e63 932 /*
b58b6b5b 933 * The final LLI terminates the LLI.
e8689e63 934 */
b58b6b5b
RKAL		 935 llis_va[num_llis - 1].next = 0;
936 /*
937 * The final LLI element shall also fire an interrupt
938 */
939 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
e8689e63
LW		 940
941 /* Now store the channel register values */
942 txd->csrc = llis_va[0].src;
943 txd->cdst = llis_va[0].dst;
b58b6b5b 944 txd->clli = llis_va[0].next;
e8689e63
LW		 945 txd->cctl = llis_va[0].cctl;
946 /* ccfg will be set at physical channel allocation time */
947
948#ifdef VERBOSE_DEBUG
949 {
950 int i;
951
952 for (i = 0; i < num_llis; i++) {
953 dev_vdbg(&pl08x->adev->dev,
9c132992 954 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
e8689e63
LW		 955 i,
956 &llis_va[i],
957 llis_va[i].src,
958 llis_va[i].dst,
959 llis_va[i].cctl,
960 llis_va[i].next
961 );
962 }
963 }
964#endif
965
966 return num_llis;
967}
968
969/* You should call this with the struct pl08x lock held */
970static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
971 struct pl08x_txd *txd)
972{
e8689e63
LW		 973 /* Free the LLI */
974 dma_pool_free(pl08x->pool, txd->llis_va,
975 txd->llis_bus);
976
977 pl08x->pool_ctr--;
978
979 kfree(txd);
980}
981
982static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
983 struct pl08x_dma_chan *plchan)
984{
985 struct pl08x_txd *txdi = NULL;
986 struct pl08x_txd *next;
987
988 if (!list_empty(&plchan->desc_list)) {
989 list_for_each_entry_safe(txdi,
990 next, &plchan->desc_list, node) {
991 list_del(&txdi->node);
992 pl08x_free_txd(pl08x, txdi);
993 }
994
995 }
996}
997
998/*
999 * The DMA ENGINE API
1000 */
1001static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1002{
1003 return 0;
1004}
1005
1006static void pl08x_free_chan_resources(struct dma_chan *chan)
1007{
1008}
1009
1010/*
1011 * This should be called with the channel plchan->lock held
1012 */
1013static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1014 struct pl08x_txd *txd)
1015{
1016 struct pl08x_driver_data *pl08x = plchan->host;
1017 struct pl08x_phy_chan *ch;
1018 int ret;
1019
1020 /* Check if we already have a channel */
1021 if (plchan->phychan)
1022 return 0;
1023
1024 ch = pl08x_get_phy_channel(pl08x, plchan);
1025 if (!ch) {
1026 /* No physical channel available, cope with it */
1027 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1028 return -EBUSY;
1029 }
1030
1031 /*
1032 * OK we have a physical channel: for memcpy() this is all we
1033 * need, but for slaves the physical signals may be muxed!
1034 * Can the platform allow us to use this channel?
1035 */
1036 if (plchan->slave &&
1037 ch->signal < 0 &&
1038 pl08x->pd->get_signal) {
1039 ret = pl08x->pd->get_signal(plchan);
1040 if (ret < 0) {
1041 dev_dbg(&pl08x->adev->dev,
1042 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1043 ch->id, plchan->name);
1044 /* Release physical channel & return */
1045 pl08x_put_phy_channel(pl08x, ch);
1046 return -EBUSY;
1047 }
1048 ch->signal = ret;
1049 }
1050
1051 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1052 ch->id,
1053 ch->signal,
1054 plchan->name);
1055
1056 plchan->phychan = ch;
1057
1058 return 0;
1059}
1060
1061static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1062{
1063 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1064
91aa5fad
RKAL		 1065 plchan->chan.cookie += 1;
1066 if (plchan->chan.cookie < 0)
1067 plchan->chan.cookie = 1;
1068 tx->cookie = plchan->chan.cookie;
e8689e63
LW		 1069 /* This unlock follows the lock in the prep() function */
1070 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1071
1072 return tx->cookie;
1073}
1074
1075static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1076 struct dma_chan *chan, unsigned long flags)
1077{
1078 struct dma_async_tx_descriptor *retval = NULL;
1079
1080 return retval;
1081}
1082
1083/*
1084 * Code accessing dma_async_is_complete() in a tight loop
1085 * may give problems - could schedule where indicated.
1086 * If slaves are relying on interrupts to signal completion this
1087 * function must not be called with interrupts disabled
1088 */
1089static enum dma_status
1090pl08x_dma_tx_status(struct dma_chan *chan,
1091 dma_cookie_t cookie,
1092 struct dma_tx_state *txstate)
1093{
1094 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1095 dma_cookie_t last_used;
1096 dma_cookie_t last_complete;
1097 enum dma_status ret;
1098 u32 bytesleft = 0;
1099
91aa5fad 1100 last_used = plchan->chan.cookie;
e8689e63
LW		 1101 last_complete = plchan->lc;
1102
1103 ret = dma_async_is_complete(cookie, last_complete, last_used);
1104 if (ret == DMA_SUCCESS) {
1105 dma_set_tx_state(txstate, last_complete, last_used, 0);
1106 return ret;
1107 }
1108
1109 /*
1110 * schedule(); could be inserted here
1111 */
1112
1113 /*
1114 * This cookie not complete yet
1115 */
91aa5fad 1116 last_used = plchan->chan.cookie;
e8689e63
LW		 1117 last_complete = plchan->lc;
1118
1119 /* Get number of bytes left in the active transactions and queue */
1120 bytesleft = pl08x_getbytes_chan(plchan);
1121
1122 dma_set_tx_state(txstate, last_complete, last_used,
1123 bytesleft);
1124
1125 if (plchan->state == PL08X_CHAN_PAUSED)
1126 return DMA_PAUSED;
1127
1128 /* Whether waiting or running, we're in progress */
1129 return DMA_IN_PROGRESS;
1130}
1131
1132/* PrimeCell DMA extension */
1133struct burst_table {
1134 int burstwords;
1135 u32 reg;
1136};
1137
1138static const struct burst_table burst_sizes[] = {
1139 {
1140 .burstwords = 256,
1141 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1142 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1143 },
1144 {
1145 .burstwords = 128,
1146 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1147 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1148 },
1149 {
1150 .burstwords = 64,
1151 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1152 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1153 },
1154 {
1155 .burstwords = 32,
1156 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1157 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1158 },
1159 {
1160 .burstwords = 16,
1161 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1162 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1163 },
1164 {
1165 .burstwords = 8,
1166 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1167 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1168 },
1169 {
1170 .burstwords = 4,
1171 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1172 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1173 },
1174 {
1175 .burstwords = 1,
1176 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1177 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1178 },
1179};
1180
1181static void dma_set_runtime_config(struct dma_chan *chan,
1182 struct dma_slave_config *config)
1183{
1184 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1185 struct pl08x_driver_data *pl08x = plchan->host;
1186 struct pl08x_channel_data *cd = plchan->cd;
1187 enum dma_slave_buswidth addr_width;
1188 u32 maxburst;
1189 u32 cctl = 0;
1190 /* Mask out all except src and dst channel */
1191 u32 ccfg = cd->ccfg & 0x000003DEU;
4440aacf 1192 int i;
e8689e63
LW		 1193
1194 /* Transfer direction */
1195 plchan->runtime_direction = config->direction;
1196 if (config->direction == DMA_TO_DEVICE) {
1197 plchan->runtime_addr = config->dst_addr;
1198 cctl |= PL080_CONTROL_SRC_INCR;
1199 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1200 addr_width = config->dst_addr_width;
1201 maxburst = config->dst_maxburst;
1202 } else if (config->direction == DMA_FROM_DEVICE) {
1203 plchan->runtime_addr = config->src_addr;
1204 cctl |= PL080_CONTROL_DST_INCR;
1205 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1206 addr_width = config->src_addr_width;
1207 maxburst = config->src_maxburst;
1208 } else {
1209 dev_err(&pl08x->adev->dev,
1210 "bad runtime_config: alien transfer direction\n");
1211 return;
1212 }
1213
1214 switch (addr_width) {
1215 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1216 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1217 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1218 break;
1219 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1220 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1221 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1222 break;
1223 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1224 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1225 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1226 break;
1227 default:
1228 dev_err(&pl08x->adev->dev,
1229 "bad runtime_config: alien address width\n");
1230 return;
1231 }
1232
1233 /*
1234 * Now decide on a maxburst:
4440aacf
RKAL		 1235 * If this channel will only request single transfers, set this
1236 * down to ONE element. Also select one element if no maxburst
1237 * is specified.
e8689e63 1238 */
4440aacf 1239 if (plchan->cd->single || maxburst == 0) {
e8689e63
LW		 1240 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1241 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1242 } else {
4440aacf 1243 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
e8689e63
LW		 1244 if (burst_sizes[i].burstwords <= maxburst)
1245 break;
e8689e63
LW		 1246 cctl |= burst_sizes[i].reg;
1247 }
1248
1249 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1250 cctl &= ~PL080_CONTROL_PROT_MASK;
1251 cctl |= PL080_CONTROL_PROT_SYS;
1252
1253 /* Modify the default channel data to fit PrimeCell request */
1254 cd->cctl = cctl;
1255 cd->ccfg = ccfg;
1256
1257 dev_dbg(&pl08x->adev->dev,
1258 "configured channel %s (%s) for %s, data width %d, "
9c132992 1259 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
e8689e63
LW		 1260 dma_chan_name(chan), plchan->name,
1261 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1262 addr_width,
1263 maxburst,
1264 cctl, ccfg);
1265}
1266
1267/*
1268 * Slave transactions callback to the slave device to allow
1269 * synchronization of slave DMA signals with the DMAC enable
1270 */
1271static void pl08x_issue_pending(struct dma_chan *chan)
1272{
1273 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1274 struct pl08x_driver_data *pl08x = plchan->host;
1275 unsigned long flags;
1276
1277 spin_lock_irqsave(&plchan->lock, flags);
9c0bb43b
RKAL		 1278 /* Something is already active, or we're waiting for a channel... */
1279 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1280 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63 1281 return;
9c0bb43b 1282 }
e8689e63
LW		 1283
1284 /* Take the first element in the queue and execute it */
1285 if (!list_empty(&plchan->desc_list)) {
1286 struct pl08x_txd *next;
1287
1288 next = list_first_entry(&plchan->desc_list,
1289 struct pl08x_txd,
1290 node);
1291 list_del(&next->node);
1292 plchan->at = next;
1293 plchan->state = PL08X_CHAN_RUNNING;
1294
1295 /* Configure the physical channel for the active txd */
1296 pl08x_config_phychan_for_txd(plchan);
1297 pl08x_set_cregs(pl08x, plchan->phychan);
1298 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1299 }
1300
1301 spin_unlock_irqrestore(&plchan->lock, flags);
1302}
1303
1304static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1305 struct pl08x_txd *txd)
1306{
1307 int num_llis;
1308 struct pl08x_driver_data *pl08x = plchan->host;
1309 int ret;
1310
1311 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
dafa7317
RKAL		 1312 if (!num_llis) {
1313 kfree(txd);
e8689e63 1314 return -EINVAL;
dafa7317 1315 }
e8689e63
LW		 1316
1317 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1318
b58b6b5b 1319 list_add_tail(&txd->node, &plchan->desc_list);
e8689e63
LW		 1320
1321 /*
1322 * See if we already have a physical channel allocated,
1323 * else this is the time to try to get one.
1324 */
1325 ret = prep_phy_channel(plchan, txd);
1326 if (ret) {
1327 /*
1328 * No physical channel available, we will
1329 * stack up the memcpy channels until there is a channel
1330 * available to handle it whereas slave transfers may
1331 * have been denied due to platform channel muxing restrictions
1332 * and since there is no guarantee that this will ever be
e8b5e11d
RKAL		 1333 * resolved, and since the signal must be acquired AFTER
1334 * acquiring the physical channel, we will let them be NACK:ed
e8689e63
LW		 1335 * with -EBUSY here. The drivers can alway retry the prep()
1336 * call if they are eager on doing this using DMA.
1337 */
1338 if (plchan->slave) {
1339 pl08x_free_txd_list(pl08x, plchan);
1340 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1341 return -EBUSY;
1342 }
1343 /* Do this memcpy whenever there is a channel ready */
1344 plchan->state = PL08X_CHAN_WAITING;
1345 plchan->waiting = txd;
1346 } else
1347 /*
1348 * Else we're all set, paused and ready to roll,
1349 * status will switch to PL08X_CHAN_RUNNING when
1350 * we call issue_pending(). If there is something
1351 * running on the channel already we don't change
1352 * its state.
1353 */
1354 if (plchan->state == PL08X_CHAN_IDLE)
1355 plchan->state = PL08X_CHAN_PAUSED;
1356
1357 /*
1358 * Notice that we leave plchan->lock locked on purpose:
1359 * it will be unlocked in the subsequent tx_submit()
1360 * call. This is a consequence of the current API.
1361 */
1362
1363 return 0;
1364}
1365
ac3cd20d
RKAL		 1366static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1367{
1368 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1369
1370 if (txd) {
1371 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1372 txd->tx.tx_submit = pl08x_tx_submit;
1373 INIT_LIST_HEAD(&txd->node);
1374 }
1375 return txd;
1376}
1377
e8689e63
LW		 1378/*
1379 * Initialize a descriptor to be used by memcpy submit
1380 */
1381static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1382 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1383 size_t len, unsigned long flags)
1384{
1385 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1386 struct pl08x_driver_data *pl08x = plchan->host;
1387 struct pl08x_txd *txd;
1388 int ret;
1389
ac3cd20d 1390 txd = pl08x_get_txd(plchan);
e8689e63
LW		 1391 if (!txd) {
1392 dev_err(&pl08x->adev->dev,
1393 "%s no memory for descriptor\n", __func__);
1394 return NULL;
1395 }
1396
e8689e63
LW		 1397 txd->direction = DMA_NONE;
1398 txd->srcbus.addr = src;
1399 txd->dstbus.addr = dest;
1400
1401 /* Set platform data for m2m */
1402 txd->cd = &pl08x->pd->memcpy_channel;
1403 /* Both to be incremented or the code will break */
1404 txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
e8689e63
LW		 1405 txd->len = len;
1406
e8689e63
LW		 1407 ret = pl08x_prep_channel_resources(plchan, txd);
1408 if (ret)
1409 return NULL;
1410 /*
1411 * NB: the channel lock is held at this point so tx_submit()
1412 * must be called in direct succession.
1413 */
1414
1415 return &txd->tx;
1416}
1417
3e2a037c 1418static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
e8689e63
LW		 1419 struct dma_chan *chan, struct scatterlist *sgl,
1420 unsigned int sg_len, enum dma_data_direction direction,
1421 unsigned long flags)
1422{
1423 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1424 struct pl08x_driver_data *pl08x = plchan->host;
1425 struct pl08x_txd *txd;
1426 int ret;
1427
1428 /*
1429 * Current implementation ASSUMES only one sg
1430 */
1431 if (sg_len != 1) {
1432 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1433 __func__);
1434 BUG();
1435 }
1436
1437 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1438 __func__, sgl->length, plchan->name);
1439
ac3cd20d 1440 txd = pl08x_get_txd(plchan);
e8689e63
LW		 1441 if (!txd) {
1442 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1443 return NULL;
1444 }
1445
e8689e63
LW		 1446 if (direction != plchan->runtime_direction)
1447 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1448 "the direction configured for the PrimeCell\n",
1449 __func__);
1450
1451 /*
1452 * Set up addresses, the PrimeCell configured address
1453 * will take precedence since this may configure the
1454 * channel target address dynamically at runtime.
1455 */
1456 txd->direction = direction;
1457 if (direction == DMA_TO_DEVICE) {
1458 txd->srcbus.addr = sgl->dma_address;
1459 if (plchan->runtime_addr)
1460 txd->dstbus.addr = plchan->runtime_addr;
1461 else
1462 txd->dstbus.addr = plchan->cd->addr;
1463 } else if (direction == DMA_FROM_DEVICE) {
1464 if (plchan->runtime_addr)
1465 txd->srcbus.addr = plchan->runtime_addr;
1466 else
1467 txd->srcbus.addr = plchan->cd->addr;
1468 txd->dstbus.addr = sgl->dma_address;
1469 } else {
1470 dev_err(&pl08x->adev->dev,
1471 "%s direction unsupported\n", __func__);
1472 return NULL;
1473 }
1474 txd->cd = plchan->cd;
e8689e63 1475 txd->len = sgl->length;
e8689e63
LW		 1476
1477 ret = pl08x_prep_channel_resources(plchan, txd);
1478 if (ret)
1479 return NULL;
1480 /*
1481 * NB: the channel lock is held at this point so tx_submit()
1482 * must be called in direct succession.
1483 */
1484
1485 return &txd->tx;
1486}
1487
1488static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1489 unsigned long arg)
1490{
1491 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1492 struct pl08x_driver_data *pl08x = plchan->host;
1493 unsigned long flags;
1494 int ret = 0;
1495
1496 /* Controls applicable to inactive channels */
1497 if (cmd == DMA_SLAVE_CONFIG) {
1498 dma_set_runtime_config(chan,
1499 (struct dma_slave_config *)
1500 arg);
1501 return 0;
1502 }
1503
1504 /*
1505 * Anything succeeds on channels with no physical allocation and
1506 * no queued transfers.
1507 */
1508 spin_lock_irqsave(&plchan->lock, flags);
1509 if (!plchan->phychan && !plchan->at) {
1510 spin_unlock_irqrestore(&plchan->lock, flags);
1511 return 0;
1512 }
1513
1514 switch (cmd) {
1515 case DMA_TERMINATE_ALL:
1516 plchan->state = PL08X_CHAN_IDLE;
1517
1518 if (plchan->phychan) {
1519 pl08x_stop_phy_chan(plchan->phychan);
1520
1521 /*
1522 * Mark physical channel as free and free any slave
1523 * signal
1524 */
1525 if ((plchan->phychan->signal >= 0) &&
1526 pl08x->pd->put_signal) {
1527 pl08x->pd->put_signal(plchan);
1528 plchan->phychan->signal = -1;
1529 }
1530 pl08x_put_phy_channel(pl08x, plchan->phychan);
1531 plchan->phychan = NULL;
1532 }
e8689e63
LW		 1533 /* Dequeue jobs and free LLIs */
1534 if (plchan->at) {
1535 pl08x_free_txd(pl08x, plchan->at);
1536 plchan->at = NULL;
1537 }
1538 /* Dequeue jobs not yet fired as well */
1539 pl08x_free_txd_list(pl08x, plchan);
1540 break;
1541 case DMA_PAUSE:
1542 pl08x_pause_phy_chan(plchan->phychan);
1543 plchan->state = PL08X_CHAN_PAUSED;
1544 break;
1545 case DMA_RESUME:
1546 pl08x_resume_phy_chan(plchan->phychan);
1547 plchan->state = PL08X_CHAN_RUNNING;
1548 break;
1549 default:
1550 /* Unknown command */
1551 ret = -ENXIO;
1552 break;
1553 }
1554
1555 spin_unlock_irqrestore(&plchan->lock, flags);
1556
1557 return ret;
1558}
1559
1560bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1561{
1562 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1563 char *name = chan_id;
1564
1565 /* Check that the channel is not taken! */
1566 if (!strcmp(plchan->name, name))
1567 return true;
1568
1569 return false;
1570}
1571
1572/*
1573 * Just check that the device is there and active
1574 * TODO: turn this bit on/off depending on the number of
1575 * physical channels actually used, if it is zero... well
1576 * shut it off. That will save some power. Cut the clock
1577 * at the same time.
1578 */
1579static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1580{
1581 u32 val;
1582
1583 val = readl(pl08x->base + PL080_CONFIG);
1584 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
e8b5e11d 1585 /* We implicitly clear bit 1 and that means little-endian mode */
e8689e63
LW		 1586 val |= PL080_CONFIG_ENABLE;
1587 writel(val, pl08x->base + PL080_CONFIG);
1588}
1589
1590static void pl08x_tasklet(unsigned long data)
1591{
1592 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1593 struct pl08x_phy_chan *phychan = plchan->phychan;
1594 struct pl08x_driver_data *pl08x = plchan->host;
bf072af4 1595 unsigned long flags;
e8689e63 1596
bf072af4 1597 spin_lock_irqsave(&plchan->lock, flags);
e8689e63
LW		 1598
1599 if (plchan->at) {
1600 dma_async_tx_callback callback =
1601 plchan->at->tx.callback;
1602 void *callback_param =
1603 plchan->at->tx.callback_param;
1604
1605 /*
1606 * Update last completed
1607 */
91aa5fad 1608 plchan->lc = plchan->at->tx.cookie;
e8689e63
LW		 1609
1610 /*
1611 * Callback to signal completion
1612 */
1613 if (callback)
1614 callback(callback_param);
1615
e8689e63 1616 /*
b58b6b5b 1617 * Free the descriptor
e8689e63 1618 */
b58b6b5b
RKAL		 1619 pl08x_free_txd(pl08x, plchan->at);
1620 plchan->at = NULL;
e8689e63
LW		 1621 }
1622 /*
1623 * If a new descriptor is queued, set it up
1624 * plchan->at is NULL here
1625 */
1626 if (!list_empty(&plchan->desc_list)) {
1627 struct pl08x_txd *next;
1628
1629 next = list_first_entry(&plchan->desc_list,
1630 struct pl08x_txd,
1631 node);
1632 list_del(&next->node);
1633 plchan->at = next;
1634 /* Configure the physical channel for the next txd */
1635 pl08x_config_phychan_for_txd(plchan);
1636 pl08x_set_cregs(pl08x, plchan->phychan);
1637 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1638 } else {
1639 struct pl08x_dma_chan *waiting = NULL;
1640
1641 /*
1642 * No more jobs, so free up the physical channel
1643 * Free any allocated signal on slave transfers too
1644 */
1645 if ((phychan->signal >= 0) && pl08x->pd->put_signal) {
1646 pl08x->pd->put_signal(plchan);
1647 phychan->signal = -1;
1648 }
1649 pl08x_put_phy_channel(pl08x, phychan);
1650 plchan->phychan = NULL;
1651 plchan->state = PL08X_CHAN_IDLE;
1652
1653 /*
1654 * And NOW before anyone else can grab that free:d
1655 * up physical channel, see if there is some memcpy
1656 * pending that seriously needs to start because of
1657 * being stacked up while we were choking the
1658 * physical channels with data.
1659 */
1660 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1661 chan.device_node) {
1662 if (waiting->state == PL08X_CHAN_WAITING &&
1663 waiting->waiting != NULL) {
1664 int ret;
1665
1666 /* This should REALLY not fail now */
1667 ret = prep_phy_channel(waiting,
1668 waiting->waiting);
1669 BUG_ON(ret);
1670 waiting->state = PL08X_CHAN_RUNNING;
1671 waiting->waiting = NULL;
1672 pl08x_issue_pending(&waiting->chan);
1673 break;
1674 }
1675 }
1676 }
1677
bf072af4 1678 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63
LW		 1679}
1680
1681static irqreturn_t pl08x_irq(int irq, void *dev)
1682{
1683 struct pl08x_driver_data *pl08x = dev;
1684 u32 mask = 0;
1685 u32 val;
1686 int i;
1687
1688 val = readl(pl08x->base + PL080_ERR_STATUS);
1689 if (val) {
1690 /*
1691 * An error interrupt (on one or more channels)
1692 */
1693 dev_err(&pl08x->adev->dev,
1694 "%s error interrupt, register value 0x%08x\n",
1695 __func__, val);
1696 /*
1697 * Simply clear ALL PL08X error interrupts,
1698 * regardless of channel and cause
1699 * FIXME: should be 0x00000003 on PL081 really.
1700 */
1701 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1702 }
1703 val = readl(pl08x->base + PL080_INT_STATUS);
1704 for (i = 0; i < pl08x->vd->channels; i++) {
1705 if ((1 << i) & val) {
1706 /* Locate physical channel */
1707 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1708 struct pl08x_dma_chan *plchan = phychan->serving;
1709
1710 /* Schedule tasklet on this channel */
1711 tasklet_schedule(&plchan->tasklet);
1712
1713 mask |= (1 << i);
1714 }
1715 }
1716 /*
1717 * Clear only the terminal interrupts on channels we processed
1718 */
1719 writel(mask, pl08x->base + PL080_TC_CLEAR);
1720
1721 return mask ? IRQ_HANDLED : IRQ_NONE;
1722}
1723
1724/*
1725 * Initialise the DMAC memcpy/slave channels.
1726 * Make a local wrapper to hold required data
1727 */
1728static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1729 struct dma_device *dmadev,
1730 unsigned int channels,
1731 bool slave)
1732{
1733 struct pl08x_dma_chan *chan;
1734 int i;
1735
1736 INIT_LIST_HEAD(&dmadev->channels);
1737 /*
1738 * Register as many many memcpy as we have physical channels,
1739 * we won't always be able to use all but the code will have
1740 * to cope with that situation.
1741 */
1742 for (i = 0; i < channels; i++) {
1743 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1744 if (!chan) {
1745 dev_err(&pl08x->adev->dev,
1746 "%s no memory for channel\n", __func__);
1747 return -ENOMEM;
1748 }
1749
1750 chan->host = pl08x;
1751 chan->state = PL08X_CHAN_IDLE;
1752
1753 if (slave) {
1754 chan->slave = true;
1755 chan->name = pl08x->pd->slave_channels[i].bus_id;
1756 chan->cd = &pl08x->pd->slave_channels[i];
1757 } else {
1758 chan->cd = &pl08x->pd->memcpy_channel;
1759 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1760 if (!chan->name) {
1761 kfree(chan);
1762 return -ENOMEM;
1763 }
1764 }
b58b6b5b
RKAL		 1765 if (chan->cd->circular_buffer) {
1766 dev_err(&pl08x->adev->dev,
1767 "channel %s: circular buffers not supported\n",
1768 chan->name);
1769 kfree(chan);
1770 continue;
1771 }
e8689e63
LW		 1772 dev_info(&pl08x->adev->dev,
1773 "initialize virtual channel \"%s\"\n",
1774 chan->name);
1775
1776 chan->chan.device = dmadev;
91aa5fad
RKAL		 1777 chan->chan.cookie = 0;
1778 chan->lc = 0;
e8689e63
LW		 1779
1780 spin_lock_init(&chan->lock);
1781 INIT_LIST_HEAD(&chan->desc_list);
1782 tasklet_init(&chan->tasklet, pl08x_tasklet,
1783 (unsigned long) chan);
1784
1785 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1786 }
1787 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1788 i, slave ? "slave" : "memcpy");
1789 return i;
1790}
1791
1792static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1793{
1794 struct pl08x_dma_chan *chan = NULL;
1795 struct pl08x_dma_chan *next;
1796
1797 list_for_each_entry_safe(chan,
1798 next, &dmadev->channels, chan.device_node) {
1799 list_del(&chan->chan.device_node);
1800 kfree(chan);
1801 }
1802}
1803
1804#ifdef CONFIG_DEBUG_FS
1805static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1806{
1807 switch (state) {
1808 case PL08X_CHAN_IDLE:
1809 return "idle";
1810 case PL08X_CHAN_RUNNING:
1811 return "running";
1812 case PL08X_CHAN_PAUSED:
1813 return "paused";
1814 case PL08X_CHAN_WAITING:
1815 return "waiting";
1816 default:
1817 break;
1818 }
1819 return "UNKNOWN STATE";
1820}
1821
1822static int pl08x_debugfs_show(struct seq_file *s, void *data)
1823{
1824 struct pl08x_driver_data *pl08x = s->private;
1825 struct pl08x_dma_chan *chan;
1826 struct pl08x_phy_chan *ch;
1827 unsigned long flags;
1828 int i;
1829
1830 seq_printf(s, "PL08x physical channels:\n");
1831 seq_printf(s, "CHANNEL:\tUSER:\n");
1832 seq_printf(s, "--------\t-----\n");
1833 for (i = 0; i < pl08x->vd->channels; i++) {
1834 struct pl08x_dma_chan *virt_chan;
1835
1836 ch = &pl08x->phy_chans[i];
1837
1838 spin_lock_irqsave(&ch->lock, flags);
1839 virt_chan = ch->serving;
1840
1841 seq_printf(s, "%d\t\t%s\n",
1842 ch->id, virt_chan ? virt_chan->name : "(none)");
1843
1844 spin_unlock_irqrestore(&ch->lock, flags);
1845 }
1846
1847 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1848 seq_printf(s, "CHANNEL:\tSTATE:\n");
1849 seq_printf(s, "--------\t------\n");
1850 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
3e2a037c 1851 seq_printf(s, "%s\t\t%s\n", chan->name,
e8689e63
LW		 1852 pl08x_state_str(chan->state));
1853 }
1854
1855 seq_printf(s, "\nPL08x virtual slave channels:\n");
1856 seq_printf(s, "CHANNEL:\tSTATE:\n");
1857 seq_printf(s, "--------\t------\n");
1858 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
3e2a037c 1859 seq_printf(s, "%s\t\t%s\n", chan->name,
e8689e63
LW		 1860 pl08x_state_str(chan->state));
1861 }
1862
1863 return 0;
1864}
1865
1866static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1867{
1868 return single_open(file, pl08x_debugfs_show, inode->i_private);
1869}
1870
1871static const struct file_operations pl08x_debugfs_operations = {
1872 .open = pl08x_debugfs_open,
1873 .read = seq_read,
1874 .llseek = seq_lseek,
1875 .release = single_release,
1876};
1877
1878static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1879{
1880 /* Expose a simple debugfs interface to view all clocks */
1881 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1882 NULL, pl08x,
1883 &pl08x_debugfs_operations);
1884}
1885
1886#else
1887static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1888{
1889}
1890#endif
1891
1892static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1893{
1894 struct pl08x_driver_data *pl08x;
f96ca9ec 1895 const struct vendor_data *vd = id->data;
e8689e63
LW		 1896 int ret = 0;
1897 int i;
1898
1899 ret = amba_request_regions(adev, NULL);
1900 if (ret)
1901 return ret;
1902
1903 /* Create the driver state holder */
1904 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1905 if (!pl08x) {
1906 ret = -ENOMEM;
1907 goto out_no_pl08x;
1908 }
1909
1910 /* Initialize memcpy engine */
1911 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1912 pl08x->memcpy.dev = &adev->dev;
1913 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1914 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1915 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1916 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1917 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1918 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1919 pl08x->memcpy.device_control = pl08x_control;
1920
1921 /* Initialize slave engine */
1922 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1923 pl08x->slave.dev = &adev->dev;
1924 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1925 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1926 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1927 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1928 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1929 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1930 pl08x->slave.device_control = pl08x_control;
1931
1932 /* Get the platform data */
1933 pl08x->pd = dev_get_platdata(&adev->dev);
1934 if (!pl08x->pd) {
1935 dev_err(&adev->dev, "no platform data supplied\n");
1936 goto out_no_platdata;
1937 }
1938
1939 /* Assign useful pointers to the driver state */
1940 pl08x->adev = adev;
1941 pl08x->vd = vd;
1942
1943 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1944 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1945 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1946 if (!pl08x->pool) {
1947 ret = -ENOMEM;
1948 goto out_no_lli_pool;
1949 }
1950
1951 spin_lock_init(&pl08x->lock);
1952
1953 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1954 if (!pl08x->base) {
1955 ret = -ENOMEM;
1956 goto out_no_ioremap;
1957 }
1958
1959 /* Turn on the PL08x */
1960 pl08x_ensure_on(pl08x);
1961
1962 /*
1963 * Attach the interrupt handler
1964 */
1965 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1966 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1967
1968 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
b05cd8f4 1969 DRIVER_NAME, pl08x);
e8689e63
LW		 1970 if (ret) {
1971 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1972 __func__, adev->irq[0]);
1973 goto out_no_irq;
1974 }
1975
1976 /* Initialize physical channels */
1977 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1978 GFP_KERNEL);
1979 if (!pl08x->phy_chans) {
1980 dev_err(&adev->dev, "%s failed to allocate "
1981 "physical channel holders\n",
1982 __func__);
1983 goto out_no_phychans;
1984 }
1985
1986 for (i = 0; i < vd->channels; i++) {
1987 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1988
1989 ch->id = i;
1990 ch->base = pl08x->base + PL080_Cx_BASE(i);
1991 spin_lock_init(&ch->lock);
1992 ch->serving = NULL;
1993 ch->signal = -1;
1994 dev_info(&adev->dev,
1995 "physical channel %d is %s\n", i,
1996 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1997 }
1998
1999 /* Register as many memcpy channels as there are physical channels */
2000 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2001 pl08x->vd->channels, false);
2002 if (ret <= 0) {
2003 dev_warn(&pl08x->adev->dev,
2004 "%s failed to enumerate memcpy channels - %d\n",
2005 __func__, ret);
2006 goto out_no_memcpy;
2007 }
2008 pl08x->memcpy.chancnt = ret;
2009
2010 /* Register slave channels */
2011 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2012 pl08x->pd->num_slave_channels,
2013 true);
2014 if (ret <= 0) {
2015 dev_warn(&pl08x->adev->dev,
2016 "%s failed to enumerate slave channels - %d\n",
2017 __func__, ret);
2018 goto out_no_slave;
2019 }
2020 pl08x->slave.chancnt = ret;
2021
2022 ret = dma_async_device_register(&pl08x->memcpy);
2023 if (ret) {
2024 dev_warn(&pl08x->adev->dev,
2025 "%s failed to register memcpy as an async device - %d\n",
2026 __func__, ret);
2027 goto out_no_memcpy_reg;
2028 }
2029
2030 ret = dma_async_device_register(&pl08x->slave);
2031 if (ret) {
2032 dev_warn(&pl08x->adev->dev,
2033 "%s failed to register slave as an async device - %d\n",
2034 __func__, ret);
2035 goto out_no_slave_reg;
2036 }
2037
2038 amba_set_drvdata(adev, pl08x);
2039 init_pl08x_debugfs(pl08x);
b05cd8f4
RKAL		 2040 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2041 amba_part(adev), amba_rev(adev),
2042 (unsigned long long)adev->res.start, adev->irq[0]);
e8689e63
LW		 2043 return 0;
2044
2045out_no_slave_reg:
2046 dma_async_device_unregister(&pl08x->memcpy);
2047out_no_memcpy_reg:
2048 pl08x_free_virtual_channels(&pl08x->slave);
2049out_no_slave:
2050 pl08x_free_virtual_channels(&pl08x->memcpy);
2051out_no_memcpy:
2052 kfree(pl08x->phy_chans);
2053out_no_phychans:
2054 free_irq(adev->irq[0], pl08x);
2055out_no_irq:
2056 iounmap(pl08x->base);
2057out_no_ioremap:
2058 dma_pool_destroy(pl08x->pool);
2059out_no_lli_pool:
2060out_no_platdata:
2061 kfree(pl08x);
2062out_no_pl08x:
2063 amba_release_regions(adev);
2064 return ret;
2065}
2066
2067/* PL080 has 8 channels and the PL080 have just 2 */
2068static struct vendor_data vendor_pl080 = {
e8689e63
LW		 2069 .channels = 8,
2070 .dualmaster = true,
2071};
2072
2073static struct vendor_data vendor_pl081 = {
e8689e63
LW		 2074 .channels = 2,
2075 .dualmaster = false,
2076};
2077
2078static struct amba_id pl08x_ids[] = {
2079 /* PL080 */
2080 {
2081 .id = 0x00041080,
2082 .mask = 0x000fffff,
2083 .data = &vendor_pl080,
2084 },
2085 /* PL081 */
2086 {
2087 .id = 0x00041081,
2088 .mask = 0x000fffff,
2089 .data = &vendor_pl081,
2090 },
2091 /* Nomadik 8815 PL080 variant */
2092 {
2093 .id = 0x00280880,
2094 .mask = 0x00ffffff,
2095 .data = &vendor_pl080,
2096 },
2097 { 0, 0 },
2098};
2099
2100static struct amba_driver pl08x_amba_driver = {
2101 .drv.name = DRIVER_NAME,
2102 .id_table = pl08x_ids,
2103 .probe = pl08x_probe,
2104};
2105
2106static int __init pl08x_init(void)
2107{
2108 int retval;
2109 retval = amba_driver_register(&pl08x_amba_driver);
2110 if (retval)
2111 printk(KERN_WARNING DRIVER_NAME
e8b5e11d 2112 "failed to register as an AMBA device (%d)\n",
e8689e63
LW		 2113 retval);
2114 return retval;
2115}
2116subsys_initcall(pl08x_init);
Linux kernel - Deliverables
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