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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
e8b5e11d | 22 | * The full GNU General Public License is in this distribution in the |
e8689e63 LW |
23 | * file called COPYING. |
24 | * | |
25 | * Documentation: ARM DDI 0196G == PL080 | |
26 | * Documentation: ARM DDI 0218E == PL081 | |
27 | * | |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to | |
29 | * any channel. | |
30 | * | |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
69 | * Only the former works sanely with scatter lists, so we only implement | |
70 | * the DMAC flow control method. However, peripherals which use the LBREQ | |
71 | * and LSREQ signals (eg, MMCI) are unable to use this mode, which through | |
72 | * these hardware restrictions prevents them from using scatter DMA. | |
e8689e63 LW |
73 | * |
74 | * Global TODO: | |
75 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
76 | */ | |
77 | #include <linux/device.h> | |
78 | #include <linux/init.h> | |
79 | #include <linux/module.h> | |
e8689e63 LW |
80 | #include <linux/interrupt.h> |
81 | #include <linux/slab.h> | |
82 | #include <linux/dmapool.h> | |
e8689e63 | 83 | #include <linux/dmaengine.h> |
730404ac | 84 | #include <linux/amba/bus.h> |
e8689e63 LW |
85 | #include <linux/amba/pl08x.h> |
86 | #include <linux/debugfs.h> | |
87 | #include <linux/seq_file.h> | |
88 | ||
89 | #include <asm/hardware/pl080.h> | |
e8689e63 LW |
90 | |
91 | #define DRIVER_NAME "pl08xdmac" | |
92 | ||
93 | /** | |
94 | * struct vendor_data - vendor-specific config parameters | |
e8b5e11d | 95 | * for PL08x derivatives |
e8689e63 LW |
96 | * @channels: the number of channels available in this variant |
97 | * @dualmaster: whether this version supports dual AHB masters | |
98 | * or not. | |
99 | */ | |
100 | struct vendor_data { | |
e8689e63 LW |
101 | u8 channels; |
102 | bool dualmaster; | |
103 | }; | |
104 | ||
105 | /* | |
106 | * PL08X private data structures | |
e8b5e11d | 107 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
108 | * start & end do not - their bus bit info is in cctl. Also note that these |
109 | * are fixed 32-bit quantities. | |
e8689e63 | 110 | */ |
7cb72ad9 | 111 | struct pl08x_lli { |
e25761d7 RKAL |
112 | u32 src; |
113 | u32 dst; | |
bfddfb45 | 114 | u32 lli; |
e8689e63 LW |
115 | u32 cctl; |
116 | }; | |
117 | ||
118 | /** | |
119 | * struct pl08x_driver_data - the local state holder for the PL08x | |
120 | * @slave: slave engine for this instance | |
121 | * @memcpy: memcpy engine for this instance | |
122 | * @base: virtual memory base (remapped) for the PL08x | |
123 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
124 | * @vd: vendor data for this PL08x variant | |
125 | * @pd: platform data passed in from the platform/machine | |
126 | * @phy_chans: array of data for the physical channels | |
127 | * @pool: a pool for the LLI descriptors | |
128 | * @pool_ctr: counter of LLIs in the pool | |
30749cb4 RKAL |
129 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches |
130 | * @mem_buses: set to indicate memory transfers on AHB2. | |
e8689e63 LW |
131 | * @lock: a spinlock for this struct |
132 | */ | |
133 | struct pl08x_driver_data { | |
134 | struct dma_device slave; | |
135 | struct dma_device memcpy; | |
136 | void __iomem *base; | |
137 | struct amba_device *adev; | |
f96ca9ec | 138 | const struct vendor_data *vd; |
e8689e63 LW |
139 | struct pl08x_platform_data *pd; |
140 | struct pl08x_phy_chan *phy_chans; | |
141 | struct dma_pool *pool; | |
142 | int pool_ctr; | |
30749cb4 RKAL |
143 | u8 lli_buses; |
144 | u8 mem_buses; | |
e8689e63 LW |
145 | spinlock_t lock; |
146 | }; | |
147 | ||
148 | /* | |
149 | * PL08X specific defines | |
150 | */ | |
151 | ||
152 | /* | |
153 | * Memory boundaries: the manual for PL08x says that the controller | |
154 | * cannot read past a 1KiB boundary, so these defines are used to | |
155 | * create transfer LLIs that do not cross such boundaries. | |
156 | */ | |
157 | #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */ | |
158 | #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT) | |
159 | ||
160 | /* Minimum period between work queue runs */ | |
161 | #define PL08X_WQ_PERIODMIN 20 | |
162 | ||
163 | /* Size (bytes) of each LLI buffer allocated for one transfer */ | |
164 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
165 | ||
e8b5e11d | 166 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
e8689e63 | 167 | #define PL08X_MAX_ALLOCS 0x40 |
7cb72ad9 | 168 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
169 | #define PL08X_ALIGN 8 |
170 | ||
171 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
172 | { | |
173 | return container_of(chan, struct pl08x_dma_chan, chan); | |
174 | } | |
175 | ||
176 | /* | |
177 | * Physical channel handling | |
178 | */ | |
179 | ||
180 | /* Whether a certain channel is busy or not */ | |
181 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
182 | { | |
183 | unsigned int val; | |
184 | ||
185 | val = readl(ch->base + PL080_CH_CONFIG); | |
186 | return val & PL080_CONFIG_ACTIVE; | |
187 | } | |
188 | ||
189 | /* | |
190 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 191 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
192 | * been set when the LLIs were constructed. Poke them into the hardware |
193 | * and start the transfer. | |
e8689e63 | 194 | */ |
c885bee4 RKAL |
195 | static void pl08x_start_txd(struct pl08x_dma_chan *plchan, |
196 | struct pl08x_txd *txd) | |
e8689e63 | 197 | { |
c885bee4 | 198 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 199 | struct pl08x_phy_chan *phychan = plchan->phychan; |
19524d77 | 200 | struct pl08x_lli *lli = &txd->llis_va[0]; |
09b3c323 | 201 | u32 val; |
c885bee4 RKAL |
202 | |
203 | plchan->at = txd; | |
e8689e63 | 204 | |
c885bee4 RKAL |
205 | /* Wait for channel inactive */ |
206 | while (pl08x_phy_channel_busy(phychan)) | |
207 | cpu_relax(); | |
e8689e63 | 208 | |
c885bee4 RKAL |
209 | dev_vdbg(&pl08x->adev->dev, |
210 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
211 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
212 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 213 | txd->ccfg); |
19524d77 RKAL |
214 | |
215 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
216 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
217 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
218 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 219 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
220 | |
221 | /* Enable the DMA channel */ | |
222 | /* Do not access config register until channel shows as disabled */ | |
223 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 224 | cpu_relax(); |
e8689e63 | 225 | |
c885bee4 RKAL |
226 | /* Do not access config register until channel shows as inactive */ |
227 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 228 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 229 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 230 | |
c885bee4 | 231 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
232 | } |
233 | ||
234 | /* | |
235 | * Overall DMAC remains enabled always. | |
236 | * | |
237 | * Disabling individual channels could lose data. | |
238 | * | |
239 | * Disable the peripheral DMA after disabling the DMAC | |
240 | * in order to allow the DMAC FIFO to drain, and | |
241 | * hence allow the channel to show inactive | |
242 | * | |
243 | */ | |
244 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
245 | { | |
246 | u32 val; | |
247 | ||
248 | /* Set the HALT bit and wait for the FIFO to drain */ | |
249 | val = readl(ch->base + PL080_CH_CONFIG); | |
250 | val |= PL080_CONFIG_HALT; | |
251 | writel(val, ch->base + PL080_CH_CONFIG); | |
252 | ||
253 | /* Wait for channel inactive */ | |
254 | while (pl08x_phy_channel_busy(ch)) | |
19386b32 | 255 | cpu_relax(); |
e8689e63 LW |
256 | } |
257 | ||
258 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
259 | { | |
260 | u32 val; | |
261 | ||
262 | /* Clear the HALT bit */ | |
263 | val = readl(ch->base + PL080_CH_CONFIG); | |
264 | val &= ~PL080_CONFIG_HALT; | |
265 | writel(val, ch->base + PL080_CH_CONFIG); | |
266 | } | |
267 | ||
268 | ||
269 | /* Stops the channel */ | |
270 | static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch) | |
271 | { | |
272 | u32 val; | |
273 | ||
274 | pl08x_pause_phy_chan(ch); | |
275 | ||
276 | /* Disable channel */ | |
277 | val = readl(ch->base + PL080_CH_CONFIG); | |
278 | val &= ~PL080_CONFIG_ENABLE; | |
279 | val &= ~PL080_CONFIG_ERR_IRQ_MASK; | |
280 | val &= ~PL080_CONFIG_TC_IRQ_MASK; | |
281 | writel(val, ch->base + PL080_CH_CONFIG); | |
282 | } | |
283 | ||
284 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
285 | { | |
286 | /* The source width defines the number of bytes */ | |
287 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
288 | ||
289 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
290 | case PL080_WIDTH_8BIT: | |
291 | break; | |
292 | case PL080_WIDTH_16BIT: | |
293 | bytes *= 2; | |
294 | break; | |
295 | case PL080_WIDTH_32BIT: | |
296 | bytes *= 4; | |
297 | break; | |
298 | } | |
299 | return bytes; | |
300 | } | |
301 | ||
302 | /* The channel should be paused when calling this */ | |
303 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
304 | { | |
305 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
306 | struct pl08x_txd *txd; |
307 | unsigned long flags; | |
cace6585 | 308 | size_t bytes = 0; |
e8689e63 LW |
309 | |
310 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
311 | ch = plchan->phychan; |
312 | txd = plchan->at; | |
313 | ||
314 | /* | |
db9f136a RKAL |
315 | * Follow the LLIs to get the number of remaining |
316 | * bytes in the currently active transaction. | |
e8689e63 LW |
317 | */ |
318 | if (ch && txd) { | |
4c0df6a3 | 319 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 320 | |
db9f136a | 321 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
322 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
323 | ||
324 | if (clli) { | |
db9f136a RKAL |
325 | struct pl08x_lli *llis_va = txd->llis_va; |
326 | dma_addr_t llis_bus = txd->llis_bus; | |
327 | int index; | |
328 | ||
329 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
330 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 331 | |
db9f136a RKAL |
332 | /* |
333 | * Locate the next LLI - as this is an array, | |
334 | * it's simple maths to find. | |
335 | */ | |
336 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
337 | ||
338 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
339 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 340 | |
e8689e63 | 341 | /* |
e8b5e11d | 342 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 343 | */ |
db9f136a RKAL |
344 | if (!llis_va[index].lli) |
345 | break; | |
e8689e63 LW |
346 | } |
347 | } | |
348 | } | |
349 | ||
350 | /* Sum up all queued transactions */ | |
351 | if (!list_empty(&plchan->desc_list)) { | |
db9f136a | 352 | struct pl08x_txd *txdi; |
e8689e63 LW |
353 | list_for_each_entry(txdi, &plchan->desc_list, node) { |
354 | bytes += txdi->len; | |
355 | } | |
e8689e63 LW |
356 | } |
357 | ||
358 | spin_unlock_irqrestore(&plchan->lock, flags); | |
359 | ||
360 | return bytes; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Allocate a physical channel for a virtual channel | |
365 | */ | |
366 | static struct pl08x_phy_chan * | |
367 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
368 | struct pl08x_dma_chan *virt_chan) | |
369 | { | |
370 | struct pl08x_phy_chan *ch = NULL; | |
371 | unsigned long flags; | |
372 | int i; | |
373 | ||
374 | /* | |
375 | * Try to locate a physical channel to be used for | |
376 | * this transfer. If all are taken return NULL and | |
377 | * the requester will have to cope by using some fallback | |
378 | * PIO mode or retrying later. | |
379 | */ | |
380 | for (i = 0; i < pl08x->vd->channels; i++) { | |
381 | ch = &pl08x->phy_chans[i]; | |
382 | ||
383 | spin_lock_irqsave(&ch->lock, flags); | |
384 | ||
385 | if (!ch->serving) { | |
386 | ch->serving = virt_chan; | |
387 | ch->signal = -1; | |
388 | spin_unlock_irqrestore(&ch->lock, flags); | |
389 | break; | |
390 | } | |
391 | ||
392 | spin_unlock_irqrestore(&ch->lock, flags); | |
393 | } | |
394 | ||
395 | if (i == pl08x->vd->channels) { | |
396 | /* No physical channel available, cope with it */ | |
397 | return NULL; | |
398 | } | |
399 | ||
400 | return ch; | |
401 | } | |
402 | ||
403 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
404 | struct pl08x_phy_chan *ch) | |
405 | { | |
406 | unsigned long flags; | |
407 | ||
408 | /* Stop the channel and clear its interrupts */ | |
409 | pl08x_stop_phy_chan(ch); | |
410 | writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR); | |
411 | writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR); | |
412 | ||
413 | /* Mark it as free */ | |
414 | spin_lock_irqsave(&ch->lock, flags); | |
415 | ch->serving = NULL; | |
416 | spin_unlock_irqrestore(&ch->lock, flags); | |
417 | } | |
418 | ||
419 | /* | |
420 | * LLI handling | |
421 | */ | |
422 | ||
423 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
424 | { | |
425 | switch (coded) { | |
426 | case PL080_WIDTH_8BIT: | |
427 | return 1; | |
428 | case PL080_WIDTH_16BIT: | |
429 | return 2; | |
430 | case PL080_WIDTH_32BIT: | |
431 | return 4; | |
432 | default: | |
433 | break; | |
434 | } | |
435 | BUG(); | |
436 | return 0; | |
437 | } | |
438 | ||
439 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 440 | size_t tsize) |
e8689e63 LW |
441 | { |
442 | u32 retbits = cctl; | |
443 | ||
e8b5e11d | 444 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
445 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
446 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
447 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
448 | ||
449 | /* Then set the bits according to the parameters */ | |
450 | switch (srcwidth) { | |
451 | case 1: | |
452 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
453 | break; | |
454 | case 2: | |
455 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
456 | break; | |
457 | case 4: | |
458 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
459 | break; | |
460 | default: | |
461 | BUG(); | |
462 | break; | |
463 | } | |
464 | ||
465 | switch (dstwidth) { | |
466 | case 1: | |
467 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
468 | break; | |
469 | case 2: | |
470 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
471 | break; | |
472 | case 4: | |
473 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
474 | break; | |
475 | default: | |
476 | BUG(); | |
477 | break; | |
478 | } | |
479 | ||
480 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
481 | return retbits; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Autoselect a master bus to use for the transfer | |
486 | * this prefers the destination bus if both available | |
487 | * if fixed address on one bus the other will be chosen | |
488 | */ | |
3e2a037c | 489 | static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus, |
e8689e63 LW |
490 | struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus, |
491 | struct pl08x_bus_data **sbus, u32 cctl) | |
492 | { | |
493 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
494 | *mbus = src_bus; | |
495 | *sbus = dst_bus; | |
496 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { | |
497 | *mbus = dst_bus; | |
498 | *sbus = src_bus; | |
499 | } else { | |
500 | if (dst_bus->buswidth == 4) { | |
501 | *mbus = dst_bus; | |
502 | *sbus = src_bus; | |
503 | } else if (src_bus->buswidth == 4) { | |
504 | *mbus = src_bus; | |
505 | *sbus = dst_bus; | |
506 | } else if (dst_bus->buswidth == 2) { | |
507 | *mbus = dst_bus; | |
508 | *sbus = src_bus; | |
509 | } else if (src_bus->buswidth == 2) { | |
510 | *mbus = src_bus; | |
511 | *sbus = dst_bus; | |
512 | } else { | |
513 | /* src_bus->buswidth == 1 */ | |
514 | *mbus = dst_bus; | |
515 | *sbus = src_bus; | |
516 | } | |
517 | } | |
518 | } | |
519 | ||
520 | /* | |
521 | * Fills in one LLI for a certain transfer descriptor | |
522 | * and advance the counter | |
523 | */ | |
0059005f RKAL |
524 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
525 | struct pl08x_txd *txd, int num_llis, int len, u32 cctl, u32 *remainder) | |
e8689e63 | 526 | { |
7cb72ad9 | 527 | struct pl08x_lli *llis_va = txd->llis_va; |
56b61882 | 528 | dma_addr_t llis_bus = txd->llis_bus; |
e8689e63 LW |
529 | |
530 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
531 | ||
30749cb4 RKAL |
532 | llis_va[num_llis].cctl = cctl; |
533 | llis_va[num_llis].src = txd->srcbus.addr; | |
534 | llis_va[num_llis].dst = txd->dstbus.addr; | |
bfddfb45 | 535 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli); |
30749cb4 RKAL |
536 | if (pl08x->lli_buses & PL08X_AHB2) |
537 | llis_va[num_llis].lli |= PL080_LLI_LM_AHB2; | |
e8689e63 LW |
538 | |
539 | if (cctl & PL080_CONTROL_SRC_INCR) | |
540 | txd->srcbus.addr += len; | |
541 | if (cctl & PL080_CONTROL_DST_INCR) | |
542 | txd->dstbus.addr += len; | |
543 | ||
cace6585 RKAL |
544 | BUG_ON(*remainder < len); |
545 | ||
e8689e63 | 546 | *remainder -= len; |
e8689e63 LW |
547 | } |
548 | ||
549 | /* | |
b61be8d7 RKAL |
550 | * Return number of bytes to fill to boundary, or len. |
551 | * This calculation works for any value of addr. | |
e8689e63 | 552 | */ |
cace6585 | 553 | static inline size_t pl08x_pre_boundary(u32 addr, size_t len) |
e8689e63 | 554 | { |
b61be8d7 RKAL |
555 | size_t boundary_len = PL08X_BOUNDARY_SIZE - |
556 | (addr & (PL08X_BOUNDARY_SIZE - 1)); | |
e8689e63 | 557 | |
b61be8d7 | 558 | return min(boundary_len, len); |
e8689e63 LW |
559 | } |
560 | ||
561 | /* | |
562 | * This fills in the table of LLIs for the transfer descriptor | |
563 | * Note that we assume we never have to change the burst sizes | |
564 | * Return 0 for error | |
565 | */ | |
566 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
567 | struct pl08x_txd *txd) | |
568 | { | |
e8689e63 | 569 | struct pl08x_bus_data *mbus, *sbus; |
cace6585 | 570 | size_t remainder; |
e8689e63 LW |
571 | int num_llis = 0; |
572 | u32 cctl; | |
cace6585 RKAL |
573 | size_t max_bytes_per_lli; |
574 | size_t total_bytes = 0; | |
7cb72ad9 | 575 | struct pl08x_lli *llis_va; |
e8689e63 | 576 | |
e8689e63 LW |
577 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, |
578 | &txd->llis_bus); | |
579 | if (!txd->llis_va) { | |
580 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
581 | return 0; | |
582 | } | |
583 | ||
584 | pl08x->pool_ctr++; | |
585 | ||
70b5ed6b RKAL |
586 | /* Get the default CCTL */ |
587 | cctl = txd->cctl; | |
e8689e63 | 588 | |
e8689e63 LW |
589 | /* Find maximum width of the source bus */ |
590 | txd->srcbus.maxwidth = | |
591 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> | |
592 | PL080_CONTROL_SWIDTH_SHIFT); | |
593 | ||
594 | /* Find maximum width of the destination bus */ | |
595 | txd->dstbus.maxwidth = | |
596 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> | |
597 | PL080_CONTROL_DWIDTH_SHIFT); | |
598 | ||
599 | /* Set up the bus widths to the maximum */ | |
600 | txd->srcbus.buswidth = txd->srcbus.maxwidth; | |
601 | txd->dstbus.buswidth = txd->dstbus.maxwidth; | |
602 | dev_vdbg(&pl08x->adev->dev, | |
603 | "%s source bus is %d bytes wide, dest bus is %d bytes wide\n", | |
604 | __func__, txd->srcbus.buswidth, txd->dstbus.buswidth); | |
605 | ||
606 | ||
607 | /* | |
608 | * Bytes transferred == tsize * MIN(buswidths), not max(buswidths) | |
609 | */ | |
610 | max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) * | |
611 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
612 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 613 | "%s max bytes per lli = %zu\n", |
e8689e63 LW |
614 | __func__, max_bytes_per_lli); |
615 | ||
616 | /* We need to count this down to zero */ | |
617 | remainder = txd->len; | |
618 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 619 | "%s remainder = %zu\n", |
e8689e63 LW |
620 | __func__, remainder); |
621 | ||
622 | /* | |
623 | * Choose bus to align to | |
624 | * - prefers destination bus if both available | |
625 | * - if fixed address on one bus chooses other | |
e8b5e11d | 626 | * - modifies cctl to choose an appropriate master |
e8689e63 LW |
627 | */ |
628 | pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus, | |
629 | &mbus, &sbus, cctl); | |
630 | ||
e8689e63 LW |
631 | if (txd->len < mbus->buswidth) { |
632 | /* | |
633 | * Less than a bus width available | |
634 | * - send as single bytes | |
635 | */ | |
636 | while (remainder) { | |
637 | dev_vdbg(&pl08x->adev->dev, | |
638 | "%s single byte LLIs for a transfer of " | |
9c132992 | 639 | "less than a bus width (remain 0x%08x)\n", |
e8689e63 LW |
640 | __func__, remainder); |
641 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
0059005f | 642 | pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1, |
e8689e63 LW |
643 | cctl, &remainder); |
644 | total_bytes++; | |
645 | } | |
646 | } else { | |
647 | /* | |
648 | * Make one byte LLIs until master bus is aligned | |
649 | * - slave will then be aligned also | |
650 | */ | |
651 | while ((mbus->addr) % (mbus->buswidth)) { | |
652 | dev_vdbg(&pl08x->adev->dev, | |
653 | "%s adjustment lli for less than bus width " | |
9c132992 | 654 | "(remain 0x%08x)\n", |
e8689e63 LW |
655 | __func__, remainder); |
656 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
0059005f RKAL |
657 | pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1, |
658 | cctl, &remainder); | |
e8689e63 LW |
659 | total_bytes++; |
660 | } | |
661 | ||
662 | /* | |
663 | * Master now aligned | |
664 | * - if slave is not then we must set its width down | |
665 | */ | |
666 | if (sbus->addr % sbus->buswidth) { | |
667 | dev_dbg(&pl08x->adev->dev, | |
668 | "%s set down bus width to one byte\n", | |
669 | __func__); | |
670 | ||
671 | sbus->buswidth = 1; | |
672 | } | |
673 | ||
674 | /* | |
675 | * Make largest possible LLIs until less than one bus | |
676 | * width left | |
677 | */ | |
678 | while (remainder > (mbus->buswidth - 1)) { | |
cace6585 | 679 | size_t lli_len, target_len, tsize, odd_bytes; |
e8689e63 LW |
680 | |
681 | /* | |
682 | * If enough left try to send max possible, | |
683 | * otherwise try to send the remainder | |
684 | */ | |
d6cf7b59 | 685 | target_len = min(remainder, max_bytes_per_lli); |
e8689e63 LW |
686 | |
687 | /* | |
e8b5e11d | 688 | * Set bus lengths for incrementing buses |
e8689e63 LW |
689 | * to number of bytes which fill to next memory |
690 | * boundary | |
691 | */ | |
692 | if (cctl & PL080_CONTROL_SRC_INCR) | |
693 | txd->srcbus.fill_bytes = | |
694 | pl08x_pre_boundary( | |
695 | txd->srcbus.addr, | |
696 | remainder); | |
697 | else | |
698 | txd->srcbus.fill_bytes = | |
699 | max_bytes_per_lli; | |
700 | ||
701 | if (cctl & PL080_CONTROL_DST_INCR) | |
702 | txd->dstbus.fill_bytes = | |
703 | pl08x_pre_boundary( | |
704 | txd->dstbus.addr, | |
705 | remainder); | |
706 | else | |
707 | txd->dstbus.fill_bytes = | |
708 | max_bytes_per_lli; | |
709 | ||
710 | /* | |
711 | * Find the nearest | |
712 | */ | |
713 | lli_len = min(txd->srcbus.fill_bytes, | |
714 | txd->dstbus.fill_bytes); | |
715 | ||
716 | BUG_ON(lli_len > remainder); | |
717 | ||
718 | if (lli_len <= 0) { | |
719 | dev_err(&pl08x->adev->dev, | |
cace6585 | 720 | "%s lli_len is %zu, <= 0\n", |
e8689e63 LW |
721 | __func__, lli_len); |
722 | return 0; | |
723 | } | |
724 | ||
725 | if (lli_len == target_len) { | |
726 | /* | |
727 | * Can send what we wanted | |
728 | */ | |
729 | /* | |
730 | * Maintain alignment | |
731 | */ | |
732 | lli_len = (lli_len/mbus->buswidth) * | |
733 | mbus->buswidth; | |
734 | odd_bytes = 0; | |
735 | } else { | |
736 | /* | |
737 | * So now we know how many bytes to transfer | |
738 | * to get to the nearest boundary | |
e8b5e11d | 739 | * The next LLI will past the boundary |
e8689e63 LW |
740 | * - however we may be working to a boundary |
741 | * on the slave bus | |
742 | * We need to ensure the master stays aligned | |
743 | */ | |
744 | odd_bytes = lli_len % mbus->buswidth; | |
745 | /* | |
746 | * - and that we are working in multiples | |
747 | * of the bus widths | |
748 | */ | |
749 | lli_len -= odd_bytes; | |
750 | ||
751 | } | |
752 | ||
753 | if (lli_len) { | |
754 | /* | |
755 | * Check against minimum bus alignment: | |
756 | * Calculate actual transfer size in relation | |
757 | * to bus width an get a maximum remainder of | |
758 | * the smallest bus width - 1 | |
759 | */ | |
760 | /* FIXME: use round_down()? */ | |
761 | tsize = lli_len / min(mbus->buswidth, | |
762 | sbus->buswidth); | |
763 | lli_len = tsize * min(mbus->buswidth, | |
764 | sbus->buswidth); | |
765 | ||
766 | if (target_len != lli_len) { | |
767 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 768 | "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n", |
e8689e63 LW |
769 | __func__, target_len, lli_len, txd->len); |
770 | } | |
771 | ||
772 | cctl = pl08x_cctl_bits(cctl, | |
773 | txd->srcbus.buswidth, | |
774 | txd->dstbus.buswidth, | |
775 | tsize); | |
776 | ||
777 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 778 | "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n", |
e8689e63 | 779 | __func__, lli_len, remainder); |
0059005f RKAL |
780 | pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, |
781 | lli_len, cctl, &remainder); | |
e8689e63 LW |
782 | total_bytes += lli_len; |
783 | } | |
784 | ||
785 | ||
786 | if (odd_bytes) { | |
787 | /* | |
788 | * Creep past the boundary, | |
789 | * maintaining master alignment | |
790 | */ | |
791 | int j; | |
792 | for (j = 0; (j < mbus->buswidth) | |
793 | && (remainder); j++) { | |
794 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
795 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 796 | "%s align with boundary, single byte (remain 0x%08zx)\n", |
e8689e63 | 797 | __func__, remainder); |
0059005f RKAL |
798 | pl08x_fill_lli_for_desc(pl08x, txd, |
799 | num_llis++, 1, cctl, | |
800 | &remainder); | |
e8689e63 LW |
801 | total_bytes++; |
802 | } | |
803 | } | |
804 | } | |
805 | ||
806 | /* | |
807 | * Send any odd bytes | |
808 | */ | |
e8689e63 LW |
809 | while (remainder) { |
810 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
811 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 812 | "%s align with boundary, single odd byte (remain %zu)\n", |
e8689e63 | 813 | __func__, remainder); |
0059005f RKAL |
814 | pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1, |
815 | cctl, &remainder); | |
e8689e63 LW |
816 | total_bytes++; |
817 | } | |
818 | } | |
819 | if (total_bytes != txd->len) { | |
820 | dev_err(&pl08x->adev->dev, | |
cace6585 | 821 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", |
e8689e63 LW |
822 | __func__, total_bytes, txd->len); |
823 | return 0; | |
824 | } | |
825 | ||
826 | if (num_llis >= MAX_NUM_TSFR_LLIS) { | |
827 | dev_err(&pl08x->adev->dev, | |
828 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
829 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
830 | return 0; | |
831 | } | |
b58b6b5b RKAL |
832 | |
833 | llis_va = txd->llis_va; | |
e8689e63 | 834 | /* |
b58b6b5b | 835 | * The final LLI terminates the LLI. |
e8689e63 | 836 | */ |
bfddfb45 | 837 | llis_va[num_llis - 1].lli = 0; |
b58b6b5b RKAL |
838 | /* |
839 | * The final LLI element shall also fire an interrupt | |
840 | */ | |
841 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; | |
e8689e63 | 842 | |
e8689e63 LW |
843 | #ifdef VERBOSE_DEBUG |
844 | { | |
845 | int i; | |
846 | ||
847 | for (i = 0; i < num_llis; i++) { | |
848 | dev_vdbg(&pl08x->adev->dev, | |
9c132992 | 849 | "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n", |
e8689e63 LW |
850 | i, |
851 | &llis_va[i], | |
852 | llis_va[i].src, | |
853 | llis_va[i].dst, | |
854 | llis_va[i].cctl, | |
bfddfb45 | 855 | llis_va[i].lli |
e8689e63 LW |
856 | ); |
857 | } | |
858 | } | |
859 | #endif | |
860 | ||
861 | return num_llis; | |
862 | } | |
863 | ||
864 | /* You should call this with the struct pl08x lock held */ | |
865 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
866 | struct pl08x_txd *txd) | |
867 | { | |
e8689e63 | 868 | /* Free the LLI */ |
56b61882 | 869 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); |
e8689e63 LW |
870 | |
871 | pl08x->pool_ctr--; | |
872 | ||
873 | kfree(txd); | |
874 | } | |
875 | ||
876 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
877 | struct pl08x_dma_chan *plchan) | |
878 | { | |
879 | struct pl08x_txd *txdi = NULL; | |
880 | struct pl08x_txd *next; | |
881 | ||
882 | if (!list_empty(&plchan->desc_list)) { | |
883 | list_for_each_entry_safe(txdi, | |
884 | next, &plchan->desc_list, node) { | |
885 | list_del(&txdi->node); | |
886 | pl08x_free_txd(pl08x, txdi); | |
887 | } | |
888 | ||
889 | } | |
890 | } | |
891 | ||
892 | /* | |
893 | * The DMA ENGINE API | |
894 | */ | |
895 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
896 | { | |
897 | return 0; | |
898 | } | |
899 | ||
900 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
901 | { | |
902 | } | |
903 | ||
904 | /* | |
905 | * This should be called with the channel plchan->lock held | |
906 | */ | |
907 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
908 | struct pl08x_txd *txd) | |
909 | { | |
910 | struct pl08x_driver_data *pl08x = plchan->host; | |
911 | struct pl08x_phy_chan *ch; | |
912 | int ret; | |
913 | ||
914 | /* Check if we already have a channel */ | |
915 | if (plchan->phychan) | |
916 | return 0; | |
917 | ||
918 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
919 | if (!ch) { | |
920 | /* No physical channel available, cope with it */ | |
921 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
922 | return -EBUSY; | |
923 | } | |
924 | ||
925 | /* | |
926 | * OK we have a physical channel: for memcpy() this is all we | |
927 | * need, but for slaves the physical signals may be muxed! | |
928 | * Can the platform allow us to use this channel? | |
929 | */ | |
930 | if (plchan->slave && | |
931 | ch->signal < 0 && | |
932 | pl08x->pd->get_signal) { | |
933 | ret = pl08x->pd->get_signal(plchan); | |
934 | if (ret < 0) { | |
935 | dev_dbg(&pl08x->adev->dev, | |
936 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
937 | ch->id, plchan->name); | |
938 | /* Release physical channel & return */ | |
939 | pl08x_put_phy_channel(pl08x, ch); | |
940 | return -EBUSY; | |
941 | } | |
942 | ch->signal = ret; | |
09b3c323 RKAL |
943 | |
944 | /* Assign the flow control signal to this channel */ | |
945 | if (txd->direction == DMA_TO_DEVICE) | |
946 | txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
947 | else if (txd->direction == DMA_FROM_DEVICE) | |
948 | txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
e8689e63 LW |
949 | } |
950 | ||
951 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", | |
952 | ch->id, | |
953 | ch->signal, | |
954 | plchan->name); | |
955 | ||
956 | plchan->phychan = ch; | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
8c8cc2b1 RKAL |
961 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
962 | { | |
963 | struct pl08x_driver_data *pl08x = plchan->host; | |
964 | ||
965 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
966 | pl08x->pd->put_signal(plchan); | |
967 | plchan->phychan->signal = -1; | |
968 | } | |
969 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
970 | plchan->phychan = NULL; | |
971 | } | |
972 | ||
e8689e63 LW |
973 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
974 | { | |
975 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
976 | ||
91aa5fad RKAL |
977 | plchan->chan.cookie += 1; |
978 | if (plchan->chan.cookie < 0) | |
979 | plchan->chan.cookie = 1; | |
980 | tx->cookie = plchan->chan.cookie; | |
e8689e63 LW |
981 | /* This unlock follows the lock in the prep() function */ |
982 | spin_unlock_irqrestore(&plchan->lock, plchan->lockflags); | |
983 | ||
984 | return tx->cookie; | |
985 | } | |
986 | ||
987 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
988 | struct dma_chan *chan, unsigned long flags) | |
989 | { | |
990 | struct dma_async_tx_descriptor *retval = NULL; | |
991 | ||
992 | return retval; | |
993 | } | |
994 | ||
995 | /* | |
996 | * Code accessing dma_async_is_complete() in a tight loop | |
997 | * may give problems - could schedule where indicated. | |
998 | * If slaves are relying on interrupts to signal completion this | |
999 | * function must not be called with interrupts disabled | |
1000 | */ | |
1001 | static enum dma_status | |
1002 | pl08x_dma_tx_status(struct dma_chan *chan, | |
1003 | dma_cookie_t cookie, | |
1004 | struct dma_tx_state *txstate) | |
1005 | { | |
1006 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1007 | dma_cookie_t last_used; | |
1008 | dma_cookie_t last_complete; | |
1009 | enum dma_status ret; | |
1010 | u32 bytesleft = 0; | |
1011 | ||
91aa5fad | 1012 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1013 | last_complete = plchan->lc; |
1014 | ||
1015 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1016 | if (ret == DMA_SUCCESS) { | |
1017 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * schedule(); could be inserted here | |
1023 | */ | |
1024 | ||
1025 | /* | |
1026 | * This cookie not complete yet | |
1027 | */ | |
91aa5fad | 1028 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1029 | last_complete = plchan->lc; |
1030 | ||
1031 | /* Get number of bytes left in the active transactions and queue */ | |
1032 | bytesleft = pl08x_getbytes_chan(plchan); | |
1033 | ||
1034 | dma_set_tx_state(txstate, last_complete, last_used, | |
1035 | bytesleft); | |
1036 | ||
1037 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1038 | return DMA_PAUSED; | |
1039 | ||
1040 | /* Whether waiting or running, we're in progress */ | |
1041 | return DMA_IN_PROGRESS; | |
1042 | } | |
1043 | ||
1044 | /* PrimeCell DMA extension */ | |
1045 | struct burst_table { | |
1046 | int burstwords; | |
1047 | u32 reg; | |
1048 | }; | |
1049 | ||
1050 | static const struct burst_table burst_sizes[] = { | |
1051 | { | |
1052 | .burstwords = 256, | |
1053 | .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1054 | (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1055 | }, | |
1056 | { | |
1057 | .burstwords = 128, | |
1058 | .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1059 | (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1060 | }, | |
1061 | { | |
1062 | .burstwords = 64, | |
1063 | .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1064 | (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1065 | }, | |
1066 | { | |
1067 | .burstwords = 32, | |
1068 | .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1069 | (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1070 | }, | |
1071 | { | |
1072 | .burstwords = 16, | |
1073 | .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1074 | (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1075 | }, | |
1076 | { | |
1077 | .burstwords = 8, | |
1078 | .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1079 | (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1080 | }, | |
1081 | { | |
1082 | .burstwords = 4, | |
1083 | .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1084 | (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1085 | }, | |
1086 | { | |
1087 | .burstwords = 1, | |
1088 | .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1089 | (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1090 | }, | |
1091 | }; | |
1092 | ||
1093 | static void dma_set_runtime_config(struct dma_chan *chan, | |
1094 | struct dma_slave_config *config) | |
1095 | { | |
1096 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1097 | struct pl08x_driver_data *pl08x = plchan->host; | |
1098 | struct pl08x_channel_data *cd = plchan->cd; | |
1099 | enum dma_slave_buswidth addr_width; | |
1100 | u32 maxburst; | |
1101 | u32 cctl = 0; | |
4440aacf | 1102 | int i; |
e8689e63 LW |
1103 | |
1104 | /* Transfer direction */ | |
1105 | plchan->runtime_direction = config->direction; | |
1106 | if (config->direction == DMA_TO_DEVICE) { | |
1107 | plchan->runtime_addr = config->dst_addr; | |
e8689e63 LW |
1108 | addr_width = config->dst_addr_width; |
1109 | maxburst = config->dst_maxburst; | |
1110 | } else if (config->direction == DMA_FROM_DEVICE) { | |
1111 | plchan->runtime_addr = config->src_addr; | |
e8689e63 LW |
1112 | addr_width = config->src_addr_width; |
1113 | maxburst = config->src_maxburst; | |
1114 | } else { | |
1115 | dev_err(&pl08x->adev->dev, | |
1116 | "bad runtime_config: alien transfer direction\n"); | |
1117 | return; | |
1118 | } | |
1119 | ||
1120 | switch (addr_width) { | |
1121 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1122 | cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1123 | (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1124 | break; | |
1125 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1126 | cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1127 | (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1128 | break; | |
1129 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1130 | cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1131 | (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1132 | break; | |
1133 | default: | |
1134 | dev_err(&pl08x->adev->dev, | |
1135 | "bad runtime_config: alien address width\n"); | |
1136 | return; | |
1137 | } | |
1138 | ||
1139 | /* | |
1140 | * Now decide on a maxburst: | |
4440aacf RKAL |
1141 | * If this channel will only request single transfers, set this |
1142 | * down to ONE element. Also select one element if no maxburst | |
1143 | * is specified. | |
e8689e63 | 1144 | */ |
4440aacf | 1145 | if (plchan->cd->single || maxburst == 0) { |
e8689e63 LW |
1146 | cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) | |
1147 | (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT); | |
1148 | } else { | |
4440aacf | 1149 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) |
e8689e63 LW |
1150 | if (burst_sizes[i].burstwords <= maxburst) |
1151 | break; | |
e8689e63 LW |
1152 | cctl |= burst_sizes[i].reg; |
1153 | } | |
1154 | ||
e8689e63 LW |
1155 | /* Modify the default channel data to fit PrimeCell request */ |
1156 | cd->cctl = cctl; | |
e8689e63 LW |
1157 | |
1158 | dev_dbg(&pl08x->adev->dev, | |
1159 | "configured channel %s (%s) for %s, data width %d, " | |
4983a04f | 1160 | "maxburst %d words, LE, CCTL=0x%08x\n", |
e8689e63 LW |
1161 | dma_chan_name(chan), plchan->name, |
1162 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
1163 | addr_width, | |
1164 | maxburst, | |
4983a04f | 1165 | cctl); |
e8689e63 LW |
1166 | } |
1167 | ||
1168 | /* | |
1169 | * Slave transactions callback to the slave device to allow | |
1170 | * synchronization of slave DMA signals with the DMAC enable | |
1171 | */ | |
1172 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1173 | { | |
1174 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1175 | unsigned long flags; |
1176 | ||
1177 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1178 | /* Something is already active, or we're waiting for a channel... */ |
1179 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1180 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1181 | return; |
9c0bb43b | 1182 | } |
e8689e63 LW |
1183 | |
1184 | /* Take the first element in the queue and execute it */ | |
1185 | if (!list_empty(&plchan->desc_list)) { | |
1186 | struct pl08x_txd *next; | |
1187 | ||
1188 | next = list_first_entry(&plchan->desc_list, | |
1189 | struct pl08x_txd, | |
1190 | node); | |
1191 | list_del(&next->node); | |
e8689e63 LW |
1192 | plchan->state = PL08X_CHAN_RUNNING; |
1193 | ||
c885bee4 | 1194 | pl08x_start_txd(plchan, next); |
e8689e63 LW |
1195 | } |
1196 | ||
1197 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1198 | } | |
1199 | ||
1200 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1201 | struct pl08x_txd *txd) | |
1202 | { | |
1203 | int num_llis; | |
1204 | struct pl08x_driver_data *pl08x = plchan->host; | |
1205 | int ret; | |
1206 | ||
1207 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 RKAL |
1208 | if (!num_llis) { |
1209 | kfree(txd); | |
e8689e63 | 1210 | return -EINVAL; |
dafa7317 | 1211 | } |
e8689e63 LW |
1212 | |
1213 | spin_lock_irqsave(&plchan->lock, plchan->lockflags); | |
1214 | ||
b58b6b5b | 1215 | list_add_tail(&txd->node, &plchan->desc_list); |
e8689e63 LW |
1216 | |
1217 | /* | |
1218 | * See if we already have a physical channel allocated, | |
1219 | * else this is the time to try to get one. | |
1220 | */ | |
1221 | ret = prep_phy_channel(plchan, txd); | |
1222 | if (ret) { | |
1223 | /* | |
1224 | * No physical channel available, we will | |
1225 | * stack up the memcpy channels until there is a channel | |
1226 | * available to handle it whereas slave transfers may | |
1227 | * have been denied due to platform channel muxing restrictions | |
1228 | * and since there is no guarantee that this will ever be | |
e8b5e11d RKAL |
1229 | * resolved, and since the signal must be acquired AFTER |
1230 | * acquiring the physical channel, we will let them be NACK:ed | |
e8689e63 LW |
1231 | * with -EBUSY here. The drivers can alway retry the prep() |
1232 | * call if they are eager on doing this using DMA. | |
1233 | */ | |
1234 | if (plchan->slave) { | |
1235 | pl08x_free_txd_list(pl08x, plchan); | |
1236 | spin_unlock_irqrestore(&plchan->lock, plchan->lockflags); | |
1237 | return -EBUSY; | |
1238 | } | |
1239 | /* Do this memcpy whenever there is a channel ready */ | |
1240 | plchan->state = PL08X_CHAN_WAITING; | |
1241 | plchan->waiting = txd; | |
1242 | } else | |
1243 | /* | |
1244 | * Else we're all set, paused and ready to roll, | |
1245 | * status will switch to PL08X_CHAN_RUNNING when | |
1246 | * we call issue_pending(). If there is something | |
1247 | * running on the channel already we don't change | |
1248 | * its state. | |
1249 | */ | |
1250 | if (plchan->state == PL08X_CHAN_IDLE) | |
1251 | plchan->state = PL08X_CHAN_PAUSED; | |
1252 | ||
1253 | /* | |
1254 | * Notice that we leave plchan->lock locked on purpose: | |
1255 | * it will be unlocked in the subsequent tx_submit() | |
1256 | * call. This is a consequence of the current API. | |
1257 | */ | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
30749cb4 RKAL |
1262 | /* |
1263 | * Given the source and destination available bus masks, select which | |
1264 | * will be routed to each port. We try to have source and destination | |
1265 | * on separate ports, but always respect the allowable settings. | |
1266 | */ | |
1267 | static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst) | |
1268 | { | |
1269 | u32 cctl = 0; | |
1270 | ||
1271 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1272 | cctl |= PL080_CONTROL_DST_AHB2; | |
1273 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1274 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1275 | ||
1276 | return cctl; | |
1277 | } | |
1278 | ||
ac3cd20d RKAL |
1279 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
1280 | { | |
1281 | struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT); | |
1282 | ||
1283 | if (txd) { | |
1284 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
1285 | txd->tx.tx_submit = pl08x_tx_submit; | |
1286 | INIT_LIST_HEAD(&txd->node); | |
4983a04f RKAL |
1287 | |
1288 | /* Always enable error and terminal interrupts */ | |
1289 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1290 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1291 | } |
1292 | return txd; | |
1293 | } | |
1294 | ||
e8689e63 LW |
1295 | /* |
1296 | * Initialize a descriptor to be used by memcpy submit | |
1297 | */ | |
1298 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1299 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1300 | size_t len, unsigned long flags) | |
1301 | { | |
1302 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1303 | struct pl08x_driver_data *pl08x = plchan->host; | |
1304 | struct pl08x_txd *txd; | |
1305 | int ret; | |
1306 | ||
ac3cd20d | 1307 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1308 | if (!txd) { |
1309 | dev_err(&pl08x->adev->dev, | |
1310 | "%s no memory for descriptor\n", __func__); | |
1311 | return NULL; | |
1312 | } | |
1313 | ||
e8689e63 LW |
1314 | txd->direction = DMA_NONE; |
1315 | txd->srcbus.addr = src; | |
1316 | txd->dstbus.addr = dest; | |
c7da9a56 | 1317 | txd->len = len; |
e8689e63 LW |
1318 | |
1319 | /* Set platform data for m2m */ | |
4983a04f | 1320 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
c7da9a56 RKAL |
1321 | txd->cctl = pl08x->pd->memcpy_channel.cctl & |
1322 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
4983a04f | 1323 | |
e8689e63 | 1324 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1325 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1326 | |
c7da9a56 | 1327 | if (pl08x->vd->dualmaster) |
30749cb4 RKAL |
1328 | txd->cctl |= pl08x_select_bus(pl08x, |
1329 | pl08x->mem_buses, pl08x->mem_buses); | |
e8689e63 | 1330 | |
e8689e63 LW |
1331 | ret = pl08x_prep_channel_resources(plchan, txd); |
1332 | if (ret) | |
1333 | return NULL; | |
1334 | /* | |
1335 | * NB: the channel lock is held at this point so tx_submit() | |
1336 | * must be called in direct succession. | |
1337 | */ | |
1338 | ||
1339 | return &txd->tx; | |
1340 | } | |
1341 | ||
3e2a037c | 1342 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 LW |
1343 | struct dma_chan *chan, struct scatterlist *sgl, |
1344 | unsigned int sg_len, enum dma_data_direction direction, | |
1345 | unsigned long flags) | |
1346 | { | |
1347 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1348 | struct pl08x_driver_data *pl08x = plchan->host; | |
1349 | struct pl08x_txd *txd; | |
30749cb4 | 1350 | u8 src_buses, dst_buses; |
e8689e63 LW |
1351 | int ret; |
1352 | ||
1353 | /* | |
1354 | * Current implementation ASSUMES only one sg | |
1355 | */ | |
1356 | if (sg_len != 1) { | |
1357 | dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n", | |
1358 | __func__); | |
1359 | BUG(); | |
1360 | } | |
1361 | ||
1362 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
1363 | __func__, sgl->length, plchan->name); | |
1364 | ||
ac3cd20d | 1365 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1366 | if (!txd) { |
1367 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1368 | return NULL; | |
1369 | } | |
1370 | ||
e8689e63 LW |
1371 | if (direction != plchan->runtime_direction) |
1372 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1373 | "the direction configured for the PrimeCell\n", | |
1374 | __func__); | |
1375 | ||
1376 | /* | |
1377 | * Set up addresses, the PrimeCell configured address | |
1378 | * will take precedence since this may configure the | |
1379 | * channel target address dynamically at runtime. | |
1380 | */ | |
1381 | txd->direction = direction; | |
c7da9a56 RKAL |
1382 | txd->len = sgl->length; |
1383 | ||
1cae78f1 | 1384 | txd->cctl = plchan->cd->cctl & |
c7da9a56 RKAL |
1385 | ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | |
1386 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1cae78f1 RKAL |
1387 | PL080_CONTROL_PROT_MASK); |
1388 | ||
1389 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1390 | txd->cctl |= PL080_CONTROL_PROT_SYS; | |
70b5ed6b | 1391 | |
e8689e63 | 1392 | if (direction == DMA_TO_DEVICE) { |
4983a04f | 1393 | txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
1cae78f1 | 1394 | txd->cctl |= PL080_CONTROL_SRC_INCR; |
e8689e63 LW |
1395 | txd->srcbus.addr = sgl->dma_address; |
1396 | if (plchan->runtime_addr) | |
1397 | txd->dstbus.addr = plchan->runtime_addr; | |
1398 | else | |
1399 | txd->dstbus.addr = plchan->cd->addr; | |
30749cb4 RKAL |
1400 | src_buses = pl08x->mem_buses; |
1401 | dst_buses = plchan->cd->periph_buses; | |
e8689e63 | 1402 | } else if (direction == DMA_FROM_DEVICE) { |
4983a04f | 1403 | txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
1cae78f1 | 1404 | txd->cctl |= PL080_CONTROL_DST_INCR; |
e8689e63 LW |
1405 | if (plchan->runtime_addr) |
1406 | txd->srcbus.addr = plchan->runtime_addr; | |
1407 | else | |
1408 | txd->srcbus.addr = plchan->cd->addr; | |
1409 | txd->dstbus.addr = sgl->dma_address; | |
30749cb4 RKAL |
1410 | src_buses = plchan->cd->periph_buses; |
1411 | dst_buses = pl08x->mem_buses; | |
e8689e63 LW |
1412 | } else { |
1413 | dev_err(&pl08x->adev->dev, | |
1414 | "%s direction unsupported\n", __func__); | |
1415 | return NULL; | |
1416 | } | |
e8689e63 | 1417 | |
30749cb4 RKAL |
1418 | txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses); |
1419 | ||
e8689e63 LW |
1420 | ret = pl08x_prep_channel_resources(plchan, txd); |
1421 | if (ret) | |
1422 | return NULL; | |
1423 | /* | |
1424 | * NB: the channel lock is held at this point so tx_submit() | |
1425 | * must be called in direct succession. | |
1426 | */ | |
1427 | ||
1428 | return &txd->tx; | |
1429 | } | |
1430 | ||
1431 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1432 | unsigned long arg) | |
1433 | { | |
1434 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1435 | struct pl08x_driver_data *pl08x = plchan->host; | |
1436 | unsigned long flags; | |
1437 | int ret = 0; | |
1438 | ||
1439 | /* Controls applicable to inactive channels */ | |
1440 | if (cmd == DMA_SLAVE_CONFIG) { | |
1441 | dma_set_runtime_config(chan, | |
1442 | (struct dma_slave_config *) | |
1443 | arg); | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | /* | |
1448 | * Anything succeeds on channels with no physical allocation and | |
1449 | * no queued transfers. | |
1450 | */ | |
1451 | spin_lock_irqsave(&plchan->lock, flags); | |
1452 | if (!plchan->phychan && !plchan->at) { | |
1453 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | switch (cmd) { | |
1458 | case DMA_TERMINATE_ALL: | |
1459 | plchan->state = PL08X_CHAN_IDLE; | |
1460 | ||
1461 | if (plchan->phychan) { | |
1462 | pl08x_stop_phy_chan(plchan->phychan); | |
1463 | ||
1464 | /* | |
1465 | * Mark physical channel as free and free any slave | |
1466 | * signal | |
1467 | */ | |
8c8cc2b1 | 1468 | release_phy_channel(plchan); |
e8689e63 | 1469 | } |
e8689e63 LW |
1470 | /* Dequeue jobs and free LLIs */ |
1471 | if (plchan->at) { | |
1472 | pl08x_free_txd(pl08x, plchan->at); | |
1473 | plchan->at = NULL; | |
1474 | } | |
1475 | /* Dequeue jobs not yet fired as well */ | |
1476 | pl08x_free_txd_list(pl08x, plchan); | |
1477 | break; | |
1478 | case DMA_PAUSE: | |
1479 | pl08x_pause_phy_chan(plchan->phychan); | |
1480 | plchan->state = PL08X_CHAN_PAUSED; | |
1481 | break; | |
1482 | case DMA_RESUME: | |
1483 | pl08x_resume_phy_chan(plchan->phychan); | |
1484 | plchan->state = PL08X_CHAN_RUNNING; | |
1485 | break; | |
1486 | default: | |
1487 | /* Unknown command */ | |
1488 | ret = -ENXIO; | |
1489 | break; | |
1490 | } | |
1491 | ||
1492 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1493 | ||
1494 | return ret; | |
1495 | } | |
1496 | ||
1497 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1498 | { | |
1499 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1500 | char *name = chan_id; | |
1501 | ||
1502 | /* Check that the channel is not taken! */ | |
1503 | if (!strcmp(plchan->name, name)) | |
1504 | return true; | |
1505 | ||
1506 | return false; | |
1507 | } | |
1508 | ||
1509 | /* | |
1510 | * Just check that the device is there and active | |
1511 | * TODO: turn this bit on/off depending on the number of | |
1512 | * physical channels actually used, if it is zero... well | |
1513 | * shut it off. That will save some power. Cut the clock | |
1514 | * at the same time. | |
1515 | */ | |
1516 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1517 | { | |
1518 | u32 val; | |
1519 | ||
1520 | val = readl(pl08x->base + PL080_CONFIG); | |
1521 | val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE); | |
e8b5e11d | 1522 | /* We implicitly clear bit 1 and that means little-endian mode */ |
e8689e63 LW |
1523 | val |= PL080_CONFIG_ENABLE; |
1524 | writel(val, pl08x->base + PL080_CONFIG); | |
1525 | } | |
1526 | ||
1527 | static void pl08x_tasklet(unsigned long data) | |
1528 | { | |
1529 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1530 | struct pl08x_driver_data *pl08x = plchan->host; |
858c21c0 RKAL |
1531 | struct pl08x_txd *txd; |
1532 | dma_async_tx_callback callback = NULL; | |
1533 | void *callback_param = NULL; | |
bf072af4 | 1534 | unsigned long flags; |
e8689e63 | 1535 | |
bf072af4 | 1536 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1537 | |
858c21c0 RKAL |
1538 | txd = plchan->at; |
1539 | plchan->at = NULL; | |
e8689e63 | 1540 | |
858c21c0 RKAL |
1541 | if (txd) { |
1542 | callback = txd->tx.callback; | |
1543 | callback_param = txd->tx.callback_param; | |
e8689e63 LW |
1544 | |
1545 | /* | |
858c21c0 | 1546 | * Update last completed |
e8689e63 | 1547 | */ |
858c21c0 | 1548 | plchan->lc = txd->tx.cookie; |
e8689e63 | 1549 | |
e8689e63 | 1550 | /* |
b58b6b5b | 1551 | * Free the descriptor |
e8689e63 | 1552 | */ |
858c21c0 | 1553 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1554 | } |
1555 | /* | |
1556 | * If a new descriptor is queued, set it up | |
1557 | * plchan->at is NULL here | |
1558 | */ | |
1559 | if (!list_empty(&plchan->desc_list)) { | |
1560 | struct pl08x_txd *next; | |
1561 | ||
1562 | next = list_first_entry(&plchan->desc_list, | |
1563 | struct pl08x_txd, | |
1564 | node); | |
1565 | list_del(&next->node); | |
c885bee4 RKAL |
1566 | |
1567 | pl08x_start_txd(plchan, next); | |
e8689e63 LW |
1568 | } else { |
1569 | struct pl08x_dma_chan *waiting = NULL; | |
1570 | ||
1571 | /* | |
1572 | * No more jobs, so free up the physical channel | |
1573 | * Free any allocated signal on slave transfers too | |
1574 | */ | |
8c8cc2b1 | 1575 | release_phy_channel(plchan); |
e8689e63 LW |
1576 | plchan->state = PL08X_CHAN_IDLE; |
1577 | ||
1578 | /* | |
1579 | * And NOW before anyone else can grab that free:d | |
1580 | * up physical channel, see if there is some memcpy | |
1581 | * pending that seriously needs to start because of | |
1582 | * being stacked up while we were choking the | |
1583 | * physical channels with data. | |
1584 | */ | |
1585 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1586 | chan.device_node) { | |
1587 | if (waiting->state == PL08X_CHAN_WAITING && | |
1588 | waiting->waiting != NULL) { | |
1589 | int ret; | |
1590 | ||
1591 | /* This should REALLY not fail now */ | |
1592 | ret = prep_phy_channel(waiting, | |
1593 | waiting->waiting); | |
1594 | BUG_ON(ret); | |
1595 | waiting->state = PL08X_CHAN_RUNNING; | |
1596 | waiting->waiting = NULL; | |
1597 | pl08x_issue_pending(&waiting->chan); | |
1598 | break; | |
1599 | } | |
1600 | } | |
1601 | } | |
1602 | ||
bf072af4 | 1603 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 RKAL |
1604 | |
1605 | /* Callback to signal completion */ | |
1606 | if (callback) | |
1607 | callback(callback_param); | |
e8689e63 LW |
1608 | } |
1609 | ||
1610 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1611 | { | |
1612 | struct pl08x_driver_data *pl08x = dev; | |
1613 | u32 mask = 0; | |
1614 | u32 val; | |
1615 | int i; | |
1616 | ||
1617 | val = readl(pl08x->base + PL080_ERR_STATUS); | |
1618 | if (val) { | |
1619 | /* | |
1620 | * An error interrupt (on one or more channels) | |
1621 | */ | |
1622 | dev_err(&pl08x->adev->dev, | |
1623 | "%s error interrupt, register value 0x%08x\n", | |
1624 | __func__, val); | |
1625 | /* | |
1626 | * Simply clear ALL PL08X error interrupts, | |
1627 | * regardless of channel and cause | |
1628 | * FIXME: should be 0x00000003 on PL081 really. | |
1629 | */ | |
1630 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
1631 | } | |
1632 | val = readl(pl08x->base + PL080_INT_STATUS); | |
1633 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1634 | if ((1 << i) & val) { | |
1635 | /* Locate physical channel */ | |
1636 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1637 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1638 | ||
1639 | /* Schedule tasklet on this channel */ | |
1640 | tasklet_schedule(&plchan->tasklet); | |
1641 | ||
1642 | mask |= (1 << i); | |
1643 | } | |
1644 | } | |
1645 | /* | |
1646 | * Clear only the terminal interrupts on channels we processed | |
1647 | */ | |
1648 | writel(mask, pl08x->base + PL080_TC_CLEAR); | |
1649 | ||
1650 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1651 | } | |
1652 | ||
1653 | /* | |
1654 | * Initialise the DMAC memcpy/slave channels. | |
1655 | * Make a local wrapper to hold required data | |
1656 | */ | |
1657 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
1658 | struct dma_device *dmadev, | |
1659 | unsigned int channels, | |
1660 | bool slave) | |
1661 | { | |
1662 | struct pl08x_dma_chan *chan; | |
1663 | int i; | |
1664 | ||
1665 | INIT_LIST_HEAD(&dmadev->channels); | |
1666 | /* | |
1667 | * Register as many many memcpy as we have physical channels, | |
1668 | * we won't always be able to use all but the code will have | |
1669 | * to cope with that situation. | |
1670 | */ | |
1671 | for (i = 0; i < channels; i++) { | |
1672 | chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL); | |
1673 | if (!chan) { | |
1674 | dev_err(&pl08x->adev->dev, | |
1675 | "%s no memory for channel\n", __func__); | |
1676 | return -ENOMEM; | |
1677 | } | |
1678 | ||
1679 | chan->host = pl08x; | |
1680 | chan->state = PL08X_CHAN_IDLE; | |
1681 | ||
1682 | if (slave) { | |
1683 | chan->slave = true; | |
1684 | chan->name = pl08x->pd->slave_channels[i].bus_id; | |
1685 | chan->cd = &pl08x->pd->slave_channels[i]; | |
1686 | } else { | |
1687 | chan->cd = &pl08x->pd->memcpy_channel; | |
1688 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1689 | if (!chan->name) { | |
1690 | kfree(chan); | |
1691 | return -ENOMEM; | |
1692 | } | |
1693 | } | |
b58b6b5b RKAL |
1694 | if (chan->cd->circular_buffer) { |
1695 | dev_err(&pl08x->adev->dev, | |
1696 | "channel %s: circular buffers not supported\n", | |
1697 | chan->name); | |
1698 | kfree(chan); | |
1699 | continue; | |
1700 | } | |
e8689e63 LW |
1701 | dev_info(&pl08x->adev->dev, |
1702 | "initialize virtual channel \"%s\"\n", | |
1703 | chan->name); | |
1704 | ||
1705 | chan->chan.device = dmadev; | |
91aa5fad RKAL |
1706 | chan->chan.cookie = 0; |
1707 | chan->lc = 0; | |
e8689e63 LW |
1708 | |
1709 | spin_lock_init(&chan->lock); | |
1710 | INIT_LIST_HEAD(&chan->desc_list); | |
1711 | tasklet_init(&chan->tasklet, pl08x_tasklet, | |
1712 | (unsigned long) chan); | |
1713 | ||
1714 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1715 | } | |
1716 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1717 | i, slave ? "slave" : "memcpy"); | |
1718 | return i; | |
1719 | } | |
1720 | ||
1721 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1722 | { | |
1723 | struct pl08x_dma_chan *chan = NULL; | |
1724 | struct pl08x_dma_chan *next; | |
1725 | ||
1726 | list_for_each_entry_safe(chan, | |
1727 | next, &dmadev->channels, chan.device_node) { | |
1728 | list_del(&chan->chan.device_node); | |
1729 | kfree(chan); | |
1730 | } | |
1731 | } | |
1732 | ||
1733 | #ifdef CONFIG_DEBUG_FS | |
1734 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1735 | { | |
1736 | switch (state) { | |
1737 | case PL08X_CHAN_IDLE: | |
1738 | return "idle"; | |
1739 | case PL08X_CHAN_RUNNING: | |
1740 | return "running"; | |
1741 | case PL08X_CHAN_PAUSED: | |
1742 | return "paused"; | |
1743 | case PL08X_CHAN_WAITING: | |
1744 | return "waiting"; | |
1745 | default: | |
1746 | break; | |
1747 | } | |
1748 | return "UNKNOWN STATE"; | |
1749 | } | |
1750 | ||
1751 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1752 | { | |
1753 | struct pl08x_driver_data *pl08x = s->private; | |
1754 | struct pl08x_dma_chan *chan; | |
1755 | struct pl08x_phy_chan *ch; | |
1756 | unsigned long flags; | |
1757 | int i; | |
1758 | ||
1759 | seq_printf(s, "PL08x physical channels:\n"); | |
1760 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1761 | seq_printf(s, "--------\t-----\n"); | |
1762 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1763 | struct pl08x_dma_chan *virt_chan; | |
1764 | ||
1765 | ch = &pl08x->phy_chans[i]; | |
1766 | ||
1767 | spin_lock_irqsave(&ch->lock, flags); | |
1768 | virt_chan = ch->serving; | |
1769 | ||
1770 | seq_printf(s, "%d\t\t%s\n", | |
1771 | ch->id, virt_chan ? virt_chan->name : "(none)"); | |
1772 | ||
1773 | spin_unlock_irqrestore(&ch->lock, flags); | |
1774 | } | |
1775 | ||
1776 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1777 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1778 | seq_printf(s, "--------\t------\n"); | |
1779 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1780 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1781 | pl08x_state_str(chan->state)); |
1782 | } | |
1783 | ||
1784 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1785 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1786 | seq_printf(s, "--------\t------\n"); | |
1787 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1788 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1789 | pl08x_state_str(chan->state)); |
1790 | } | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
1795 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1796 | { | |
1797 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1798 | } | |
1799 | ||
1800 | static const struct file_operations pl08x_debugfs_operations = { | |
1801 | .open = pl08x_debugfs_open, | |
1802 | .read = seq_read, | |
1803 | .llseek = seq_lseek, | |
1804 | .release = single_release, | |
1805 | }; | |
1806 | ||
1807 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1808 | { | |
1809 | /* Expose a simple debugfs interface to view all clocks */ | |
1810 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO, | |
1811 | NULL, pl08x, | |
1812 | &pl08x_debugfs_operations); | |
1813 | } | |
1814 | ||
1815 | #else | |
1816 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1817 | { | |
1818 | } | |
1819 | #endif | |
1820 | ||
1821 | static int pl08x_probe(struct amba_device *adev, struct amba_id *id) | |
1822 | { | |
1823 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1824 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1825 | int ret = 0; |
1826 | int i; | |
1827 | ||
1828 | ret = amba_request_regions(adev, NULL); | |
1829 | if (ret) | |
1830 | return ret; | |
1831 | ||
1832 | /* Create the driver state holder */ | |
1833 | pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL); | |
1834 | if (!pl08x) { | |
1835 | ret = -ENOMEM; | |
1836 | goto out_no_pl08x; | |
1837 | } | |
1838 | ||
1839 | /* Initialize memcpy engine */ | |
1840 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1841 | pl08x->memcpy.dev = &adev->dev; | |
1842 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1843 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1844 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1845 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1846 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1847 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1848 | pl08x->memcpy.device_control = pl08x_control; | |
1849 | ||
1850 | /* Initialize slave engine */ | |
1851 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1852 | pl08x->slave.dev = &adev->dev; | |
1853 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1854 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1855 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1856 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1857 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1858 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1859 | pl08x->slave.device_control = pl08x_control; | |
1860 | ||
1861 | /* Get the platform data */ | |
1862 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1863 | if (!pl08x->pd) { | |
1864 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1865 | goto out_no_platdata; | |
1866 | } | |
1867 | ||
1868 | /* Assign useful pointers to the driver state */ | |
1869 | pl08x->adev = adev; | |
1870 | pl08x->vd = vd; | |
1871 | ||
30749cb4 RKAL |
1872 | /* By default, AHB1 only. If dualmaster, from platform */ |
1873 | pl08x->lli_buses = PL08X_AHB1; | |
1874 | pl08x->mem_buses = PL08X_AHB1; | |
1875 | if (pl08x->vd->dualmaster) { | |
1876 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1877 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1878 | } | |
1879 | ||
e8689e63 LW |
1880 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1881 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1882 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1883 | if (!pl08x->pool) { | |
1884 | ret = -ENOMEM; | |
1885 | goto out_no_lli_pool; | |
1886 | } | |
1887 | ||
1888 | spin_lock_init(&pl08x->lock); | |
1889 | ||
1890 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); | |
1891 | if (!pl08x->base) { | |
1892 | ret = -ENOMEM; | |
1893 | goto out_no_ioremap; | |
1894 | } | |
1895 | ||
1896 | /* Turn on the PL08x */ | |
1897 | pl08x_ensure_on(pl08x); | |
1898 | ||
1899 | /* | |
1900 | * Attach the interrupt handler | |
1901 | */ | |
1902 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
1903 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1904 | ||
1905 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1906 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1907 | if (ret) { |
1908 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1909 | __func__, adev->irq[0]); | |
1910 | goto out_no_irq; | |
1911 | } | |
1912 | ||
1913 | /* Initialize physical channels */ | |
1914 | pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)), | |
1915 | GFP_KERNEL); | |
1916 | if (!pl08x->phy_chans) { | |
1917 | dev_err(&adev->dev, "%s failed to allocate " | |
1918 | "physical channel holders\n", | |
1919 | __func__); | |
1920 | goto out_no_phychans; | |
1921 | } | |
1922 | ||
1923 | for (i = 0; i < vd->channels; i++) { | |
1924 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1925 | ||
1926 | ch->id = i; | |
1927 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1928 | spin_lock_init(&ch->lock); | |
1929 | ch->serving = NULL; | |
1930 | ch->signal = -1; | |
1931 | dev_info(&adev->dev, | |
1932 | "physical channel %d is %s\n", i, | |
1933 | pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
1934 | } | |
1935 | ||
1936 | /* Register as many memcpy channels as there are physical channels */ | |
1937 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1938 | pl08x->vd->channels, false); | |
1939 | if (ret <= 0) { | |
1940 | dev_warn(&pl08x->adev->dev, | |
1941 | "%s failed to enumerate memcpy channels - %d\n", | |
1942 | __func__, ret); | |
1943 | goto out_no_memcpy; | |
1944 | } | |
1945 | pl08x->memcpy.chancnt = ret; | |
1946 | ||
1947 | /* Register slave channels */ | |
1948 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
1949 | pl08x->pd->num_slave_channels, | |
1950 | true); | |
1951 | if (ret <= 0) { | |
1952 | dev_warn(&pl08x->adev->dev, | |
1953 | "%s failed to enumerate slave channels - %d\n", | |
1954 | __func__, ret); | |
1955 | goto out_no_slave; | |
1956 | } | |
1957 | pl08x->slave.chancnt = ret; | |
1958 | ||
1959 | ret = dma_async_device_register(&pl08x->memcpy); | |
1960 | if (ret) { | |
1961 | dev_warn(&pl08x->adev->dev, | |
1962 | "%s failed to register memcpy as an async device - %d\n", | |
1963 | __func__, ret); | |
1964 | goto out_no_memcpy_reg; | |
1965 | } | |
1966 | ||
1967 | ret = dma_async_device_register(&pl08x->slave); | |
1968 | if (ret) { | |
1969 | dev_warn(&pl08x->adev->dev, | |
1970 | "%s failed to register slave as an async device - %d\n", | |
1971 | __func__, ret); | |
1972 | goto out_no_slave_reg; | |
1973 | } | |
1974 | ||
1975 | amba_set_drvdata(adev, pl08x); | |
1976 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
1977 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
1978 | amba_part(adev), amba_rev(adev), | |
1979 | (unsigned long long)adev->res.start, adev->irq[0]); | |
e8689e63 LW |
1980 | return 0; |
1981 | ||
1982 | out_no_slave_reg: | |
1983 | dma_async_device_unregister(&pl08x->memcpy); | |
1984 | out_no_memcpy_reg: | |
1985 | pl08x_free_virtual_channels(&pl08x->slave); | |
1986 | out_no_slave: | |
1987 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
1988 | out_no_memcpy: | |
1989 | kfree(pl08x->phy_chans); | |
1990 | out_no_phychans: | |
1991 | free_irq(adev->irq[0], pl08x); | |
1992 | out_no_irq: | |
1993 | iounmap(pl08x->base); | |
1994 | out_no_ioremap: | |
1995 | dma_pool_destroy(pl08x->pool); | |
1996 | out_no_lli_pool: | |
1997 | out_no_platdata: | |
1998 | kfree(pl08x); | |
1999 | out_no_pl08x: | |
2000 | amba_release_regions(adev); | |
2001 | return ret; | |
2002 | } | |
2003 | ||
2004 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2005 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2006 | .channels = 8, |
2007 | .dualmaster = true, | |
2008 | }; | |
2009 | ||
2010 | static struct vendor_data vendor_pl081 = { | |
e8689e63 LW |
2011 | .channels = 2, |
2012 | .dualmaster = false, | |
2013 | }; | |
2014 | ||
2015 | static struct amba_id pl08x_ids[] = { | |
2016 | /* PL080 */ | |
2017 | { | |
2018 | .id = 0x00041080, | |
2019 | .mask = 0x000fffff, | |
2020 | .data = &vendor_pl080, | |
2021 | }, | |
2022 | /* PL081 */ | |
2023 | { | |
2024 | .id = 0x00041081, | |
2025 | .mask = 0x000fffff, | |
2026 | .data = &vendor_pl081, | |
2027 | }, | |
2028 | /* Nomadik 8815 PL080 variant */ | |
2029 | { | |
2030 | .id = 0x00280880, | |
2031 | .mask = 0x00ffffff, | |
2032 | .data = &vendor_pl080, | |
2033 | }, | |
2034 | { 0, 0 }, | |
2035 | }; | |
2036 | ||
2037 | static struct amba_driver pl08x_amba_driver = { | |
2038 | .drv.name = DRIVER_NAME, | |
2039 | .id_table = pl08x_ids, | |
2040 | .probe = pl08x_probe, | |
2041 | }; | |
2042 | ||
2043 | static int __init pl08x_init(void) | |
2044 | { | |
2045 | int retval; | |
2046 | retval = amba_driver_register(&pl08x_amba_driver); | |
2047 | if (retval) | |
2048 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2049 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2050 | retval); |
2051 | return retval; | |
2052 | } | |
2053 | subsys_initcall(pl08x_init); |