Commit | Line | Data |
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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
c13c8260 CL |
14 | * The full GNU General Public License is included in this distribution in the |
15 | * file called COPYING. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * This code implements the DMA subsystem. It provides a HW-neutral interface | |
20 | * for other kernel code to use asynchronous memory copy capabilities, | |
21 | * if present, and allows different HW DMA drivers to register as providing | |
22 | * this capability. | |
23 | * | |
24 | * Due to the fact we are accelerating what is already a relatively fast | |
25 | * operation, the code goes to great lengths to avoid additional overhead, | |
26 | * such as locking. | |
27 | * | |
28 | * LOCKING: | |
29 | * | |
aa1e6f1a DW |
30 | * The subsystem keeps a global list of dma_device structs it is protected by a |
31 | * mutex, dma_list_mutex. | |
c13c8260 | 32 | * |
f27c580c DW |
33 | * A subsystem can get access to a channel by calling dmaengine_get() followed |
34 | * by dma_find_channel(), or if it has need for an exclusive channel it can call | |
35 | * dma_request_channel(). Once a channel is allocated a reference is taken | |
36 | * against its corresponding driver to disable removal. | |
37 | * | |
c13c8260 CL |
38 | * Each device has a channels list, which runs unlocked but is never modified |
39 | * once the device is registered, it's just setup by the driver. | |
40 | * | |
f27c580c | 41 | * See Documentation/dmaengine.txt for more details |
c13c8260 CL |
42 | */ |
43 | ||
63433250 JP |
44 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
45 | ||
a8135d0d | 46 | #include <linux/platform_device.h> |
b7f080cf | 47 | #include <linux/dma-mapping.h> |
c13c8260 CL |
48 | #include <linux/init.h> |
49 | #include <linux/module.h> | |
7405f74b | 50 | #include <linux/mm.h> |
c13c8260 CL |
51 | #include <linux/device.h> |
52 | #include <linux/dmaengine.h> | |
53 | #include <linux/hardirq.h> | |
54 | #include <linux/spinlock.h> | |
55 | #include <linux/percpu.h> | |
56 | #include <linux/rcupdate.h> | |
57 | #include <linux/mutex.h> | |
7405f74b | 58 | #include <linux/jiffies.h> |
2ba05622 | 59 | #include <linux/rculist.h> |
864498aa | 60 | #include <linux/idr.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
4e82f5dd AS |
62 | #include <linux/acpi.h> |
63 | #include <linux/acpi_dma.h> | |
9a6cecc8 | 64 | #include <linux/of_dma.h> |
45c463ae | 65 | #include <linux/mempool.h> |
c13c8260 CL |
66 | |
67 | static DEFINE_MUTEX(dma_list_mutex); | |
21ef4b8b | 68 | static DEFINE_IDR(dma_idr); |
c13c8260 | 69 | static LIST_HEAD(dma_device_list); |
6f49a57a | 70 | static long dmaengine_ref_count; |
c13c8260 CL |
71 | |
72 | /* --- sysfs implementation --- */ | |
73 | ||
41d5e59c DW |
74 | /** |
75 | * dev_to_dma_chan - convert a device pointer to the its sysfs container object | |
76 | * @dev - device node | |
77 | * | |
78 | * Must be called under dma_list_mutex | |
79 | */ | |
80 | static struct dma_chan *dev_to_dma_chan(struct device *dev) | |
81 | { | |
82 | struct dma_chan_dev *chan_dev; | |
83 | ||
84 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
85 | return chan_dev->chan; | |
86 | } | |
87 | ||
58b267d3 GKH |
88 | static ssize_t memcpy_count_show(struct device *dev, |
89 | struct device_attribute *attr, char *buf) | |
c13c8260 | 90 | { |
41d5e59c | 91 | struct dma_chan *chan; |
c13c8260 CL |
92 | unsigned long count = 0; |
93 | int i; | |
41d5e59c | 94 | int err; |
c13c8260 | 95 | |
41d5e59c DW |
96 | mutex_lock(&dma_list_mutex); |
97 | chan = dev_to_dma_chan(dev); | |
98 | if (chan) { | |
99 | for_each_possible_cpu(i) | |
100 | count += per_cpu_ptr(chan->local, i)->memcpy_count; | |
101 | err = sprintf(buf, "%lu\n", count); | |
102 | } else | |
103 | err = -ENODEV; | |
104 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 105 | |
41d5e59c | 106 | return err; |
c13c8260 | 107 | } |
58b267d3 | 108 | static DEVICE_ATTR_RO(memcpy_count); |
c13c8260 | 109 | |
58b267d3 GKH |
110 | static ssize_t bytes_transferred_show(struct device *dev, |
111 | struct device_attribute *attr, char *buf) | |
c13c8260 | 112 | { |
41d5e59c | 113 | struct dma_chan *chan; |
c13c8260 CL |
114 | unsigned long count = 0; |
115 | int i; | |
41d5e59c | 116 | int err; |
c13c8260 | 117 | |
41d5e59c DW |
118 | mutex_lock(&dma_list_mutex); |
119 | chan = dev_to_dma_chan(dev); | |
120 | if (chan) { | |
121 | for_each_possible_cpu(i) | |
122 | count += per_cpu_ptr(chan->local, i)->bytes_transferred; | |
123 | err = sprintf(buf, "%lu\n", count); | |
124 | } else | |
125 | err = -ENODEV; | |
126 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 127 | |
41d5e59c | 128 | return err; |
c13c8260 | 129 | } |
58b267d3 | 130 | static DEVICE_ATTR_RO(bytes_transferred); |
c13c8260 | 131 | |
58b267d3 GKH |
132 | static ssize_t in_use_show(struct device *dev, struct device_attribute *attr, |
133 | char *buf) | |
c13c8260 | 134 | { |
41d5e59c DW |
135 | struct dma_chan *chan; |
136 | int err; | |
c13c8260 | 137 | |
41d5e59c DW |
138 | mutex_lock(&dma_list_mutex); |
139 | chan = dev_to_dma_chan(dev); | |
140 | if (chan) | |
141 | err = sprintf(buf, "%d\n", chan->client_count); | |
142 | else | |
143 | err = -ENODEV; | |
144 | mutex_unlock(&dma_list_mutex); | |
145 | ||
146 | return err; | |
c13c8260 | 147 | } |
58b267d3 | 148 | static DEVICE_ATTR_RO(in_use); |
c13c8260 | 149 | |
58b267d3 GKH |
150 | static struct attribute *dma_dev_attrs[] = { |
151 | &dev_attr_memcpy_count.attr, | |
152 | &dev_attr_bytes_transferred.attr, | |
153 | &dev_attr_in_use.attr, | |
154 | NULL, | |
c13c8260 | 155 | }; |
58b267d3 | 156 | ATTRIBUTE_GROUPS(dma_dev); |
c13c8260 | 157 | |
41d5e59c DW |
158 | static void chan_dev_release(struct device *dev) |
159 | { | |
160 | struct dma_chan_dev *chan_dev; | |
161 | ||
162 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
864498aa DW |
163 | if (atomic_dec_and_test(chan_dev->idr_ref)) { |
164 | mutex_lock(&dma_list_mutex); | |
165 | idr_remove(&dma_idr, chan_dev->dev_id); | |
166 | mutex_unlock(&dma_list_mutex); | |
167 | kfree(chan_dev->idr_ref); | |
168 | } | |
41d5e59c DW |
169 | kfree(chan_dev); |
170 | } | |
171 | ||
c13c8260 | 172 | static struct class dma_devclass = { |
891f78ea | 173 | .name = "dma", |
58b267d3 | 174 | .dev_groups = dma_dev_groups, |
41d5e59c | 175 | .dev_release = chan_dev_release, |
c13c8260 CL |
176 | }; |
177 | ||
178 | /* --- client and device registration --- */ | |
179 | ||
59b5ec21 DW |
180 | #define dma_device_satisfies_mask(device, mask) \ |
181 | __dma_device_satisfies_mask((device), &(mask)) | |
d379b01e | 182 | static int |
a53e28da LPC |
183 | __dma_device_satisfies_mask(struct dma_device *device, |
184 | const dma_cap_mask_t *want) | |
d379b01e DW |
185 | { |
186 | dma_cap_mask_t has; | |
187 | ||
59b5ec21 | 188 | bitmap_and(has.bits, want->bits, device->cap_mask.bits, |
d379b01e DW |
189 | DMA_TX_TYPE_END); |
190 | return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END); | |
191 | } | |
192 | ||
6f49a57a DW |
193 | static struct module *dma_chan_to_owner(struct dma_chan *chan) |
194 | { | |
195 | return chan->device->dev->driver->owner; | |
196 | } | |
197 | ||
198 | /** | |
199 | * balance_ref_count - catch up the channel reference count | |
200 | * @chan - channel to balance ->client_count versus dmaengine_ref_count | |
201 | * | |
202 | * balance_ref_count must be called under dma_list_mutex | |
203 | */ | |
204 | static void balance_ref_count(struct dma_chan *chan) | |
205 | { | |
206 | struct module *owner = dma_chan_to_owner(chan); | |
207 | ||
208 | while (chan->client_count < dmaengine_ref_count) { | |
209 | __module_get(owner); | |
210 | chan->client_count++; | |
211 | } | |
212 | } | |
213 | ||
214 | /** | |
215 | * dma_chan_get - try to grab a dma channel's parent driver module | |
216 | * @chan - channel to grab | |
217 | * | |
218 | * Must be called under dma_list_mutex | |
219 | */ | |
220 | static int dma_chan_get(struct dma_chan *chan) | |
221 | { | |
6f49a57a | 222 | struct module *owner = dma_chan_to_owner(chan); |
d2f4f99d | 223 | int ret; |
6f49a57a | 224 | |
d2f4f99d | 225 | /* The channel is already in use, update client count */ |
6f49a57a DW |
226 | if (chan->client_count) { |
227 | __module_get(owner); | |
d2f4f99d MR |
228 | goto out; |
229 | } | |
6f49a57a | 230 | |
d2f4f99d MR |
231 | if (!try_module_get(owner)) |
232 | return -ENODEV; | |
6f49a57a DW |
233 | |
234 | /* allocate upon first client reference */ | |
c4b54a64 MR |
235 | if (chan->device->device_alloc_chan_resources) { |
236 | ret = chan->device->device_alloc_chan_resources(chan); | |
237 | if (ret < 0) | |
238 | goto err_out; | |
239 | } | |
6f49a57a | 240 | |
d2f4f99d MR |
241 | if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) |
242 | balance_ref_count(chan); | |
243 | ||
244 | out: | |
245 | chan->client_count++; | |
246 | return 0; | |
247 | ||
248 | err_out: | |
249 | module_put(owner); | |
250 | return ret; | |
6f49a57a DW |
251 | } |
252 | ||
253 | /** | |
254 | * dma_chan_put - drop a reference to a dma channel's parent driver module | |
255 | * @chan - channel to release | |
256 | * | |
257 | * Must be called under dma_list_mutex | |
258 | */ | |
259 | static void dma_chan_put(struct dma_chan *chan) | |
260 | { | |
c4b54a64 | 261 | /* This channel is not in use, bail out */ |
6f49a57a | 262 | if (!chan->client_count) |
c4b54a64 MR |
263 | return; |
264 | ||
6f49a57a DW |
265 | chan->client_count--; |
266 | module_put(dma_chan_to_owner(chan)); | |
c4b54a64 MR |
267 | |
268 | /* This channel is not in use anymore, free it */ | |
b36f09c3 LPC |
269 | if (!chan->client_count && chan->device->device_free_chan_resources) { |
270 | /* Make sure all operations have completed */ | |
271 | dmaengine_synchronize(chan); | |
6f49a57a | 272 | chan->device->device_free_chan_resources(chan); |
b36f09c3 | 273 | } |
56f13c0d PU |
274 | |
275 | /* If the channel is used via a DMA request router, free the mapping */ | |
276 | if (chan->router && chan->router->route_free) { | |
277 | chan->router->route_free(chan->router->dev, chan->route_data); | |
278 | chan->router = NULL; | |
279 | chan->route_data = NULL; | |
280 | } | |
6f49a57a DW |
281 | } |
282 | ||
7405f74b DW |
283 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) |
284 | { | |
285 | enum dma_status status; | |
286 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); | |
287 | ||
288 | dma_async_issue_pending(chan); | |
289 | do { | |
290 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); | |
291 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
ef859312 | 292 | dev_err(chan->device->dev, "%s: timeout!\n", __func__); |
7405f74b DW |
293 | return DMA_ERROR; |
294 | } | |
2cbe7feb BZ |
295 | if (status != DMA_IN_PROGRESS) |
296 | break; | |
297 | cpu_relax(); | |
298 | } while (1); | |
7405f74b DW |
299 | |
300 | return status; | |
301 | } | |
302 | EXPORT_SYMBOL(dma_sync_wait); | |
303 | ||
bec08513 DW |
304 | /** |
305 | * dma_cap_mask_all - enable iteration over all operation types | |
306 | */ | |
307 | static dma_cap_mask_t dma_cap_mask_all; | |
308 | ||
309 | /** | |
310 | * dma_chan_tbl_ent - tracks channel allocations per core/operation | |
311 | * @chan - associated channel for this entry | |
312 | */ | |
313 | struct dma_chan_tbl_ent { | |
314 | struct dma_chan *chan; | |
315 | }; | |
316 | ||
317 | /** | |
318 | * channel_table - percpu lookup table for memory-to-memory offload providers | |
319 | */ | |
a29d8b8e | 320 | static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END]; |
bec08513 DW |
321 | |
322 | static int __init dma_channel_table_init(void) | |
323 | { | |
324 | enum dma_transaction_type cap; | |
325 | int err = 0; | |
326 | ||
327 | bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END); | |
328 | ||
59b5ec21 DW |
329 | /* 'interrupt', 'private', and 'slave' are channel capabilities, |
330 | * but are not associated with an operation so they do not need | |
331 | * an entry in the channel_table | |
bec08513 DW |
332 | */ |
333 | clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits); | |
59b5ec21 | 334 | clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits); |
bec08513 DW |
335 | clear_bit(DMA_SLAVE, dma_cap_mask_all.bits); |
336 | ||
337 | for_each_dma_cap_mask(cap, dma_cap_mask_all) { | |
338 | channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent); | |
339 | if (!channel_table[cap]) { | |
340 | err = -ENOMEM; | |
341 | break; | |
342 | } | |
343 | } | |
344 | ||
345 | if (err) { | |
63433250 | 346 | pr_err("initialization failure\n"); |
bec08513 | 347 | for_each_dma_cap_mask(cap, dma_cap_mask_all) |
a9507ca3 | 348 | free_percpu(channel_table[cap]); |
bec08513 DW |
349 | } |
350 | ||
351 | return err; | |
352 | } | |
652afc27 | 353 | arch_initcall(dma_channel_table_init); |
bec08513 DW |
354 | |
355 | /** | |
356 | * dma_find_channel - find a channel to carry out the operation | |
357 | * @tx_type: transaction type | |
358 | */ | |
359 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | |
360 | { | |
e7dcaa47 | 361 | return this_cpu_read(channel_table[tx_type]->chan); |
bec08513 DW |
362 | } |
363 | EXPORT_SYMBOL(dma_find_channel); | |
a2bd1140 | 364 | |
2ba05622 DW |
365 | /** |
366 | * dma_issue_pending_all - flush all pending operations across all channels | |
367 | */ | |
368 | void dma_issue_pending_all(void) | |
369 | { | |
370 | struct dma_device *device; | |
371 | struct dma_chan *chan; | |
372 | ||
2ba05622 | 373 | rcu_read_lock(); |
59b5ec21 DW |
374 | list_for_each_entry_rcu(device, &dma_device_list, global_node) { |
375 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
376 | continue; | |
2ba05622 DW |
377 | list_for_each_entry(chan, &device->channels, device_node) |
378 | if (chan->client_count) | |
379 | device->device_issue_pending(chan); | |
59b5ec21 | 380 | } |
2ba05622 DW |
381 | rcu_read_unlock(); |
382 | } | |
383 | EXPORT_SYMBOL(dma_issue_pending_all); | |
384 | ||
bec08513 | 385 | /** |
c4d27c4d BG |
386 | * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu |
387 | */ | |
388 | static bool dma_chan_is_local(struct dma_chan *chan, int cpu) | |
389 | { | |
390 | int node = dev_to_node(chan->device->dev); | |
391 | return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node)); | |
392 | } | |
393 | ||
394 | /** | |
395 | * min_chan - returns the channel with min count and in the same numa-node as the cpu | |
bec08513 | 396 | * @cap: capability to match |
c4d27c4d | 397 | * @cpu: cpu index which the channel should be close to |
bec08513 | 398 | * |
c4d27c4d BG |
399 | * If some channels are close to the given cpu, the one with the lowest |
400 | * reference count is returned. Otherwise, cpu is ignored and only the | |
401 | * reference count is taken into account. | |
402 | * Must be called under dma_list_mutex. | |
bec08513 | 403 | */ |
c4d27c4d | 404 | static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu) |
bec08513 DW |
405 | { |
406 | struct dma_device *device; | |
407 | struct dma_chan *chan; | |
bec08513 | 408 | struct dma_chan *min = NULL; |
c4d27c4d | 409 | struct dma_chan *localmin = NULL; |
bec08513 DW |
410 | |
411 | list_for_each_entry(device, &dma_device_list, global_node) { | |
59b5ec21 DW |
412 | if (!dma_has_cap(cap, device->cap_mask) || |
413 | dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
bec08513 DW |
414 | continue; |
415 | list_for_each_entry(chan, &device->channels, device_node) { | |
416 | if (!chan->client_count) | |
417 | continue; | |
c4d27c4d | 418 | if (!min || chan->table_count < min->table_count) |
bec08513 DW |
419 | min = chan; |
420 | ||
c4d27c4d BG |
421 | if (dma_chan_is_local(chan, cpu)) |
422 | if (!localmin || | |
423 | chan->table_count < localmin->table_count) | |
424 | localmin = chan; | |
bec08513 | 425 | } |
bec08513 DW |
426 | } |
427 | ||
c4d27c4d | 428 | chan = localmin ? localmin : min; |
bec08513 | 429 | |
c4d27c4d BG |
430 | if (chan) |
431 | chan->table_count++; | |
bec08513 | 432 | |
c4d27c4d | 433 | return chan; |
bec08513 DW |
434 | } |
435 | ||
436 | /** | |
437 | * dma_channel_rebalance - redistribute the available channels | |
438 | * | |
439 | * Optimize for cpu isolation (each cpu gets a dedicated channel for an | |
440 | * operation type) in the SMP case, and operation isolation (avoid | |
441 | * multi-tasking channels) in the non-SMP case. Must be called under | |
442 | * dma_list_mutex. | |
443 | */ | |
444 | static void dma_channel_rebalance(void) | |
445 | { | |
446 | struct dma_chan *chan; | |
447 | struct dma_device *device; | |
448 | int cpu; | |
449 | int cap; | |
bec08513 DW |
450 | |
451 | /* undo the last distribution */ | |
452 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
453 | for_each_possible_cpu(cpu) | |
454 | per_cpu_ptr(channel_table[cap], cpu)->chan = NULL; | |
455 | ||
59b5ec21 DW |
456 | list_for_each_entry(device, &dma_device_list, global_node) { |
457 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
458 | continue; | |
bec08513 DW |
459 | list_for_each_entry(chan, &device->channels, device_node) |
460 | chan->table_count = 0; | |
59b5ec21 | 461 | } |
bec08513 DW |
462 | |
463 | /* don't populate the channel_table if no clients are available */ | |
464 | if (!dmaengine_ref_count) | |
465 | return; | |
466 | ||
467 | /* redistribute available channels */ | |
bec08513 DW |
468 | for_each_dma_cap_mask(cap, dma_cap_mask_all) |
469 | for_each_online_cpu(cpu) { | |
c4d27c4d | 470 | chan = min_chan(cap, cpu); |
bec08513 DW |
471 | per_cpu_ptr(channel_table[cap], cpu)->chan = chan; |
472 | } | |
473 | } | |
474 | ||
0d5484b1 LP |
475 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) |
476 | { | |
477 | struct dma_device *device; | |
478 | ||
479 | if (!chan || !caps) | |
480 | return -EINVAL; | |
481 | ||
482 | device = chan->device; | |
483 | ||
484 | /* check if the channel supports slave transactions */ | |
dd4e91d5 AS |
485 | if (!(test_bit(DMA_SLAVE, device->cap_mask.bits) || |
486 | test_bit(DMA_CYCLIC, device->cap_mask.bits))) | |
0d5484b1 LP |
487 | return -ENXIO; |
488 | ||
489 | /* | |
490 | * Check whether it reports it uses the generic slave | |
491 | * capabilities, if not, that means it doesn't support any | |
492 | * kind of slave capabilities reporting. | |
493 | */ | |
494 | if (!device->directions) | |
495 | return -ENXIO; | |
496 | ||
497 | caps->src_addr_widths = device->src_addr_widths; | |
498 | caps->dst_addr_widths = device->dst_addr_widths; | |
499 | caps->directions = device->directions; | |
6d5bbed3 | 500 | caps->max_burst = device->max_burst; |
0d5484b1 | 501 | caps->residue_granularity = device->residue_granularity; |
9eeacd3a | 502 | caps->descriptor_reuse = device->descriptor_reuse; |
0d5484b1 | 503 | |
88d04643 KK |
504 | /* |
505 | * Some devices implement only pause (e.g. to get residuum) but no | |
506 | * resume. However cmd_pause is advertised as pause AND resume. | |
507 | */ | |
508 | caps->cmd_pause = !!(device->device_pause && device->device_resume); | |
0d5484b1 LP |
509 | caps->cmd_terminate = !!device->device_terminate_all; |
510 | ||
511 | return 0; | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(dma_get_slave_caps); | |
514 | ||
a53e28da LPC |
515 | static struct dma_chan *private_candidate(const dma_cap_mask_t *mask, |
516 | struct dma_device *dev, | |
e2346677 | 517 | dma_filter_fn fn, void *fn_param) |
59b5ec21 DW |
518 | { |
519 | struct dma_chan *chan; | |
59b5ec21 | 520 | |
26b64256 | 521 | if (mask && !__dma_device_satisfies_mask(dev, mask)) { |
ef859312 | 522 | dev_dbg(dev->dev, "%s: wrong capabilities\n", __func__); |
59b5ec21 DW |
523 | return NULL; |
524 | } | |
525 | /* devices with multiple channels need special handling as we need to | |
526 | * ensure that all channels are either private or public. | |
527 | */ | |
528 | if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask)) | |
529 | list_for_each_entry(chan, &dev->channels, device_node) { | |
530 | /* some channels are already publicly allocated */ | |
531 | if (chan->client_count) | |
532 | return NULL; | |
533 | } | |
534 | ||
535 | list_for_each_entry(chan, &dev->channels, device_node) { | |
536 | if (chan->client_count) { | |
ef859312 | 537 | dev_dbg(dev->dev, "%s: %s busy\n", |
41d5e59c | 538 | __func__, dma_chan_name(chan)); |
59b5ec21 DW |
539 | continue; |
540 | } | |
e2346677 | 541 | if (fn && !fn(chan, fn_param)) { |
ef859312 | 542 | dev_dbg(dev->dev, "%s: %s filter said false\n", |
e2346677 DW |
543 | __func__, dma_chan_name(chan)); |
544 | continue; | |
545 | } | |
546 | return chan; | |
59b5ec21 DW |
547 | } |
548 | ||
e2346677 | 549 | return NULL; |
59b5ec21 DW |
550 | } |
551 | ||
7bd903c5 PU |
552 | static struct dma_chan *find_candidate(struct dma_device *device, |
553 | const dma_cap_mask_t *mask, | |
554 | dma_filter_fn fn, void *fn_param) | |
555 | { | |
556 | struct dma_chan *chan = private_candidate(mask, device, fn, fn_param); | |
557 | int err; | |
558 | ||
559 | if (chan) { | |
560 | /* Found a suitable channel, try to grab, prep, and return it. | |
561 | * We first set DMA_PRIVATE to disable balance_ref_count as this | |
562 | * channel will not be published in the general-purpose | |
563 | * allocator | |
564 | */ | |
565 | dma_cap_set(DMA_PRIVATE, device->cap_mask); | |
566 | device->privatecnt++; | |
567 | err = dma_chan_get(chan); | |
568 | ||
569 | if (err) { | |
570 | if (err == -ENODEV) { | |
ef859312 JN |
571 | dev_dbg(device->dev, "%s: %s module removed\n", |
572 | __func__, dma_chan_name(chan)); | |
7bd903c5 PU |
573 | list_del_rcu(&device->global_node); |
574 | } else | |
ef859312 JN |
575 | dev_dbg(device->dev, |
576 | "%s: failed to get %s: (%d)\n", | |
7bd903c5 PU |
577 | __func__, dma_chan_name(chan), err); |
578 | ||
579 | if (--device->privatecnt == 0) | |
580 | dma_cap_clear(DMA_PRIVATE, device->cap_mask); | |
581 | ||
582 | chan = ERR_PTR(err); | |
583 | } | |
584 | } | |
585 | ||
586 | return chan ? chan : ERR_PTR(-EPROBE_DEFER); | |
587 | } | |
588 | ||
59b5ec21 | 589 | /** |
19d643d6 | 590 | * dma_get_slave_channel - try to get specific channel exclusively |
7bb587f4 ZG |
591 | * @chan: target channel |
592 | */ | |
593 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan) | |
594 | { | |
595 | int err = -EBUSY; | |
596 | ||
597 | /* lock against __dma_request_channel */ | |
598 | mutex_lock(&dma_list_mutex); | |
599 | ||
d9a6c8f5 | 600 | if (chan->client_count == 0) { |
214fc4e4 PU |
601 | struct dma_device *device = chan->device; |
602 | ||
603 | dma_cap_set(DMA_PRIVATE, device->cap_mask); | |
604 | device->privatecnt++; | |
7bb587f4 | 605 | err = dma_chan_get(chan); |
214fc4e4 | 606 | if (err) { |
ef859312 JN |
607 | dev_dbg(chan->device->dev, |
608 | "%s: failed to get %s: (%d)\n", | |
d9a6c8f5 | 609 | __func__, dma_chan_name(chan), err); |
214fc4e4 PU |
610 | chan = NULL; |
611 | if (--device->privatecnt == 0) | |
612 | dma_cap_clear(DMA_PRIVATE, device->cap_mask); | |
613 | } | |
d9a6c8f5 | 614 | } else |
7bb587f4 ZG |
615 | chan = NULL; |
616 | ||
617 | mutex_unlock(&dma_list_mutex); | |
618 | ||
7bb587f4 ZG |
619 | |
620 | return chan; | |
621 | } | |
622 | EXPORT_SYMBOL_GPL(dma_get_slave_channel); | |
623 | ||
8010dad5 SW |
624 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device) |
625 | { | |
626 | dma_cap_mask_t mask; | |
627 | struct dma_chan *chan; | |
8010dad5 SW |
628 | |
629 | dma_cap_zero(mask); | |
630 | dma_cap_set(DMA_SLAVE, mask); | |
631 | ||
632 | /* lock against __dma_request_channel */ | |
633 | mutex_lock(&dma_list_mutex); | |
634 | ||
7bd903c5 | 635 | chan = find_candidate(device, &mask, NULL, NULL); |
8010dad5 SW |
636 | |
637 | mutex_unlock(&dma_list_mutex); | |
638 | ||
7bd903c5 | 639 | return IS_ERR(chan) ? NULL : chan; |
8010dad5 SW |
640 | } |
641 | EXPORT_SYMBOL_GPL(dma_get_any_slave_channel); | |
642 | ||
59b5ec21 | 643 | /** |
6b9019a7 | 644 | * __dma_request_channel - try to allocate an exclusive channel |
59b5ec21 DW |
645 | * @mask: capabilities that the channel must satisfy |
646 | * @fn: optional callback to disposition available channels | |
647 | * @fn_param: opaque parameter to pass to dma_filter_fn | |
0ad7c000 SW |
648 | * |
649 | * Returns pointer to appropriate DMA channel on success or NULL. | |
59b5ec21 | 650 | */ |
a53e28da LPC |
651 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
652 | dma_filter_fn fn, void *fn_param) | |
59b5ec21 DW |
653 | { |
654 | struct dma_device *device, *_d; | |
655 | struct dma_chan *chan = NULL; | |
59b5ec21 DW |
656 | |
657 | /* Find a channel */ | |
658 | mutex_lock(&dma_list_mutex); | |
659 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { | |
7bd903c5 PU |
660 | chan = find_candidate(device, mask, fn, fn_param); |
661 | if (!IS_ERR(chan)) | |
662 | break; | |
59b5ec21 | 663 | |
7bd903c5 | 664 | chan = NULL; |
59b5ec21 DW |
665 | } |
666 | mutex_unlock(&dma_list_mutex); | |
667 | ||
4c4d7f87 | 668 | pr_debug("%s: %s (%s)\n", |
63433250 JP |
669 | __func__, |
670 | chan ? "success" : "fail", | |
41d5e59c | 671 | chan ? dma_chan_name(chan) : NULL); |
59b5ec21 DW |
672 | |
673 | return chan; | |
674 | } | |
675 | EXPORT_SYMBOL_GPL(__dma_request_channel); | |
676 | ||
a8135d0d PU |
677 | static const struct dma_slave_map *dma_filter_match(struct dma_device *device, |
678 | const char *name, | |
679 | struct device *dev) | |
680 | { | |
681 | int i; | |
682 | ||
683 | if (!device->filter.mapcnt) | |
684 | return NULL; | |
685 | ||
686 | for (i = 0; i < device->filter.mapcnt; i++) { | |
687 | const struct dma_slave_map *map = &device->filter.map[i]; | |
688 | ||
689 | if (!strcmp(map->devname, dev_name(dev)) && | |
690 | !strcmp(map->slave, name)) | |
691 | return map; | |
692 | } | |
693 | ||
694 | return NULL; | |
695 | } | |
696 | ||
9a6cecc8 | 697 | /** |
a8135d0d | 698 | * dma_request_chan - try to allocate an exclusive slave channel |
9a6cecc8 JH |
699 | * @dev: pointer to client device structure |
700 | * @name: slave channel name | |
0ad7c000 SW |
701 | * |
702 | * Returns pointer to appropriate DMA channel on success or an error pointer. | |
9a6cecc8 | 703 | */ |
a8135d0d | 704 | struct dma_chan *dma_request_chan(struct device *dev, const char *name) |
9a6cecc8 | 705 | { |
a8135d0d PU |
706 | struct dma_device *d, *_d; |
707 | struct dma_chan *chan = NULL; | |
708 | ||
9a6cecc8 JH |
709 | /* If device-tree is present get slave info from here */ |
710 | if (dev->of_node) | |
a8135d0d | 711 | chan = of_dma_request_slave_channel(dev->of_node, name); |
9a6cecc8 | 712 | |
4e82f5dd | 713 | /* If device was enumerated by ACPI get slave info from here */ |
a8135d0d PU |
714 | if (has_acpi_companion(dev) && !chan) |
715 | chan = acpi_dma_request_slave_chan_by_name(dev, name); | |
716 | ||
717 | if (chan) { | |
718 | /* Valid channel found or requester need to be deferred */ | |
719 | if (!IS_ERR(chan) || PTR_ERR(chan) == -EPROBE_DEFER) | |
720 | return chan; | |
721 | } | |
722 | ||
723 | /* Try to find the channel via the DMA filter map(s) */ | |
724 | mutex_lock(&dma_list_mutex); | |
725 | list_for_each_entry_safe(d, _d, &dma_device_list, global_node) { | |
726 | dma_cap_mask_t mask; | |
727 | const struct dma_slave_map *map = dma_filter_match(d, name, dev); | |
4e82f5dd | 728 | |
a8135d0d PU |
729 | if (!map) |
730 | continue; | |
731 | ||
732 | dma_cap_zero(mask); | |
733 | dma_cap_set(DMA_SLAVE, mask); | |
4e82f5dd | 734 | |
a8135d0d PU |
735 | chan = find_candidate(d, &mask, d->filter.fn, map->param); |
736 | if (!IS_ERR(chan)) | |
737 | break; | |
738 | } | |
739 | mutex_unlock(&dma_list_mutex); | |
740 | ||
741 | return chan ? chan : ERR_PTR(-EPROBE_DEFER); | |
0ad7c000 | 742 | } |
a8135d0d | 743 | EXPORT_SYMBOL_GPL(dma_request_chan); |
0ad7c000 SW |
744 | |
745 | /** | |
746 | * dma_request_slave_channel - try to allocate an exclusive slave channel | |
747 | * @dev: pointer to client device structure | |
748 | * @name: slave channel name | |
749 | * | |
750 | * Returns pointer to appropriate DMA channel on success or NULL. | |
751 | */ | |
752 | struct dma_chan *dma_request_slave_channel(struct device *dev, | |
753 | const char *name) | |
754 | { | |
a8135d0d | 755 | struct dma_chan *ch = dma_request_chan(dev, name); |
0ad7c000 SW |
756 | if (IS_ERR(ch)) |
757 | return NULL; | |
05aa1a77 | 758 | |
0ad7c000 | 759 | return ch; |
9a6cecc8 JH |
760 | } |
761 | EXPORT_SYMBOL_GPL(dma_request_slave_channel); | |
762 | ||
a8135d0d PU |
763 | /** |
764 | * dma_request_chan_by_mask - allocate a channel satisfying certain capabilities | |
765 | * @mask: capabilities that the channel must satisfy | |
766 | * | |
767 | * Returns pointer to appropriate DMA channel on success or an error pointer. | |
768 | */ | |
769 | struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask) | |
770 | { | |
771 | struct dma_chan *chan; | |
772 | ||
773 | if (!mask) | |
774 | return ERR_PTR(-ENODEV); | |
775 | ||
776 | chan = __dma_request_channel(mask, NULL, NULL); | |
777 | if (!chan) | |
778 | chan = ERR_PTR(-ENODEV); | |
779 | ||
780 | return chan; | |
781 | } | |
782 | EXPORT_SYMBOL_GPL(dma_request_chan_by_mask); | |
783 | ||
59b5ec21 DW |
784 | void dma_release_channel(struct dma_chan *chan) |
785 | { | |
786 | mutex_lock(&dma_list_mutex); | |
787 | WARN_ONCE(chan->client_count != 1, | |
788 | "chan reference count %d != 1\n", chan->client_count); | |
789 | dma_chan_put(chan); | |
0f571515 AN |
790 | /* drop PRIVATE cap enabled by __dma_request_channel() */ |
791 | if (--chan->device->privatecnt == 0) | |
792 | dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask); | |
59b5ec21 DW |
793 | mutex_unlock(&dma_list_mutex); |
794 | } | |
795 | EXPORT_SYMBOL_GPL(dma_release_channel); | |
796 | ||
d379b01e | 797 | /** |
209b84a8 | 798 | * dmaengine_get - register interest in dma_channels |
d379b01e | 799 | */ |
209b84a8 | 800 | void dmaengine_get(void) |
d379b01e | 801 | { |
6f49a57a DW |
802 | struct dma_device *device, *_d; |
803 | struct dma_chan *chan; | |
804 | int err; | |
805 | ||
c13c8260 | 806 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
807 | dmaengine_ref_count++; |
808 | ||
809 | /* try to grab channels */ | |
59b5ec21 DW |
810 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { |
811 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
812 | continue; | |
6f49a57a DW |
813 | list_for_each_entry(chan, &device->channels, device_node) { |
814 | err = dma_chan_get(chan); | |
815 | if (err == -ENODEV) { | |
816 | /* module removed before we could use it */ | |
2ba05622 | 817 | list_del_rcu(&device->global_node); |
6f49a57a DW |
818 | break; |
819 | } else if (err) | |
ef859312 JN |
820 | dev_dbg(chan->device->dev, |
821 | "%s: failed to get %s: (%d)\n", | |
822 | __func__, dma_chan_name(chan), err); | |
6f49a57a | 823 | } |
59b5ec21 | 824 | } |
6f49a57a | 825 | |
bec08513 DW |
826 | /* if this is the first reference and there were channels |
827 | * waiting we need to rebalance to get those channels | |
828 | * incorporated into the channel table | |
829 | */ | |
830 | if (dmaengine_ref_count == 1) | |
831 | dma_channel_rebalance(); | |
c13c8260 | 832 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 833 | } |
209b84a8 | 834 | EXPORT_SYMBOL(dmaengine_get); |
c13c8260 CL |
835 | |
836 | /** | |
209b84a8 | 837 | * dmaengine_put - let dma drivers be removed when ref_count == 0 |
c13c8260 | 838 | */ |
209b84a8 | 839 | void dmaengine_put(void) |
c13c8260 | 840 | { |
d379b01e | 841 | struct dma_device *device; |
c13c8260 CL |
842 | struct dma_chan *chan; |
843 | ||
c13c8260 | 844 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
845 | dmaengine_ref_count--; |
846 | BUG_ON(dmaengine_ref_count < 0); | |
847 | /* drop channel references */ | |
59b5ec21 DW |
848 | list_for_each_entry(device, &dma_device_list, global_node) { |
849 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
850 | continue; | |
6f49a57a DW |
851 | list_for_each_entry(chan, &device->channels, device_node) |
852 | dma_chan_put(chan); | |
59b5ec21 | 853 | } |
c13c8260 | 854 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 855 | } |
209b84a8 | 856 | EXPORT_SYMBOL(dmaengine_put); |
c13c8260 | 857 | |
138f4c35 DW |
858 | static bool device_has_all_tx_types(struct dma_device *device) |
859 | { | |
860 | /* A device that satisfies this test has channels that will never cause | |
861 | * an async_tx channel switch event as all possible operation types can | |
862 | * be handled. | |
863 | */ | |
864 | #ifdef CONFIG_ASYNC_TX_DMA | |
865 | if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask)) | |
866 | return false; | |
867 | #endif | |
868 | ||
d57d3a48 | 869 | #if IS_ENABLED(CONFIG_ASYNC_MEMCPY) |
138f4c35 DW |
870 | if (!dma_has_cap(DMA_MEMCPY, device->cap_mask)) |
871 | return false; | |
872 | #endif | |
873 | ||
d57d3a48 | 874 | #if IS_ENABLED(CONFIG_ASYNC_XOR) |
138f4c35 DW |
875 | if (!dma_has_cap(DMA_XOR, device->cap_mask)) |
876 | return false; | |
7b3cc2b1 DW |
877 | |
878 | #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
4499a24d DW |
879 | if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask)) |
880 | return false; | |
138f4c35 | 881 | #endif |
7b3cc2b1 | 882 | #endif |
138f4c35 | 883 | |
d57d3a48 | 884 | #if IS_ENABLED(CONFIG_ASYNC_PQ) |
138f4c35 DW |
885 | if (!dma_has_cap(DMA_PQ, device->cap_mask)) |
886 | return false; | |
7b3cc2b1 DW |
887 | |
888 | #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA | |
4499a24d DW |
889 | if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask)) |
890 | return false; | |
138f4c35 | 891 | #endif |
7b3cc2b1 | 892 | #endif |
138f4c35 DW |
893 | |
894 | return true; | |
895 | } | |
896 | ||
257b17ca DW |
897 | static int get_dma_id(struct dma_device *device) |
898 | { | |
899 | int rc; | |
900 | ||
257b17ca | 901 | mutex_lock(&dma_list_mutex); |
257b17ca | 902 | |
69ee266b TH |
903 | rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL); |
904 | if (rc >= 0) | |
905 | device->dev_id = rc; | |
906 | ||
907 | mutex_unlock(&dma_list_mutex); | |
908 | return rc < 0 ? rc : 0; | |
257b17ca DW |
909 | } |
910 | ||
c13c8260 | 911 | /** |
6508871e | 912 | * dma_async_device_register - registers DMA devices found |
c13c8260 CL |
913 | * @device: &dma_device |
914 | */ | |
915 | int dma_async_device_register(struct dma_device *device) | |
916 | { | |
ff487fb7 | 917 | int chancnt = 0, rc; |
c13c8260 | 918 | struct dma_chan* chan; |
864498aa | 919 | atomic_t *idr_ref; |
c13c8260 CL |
920 | |
921 | if (!device) | |
922 | return -ENODEV; | |
923 | ||
7405f74b DW |
924 | /* validate device routines */ |
925 | BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) && | |
926 | !device->device_prep_dma_memcpy); | |
927 | BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) && | |
928 | !device->device_prep_dma_xor); | |
099f53cb DW |
929 | BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) && |
930 | !device->device_prep_dma_xor_val); | |
b2f46fd8 DW |
931 | BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) && |
932 | !device->device_prep_dma_pq); | |
933 | BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) && | |
934 | !device->device_prep_dma_pq_val); | |
4983a501 MR |
935 | BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) && |
936 | !device->device_prep_dma_memset); | |
9b941c66 | 937 | BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) && |
7405f74b | 938 | !device->device_prep_dma_interrupt); |
a86ee03c IS |
939 | BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) && |
940 | !device->device_prep_dma_sg); | |
782bc950 SH |
941 | BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) && |
942 | !device->device_prep_dma_cyclic); | |
b14dab79 JB |
943 | BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && |
944 | !device->device_prep_interleaved_dma); | |
7405f74b | 945 | |
07934481 | 946 | BUG_ON(!device->device_tx_status); |
7405f74b DW |
947 | BUG_ON(!device->device_issue_pending); |
948 | BUG_ON(!device->dev); | |
949 | ||
138f4c35 | 950 | /* note: this only matters in the |
5fc6d897 | 951 | * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case |
138f4c35 DW |
952 | */ |
953 | if (device_has_all_tx_types(device)) | |
954 | dma_cap_set(DMA_ASYNC_TX, device->cap_mask); | |
955 | ||
864498aa DW |
956 | idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL); |
957 | if (!idr_ref) | |
958 | return -ENOMEM; | |
257b17ca DW |
959 | rc = get_dma_id(device); |
960 | if (rc != 0) { | |
961 | kfree(idr_ref); | |
864498aa | 962 | return rc; |
257b17ca DW |
963 | } |
964 | ||
965 | atomic_set(idr_ref, 0); | |
c13c8260 CL |
966 | |
967 | /* represent channels in sysfs. Probably want devs too */ | |
968 | list_for_each_entry(chan, &device->channels, device_node) { | |
257b17ca | 969 | rc = -ENOMEM; |
c13c8260 CL |
970 | chan->local = alloc_percpu(typeof(*chan->local)); |
971 | if (chan->local == NULL) | |
257b17ca | 972 | goto err_out; |
41d5e59c DW |
973 | chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); |
974 | if (chan->dev == NULL) { | |
975 | free_percpu(chan->local); | |
257b17ca DW |
976 | chan->local = NULL; |
977 | goto err_out; | |
41d5e59c | 978 | } |
c13c8260 CL |
979 | |
980 | chan->chan_id = chancnt++; | |
41d5e59c DW |
981 | chan->dev->device.class = &dma_devclass; |
982 | chan->dev->device.parent = device->dev; | |
983 | chan->dev->chan = chan; | |
864498aa DW |
984 | chan->dev->idr_ref = idr_ref; |
985 | chan->dev->dev_id = device->dev_id; | |
986 | atomic_inc(idr_ref); | |
41d5e59c | 987 | dev_set_name(&chan->dev->device, "dma%dchan%d", |
06190d84 | 988 | device->dev_id, chan->chan_id); |
c13c8260 | 989 | |
41d5e59c | 990 | rc = device_register(&chan->dev->device); |
ff487fb7 | 991 | if (rc) { |
ff487fb7 JG |
992 | free_percpu(chan->local); |
993 | chan->local = NULL; | |
257b17ca DW |
994 | kfree(chan->dev); |
995 | atomic_dec(idr_ref); | |
ff487fb7 JG |
996 | goto err_out; |
997 | } | |
7cc5bf9a | 998 | chan->client_count = 0; |
c13c8260 | 999 | } |
59b5ec21 | 1000 | device->chancnt = chancnt; |
c13c8260 CL |
1001 | |
1002 | mutex_lock(&dma_list_mutex); | |
59b5ec21 DW |
1003 | /* take references on public channels */ |
1004 | if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
6f49a57a DW |
1005 | list_for_each_entry(chan, &device->channels, device_node) { |
1006 | /* if clients are already waiting for channels we need | |
1007 | * to take references on their behalf | |
1008 | */ | |
1009 | if (dma_chan_get(chan) == -ENODEV) { | |
1010 | /* note we can only get here for the first | |
1011 | * channel as the remaining channels are | |
1012 | * guaranteed to get a reference | |
1013 | */ | |
1014 | rc = -ENODEV; | |
1015 | mutex_unlock(&dma_list_mutex); | |
1016 | goto err_out; | |
1017 | } | |
1018 | } | |
2ba05622 | 1019 | list_add_tail_rcu(&device->global_node, &dma_device_list); |
0f571515 AN |
1020 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) |
1021 | device->privatecnt++; /* Always private */ | |
bec08513 | 1022 | dma_channel_rebalance(); |
c13c8260 CL |
1023 | mutex_unlock(&dma_list_mutex); |
1024 | ||
c13c8260 | 1025 | return 0; |
ff487fb7 JG |
1026 | |
1027 | err_out: | |
257b17ca DW |
1028 | /* if we never registered a channel just release the idr */ |
1029 | if (atomic_read(idr_ref) == 0) { | |
1030 | mutex_lock(&dma_list_mutex); | |
1031 | idr_remove(&dma_idr, device->dev_id); | |
1032 | mutex_unlock(&dma_list_mutex); | |
1033 | kfree(idr_ref); | |
1034 | return rc; | |
1035 | } | |
1036 | ||
ff487fb7 JG |
1037 | list_for_each_entry(chan, &device->channels, device_node) { |
1038 | if (chan->local == NULL) | |
1039 | continue; | |
41d5e59c DW |
1040 | mutex_lock(&dma_list_mutex); |
1041 | chan->dev->chan = NULL; | |
1042 | mutex_unlock(&dma_list_mutex); | |
1043 | device_unregister(&chan->dev->device); | |
ff487fb7 JG |
1044 | free_percpu(chan->local); |
1045 | } | |
1046 | return rc; | |
c13c8260 | 1047 | } |
765e3d8a | 1048 | EXPORT_SYMBOL(dma_async_device_register); |
c13c8260 | 1049 | |
6508871e | 1050 | /** |
6f49a57a | 1051 | * dma_async_device_unregister - unregister a DMA device |
6508871e | 1052 | * @device: &dma_device |
f27c580c DW |
1053 | * |
1054 | * This routine is called by dma driver exit routines, dmaengine holds module | |
1055 | * references to prevent it being called while channels are in use. | |
6508871e RD |
1056 | */ |
1057 | void dma_async_device_unregister(struct dma_device *device) | |
c13c8260 CL |
1058 | { |
1059 | struct dma_chan *chan; | |
c13c8260 CL |
1060 | |
1061 | mutex_lock(&dma_list_mutex); | |
2ba05622 | 1062 | list_del_rcu(&device->global_node); |
bec08513 | 1063 | dma_channel_rebalance(); |
c13c8260 CL |
1064 | mutex_unlock(&dma_list_mutex); |
1065 | ||
1066 | list_for_each_entry(chan, &device->channels, device_node) { | |
6f49a57a DW |
1067 | WARN_ONCE(chan->client_count, |
1068 | "%s called while %d clients hold a reference\n", | |
1069 | __func__, chan->client_count); | |
41d5e59c DW |
1070 | mutex_lock(&dma_list_mutex); |
1071 | chan->dev->chan = NULL; | |
1072 | mutex_unlock(&dma_list_mutex); | |
1073 | device_unregister(&chan->dev->device); | |
adef4772 | 1074 | free_percpu(chan->local); |
c13c8260 | 1075 | } |
c13c8260 | 1076 | } |
765e3d8a | 1077 | EXPORT_SYMBOL(dma_async_device_unregister); |
c13c8260 | 1078 | |
45c463ae DW |
1079 | struct dmaengine_unmap_pool { |
1080 | struct kmem_cache *cache; | |
1081 | const char *name; | |
1082 | mempool_t *pool; | |
1083 | size_t size; | |
1084 | }; | |
7405f74b | 1085 | |
45c463ae DW |
1086 | #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) } |
1087 | static struct dmaengine_unmap_pool unmap_pool[] = { | |
1088 | __UNMAP_POOL(2), | |
3cc377b9 | 1089 | #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) |
45c463ae DW |
1090 | __UNMAP_POOL(16), |
1091 | __UNMAP_POOL(128), | |
1092 | __UNMAP_POOL(256), | |
1093 | #endif | |
1094 | }; | |
0036731c | 1095 | |
45c463ae DW |
1096 | static struct dmaengine_unmap_pool *__get_unmap_pool(int nr) |
1097 | { | |
1098 | int order = get_count_order(nr); | |
1099 | ||
1100 | switch (order) { | |
1101 | case 0 ... 1: | |
1102 | return &unmap_pool[0]; | |
1103 | case 2 ... 4: | |
1104 | return &unmap_pool[1]; | |
1105 | case 5 ... 7: | |
1106 | return &unmap_pool[2]; | |
1107 | case 8: | |
1108 | return &unmap_pool[3]; | |
1109 | default: | |
1110 | BUG(); | |
1111 | return NULL; | |
0036731c | 1112 | } |
45c463ae | 1113 | } |
7405f74b | 1114 | |
45c463ae DW |
1115 | static void dmaengine_unmap(struct kref *kref) |
1116 | { | |
1117 | struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref); | |
1118 | struct device *dev = unmap->dev; | |
1119 | int cnt, i; | |
1120 | ||
1121 | cnt = unmap->to_cnt; | |
1122 | for (i = 0; i < cnt; i++) | |
1123 | dma_unmap_page(dev, unmap->addr[i], unmap->len, | |
1124 | DMA_TO_DEVICE); | |
1125 | cnt += unmap->from_cnt; | |
1126 | for (; i < cnt; i++) | |
1127 | dma_unmap_page(dev, unmap->addr[i], unmap->len, | |
1128 | DMA_FROM_DEVICE); | |
1129 | cnt += unmap->bidi_cnt; | |
7476bd79 DW |
1130 | for (; i < cnt; i++) { |
1131 | if (unmap->addr[i] == 0) | |
1132 | continue; | |
45c463ae DW |
1133 | dma_unmap_page(dev, unmap->addr[i], unmap->len, |
1134 | DMA_BIDIRECTIONAL); | |
7476bd79 | 1135 | } |
c1f43dd9 | 1136 | cnt = unmap->map_cnt; |
45c463ae DW |
1137 | mempool_free(unmap, __get_unmap_pool(cnt)->pool); |
1138 | } | |
7405f74b | 1139 | |
45c463ae DW |
1140 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) |
1141 | { | |
1142 | if (unmap) | |
1143 | kref_put(&unmap->kref, dmaengine_unmap); | |
1144 | } | |
1145 | EXPORT_SYMBOL_GPL(dmaengine_unmap_put); | |
7405f74b | 1146 | |
45c463ae DW |
1147 | static void dmaengine_destroy_unmap_pool(void) |
1148 | { | |
1149 | int i; | |
1150 | ||
1151 | for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { | |
1152 | struct dmaengine_unmap_pool *p = &unmap_pool[i]; | |
1153 | ||
240eb916 | 1154 | mempool_destroy(p->pool); |
45c463ae | 1155 | p->pool = NULL; |
240eb916 | 1156 | kmem_cache_destroy(p->cache); |
45c463ae DW |
1157 | p->cache = NULL; |
1158 | } | |
7405f74b | 1159 | } |
7405f74b | 1160 | |
45c463ae | 1161 | static int __init dmaengine_init_unmap_pool(void) |
7405f74b | 1162 | { |
45c463ae | 1163 | int i; |
7405f74b | 1164 | |
45c463ae DW |
1165 | for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { |
1166 | struct dmaengine_unmap_pool *p = &unmap_pool[i]; | |
1167 | size_t size; | |
0036731c | 1168 | |
45c463ae DW |
1169 | size = sizeof(struct dmaengine_unmap_data) + |
1170 | sizeof(dma_addr_t) * p->size; | |
1171 | ||
1172 | p->cache = kmem_cache_create(p->name, size, 0, | |
1173 | SLAB_HWCACHE_ALIGN, NULL); | |
1174 | if (!p->cache) | |
1175 | break; | |
1176 | p->pool = mempool_create_slab_pool(1, p->cache); | |
1177 | if (!p->pool) | |
1178 | break; | |
0036731c | 1179 | } |
7405f74b | 1180 | |
45c463ae DW |
1181 | if (i == ARRAY_SIZE(unmap_pool)) |
1182 | return 0; | |
7405f74b | 1183 | |
45c463ae DW |
1184 | dmaengine_destroy_unmap_pool(); |
1185 | return -ENOMEM; | |
1186 | } | |
7405f74b | 1187 | |
89716462 | 1188 | struct dmaengine_unmap_data * |
45c463ae DW |
1189 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) |
1190 | { | |
1191 | struct dmaengine_unmap_data *unmap; | |
1192 | ||
1193 | unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags); | |
1194 | if (!unmap) | |
1195 | return NULL; | |
1196 | ||
1197 | memset(unmap, 0, sizeof(*unmap)); | |
1198 | kref_init(&unmap->kref); | |
1199 | unmap->dev = dev; | |
c1f43dd9 | 1200 | unmap->map_cnt = nr; |
45c463ae DW |
1201 | |
1202 | return unmap; | |
7405f74b | 1203 | } |
89716462 | 1204 | EXPORT_SYMBOL(dmaengine_get_unmap_data); |
7405f74b | 1205 | |
7405f74b DW |
1206 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
1207 | struct dma_chan *chan) | |
1208 | { | |
1209 | tx->chan = chan; | |
5fc6d897 | 1210 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
7405f74b | 1211 | spin_lock_init(&tx->lock); |
caa20d97 | 1212 | #endif |
7405f74b DW |
1213 | } |
1214 | EXPORT_SYMBOL(dma_async_tx_descriptor_init); | |
1215 | ||
07f2211e DW |
1216 | /* dma_wait_for_async_tx - spin wait for a transaction to complete |
1217 | * @tx: in-flight transaction to wait on | |
07f2211e DW |
1218 | */ |
1219 | enum dma_status | |
1220 | dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
1221 | { | |
95475e57 | 1222 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); |
07f2211e DW |
1223 | |
1224 | if (!tx) | |
adfedd9a | 1225 | return DMA_COMPLETE; |
07f2211e | 1226 | |
95475e57 DW |
1227 | while (tx->cookie == -EBUSY) { |
1228 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
ef859312 JN |
1229 | dev_err(tx->chan->device->dev, |
1230 | "%s timeout waiting for descriptor submission\n", | |
1231 | __func__); | |
95475e57 DW |
1232 | return DMA_ERROR; |
1233 | } | |
1234 | cpu_relax(); | |
1235 | } | |
1236 | return dma_sync_wait(tx->chan, tx->cookie); | |
07f2211e DW |
1237 | } |
1238 | EXPORT_SYMBOL_GPL(dma_wait_for_async_tx); | |
1239 | ||
1240 | /* dma_run_dependencies - helper routine for dma drivers to process | |
1241 | * (start) dependent operations on their target channel | |
1242 | * @tx: transaction with dependencies | |
1243 | */ | |
1244 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx) | |
1245 | { | |
caa20d97 | 1246 | struct dma_async_tx_descriptor *dep = txd_next(tx); |
07f2211e DW |
1247 | struct dma_async_tx_descriptor *dep_next; |
1248 | struct dma_chan *chan; | |
1249 | ||
1250 | if (!dep) | |
1251 | return; | |
1252 | ||
dd59b853 | 1253 | /* we'll submit tx->next now, so clear the link */ |
caa20d97 | 1254 | txd_clear_next(tx); |
07f2211e DW |
1255 | chan = dep->chan; |
1256 | ||
1257 | /* keep submitting up until a channel switch is detected | |
1258 | * in that case we will be called again as a result of | |
1259 | * processing the interrupt from async_tx_channel_switch | |
1260 | */ | |
1261 | for (; dep; dep = dep_next) { | |
caa20d97 DW |
1262 | txd_lock(dep); |
1263 | txd_clear_parent(dep); | |
1264 | dep_next = txd_next(dep); | |
07f2211e | 1265 | if (dep_next && dep_next->chan == chan) |
caa20d97 | 1266 | txd_clear_next(dep); /* ->next will be submitted */ |
07f2211e DW |
1267 | else |
1268 | dep_next = NULL; /* submit current dep and terminate */ | |
caa20d97 | 1269 | txd_unlock(dep); |
07f2211e DW |
1270 | |
1271 | dep->tx_submit(dep); | |
1272 | } | |
1273 | ||
1274 | chan->device->device_issue_pending(chan); | |
1275 | } | |
1276 | EXPORT_SYMBOL_GPL(dma_run_dependencies); | |
1277 | ||
c13c8260 CL |
1278 | static int __init dma_bus_init(void) |
1279 | { | |
45c463ae DW |
1280 | int err = dmaengine_init_unmap_pool(); |
1281 | ||
1282 | if (err) | |
1283 | return err; | |
c13c8260 CL |
1284 | return class_register(&dma_devclass); |
1285 | } | |
652afc27 | 1286 | arch_initcall(dma_bus_init); |
c13c8260 | 1287 | |
bec08513 | 1288 |