Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / drivers / dma / dmaengine.c
CommitLineData
c13c8260
CL
1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21
22/*
23 * This code implements the DMA subsystem. It provides a HW-neutral interface
24 * for other kernel code to use asynchronous memory copy capabilities,
25 * if present, and allows different HW DMA drivers to register as providing
26 * this capability.
27 *
28 * Due to the fact we are accelerating what is already a relatively fast
29 * operation, the code goes to great lengths to avoid additional overhead,
30 * such as locking.
31 *
32 * LOCKING:
33 *
aa1e6f1a
DW
34 * The subsystem keeps a global list of dma_device structs it is protected by a
35 * mutex, dma_list_mutex.
c13c8260 36 *
f27c580c
DW
37 * A subsystem can get access to a channel by calling dmaengine_get() followed
38 * by dma_find_channel(), or if it has need for an exclusive channel it can call
39 * dma_request_channel(). Once a channel is allocated a reference is taken
40 * against its corresponding driver to disable removal.
41 *
c13c8260
CL
42 * Each device has a channels list, which runs unlocked but is never modified
43 * once the device is registered, it's just setup by the driver.
44 *
f27c580c 45 * See Documentation/dmaengine.txt for more details
c13c8260
CL
46 */
47
63433250
JP
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
b7f080cf 50#include <linux/dma-mapping.h>
c13c8260
CL
51#include <linux/init.h>
52#include <linux/module.h>
7405f74b 53#include <linux/mm.h>
c13c8260
CL
54#include <linux/device.h>
55#include <linux/dmaengine.h>
56#include <linux/hardirq.h>
57#include <linux/spinlock.h>
58#include <linux/percpu.h>
59#include <linux/rcupdate.h>
60#include <linux/mutex.h>
7405f74b 61#include <linux/jiffies.h>
2ba05622 62#include <linux/rculist.h>
864498aa 63#include <linux/idr.h>
5a0e3ad6 64#include <linux/slab.h>
4e82f5dd
AS
65#include <linux/acpi.h>
66#include <linux/acpi_dma.h>
9a6cecc8 67#include <linux/of_dma.h>
45c463ae 68#include <linux/mempool.h>
c13c8260
CL
69
70static DEFINE_MUTEX(dma_list_mutex);
21ef4b8b 71static DEFINE_IDR(dma_idr);
c13c8260 72static LIST_HEAD(dma_device_list);
6f49a57a 73static long dmaengine_ref_count;
c13c8260
CL
74
75/* --- sysfs implementation --- */
76
41d5e59c
DW
77/**
78 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
79 * @dev - device node
80 *
81 * Must be called under dma_list_mutex
82 */
83static struct dma_chan *dev_to_dma_chan(struct device *dev)
84{
85 struct dma_chan_dev *chan_dev;
86
87 chan_dev = container_of(dev, typeof(*chan_dev), device);
88 return chan_dev->chan;
89}
90
58b267d3
GKH
91static ssize_t memcpy_count_show(struct device *dev,
92 struct device_attribute *attr, char *buf)
c13c8260 93{
41d5e59c 94 struct dma_chan *chan;
c13c8260
CL
95 unsigned long count = 0;
96 int i;
41d5e59c 97 int err;
c13c8260 98
41d5e59c
DW
99 mutex_lock(&dma_list_mutex);
100 chan = dev_to_dma_chan(dev);
101 if (chan) {
102 for_each_possible_cpu(i)
103 count += per_cpu_ptr(chan->local, i)->memcpy_count;
104 err = sprintf(buf, "%lu\n", count);
105 } else
106 err = -ENODEV;
107 mutex_unlock(&dma_list_mutex);
c13c8260 108
41d5e59c 109 return err;
c13c8260 110}
58b267d3 111static DEVICE_ATTR_RO(memcpy_count);
c13c8260 112
58b267d3
GKH
113static ssize_t bytes_transferred_show(struct device *dev,
114 struct device_attribute *attr, char *buf)
c13c8260 115{
41d5e59c 116 struct dma_chan *chan;
c13c8260
CL
117 unsigned long count = 0;
118 int i;
41d5e59c 119 int err;
c13c8260 120
41d5e59c
DW
121 mutex_lock(&dma_list_mutex);
122 chan = dev_to_dma_chan(dev);
123 if (chan) {
124 for_each_possible_cpu(i)
125 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
126 err = sprintf(buf, "%lu\n", count);
127 } else
128 err = -ENODEV;
129 mutex_unlock(&dma_list_mutex);
c13c8260 130
41d5e59c 131 return err;
c13c8260 132}
58b267d3 133static DEVICE_ATTR_RO(bytes_transferred);
c13c8260 134
58b267d3
GKH
135static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
136 char *buf)
c13c8260 137{
41d5e59c
DW
138 struct dma_chan *chan;
139 int err;
c13c8260 140
41d5e59c
DW
141 mutex_lock(&dma_list_mutex);
142 chan = dev_to_dma_chan(dev);
143 if (chan)
144 err = sprintf(buf, "%d\n", chan->client_count);
145 else
146 err = -ENODEV;
147 mutex_unlock(&dma_list_mutex);
148
149 return err;
c13c8260 150}
58b267d3 151static DEVICE_ATTR_RO(in_use);
c13c8260 152
58b267d3
GKH
153static struct attribute *dma_dev_attrs[] = {
154 &dev_attr_memcpy_count.attr,
155 &dev_attr_bytes_transferred.attr,
156 &dev_attr_in_use.attr,
157 NULL,
c13c8260 158};
58b267d3 159ATTRIBUTE_GROUPS(dma_dev);
c13c8260 160
41d5e59c
DW
161static void chan_dev_release(struct device *dev)
162{
163 struct dma_chan_dev *chan_dev;
164
165 chan_dev = container_of(dev, typeof(*chan_dev), device);
864498aa
DW
166 if (atomic_dec_and_test(chan_dev->idr_ref)) {
167 mutex_lock(&dma_list_mutex);
168 idr_remove(&dma_idr, chan_dev->dev_id);
169 mutex_unlock(&dma_list_mutex);
170 kfree(chan_dev->idr_ref);
171 }
41d5e59c
DW
172 kfree(chan_dev);
173}
174
c13c8260 175static struct class dma_devclass = {
891f78ea 176 .name = "dma",
58b267d3 177 .dev_groups = dma_dev_groups,
41d5e59c 178 .dev_release = chan_dev_release,
c13c8260
CL
179};
180
181/* --- client and device registration --- */
182
59b5ec21
DW
183#define dma_device_satisfies_mask(device, mask) \
184 __dma_device_satisfies_mask((device), &(mask))
d379b01e 185static int
a53e28da
LPC
186__dma_device_satisfies_mask(struct dma_device *device,
187 const dma_cap_mask_t *want)
d379b01e
DW
188{
189 dma_cap_mask_t has;
190
59b5ec21 191 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
d379b01e
DW
192 DMA_TX_TYPE_END);
193 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
194}
195
6f49a57a
DW
196static struct module *dma_chan_to_owner(struct dma_chan *chan)
197{
198 return chan->device->dev->driver->owner;
199}
200
201/**
202 * balance_ref_count - catch up the channel reference count
203 * @chan - channel to balance ->client_count versus dmaengine_ref_count
204 *
205 * balance_ref_count must be called under dma_list_mutex
206 */
207static void balance_ref_count(struct dma_chan *chan)
208{
209 struct module *owner = dma_chan_to_owner(chan);
210
211 while (chan->client_count < dmaengine_ref_count) {
212 __module_get(owner);
213 chan->client_count++;
214 }
215}
216
217/**
218 * dma_chan_get - try to grab a dma channel's parent driver module
219 * @chan - channel to grab
220 *
221 * Must be called under dma_list_mutex
222 */
223static int dma_chan_get(struct dma_chan *chan)
224{
6f49a57a 225 struct module *owner = dma_chan_to_owner(chan);
d2f4f99d 226 int ret;
6f49a57a 227
d2f4f99d 228 /* The channel is already in use, update client count */
6f49a57a
DW
229 if (chan->client_count) {
230 __module_get(owner);
d2f4f99d
MR
231 goto out;
232 }
6f49a57a 233
d2f4f99d
MR
234 if (!try_module_get(owner))
235 return -ENODEV;
6f49a57a
DW
236
237 /* allocate upon first client reference */
c4b54a64
MR
238 if (chan->device->device_alloc_chan_resources) {
239 ret = chan->device->device_alloc_chan_resources(chan);
240 if (ret < 0)
241 goto err_out;
242 }
6f49a57a 243
d2f4f99d
MR
244 if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
245 balance_ref_count(chan);
246
247out:
248 chan->client_count++;
249 return 0;
250
251err_out:
252 module_put(owner);
253 return ret;
6f49a57a
DW
254}
255
256/**
257 * dma_chan_put - drop a reference to a dma channel's parent driver module
258 * @chan - channel to release
259 *
260 * Must be called under dma_list_mutex
261 */
262static void dma_chan_put(struct dma_chan *chan)
263{
c4b54a64 264 /* This channel is not in use, bail out */
6f49a57a 265 if (!chan->client_count)
c4b54a64
MR
266 return;
267
6f49a57a
DW
268 chan->client_count--;
269 module_put(dma_chan_to_owner(chan));
c4b54a64
MR
270
271 /* This channel is not in use anymore, free it */
272 if (!chan->client_count && chan->device->device_free_chan_resources)
6f49a57a
DW
273 chan->device->device_free_chan_resources(chan);
274}
275
7405f74b
DW
276enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
277{
278 enum dma_status status;
279 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
280
281 dma_async_issue_pending(chan);
282 do {
283 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
284 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
63433250 285 pr_err("%s: timeout!\n", __func__);
7405f74b
DW
286 return DMA_ERROR;
287 }
2cbe7feb
BZ
288 if (status != DMA_IN_PROGRESS)
289 break;
290 cpu_relax();
291 } while (1);
7405f74b
DW
292
293 return status;
294}
295EXPORT_SYMBOL(dma_sync_wait);
296
bec08513
DW
297/**
298 * dma_cap_mask_all - enable iteration over all operation types
299 */
300static dma_cap_mask_t dma_cap_mask_all;
301
302/**
303 * dma_chan_tbl_ent - tracks channel allocations per core/operation
304 * @chan - associated channel for this entry
305 */
306struct dma_chan_tbl_ent {
307 struct dma_chan *chan;
308};
309
310/**
311 * channel_table - percpu lookup table for memory-to-memory offload providers
312 */
a29d8b8e 313static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
bec08513
DW
314
315static int __init dma_channel_table_init(void)
316{
317 enum dma_transaction_type cap;
318 int err = 0;
319
320 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
321
59b5ec21
DW
322 /* 'interrupt', 'private', and 'slave' are channel capabilities,
323 * but are not associated with an operation so they do not need
324 * an entry in the channel_table
bec08513
DW
325 */
326 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 327 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
bec08513
DW
328 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
329
330 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
331 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
332 if (!channel_table[cap]) {
333 err = -ENOMEM;
334 break;
335 }
336 }
337
338 if (err) {
63433250 339 pr_err("initialization failure\n");
bec08513 340 for_each_dma_cap_mask(cap, dma_cap_mask_all)
a9507ca3 341 free_percpu(channel_table[cap]);
bec08513
DW
342 }
343
344 return err;
345}
652afc27 346arch_initcall(dma_channel_table_init);
bec08513
DW
347
348/**
349 * dma_find_channel - find a channel to carry out the operation
350 * @tx_type: transaction type
351 */
352struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
353{
e7dcaa47 354 return this_cpu_read(channel_table[tx_type]->chan);
bec08513
DW
355}
356EXPORT_SYMBOL(dma_find_channel);
357
a2bd1140
DJ
358/*
359 * net_dma_find_channel - find a channel for net_dma
360 * net_dma has alignment requirements
361 */
362struct dma_chan *net_dma_find_channel(void)
363{
364 struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
365 if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
366 return NULL;
367
368 return chan;
369}
370EXPORT_SYMBOL(net_dma_find_channel);
371
2ba05622
DW
372/**
373 * dma_issue_pending_all - flush all pending operations across all channels
374 */
375void dma_issue_pending_all(void)
376{
377 struct dma_device *device;
378 struct dma_chan *chan;
379
2ba05622 380 rcu_read_lock();
59b5ec21
DW
381 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
382 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
383 continue;
2ba05622
DW
384 list_for_each_entry(chan, &device->channels, device_node)
385 if (chan->client_count)
386 device->device_issue_pending(chan);
59b5ec21 387 }
2ba05622
DW
388 rcu_read_unlock();
389}
390EXPORT_SYMBOL(dma_issue_pending_all);
391
bec08513 392/**
c4d27c4d
BG
393 * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
394 */
395static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
396{
397 int node = dev_to_node(chan->device->dev);
398 return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
399}
400
401/**
402 * min_chan - returns the channel with min count and in the same numa-node as the cpu
bec08513 403 * @cap: capability to match
c4d27c4d 404 * @cpu: cpu index which the channel should be close to
bec08513 405 *
c4d27c4d
BG
406 * If some channels are close to the given cpu, the one with the lowest
407 * reference count is returned. Otherwise, cpu is ignored and only the
408 * reference count is taken into account.
409 * Must be called under dma_list_mutex.
bec08513 410 */
c4d27c4d 411static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
bec08513
DW
412{
413 struct dma_device *device;
414 struct dma_chan *chan;
bec08513 415 struct dma_chan *min = NULL;
c4d27c4d 416 struct dma_chan *localmin = NULL;
bec08513
DW
417
418 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
419 if (!dma_has_cap(cap, device->cap_mask) ||
420 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
421 continue;
422 list_for_each_entry(chan, &device->channels, device_node) {
423 if (!chan->client_count)
424 continue;
c4d27c4d 425 if (!min || chan->table_count < min->table_count)
bec08513
DW
426 min = chan;
427
c4d27c4d
BG
428 if (dma_chan_is_local(chan, cpu))
429 if (!localmin ||
430 chan->table_count < localmin->table_count)
431 localmin = chan;
bec08513 432 }
bec08513
DW
433 }
434
c4d27c4d 435 chan = localmin ? localmin : min;
bec08513 436
c4d27c4d
BG
437 if (chan)
438 chan->table_count++;
bec08513 439
c4d27c4d 440 return chan;
bec08513
DW
441}
442
443/**
444 * dma_channel_rebalance - redistribute the available channels
445 *
446 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
447 * operation type) in the SMP case, and operation isolation (avoid
448 * multi-tasking channels) in the non-SMP case. Must be called under
449 * dma_list_mutex.
450 */
451static void dma_channel_rebalance(void)
452{
453 struct dma_chan *chan;
454 struct dma_device *device;
455 int cpu;
456 int cap;
bec08513
DW
457
458 /* undo the last distribution */
459 for_each_dma_cap_mask(cap, dma_cap_mask_all)
460 for_each_possible_cpu(cpu)
461 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
462
59b5ec21
DW
463 list_for_each_entry(device, &dma_device_list, global_node) {
464 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
465 continue;
bec08513
DW
466 list_for_each_entry(chan, &device->channels, device_node)
467 chan->table_count = 0;
59b5ec21 468 }
bec08513
DW
469
470 /* don't populate the channel_table if no clients are available */
471 if (!dmaengine_ref_count)
472 return;
473
474 /* redistribute available channels */
bec08513
DW
475 for_each_dma_cap_mask(cap, dma_cap_mask_all)
476 for_each_online_cpu(cpu) {
c4d27c4d 477 chan = min_chan(cap, cpu);
bec08513
DW
478 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
479 }
480}
481
0d5484b1
LP
482int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
483{
484 struct dma_device *device;
485
486 if (!chan || !caps)
487 return -EINVAL;
488
489 device = chan->device;
490
491 /* check if the channel supports slave transactions */
492 if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
493 return -ENXIO;
494
495 /*
496 * Check whether it reports it uses the generic slave
497 * capabilities, if not, that means it doesn't support any
498 * kind of slave capabilities reporting.
499 */
500 if (!device->directions)
501 return -ENXIO;
502
503 caps->src_addr_widths = device->src_addr_widths;
504 caps->dst_addr_widths = device->dst_addr_widths;
505 caps->directions = device->directions;
506 caps->residue_granularity = device->residue_granularity;
507
508 caps->cmd_pause = !!device->device_pause;
509 caps->cmd_terminate = !!device->device_terminate_all;
510
511 return 0;
512}
513EXPORT_SYMBOL_GPL(dma_get_slave_caps);
514
a53e28da
LPC
515static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
516 struct dma_device *dev,
e2346677 517 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
518{
519 struct dma_chan *chan;
59b5ec21
DW
520
521 if (!__dma_device_satisfies_mask(dev, mask)) {
522 pr_debug("%s: wrong capabilities\n", __func__);
523 return NULL;
524 }
525 /* devices with multiple channels need special handling as we need to
526 * ensure that all channels are either private or public.
527 */
528 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
529 list_for_each_entry(chan, &dev->channels, device_node) {
530 /* some channels are already publicly allocated */
531 if (chan->client_count)
532 return NULL;
533 }
534
535 list_for_each_entry(chan, &dev->channels, device_node) {
536 if (chan->client_count) {
537 pr_debug("%s: %s busy\n",
41d5e59c 538 __func__, dma_chan_name(chan));
59b5ec21
DW
539 continue;
540 }
e2346677
DW
541 if (fn && !fn(chan, fn_param)) {
542 pr_debug("%s: %s filter said false\n",
543 __func__, dma_chan_name(chan));
544 continue;
545 }
546 return chan;
59b5ec21
DW
547 }
548
e2346677 549 return NULL;
59b5ec21
DW
550}
551
552/**
6b9019a7 553 * dma_request_slave_channel - try to get specific channel exclusively
7bb587f4
ZG
554 * @chan: target channel
555 */
556struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
557{
558 int err = -EBUSY;
559
560 /* lock against __dma_request_channel */
561 mutex_lock(&dma_list_mutex);
562
d9a6c8f5 563 if (chan->client_count == 0) {
7bb587f4 564 err = dma_chan_get(chan);
d9a6c8f5
VK
565 if (err)
566 pr_debug("%s: failed to get %s: (%d)\n",
567 __func__, dma_chan_name(chan), err);
568 } else
7bb587f4
ZG
569 chan = NULL;
570
571 mutex_unlock(&dma_list_mutex);
572
7bb587f4
ZG
573
574 return chan;
575}
576EXPORT_SYMBOL_GPL(dma_get_slave_channel);
577
8010dad5
SW
578struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
579{
580 dma_cap_mask_t mask;
581 struct dma_chan *chan;
582 int err;
583
584 dma_cap_zero(mask);
585 dma_cap_set(DMA_SLAVE, mask);
586
587 /* lock against __dma_request_channel */
588 mutex_lock(&dma_list_mutex);
589
590 chan = private_candidate(&mask, device, NULL, NULL);
591 if (chan) {
592 err = dma_chan_get(chan);
593 if (err) {
594 pr_debug("%s: failed to get %s: (%d)\n",
595 __func__, dma_chan_name(chan), err);
596 chan = NULL;
597 }
598 }
599
600 mutex_unlock(&dma_list_mutex);
601
602 return chan;
603}
604EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
605
59b5ec21 606/**
6b9019a7 607 * __dma_request_channel - try to allocate an exclusive channel
59b5ec21
DW
608 * @mask: capabilities that the channel must satisfy
609 * @fn: optional callback to disposition available channels
610 * @fn_param: opaque parameter to pass to dma_filter_fn
0ad7c000
SW
611 *
612 * Returns pointer to appropriate DMA channel on success or NULL.
59b5ec21 613 */
a53e28da
LPC
614struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
615 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
616{
617 struct dma_device *device, *_d;
618 struct dma_chan *chan = NULL;
59b5ec21
DW
619 int err;
620
621 /* Find a channel */
622 mutex_lock(&dma_list_mutex);
623 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
e2346677
DW
624 chan = private_candidate(mask, device, fn, fn_param);
625 if (chan) {
59b5ec21
DW
626 /* Found a suitable channel, try to grab, prep, and
627 * return it. We first set DMA_PRIVATE to disable
628 * balance_ref_count as this channel will not be
629 * published in the general-purpose allocator
630 */
631 dma_cap_set(DMA_PRIVATE, device->cap_mask);
0f571515 632 device->privatecnt++;
59b5ec21
DW
633 err = dma_chan_get(chan);
634
635 if (err == -ENODEV) {
63433250
JP
636 pr_debug("%s: %s module removed\n",
637 __func__, dma_chan_name(chan));
59b5ec21
DW
638 list_del_rcu(&device->global_node);
639 } else if (err)
d8b53489 640 pr_debug("%s: failed to get %s: (%d)\n",
63433250 641 __func__, dma_chan_name(chan), err);
59b5ec21
DW
642 else
643 break;
0f571515
AN
644 if (--device->privatecnt == 0)
645 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
e2346677
DW
646 chan = NULL;
647 }
59b5ec21
DW
648 }
649 mutex_unlock(&dma_list_mutex);
650
63433250
JP
651 pr_debug("%s: %s (%s)\n",
652 __func__,
653 chan ? "success" : "fail",
41d5e59c 654 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
655
656 return chan;
657}
658EXPORT_SYMBOL_GPL(__dma_request_channel);
659
9a6cecc8
JH
660/**
661 * dma_request_slave_channel - try to allocate an exclusive slave channel
662 * @dev: pointer to client device structure
663 * @name: slave channel name
0ad7c000
SW
664 *
665 * Returns pointer to appropriate DMA channel on success or an error pointer.
9a6cecc8 666 */
0ad7c000
SW
667struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
668 const char *name)
9a6cecc8
JH
669{
670 /* If device-tree is present get slave info from here */
671 if (dev->of_node)
672 return of_dma_request_slave_channel(dev->of_node, name);
673
4e82f5dd 674 /* If device was enumerated by ACPI get slave info from here */
0f6a928d
AS
675 if (ACPI_HANDLE(dev))
676 return acpi_dma_request_slave_chan_by_name(dev, name);
4e82f5dd 677
0ad7c000
SW
678 return ERR_PTR(-ENODEV);
679}
680EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
681
682/**
683 * dma_request_slave_channel - try to allocate an exclusive slave channel
684 * @dev: pointer to client device structure
685 * @name: slave channel name
686 *
687 * Returns pointer to appropriate DMA channel on success or NULL.
688 */
689struct dma_chan *dma_request_slave_channel(struct device *dev,
690 const char *name)
691{
692 struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
693 if (IS_ERR(ch))
694 return NULL;
695 return ch;
9a6cecc8
JH
696}
697EXPORT_SYMBOL_GPL(dma_request_slave_channel);
698
59b5ec21
DW
699void dma_release_channel(struct dma_chan *chan)
700{
701 mutex_lock(&dma_list_mutex);
702 WARN_ONCE(chan->client_count != 1,
703 "chan reference count %d != 1\n", chan->client_count);
704 dma_chan_put(chan);
0f571515
AN
705 /* drop PRIVATE cap enabled by __dma_request_channel() */
706 if (--chan->device->privatecnt == 0)
707 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
59b5ec21
DW
708 mutex_unlock(&dma_list_mutex);
709}
710EXPORT_SYMBOL_GPL(dma_release_channel);
711
d379b01e 712/**
209b84a8 713 * dmaengine_get - register interest in dma_channels
d379b01e 714 */
209b84a8 715void dmaengine_get(void)
d379b01e 716{
6f49a57a
DW
717 struct dma_device *device, *_d;
718 struct dma_chan *chan;
719 int err;
720
c13c8260 721 mutex_lock(&dma_list_mutex);
6f49a57a
DW
722 dmaengine_ref_count++;
723
724 /* try to grab channels */
59b5ec21
DW
725 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
726 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
727 continue;
6f49a57a
DW
728 list_for_each_entry(chan, &device->channels, device_node) {
729 err = dma_chan_get(chan);
730 if (err == -ENODEV) {
731 /* module removed before we could use it */
2ba05622 732 list_del_rcu(&device->global_node);
6f49a57a
DW
733 break;
734 } else if (err)
0eb5a358 735 pr_debug("%s: failed to get %s: (%d)\n",
63433250 736 __func__, dma_chan_name(chan), err);
6f49a57a 737 }
59b5ec21 738 }
6f49a57a 739
bec08513
DW
740 /* if this is the first reference and there were channels
741 * waiting we need to rebalance to get those channels
742 * incorporated into the channel table
743 */
744 if (dmaengine_ref_count == 1)
745 dma_channel_rebalance();
c13c8260 746 mutex_unlock(&dma_list_mutex);
c13c8260 747}
209b84a8 748EXPORT_SYMBOL(dmaengine_get);
c13c8260
CL
749
750/**
209b84a8 751 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 752 */
209b84a8 753void dmaengine_put(void)
c13c8260 754{
d379b01e 755 struct dma_device *device;
c13c8260
CL
756 struct dma_chan *chan;
757
c13c8260 758 mutex_lock(&dma_list_mutex);
6f49a57a
DW
759 dmaengine_ref_count--;
760 BUG_ON(dmaengine_ref_count < 0);
761 /* drop channel references */
59b5ec21
DW
762 list_for_each_entry(device, &dma_device_list, global_node) {
763 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
764 continue;
6f49a57a
DW
765 list_for_each_entry(chan, &device->channels, device_node)
766 dma_chan_put(chan);
59b5ec21 767 }
c13c8260 768 mutex_unlock(&dma_list_mutex);
c13c8260 769}
209b84a8 770EXPORT_SYMBOL(dmaengine_put);
c13c8260 771
138f4c35
DW
772static bool device_has_all_tx_types(struct dma_device *device)
773{
774 /* A device that satisfies this test has channels that will never cause
775 * an async_tx channel switch event as all possible operation types can
776 * be handled.
777 */
778 #ifdef CONFIG_ASYNC_TX_DMA
779 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
780 return false;
781 #endif
782
783 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
784 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
785 return false;
786 #endif
787
138f4c35
DW
788 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
789 if (!dma_has_cap(DMA_XOR, device->cap_mask))
790 return false;
7b3cc2b1
DW
791
792 #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
4499a24d
DW
793 if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
794 return false;
138f4c35 795 #endif
7b3cc2b1 796 #endif
138f4c35
DW
797
798 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
799 if (!dma_has_cap(DMA_PQ, device->cap_mask))
800 return false;
7b3cc2b1
DW
801
802 #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
4499a24d
DW
803 if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
804 return false;
138f4c35 805 #endif
7b3cc2b1 806 #endif
138f4c35
DW
807
808 return true;
809}
810
257b17ca
DW
811static int get_dma_id(struct dma_device *device)
812{
813 int rc;
814
257b17ca 815 mutex_lock(&dma_list_mutex);
257b17ca 816
69ee266b
TH
817 rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
818 if (rc >= 0)
819 device->dev_id = rc;
820
821 mutex_unlock(&dma_list_mutex);
822 return rc < 0 ? rc : 0;
257b17ca
DW
823}
824
c13c8260 825/**
6508871e 826 * dma_async_device_register - registers DMA devices found
c13c8260
CL
827 * @device: &dma_device
828 */
829int dma_async_device_register(struct dma_device *device)
830{
ff487fb7 831 int chancnt = 0, rc;
c13c8260 832 struct dma_chan* chan;
864498aa 833 atomic_t *idr_ref;
c13c8260
CL
834
835 if (!device)
836 return -ENODEV;
837
7405f74b
DW
838 /* validate device routines */
839 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
840 !device->device_prep_dma_memcpy);
841 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
842 !device->device_prep_dma_xor);
099f53cb
DW
843 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
844 !device->device_prep_dma_xor_val);
b2f46fd8
DW
845 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
846 !device->device_prep_dma_pq);
847 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
848 !device->device_prep_dma_pq_val);
9b941c66 849 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 850 !device->device_prep_dma_interrupt);
a86ee03c
IS
851 BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
852 !device->device_prep_dma_sg);
782bc950
SH
853 BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
854 !device->device_prep_dma_cyclic);
b14dab79
JB
855 BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
856 !device->device_prep_interleaved_dma);
7405f74b 857
07934481 858 BUG_ON(!device->device_tx_status);
7405f74b
DW
859 BUG_ON(!device->device_issue_pending);
860 BUG_ON(!device->dev);
861
138f4c35 862 /* note: this only matters in the
5fc6d897 863 * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
138f4c35
DW
864 */
865 if (device_has_all_tx_types(device))
866 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
867
864498aa
DW
868 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
869 if (!idr_ref)
870 return -ENOMEM;
257b17ca
DW
871 rc = get_dma_id(device);
872 if (rc != 0) {
873 kfree(idr_ref);
864498aa 874 return rc;
257b17ca
DW
875 }
876
877 atomic_set(idr_ref, 0);
c13c8260
CL
878
879 /* represent channels in sysfs. Probably want devs too */
880 list_for_each_entry(chan, &device->channels, device_node) {
257b17ca 881 rc = -ENOMEM;
c13c8260
CL
882 chan->local = alloc_percpu(typeof(*chan->local));
883 if (chan->local == NULL)
257b17ca 884 goto err_out;
41d5e59c
DW
885 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
886 if (chan->dev == NULL) {
887 free_percpu(chan->local);
257b17ca
DW
888 chan->local = NULL;
889 goto err_out;
41d5e59c 890 }
c13c8260
CL
891
892 chan->chan_id = chancnt++;
41d5e59c
DW
893 chan->dev->device.class = &dma_devclass;
894 chan->dev->device.parent = device->dev;
895 chan->dev->chan = chan;
864498aa
DW
896 chan->dev->idr_ref = idr_ref;
897 chan->dev->dev_id = device->dev_id;
898 atomic_inc(idr_ref);
41d5e59c 899 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 900 device->dev_id, chan->chan_id);
c13c8260 901
41d5e59c 902 rc = device_register(&chan->dev->device);
ff487fb7 903 if (rc) {
ff487fb7
JG
904 free_percpu(chan->local);
905 chan->local = NULL;
257b17ca
DW
906 kfree(chan->dev);
907 atomic_dec(idr_ref);
ff487fb7
JG
908 goto err_out;
909 }
7cc5bf9a 910 chan->client_count = 0;
c13c8260 911 }
59b5ec21 912 device->chancnt = chancnt;
c13c8260
CL
913
914 mutex_lock(&dma_list_mutex);
59b5ec21
DW
915 /* take references on public channels */
916 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
917 list_for_each_entry(chan, &device->channels, device_node) {
918 /* if clients are already waiting for channels we need
919 * to take references on their behalf
920 */
921 if (dma_chan_get(chan) == -ENODEV) {
922 /* note we can only get here for the first
923 * channel as the remaining channels are
924 * guaranteed to get a reference
925 */
926 rc = -ENODEV;
927 mutex_unlock(&dma_list_mutex);
928 goto err_out;
929 }
930 }
2ba05622 931 list_add_tail_rcu(&device->global_node, &dma_device_list);
0f571515
AN
932 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
933 device->privatecnt++; /* Always private */
bec08513 934 dma_channel_rebalance();
c13c8260
CL
935 mutex_unlock(&dma_list_mutex);
936
c13c8260 937 return 0;
ff487fb7
JG
938
939err_out:
257b17ca
DW
940 /* if we never registered a channel just release the idr */
941 if (atomic_read(idr_ref) == 0) {
942 mutex_lock(&dma_list_mutex);
943 idr_remove(&dma_idr, device->dev_id);
944 mutex_unlock(&dma_list_mutex);
945 kfree(idr_ref);
946 return rc;
947 }
948
ff487fb7
JG
949 list_for_each_entry(chan, &device->channels, device_node) {
950 if (chan->local == NULL)
951 continue;
41d5e59c
DW
952 mutex_lock(&dma_list_mutex);
953 chan->dev->chan = NULL;
954 mutex_unlock(&dma_list_mutex);
955 device_unregister(&chan->dev->device);
ff487fb7
JG
956 free_percpu(chan->local);
957 }
958 return rc;
c13c8260 959}
765e3d8a 960EXPORT_SYMBOL(dma_async_device_register);
c13c8260 961
6508871e 962/**
6f49a57a 963 * dma_async_device_unregister - unregister a DMA device
6508871e 964 * @device: &dma_device
f27c580c
DW
965 *
966 * This routine is called by dma driver exit routines, dmaengine holds module
967 * references to prevent it being called while channels are in use.
6508871e
RD
968 */
969void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
970{
971 struct dma_chan *chan;
c13c8260
CL
972
973 mutex_lock(&dma_list_mutex);
2ba05622 974 list_del_rcu(&device->global_node);
bec08513 975 dma_channel_rebalance();
c13c8260
CL
976 mutex_unlock(&dma_list_mutex);
977
978 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
979 WARN_ONCE(chan->client_count,
980 "%s called while %d clients hold a reference\n",
981 __func__, chan->client_count);
41d5e59c
DW
982 mutex_lock(&dma_list_mutex);
983 chan->dev->chan = NULL;
984 mutex_unlock(&dma_list_mutex);
985 device_unregister(&chan->dev->device);
adef4772 986 free_percpu(chan->local);
c13c8260 987 }
c13c8260 988}
765e3d8a 989EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 990
45c463ae
DW
991struct dmaengine_unmap_pool {
992 struct kmem_cache *cache;
993 const char *name;
994 mempool_t *pool;
995 size_t size;
996};
7405f74b 997
45c463ae
DW
998#define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
999static struct dmaengine_unmap_pool unmap_pool[] = {
1000 __UNMAP_POOL(2),
3cc377b9 1001 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
45c463ae
DW
1002 __UNMAP_POOL(16),
1003 __UNMAP_POOL(128),
1004 __UNMAP_POOL(256),
1005 #endif
1006};
0036731c 1007
45c463ae
DW
1008static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
1009{
1010 int order = get_count_order(nr);
1011
1012 switch (order) {
1013 case 0 ... 1:
1014 return &unmap_pool[0];
1015 case 2 ... 4:
1016 return &unmap_pool[1];
1017 case 5 ... 7:
1018 return &unmap_pool[2];
1019 case 8:
1020 return &unmap_pool[3];
1021 default:
1022 BUG();
1023 return NULL;
0036731c 1024 }
45c463ae 1025}
7405f74b 1026
45c463ae
DW
1027static void dmaengine_unmap(struct kref *kref)
1028{
1029 struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
1030 struct device *dev = unmap->dev;
1031 int cnt, i;
1032
1033 cnt = unmap->to_cnt;
1034 for (i = 0; i < cnt; i++)
1035 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1036 DMA_TO_DEVICE);
1037 cnt += unmap->from_cnt;
1038 for (; i < cnt; i++)
1039 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1040 DMA_FROM_DEVICE);
1041 cnt += unmap->bidi_cnt;
7476bd79
DW
1042 for (; i < cnt; i++) {
1043 if (unmap->addr[i] == 0)
1044 continue;
45c463ae
DW
1045 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1046 DMA_BIDIRECTIONAL);
7476bd79 1047 }
c1f43dd9 1048 cnt = unmap->map_cnt;
45c463ae
DW
1049 mempool_free(unmap, __get_unmap_pool(cnt)->pool);
1050}
7405f74b 1051
45c463ae
DW
1052void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
1053{
1054 if (unmap)
1055 kref_put(&unmap->kref, dmaengine_unmap);
1056}
1057EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
7405f74b 1058
45c463ae
DW
1059static void dmaengine_destroy_unmap_pool(void)
1060{
1061 int i;
1062
1063 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1064 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1065
1066 if (p->pool)
1067 mempool_destroy(p->pool);
1068 p->pool = NULL;
1069 if (p->cache)
1070 kmem_cache_destroy(p->cache);
1071 p->cache = NULL;
1072 }
7405f74b 1073}
7405f74b 1074
45c463ae 1075static int __init dmaengine_init_unmap_pool(void)
7405f74b 1076{
45c463ae 1077 int i;
7405f74b 1078
45c463ae
DW
1079 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1080 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1081 size_t size;
0036731c 1082
45c463ae
DW
1083 size = sizeof(struct dmaengine_unmap_data) +
1084 sizeof(dma_addr_t) * p->size;
1085
1086 p->cache = kmem_cache_create(p->name, size, 0,
1087 SLAB_HWCACHE_ALIGN, NULL);
1088 if (!p->cache)
1089 break;
1090 p->pool = mempool_create_slab_pool(1, p->cache);
1091 if (!p->pool)
1092 break;
0036731c 1093 }
7405f74b 1094
45c463ae
DW
1095 if (i == ARRAY_SIZE(unmap_pool))
1096 return 0;
7405f74b 1097
45c463ae
DW
1098 dmaengine_destroy_unmap_pool();
1099 return -ENOMEM;
1100}
7405f74b 1101
89716462 1102struct dmaengine_unmap_data *
45c463ae
DW
1103dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
1104{
1105 struct dmaengine_unmap_data *unmap;
1106
1107 unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
1108 if (!unmap)
1109 return NULL;
1110
1111 memset(unmap, 0, sizeof(*unmap));
1112 kref_init(&unmap->kref);
1113 unmap->dev = dev;
c1f43dd9 1114 unmap->map_cnt = nr;
45c463ae
DW
1115
1116 return unmap;
7405f74b 1117}
89716462 1118EXPORT_SYMBOL(dmaengine_get_unmap_data);
7405f74b 1119
7405f74b
DW
1120void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1121 struct dma_chan *chan)
1122{
1123 tx->chan = chan;
5fc6d897 1124 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
7405f74b 1125 spin_lock_init(&tx->lock);
caa20d97 1126 #endif
7405f74b
DW
1127}
1128EXPORT_SYMBOL(dma_async_tx_descriptor_init);
1129
07f2211e
DW
1130/* dma_wait_for_async_tx - spin wait for a transaction to complete
1131 * @tx: in-flight transaction to wait on
07f2211e
DW
1132 */
1133enum dma_status
1134dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1135{
95475e57 1136 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
07f2211e
DW
1137
1138 if (!tx)
adfedd9a 1139 return DMA_COMPLETE;
07f2211e 1140
95475e57
DW
1141 while (tx->cookie == -EBUSY) {
1142 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
1143 pr_err("%s timeout waiting for descriptor submission\n",
63433250 1144 __func__);
95475e57
DW
1145 return DMA_ERROR;
1146 }
1147 cpu_relax();
1148 }
1149 return dma_sync_wait(tx->chan, tx->cookie);
07f2211e
DW
1150}
1151EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1152
1153/* dma_run_dependencies - helper routine for dma drivers to process
1154 * (start) dependent operations on their target channel
1155 * @tx: transaction with dependencies
1156 */
1157void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1158{
caa20d97 1159 struct dma_async_tx_descriptor *dep = txd_next(tx);
07f2211e
DW
1160 struct dma_async_tx_descriptor *dep_next;
1161 struct dma_chan *chan;
1162
1163 if (!dep)
1164 return;
1165
dd59b853 1166 /* we'll submit tx->next now, so clear the link */
caa20d97 1167 txd_clear_next(tx);
07f2211e
DW
1168 chan = dep->chan;
1169
1170 /* keep submitting up until a channel switch is detected
1171 * in that case we will be called again as a result of
1172 * processing the interrupt from async_tx_channel_switch
1173 */
1174 for (; dep; dep = dep_next) {
caa20d97
DW
1175 txd_lock(dep);
1176 txd_clear_parent(dep);
1177 dep_next = txd_next(dep);
07f2211e 1178 if (dep_next && dep_next->chan == chan)
caa20d97 1179 txd_clear_next(dep); /* ->next will be submitted */
07f2211e
DW
1180 else
1181 dep_next = NULL; /* submit current dep and terminate */
caa20d97 1182 txd_unlock(dep);
07f2211e
DW
1183
1184 dep->tx_submit(dep);
1185 }
1186
1187 chan->device->device_issue_pending(chan);
1188}
1189EXPORT_SYMBOL_GPL(dma_run_dependencies);
1190
c13c8260
CL
1191static int __init dma_bus_init(void)
1192{
45c463ae
DW
1193 int err = dmaengine_init_unmap_pool();
1194
1195 if (err)
1196 return err;
c13c8260
CL
1197 return class_register(&dma_devclass);
1198}
652afc27 1199arch_initcall(dma_bus_init);
c13c8260 1200
bec08513 1201
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