dmaengine: Add transfer termination synchronization support
[deliverable/linux.git] / drivers / dma / dmaengine.c
CommitLineData
c13c8260
CL
1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
c13c8260
CL
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
16 */
17
18/*
19 * This code implements the DMA subsystem. It provides a HW-neutral interface
20 * for other kernel code to use asynchronous memory copy capabilities,
21 * if present, and allows different HW DMA drivers to register as providing
22 * this capability.
23 *
24 * Due to the fact we are accelerating what is already a relatively fast
25 * operation, the code goes to great lengths to avoid additional overhead,
26 * such as locking.
27 *
28 * LOCKING:
29 *
aa1e6f1a
DW
30 * The subsystem keeps a global list of dma_device structs it is protected by a
31 * mutex, dma_list_mutex.
c13c8260 32 *
f27c580c
DW
33 * A subsystem can get access to a channel by calling dmaengine_get() followed
34 * by dma_find_channel(), or if it has need for an exclusive channel it can call
35 * dma_request_channel(). Once a channel is allocated a reference is taken
36 * against its corresponding driver to disable removal.
37 *
c13c8260
CL
38 * Each device has a channels list, which runs unlocked but is never modified
39 * once the device is registered, it's just setup by the driver.
40 *
f27c580c 41 * See Documentation/dmaengine.txt for more details
c13c8260
CL
42 */
43
63433250
JP
44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
b7f080cf 46#include <linux/dma-mapping.h>
c13c8260
CL
47#include <linux/init.h>
48#include <linux/module.h>
7405f74b 49#include <linux/mm.h>
c13c8260
CL
50#include <linux/device.h>
51#include <linux/dmaengine.h>
52#include <linux/hardirq.h>
53#include <linux/spinlock.h>
54#include <linux/percpu.h>
55#include <linux/rcupdate.h>
56#include <linux/mutex.h>
7405f74b 57#include <linux/jiffies.h>
2ba05622 58#include <linux/rculist.h>
864498aa 59#include <linux/idr.h>
5a0e3ad6 60#include <linux/slab.h>
4e82f5dd
AS
61#include <linux/acpi.h>
62#include <linux/acpi_dma.h>
9a6cecc8 63#include <linux/of_dma.h>
45c463ae 64#include <linux/mempool.h>
c13c8260
CL
65
66static DEFINE_MUTEX(dma_list_mutex);
21ef4b8b 67static DEFINE_IDR(dma_idr);
c13c8260 68static LIST_HEAD(dma_device_list);
6f49a57a 69static long dmaengine_ref_count;
c13c8260
CL
70
71/* --- sysfs implementation --- */
72
41d5e59c
DW
73/**
74 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
75 * @dev - device node
76 *
77 * Must be called under dma_list_mutex
78 */
79static struct dma_chan *dev_to_dma_chan(struct device *dev)
80{
81 struct dma_chan_dev *chan_dev;
82
83 chan_dev = container_of(dev, typeof(*chan_dev), device);
84 return chan_dev->chan;
85}
86
58b267d3
GKH
87static ssize_t memcpy_count_show(struct device *dev,
88 struct device_attribute *attr, char *buf)
c13c8260 89{
41d5e59c 90 struct dma_chan *chan;
c13c8260
CL
91 unsigned long count = 0;
92 int i;
41d5e59c 93 int err;
c13c8260 94
41d5e59c
DW
95 mutex_lock(&dma_list_mutex);
96 chan = dev_to_dma_chan(dev);
97 if (chan) {
98 for_each_possible_cpu(i)
99 count += per_cpu_ptr(chan->local, i)->memcpy_count;
100 err = sprintf(buf, "%lu\n", count);
101 } else
102 err = -ENODEV;
103 mutex_unlock(&dma_list_mutex);
c13c8260 104
41d5e59c 105 return err;
c13c8260 106}
58b267d3 107static DEVICE_ATTR_RO(memcpy_count);
c13c8260 108
58b267d3
GKH
109static ssize_t bytes_transferred_show(struct device *dev,
110 struct device_attribute *attr, char *buf)
c13c8260 111{
41d5e59c 112 struct dma_chan *chan;
c13c8260
CL
113 unsigned long count = 0;
114 int i;
41d5e59c 115 int err;
c13c8260 116
41d5e59c
DW
117 mutex_lock(&dma_list_mutex);
118 chan = dev_to_dma_chan(dev);
119 if (chan) {
120 for_each_possible_cpu(i)
121 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
122 err = sprintf(buf, "%lu\n", count);
123 } else
124 err = -ENODEV;
125 mutex_unlock(&dma_list_mutex);
c13c8260 126
41d5e59c 127 return err;
c13c8260 128}
58b267d3 129static DEVICE_ATTR_RO(bytes_transferred);
c13c8260 130
58b267d3
GKH
131static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
132 char *buf)
c13c8260 133{
41d5e59c
DW
134 struct dma_chan *chan;
135 int err;
c13c8260 136
41d5e59c
DW
137 mutex_lock(&dma_list_mutex);
138 chan = dev_to_dma_chan(dev);
139 if (chan)
140 err = sprintf(buf, "%d\n", chan->client_count);
141 else
142 err = -ENODEV;
143 mutex_unlock(&dma_list_mutex);
144
145 return err;
c13c8260 146}
58b267d3 147static DEVICE_ATTR_RO(in_use);
c13c8260 148
58b267d3
GKH
149static struct attribute *dma_dev_attrs[] = {
150 &dev_attr_memcpy_count.attr,
151 &dev_attr_bytes_transferred.attr,
152 &dev_attr_in_use.attr,
153 NULL,
c13c8260 154};
58b267d3 155ATTRIBUTE_GROUPS(dma_dev);
c13c8260 156
41d5e59c
DW
157static void chan_dev_release(struct device *dev)
158{
159 struct dma_chan_dev *chan_dev;
160
161 chan_dev = container_of(dev, typeof(*chan_dev), device);
864498aa
DW
162 if (atomic_dec_and_test(chan_dev->idr_ref)) {
163 mutex_lock(&dma_list_mutex);
164 idr_remove(&dma_idr, chan_dev->dev_id);
165 mutex_unlock(&dma_list_mutex);
166 kfree(chan_dev->idr_ref);
167 }
41d5e59c
DW
168 kfree(chan_dev);
169}
170
c13c8260 171static struct class dma_devclass = {
891f78ea 172 .name = "dma",
58b267d3 173 .dev_groups = dma_dev_groups,
41d5e59c 174 .dev_release = chan_dev_release,
c13c8260
CL
175};
176
177/* --- client and device registration --- */
178
59b5ec21
DW
179#define dma_device_satisfies_mask(device, mask) \
180 __dma_device_satisfies_mask((device), &(mask))
d379b01e 181static int
a53e28da
LPC
182__dma_device_satisfies_mask(struct dma_device *device,
183 const dma_cap_mask_t *want)
d379b01e
DW
184{
185 dma_cap_mask_t has;
186
59b5ec21 187 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
d379b01e
DW
188 DMA_TX_TYPE_END);
189 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
190}
191
6f49a57a
DW
192static struct module *dma_chan_to_owner(struct dma_chan *chan)
193{
194 return chan->device->dev->driver->owner;
195}
196
197/**
198 * balance_ref_count - catch up the channel reference count
199 * @chan - channel to balance ->client_count versus dmaengine_ref_count
200 *
201 * balance_ref_count must be called under dma_list_mutex
202 */
203static void balance_ref_count(struct dma_chan *chan)
204{
205 struct module *owner = dma_chan_to_owner(chan);
206
207 while (chan->client_count < dmaengine_ref_count) {
208 __module_get(owner);
209 chan->client_count++;
210 }
211}
212
213/**
214 * dma_chan_get - try to grab a dma channel's parent driver module
215 * @chan - channel to grab
216 *
217 * Must be called under dma_list_mutex
218 */
219static int dma_chan_get(struct dma_chan *chan)
220{
6f49a57a 221 struct module *owner = dma_chan_to_owner(chan);
d2f4f99d 222 int ret;
6f49a57a 223
d2f4f99d 224 /* The channel is already in use, update client count */
6f49a57a
DW
225 if (chan->client_count) {
226 __module_get(owner);
d2f4f99d
MR
227 goto out;
228 }
6f49a57a 229
d2f4f99d
MR
230 if (!try_module_get(owner))
231 return -ENODEV;
6f49a57a
DW
232
233 /* allocate upon first client reference */
c4b54a64
MR
234 if (chan->device->device_alloc_chan_resources) {
235 ret = chan->device->device_alloc_chan_resources(chan);
236 if (ret < 0)
237 goto err_out;
238 }
6f49a57a 239
d2f4f99d
MR
240 if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
241 balance_ref_count(chan);
242
243out:
244 chan->client_count++;
245 return 0;
246
247err_out:
248 module_put(owner);
249 return ret;
6f49a57a
DW
250}
251
252/**
253 * dma_chan_put - drop a reference to a dma channel's parent driver module
254 * @chan - channel to release
255 *
256 * Must be called under dma_list_mutex
257 */
258static void dma_chan_put(struct dma_chan *chan)
259{
c4b54a64 260 /* This channel is not in use, bail out */
6f49a57a 261 if (!chan->client_count)
c4b54a64
MR
262 return;
263
6f49a57a
DW
264 chan->client_count--;
265 module_put(dma_chan_to_owner(chan));
c4b54a64
MR
266
267 /* This channel is not in use anymore, free it */
b36f09c3
LPC
268 if (!chan->client_count && chan->device->device_free_chan_resources) {
269 /* Make sure all operations have completed */
270 dmaengine_synchronize(chan);
6f49a57a 271 chan->device->device_free_chan_resources(chan);
b36f09c3 272 }
56f13c0d
PU
273
274 /* If the channel is used via a DMA request router, free the mapping */
275 if (chan->router && chan->router->route_free) {
276 chan->router->route_free(chan->router->dev, chan->route_data);
277 chan->router = NULL;
278 chan->route_data = NULL;
279 }
6f49a57a
DW
280}
281
7405f74b
DW
282enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
283{
284 enum dma_status status;
285 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
286
287 dma_async_issue_pending(chan);
288 do {
289 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
290 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
63433250 291 pr_err("%s: timeout!\n", __func__);
7405f74b
DW
292 return DMA_ERROR;
293 }
2cbe7feb
BZ
294 if (status != DMA_IN_PROGRESS)
295 break;
296 cpu_relax();
297 } while (1);
7405f74b
DW
298
299 return status;
300}
301EXPORT_SYMBOL(dma_sync_wait);
302
bec08513
DW
303/**
304 * dma_cap_mask_all - enable iteration over all operation types
305 */
306static dma_cap_mask_t dma_cap_mask_all;
307
308/**
309 * dma_chan_tbl_ent - tracks channel allocations per core/operation
310 * @chan - associated channel for this entry
311 */
312struct dma_chan_tbl_ent {
313 struct dma_chan *chan;
314};
315
316/**
317 * channel_table - percpu lookup table for memory-to-memory offload providers
318 */
a29d8b8e 319static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
bec08513
DW
320
321static int __init dma_channel_table_init(void)
322{
323 enum dma_transaction_type cap;
324 int err = 0;
325
326 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
327
59b5ec21
DW
328 /* 'interrupt', 'private', and 'slave' are channel capabilities,
329 * but are not associated with an operation so they do not need
330 * an entry in the channel_table
bec08513
DW
331 */
332 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 333 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
bec08513
DW
334 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
335
336 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
337 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
338 if (!channel_table[cap]) {
339 err = -ENOMEM;
340 break;
341 }
342 }
343
344 if (err) {
63433250 345 pr_err("initialization failure\n");
bec08513 346 for_each_dma_cap_mask(cap, dma_cap_mask_all)
a9507ca3 347 free_percpu(channel_table[cap]);
bec08513
DW
348 }
349
350 return err;
351}
652afc27 352arch_initcall(dma_channel_table_init);
bec08513
DW
353
354/**
355 * dma_find_channel - find a channel to carry out the operation
356 * @tx_type: transaction type
357 */
358struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
359{
e7dcaa47 360 return this_cpu_read(channel_table[tx_type]->chan);
bec08513
DW
361}
362EXPORT_SYMBOL(dma_find_channel);
a2bd1140 363
2ba05622
DW
364/**
365 * dma_issue_pending_all - flush all pending operations across all channels
366 */
367void dma_issue_pending_all(void)
368{
369 struct dma_device *device;
370 struct dma_chan *chan;
371
2ba05622 372 rcu_read_lock();
59b5ec21
DW
373 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
374 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
375 continue;
2ba05622
DW
376 list_for_each_entry(chan, &device->channels, device_node)
377 if (chan->client_count)
378 device->device_issue_pending(chan);
59b5ec21 379 }
2ba05622
DW
380 rcu_read_unlock();
381}
382EXPORT_SYMBOL(dma_issue_pending_all);
383
bec08513 384/**
c4d27c4d
BG
385 * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
386 */
387static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
388{
389 int node = dev_to_node(chan->device->dev);
390 return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
391}
392
393/**
394 * min_chan - returns the channel with min count and in the same numa-node as the cpu
bec08513 395 * @cap: capability to match
c4d27c4d 396 * @cpu: cpu index which the channel should be close to
bec08513 397 *
c4d27c4d
BG
398 * If some channels are close to the given cpu, the one with the lowest
399 * reference count is returned. Otherwise, cpu is ignored and only the
400 * reference count is taken into account.
401 * Must be called under dma_list_mutex.
bec08513 402 */
c4d27c4d 403static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
bec08513
DW
404{
405 struct dma_device *device;
406 struct dma_chan *chan;
bec08513 407 struct dma_chan *min = NULL;
c4d27c4d 408 struct dma_chan *localmin = NULL;
bec08513
DW
409
410 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
411 if (!dma_has_cap(cap, device->cap_mask) ||
412 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
413 continue;
414 list_for_each_entry(chan, &device->channels, device_node) {
415 if (!chan->client_count)
416 continue;
c4d27c4d 417 if (!min || chan->table_count < min->table_count)
bec08513
DW
418 min = chan;
419
c4d27c4d
BG
420 if (dma_chan_is_local(chan, cpu))
421 if (!localmin ||
422 chan->table_count < localmin->table_count)
423 localmin = chan;
bec08513 424 }
bec08513
DW
425 }
426
c4d27c4d 427 chan = localmin ? localmin : min;
bec08513 428
c4d27c4d
BG
429 if (chan)
430 chan->table_count++;
bec08513 431
c4d27c4d 432 return chan;
bec08513
DW
433}
434
435/**
436 * dma_channel_rebalance - redistribute the available channels
437 *
438 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
439 * operation type) in the SMP case, and operation isolation (avoid
440 * multi-tasking channels) in the non-SMP case. Must be called under
441 * dma_list_mutex.
442 */
443static void dma_channel_rebalance(void)
444{
445 struct dma_chan *chan;
446 struct dma_device *device;
447 int cpu;
448 int cap;
bec08513
DW
449
450 /* undo the last distribution */
451 for_each_dma_cap_mask(cap, dma_cap_mask_all)
452 for_each_possible_cpu(cpu)
453 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
454
59b5ec21
DW
455 list_for_each_entry(device, &dma_device_list, global_node) {
456 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
457 continue;
bec08513
DW
458 list_for_each_entry(chan, &device->channels, device_node)
459 chan->table_count = 0;
59b5ec21 460 }
bec08513
DW
461
462 /* don't populate the channel_table if no clients are available */
463 if (!dmaengine_ref_count)
464 return;
465
466 /* redistribute available channels */
bec08513
DW
467 for_each_dma_cap_mask(cap, dma_cap_mask_all)
468 for_each_online_cpu(cpu) {
c4d27c4d 469 chan = min_chan(cap, cpu);
bec08513
DW
470 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
471 }
472}
473
0d5484b1
LP
474int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
475{
476 struct dma_device *device;
477
478 if (!chan || !caps)
479 return -EINVAL;
480
481 device = chan->device;
482
483 /* check if the channel supports slave transactions */
484 if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
485 return -ENXIO;
486
487 /*
488 * Check whether it reports it uses the generic slave
489 * capabilities, if not, that means it doesn't support any
490 * kind of slave capabilities reporting.
491 */
492 if (!device->directions)
493 return -ENXIO;
494
495 caps->src_addr_widths = device->src_addr_widths;
496 caps->dst_addr_widths = device->dst_addr_widths;
497 caps->directions = device->directions;
498 caps->residue_granularity = device->residue_granularity;
499
88d04643
KK
500 /*
501 * Some devices implement only pause (e.g. to get residuum) but no
502 * resume. However cmd_pause is advertised as pause AND resume.
503 */
504 caps->cmd_pause = !!(device->device_pause && device->device_resume);
0d5484b1
LP
505 caps->cmd_terminate = !!device->device_terminate_all;
506
507 return 0;
508}
509EXPORT_SYMBOL_GPL(dma_get_slave_caps);
510
a53e28da
LPC
511static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
512 struct dma_device *dev,
e2346677 513 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
514{
515 struct dma_chan *chan;
59b5ec21
DW
516
517 if (!__dma_device_satisfies_mask(dev, mask)) {
518 pr_debug("%s: wrong capabilities\n", __func__);
519 return NULL;
520 }
521 /* devices with multiple channels need special handling as we need to
522 * ensure that all channels are either private or public.
523 */
524 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
525 list_for_each_entry(chan, &dev->channels, device_node) {
526 /* some channels are already publicly allocated */
527 if (chan->client_count)
528 return NULL;
529 }
530
531 list_for_each_entry(chan, &dev->channels, device_node) {
532 if (chan->client_count) {
533 pr_debug("%s: %s busy\n",
41d5e59c 534 __func__, dma_chan_name(chan));
59b5ec21
DW
535 continue;
536 }
e2346677
DW
537 if (fn && !fn(chan, fn_param)) {
538 pr_debug("%s: %s filter said false\n",
539 __func__, dma_chan_name(chan));
540 continue;
541 }
542 return chan;
59b5ec21
DW
543 }
544
e2346677 545 return NULL;
59b5ec21
DW
546}
547
548/**
19d643d6 549 * dma_get_slave_channel - try to get specific channel exclusively
7bb587f4
ZG
550 * @chan: target channel
551 */
552struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
553{
554 int err = -EBUSY;
555
556 /* lock against __dma_request_channel */
557 mutex_lock(&dma_list_mutex);
558
d9a6c8f5 559 if (chan->client_count == 0) {
214fc4e4
PU
560 struct dma_device *device = chan->device;
561
562 dma_cap_set(DMA_PRIVATE, device->cap_mask);
563 device->privatecnt++;
7bb587f4 564 err = dma_chan_get(chan);
214fc4e4 565 if (err) {
d9a6c8f5
VK
566 pr_debug("%s: failed to get %s: (%d)\n",
567 __func__, dma_chan_name(chan), err);
214fc4e4
PU
568 chan = NULL;
569 if (--device->privatecnt == 0)
570 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
571 }
d9a6c8f5 572 } else
7bb587f4
ZG
573 chan = NULL;
574
575 mutex_unlock(&dma_list_mutex);
576
7bb587f4
ZG
577
578 return chan;
579}
580EXPORT_SYMBOL_GPL(dma_get_slave_channel);
581
8010dad5
SW
582struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
583{
584 dma_cap_mask_t mask;
585 struct dma_chan *chan;
586 int err;
587
588 dma_cap_zero(mask);
589 dma_cap_set(DMA_SLAVE, mask);
590
591 /* lock against __dma_request_channel */
592 mutex_lock(&dma_list_mutex);
593
594 chan = private_candidate(&mask, device, NULL, NULL);
595 if (chan) {
63f89caa
CF
596 dma_cap_set(DMA_PRIVATE, device->cap_mask);
597 device->privatecnt++;
8010dad5
SW
598 err = dma_chan_get(chan);
599 if (err) {
600 pr_debug("%s: failed to get %s: (%d)\n",
601 __func__, dma_chan_name(chan), err);
602 chan = NULL;
63f89caa
CF
603 if (--device->privatecnt == 0)
604 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
8010dad5
SW
605 }
606 }
607
608 mutex_unlock(&dma_list_mutex);
609
610 return chan;
611}
612EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
613
59b5ec21 614/**
6b9019a7 615 * __dma_request_channel - try to allocate an exclusive channel
59b5ec21
DW
616 * @mask: capabilities that the channel must satisfy
617 * @fn: optional callback to disposition available channels
618 * @fn_param: opaque parameter to pass to dma_filter_fn
0ad7c000
SW
619 *
620 * Returns pointer to appropriate DMA channel on success or NULL.
59b5ec21 621 */
a53e28da
LPC
622struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
623 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
624{
625 struct dma_device *device, *_d;
626 struct dma_chan *chan = NULL;
59b5ec21
DW
627 int err;
628
629 /* Find a channel */
630 mutex_lock(&dma_list_mutex);
631 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
e2346677
DW
632 chan = private_candidate(mask, device, fn, fn_param);
633 if (chan) {
59b5ec21
DW
634 /* Found a suitable channel, try to grab, prep, and
635 * return it. We first set DMA_PRIVATE to disable
636 * balance_ref_count as this channel will not be
637 * published in the general-purpose allocator
638 */
639 dma_cap_set(DMA_PRIVATE, device->cap_mask);
0f571515 640 device->privatecnt++;
59b5ec21
DW
641 err = dma_chan_get(chan);
642
643 if (err == -ENODEV) {
63433250
JP
644 pr_debug("%s: %s module removed\n",
645 __func__, dma_chan_name(chan));
59b5ec21
DW
646 list_del_rcu(&device->global_node);
647 } else if (err)
d8b53489 648 pr_debug("%s: failed to get %s: (%d)\n",
63433250 649 __func__, dma_chan_name(chan), err);
59b5ec21
DW
650 else
651 break;
0f571515
AN
652 if (--device->privatecnt == 0)
653 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
e2346677
DW
654 chan = NULL;
655 }
59b5ec21
DW
656 }
657 mutex_unlock(&dma_list_mutex);
658
63433250
JP
659 pr_debug("%s: %s (%s)\n",
660 __func__,
661 chan ? "success" : "fail",
41d5e59c 662 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
663
664 return chan;
665}
666EXPORT_SYMBOL_GPL(__dma_request_channel);
667
9a6cecc8 668/**
19d643d6 669 * dma_request_slave_channel_reason - try to allocate an exclusive slave channel
9a6cecc8
JH
670 * @dev: pointer to client device structure
671 * @name: slave channel name
0ad7c000
SW
672 *
673 * Returns pointer to appropriate DMA channel on success or an error pointer.
9a6cecc8 674 */
0ad7c000
SW
675struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
676 const char *name)
9a6cecc8
JH
677{
678 /* If device-tree is present get slave info from here */
679 if (dev->of_node)
680 return of_dma_request_slave_channel(dev->of_node, name);
681
4e82f5dd 682 /* If device was enumerated by ACPI get slave info from here */
0f6a928d
AS
683 if (ACPI_HANDLE(dev))
684 return acpi_dma_request_slave_chan_by_name(dev, name);
4e82f5dd 685
0ad7c000
SW
686 return ERR_PTR(-ENODEV);
687}
688EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
689
690/**
691 * dma_request_slave_channel - try to allocate an exclusive slave channel
692 * @dev: pointer to client device structure
693 * @name: slave channel name
694 *
695 * Returns pointer to appropriate DMA channel on success or NULL.
696 */
697struct dma_chan *dma_request_slave_channel(struct device *dev,
698 const char *name)
699{
700 struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
701 if (IS_ERR(ch))
702 return NULL;
05aa1a77
RB
703
704 dma_cap_set(DMA_PRIVATE, ch->device->cap_mask);
705 ch->device->privatecnt++;
706
0ad7c000 707 return ch;
9a6cecc8
JH
708}
709EXPORT_SYMBOL_GPL(dma_request_slave_channel);
710
59b5ec21
DW
711void dma_release_channel(struct dma_chan *chan)
712{
713 mutex_lock(&dma_list_mutex);
714 WARN_ONCE(chan->client_count != 1,
715 "chan reference count %d != 1\n", chan->client_count);
716 dma_chan_put(chan);
0f571515
AN
717 /* drop PRIVATE cap enabled by __dma_request_channel() */
718 if (--chan->device->privatecnt == 0)
719 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
59b5ec21
DW
720 mutex_unlock(&dma_list_mutex);
721}
722EXPORT_SYMBOL_GPL(dma_release_channel);
723
d379b01e 724/**
209b84a8 725 * dmaengine_get - register interest in dma_channels
d379b01e 726 */
209b84a8 727void dmaengine_get(void)
d379b01e 728{
6f49a57a
DW
729 struct dma_device *device, *_d;
730 struct dma_chan *chan;
731 int err;
732
c13c8260 733 mutex_lock(&dma_list_mutex);
6f49a57a
DW
734 dmaengine_ref_count++;
735
736 /* try to grab channels */
59b5ec21
DW
737 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
738 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
739 continue;
6f49a57a
DW
740 list_for_each_entry(chan, &device->channels, device_node) {
741 err = dma_chan_get(chan);
742 if (err == -ENODEV) {
743 /* module removed before we could use it */
2ba05622 744 list_del_rcu(&device->global_node);
6f49a57a
DW
745 break;
746 } else if (err)
0eb5a358 747 pr_debug("%s: failed to get %s: (%d)\n",
63433250 748 __func__, dma_chan_name(chan), err);
6f49a57a 749 }
59b5ec21 750 }
6f49a57a 751
bec08513
DW
752 /* if this is the first reference and there were channels
753 * waiting we need to rebalance to get those channels
754 * incorporated into the channel table
755 */
756 if (dmaengine_ref_count == 1)
757 dma_channel_rebalance();
c13c8260 758 mutex_unlock(&dma_list_mutex);
c13c8260 759}
209b84a8 760EXPORT_SYMBOL(dmaengine_get);
c13c8260
CL
761
762/**
209b84a8 763 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 764 */
209b84a8 765void dmaengine_put(void)
c13c8260 766{
d379b01e 767 struct dma_device *device;
c13c8260
CL
768 struct dma_chan *chan;
769
c13c8260 770 mutex_lock(&dma_list_mutex);
6f49a57a
DW
771 dmaengine_ref_count--;
772 BUG_ON(dmaengine_ref_count < 0);
773 /* drop channel references */
59b5ec21
DW
774 list_for_each_entry(device, &dma_device_list, global_node) {
775 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
776 continue;
6f49a57a
DW
777 list_for_each_entry(chan, &device->channels, device_node)
778 dma_chan_put(chan);
59b5ec21 779 }
c13c8260 780 mutex_unlock(&dma_list_mutex);
c13c8260 781}
209b84a8 782EXPORT_SYMBOL(dmaengine_put);
c13c8260 783
138f4c35
DW
784static bool device_has_all_tx_types(struct dma_device *device)
785{
786 /* A device that satisfies this test has channels that will never cause
787 * an async_tx channel switch event as all possible operation types can
788 * be handled.
789 */
790 #ifdef CONFIG_ASYNC_TX_DMA
791 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
792 return false;
793 #endif
794
795 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
796 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
797 return false;
798 #endif
799
138f4c35
DW
800 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
801 if (!dma_has_cap(DMA_XOR, device->cap_mask))
802 return false;
7b3cc2b1
DW
803
804 #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
4499a24d
DW
805 if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
806 return false;
138f4c35 807 #endif
7b3cc2b1 808 #endif
138f4c35
DW
809
810 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
811 if (!dma_has_cap(DMA_PQ, device->cap_mask))
812 return false;
7b3cc2b1
DW
813
814 #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
4499a24d
DW
815 if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
816 return false;
138f4c35 817 #endif
7b3cc2b1 818 #endif
138f4c35
DW
819
820 return true;
821}
822
257b17ca
DW
823static int get_dma_id(struct dma_device *device)
824{
825 int rc;
826
257b17ca 827 mutex_lock(&dma_list_mutex);
257b17ca 828
69ee266b
TH
829 rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
830 if (rc >= 0)
831 device->dev_id = rc;
832
833 mutex_unlock(&dma_list_mutex);
834 return rc < 0 ? rc : 0;
257b17ca
DW
835}
836
c13c8260 837/**
6508871e 838 * dma_async_device_register - registers DMA devices found
c13c8260
CL
839 * @device: &dma_device
840 */
841int dma_async_device_register(struct dma_device *device)
842{
ff487fb7 843 int chancnt = 0, rc;
c13c8260 844 struct dma_chan* chan;
864498aa 845 atomic_t *idr_ref;
c13c8260
CL
846
847 if (!device)
848 return -ENODEV;
849
7405f74b
DW
850 /* validate device routines */
851 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
852 !device->device_prep_dma_memcpy);
853 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
854 !device->device_prep_dma_xor);
099f53cb
DW
855 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
856 !device->device_prep_dma_xor_val);
b2f46fd8
DW
857 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
858 !device->device_prep_dma_pq);
859 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
860 !device->device_prep_dma_pq_val);
4983a501
MR
861 BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
862 !device->device_prep_dma_memset);
9b941c66 863 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 864 !device->device_prep_dma_interrupt);
a86ee03c
IS
865 BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
866 !device->device_prep_dma_sg);
782bc950
SH
867 BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
868 !device->device_prep_dma_cyclic);
b14dab79
JB
869 BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
870 !device->device_prep_interleaved_dma);
7405f74b 871
07934481 872 BUG_ON(!device->device_tx_status);
7405f74b
DW
873 BUG_ON(!device->device_issue_pending);
874 BUG_ON(!device->dev);
875
138f4c35 876 /* note: this only matters in the
5fc6d897 877 * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
138f4c35
DW
878 */
879 if (device_has_all_tx_types(device))
880 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
881
864498aa
DW
882 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
883 if (!idr_ref)
884 return -ENOMEM;
257b17ca
DW
885 rc = get_dma_id(device);
886 if (rc != 0) {
887 kfree(idr_ref);
864498aa 888 return rc;
257b17ca
DW
889 }
890
891 atomic_set(idr_ref, 0);
c13c8260
CL
892
893 /* represent channels in sysfs. Probably want devs too */
894 list_for_each_entry(chan, &device->channels, device_node) {
257b17ca 895 rc = -ENOMEM;
c13c8260
CL
896 chan->local = alloc_percpu(typeof(*chan->local));
897 if (chan->local == NULL)
257b17ca 898 goto err_out;
41d5e59c
DW
899 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
900 if (chan->dev == NULL) {
901 free_percpu(chan->local);
257b17ca
DW
902 chan->local = NULL;
903 goto err_out;
41d5e59c 904 }
c13c8260
CL
905
906 chan->chan_id = chancnt++;
41d5e59c
DW
907 chan->dev->device.class = &dma_devclass;
908 chan->dev->device.parent = device->dev;
909 chan->dev->chan = chan;
864498aa
DW
910 chan->dev->idr_ref = idr_ref;
911 chan->dev->dev_id = device->dev_id;
912 atomic_inc(idr_ref);
41d5e59c 913 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 914 device->dev_id, chan->chan_id);
c13c8260 915
41d5e59c 916 rc = device_register(&chan->dev->device);
ff487fb7 917 if (rc) {
ff487fb7
JG
918 free_percpu(chan->local);
919 chan->local = NULL;
257b17ca
DW
920 kfree(chan->dev);
921 atomic_dec(idr_ref);
ff487fb7
JG
922 goto err_out;
923 }
7cc5bf9a 924 chan->client_count = 0;
c13c8260 925 }
59b5ec21 926 device->chancnt = chancnt;
c13c8260
CL
927
928 mutex_lock(&dma_list_mutex);
59b5ec21
DW
929 /* take references on public channels */
930 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
931 list_for_each_entry(chan, &device->channels, device_node) {
932 /* if clients are already waiting for channels we need
933 * to take references on their behalf
934 */
935 if (dma_chan_get(chan) == -ENODEV) {
936 /* note we can only get here for the first
937 * channel as the remaining channels are
938 * guaranteed to get a reference
939 */
940 rc = -ENODEV;
941 mutex_unlock(&dma_list_mutex);
942 goto err_out;
943 }
944 }
2ba05622 945 list_add_tail_rcu(&device->global_node, &dma_device_list);
0f571515
AN
946 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
947 device->privatecnt++; /* Always private */
bec08513 948 dma_channel_rebalance();
c13c8260
CL
949 mutex_unlock(&dma_list_mutex);
950
c13c8260 951 return 0;
ff487fb7
JG
952
953err_out:
257b17ca
DW
954 /* if we never registered a channel just release the idr */
955 if (atomic_read(idr_ref) == 0) {
956 mutex_lock(&dma_list_mutex);
957 idr_remove(&dma_idr, device->dev_id);
958 mutex_unlock(&dma_list_mutex);
959 kfree(idr_ref);
960 return rc;
961 }
962
ff487fb7
JG
963 list_for_each_entry(chan, &device->channels, device_node) {
964 if (chan->local == NULL)
965 continue;
41d5e59c
DW
966 mutex_lock(&dma_list_mutex);
967 chan->dev->chan = NULL;
968 mutex_unlock(&dma_list_mutex);
969 device_unregister(&chan->dev->device);
ff487fb7
JG
970 free_percpu(chan->local);
971 }
972 return rc;
c13c8260 973}
765e3d8a 974EXPORT_SYMBOL(dma_async_device_register);
c13c8260 975
6508871e 976/**
6f49a57a 977 * dma_async_device_unregister - unregister a DMA device
6508871e 978 * @device: &dma_device
f27c580c
DW
979 *
980 * This routine is called by dma driver exit routines, dmaengine holds module
981 * references to prevent it being called while channels are in use.
6508871e
RD
982 */
983void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
984{
985 struct dma_chan *chan;
c13c8260
CL
986
987 mutex_lock(&dma_list_mutex);
2ba05622 988 list_del_rcu(&device->global_node);
bec08513 989 dma_channel_rebalance();
c13c8260
CL
990 mutex_unlock(&dma_list_mutex);
991
992 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
993 WARN_ONCE(chan->client_count,
994 "%s called while %d clients hold a reference\n",
995 __func__, chan->client_count);
41d5e59c
DW
996 mutex_lock(&dma_list_mutex);
997 chan->dev->chan = NULL;
998 mutex_unlock(&dma_list_mutex);
999 device_unregister(&chan->dev->device);
adef4772 1000 free_percpu(chan->local);
c13c8260 1001 }
c13c8260 1002}
765e3d8a 1003EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 1004
45c463ae
DW
1005struct dmaengine_unmap_pool {
1006 struct kmem_cache *cache;
1007 const char *name;
1008 mempool_t *pool;
1009 size_t size;
1010};
7405f74b 1011
45c463ae
DW
1012#define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
1013static struct dmaengine_unmap_pool unmap_pool[] = {
1014 __UNMAP_POOL(2),
3cc377b9 1015 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
45c463ae
DW
1016 __UNMAP_POOL(16),
1017 __UNMAP_POOL(128),
1018 __UNMAP_POOL(256),
1019 #endif
1020};
0036731c 1021
45c463ae
DW
1022static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
1023{
1024 int order = get_count_order(nr);
1025
1026 switch (order) {
1027 case 0 ... 1:
1028 return &unmap_pool[0];
1029 case 2 ... 4:
1030 return &unmap_pool[1];
1031 case 5 ... 7:
1032 return &unmap_pool[2];
1033 case 8:
1034 return &unmap_pool[3];
1035 default:
1036 BUG();
1037 return NULL;
0036731c 1038 }
45c463ae 1039}
7405f74b 1040
45c463ae
DW
1041static void dmaengine_unmap(struct kref *kref)
1042{
1043 struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
1044 struct device *dev = unmap->dev;
1045 int cnt, i;
1046
1047 cnt = unmap->to_cnt;
1048 for (i = 0; i < cnt; i++)
1049 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1050 DMA_TO_DEVICE);
1051 cnt += unmap->from_cnt;
1052 for (; i < cnt; i++)
1053 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1054 DMA_FROM_DEVICE);
1055 cnt += unmap->bidi_cnt;
7476bd79
DW
1056 for (; i < cnt; i++) {
1057 if (unmap->addr[i] == 0)
1058 continue;
45c463ae
DW
1059 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1060 DMA_BIDIRECTIONAL);
7476bd79 1061 }
c1f43dd9 1062 cnt = unmap->map_cnt;
45c463ae
DW
1063 mempool_free(unmap, __get_unmap_pool(cnt)->pool);
1064}
7405f74b 1065
45c463ae
DW
1066void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
1067{
1068 if (unmap)
1069 kref_put(&unmap->kref, dmaengine_unmap);
1070}
1071EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
7405f74b 1072
45c463ae
DW
1073static void dmaengine_destroy_unmap_pool(void)
1074{
1075 int i;
1076
1077 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1078 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1079
240eb916 1080 mempool_destroy(p->pool);
45c463ae 1081 p->pool = NULL;
240eb916 1082 kmem_cache_destroy(p->cache);
45c463ae
DW
1083 p->cache = NULL;
1084 }
7405f74b 1085}
7405f74b 1086
45c463ae 1087static int __init dmaengine_init_unmap_pool(void)
7405f74b 1088{
45c463ae 1089 int i;
7405f74b 1090
45c463ae
DW
1091 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1092 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1093 size_t size;
0036731c 1094
45c463ae
DW
1095 size = sizeof(struct dmaengine_unmap_data) +
1096 sizeof(dma_addr_t) * p->size;
1097
1098 p->cache = kmem_cache_create(p->name, size, 0,
1099 SLAB_HWCACHE_ALIGN, NULL);
1100 if (!p->cache)
1101 break;
1102 p->pool = mempool_create_slab_pool(1, p->cache);
1103 if (!p->pool)
1104 break;
0036731c 1105 }
7405f74b 1106
45c463ae
DW
1107 if (i == ARRAY_SIZE(unmap_pool))
1108 return 0;
7405f74b 1109
45c463ae
DW
1110 dmaengine_destroy_unmap_pool();
1111 return -ENOMEM;
1112}
7405f74b 1113
89716462 1114struct dmaengine_unmap_data *
45c463ae
DW
1115dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
1116{
1117 struct dmaengine_unmap_data *unmap;
1118
1119 unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
1120 if (!unmap)
1121 return NULL;
1122
1123 memset(unmap, 0, sizeof(*unmap));
1124 kref_init(&unmap->kref);
1125 unmap->dev = dev;
c1f43dd9 1126 unmap->map_cnt = nr;
45c463ae
DW
1127
1128 return unmap;
7405f74b 1129}
89716462 1130EXPORT_SYMBOL(dmaengine_get_unmap_data);
7405f74b 1131
7405f74b
DW
1132void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1133 struct dma_chan *chan)
1134{
1135 tx->chan = chan;
5fc6d897 1136 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
7405f74b 1137 spin_lock_init(&tx->lock);
caa20d97 1138 #endif
7405f74b
DW
1139}
1140EXPORT_SYMBOL(dma_async_tx_descriptor_init);
1141
07f2211e
DW
1142/* dma_wait_for_async_tx - spin wait for a transaction to complete
1143 * @tx: in-flight transaction to wait on
07f2211e
DW
1144 */
1145enum dma_status
1146dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1147{
95475e57 1148 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
07f2211e
DW
1149
1150 if (!tx)
adfedd9a 1151 return DMA_COMPLETE;
07f2211e 1152
95475e57
DW
1153 while (tx->cookie == -EBUSY) {
1154 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
1155 pr_err("%s timeout waiting for descriptor submission\n",
63433250 1156 __func__);
95475e57
DW
1157 return DMA_ERROR;
1158 }
1159 cpu_relax();
1160 }
1161 return dma_sync_wait(tx->chan, tx->cookie);
07f2211e
DW
1162}
1163EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1164
1165/* dma_run_dependencies - helper routine for dma drivers to process
1166 * (start) dependent operations on their target channel
1167 * @tx: transaction with dependencies
1168 */
1169void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1170{
caa20d97 1171 struct dma_async_tx_descriptor *dep = txd_next(tx);
07f2211e
DW
1172 struct dma_async_tx_descriptor *dep_next;
1173 struct dma_chan *chan;
1174
1175 if (!dep)
1176 return;
1177
dd59b853 1178 /* we'll submit tx->next now, so clear the link */
caa20d97 1179 txd_clear_next(tx);
07f2211e
DW
1180 chan = dep->chan;
1181
1182 /* keep submitting up until a channel switch is detected
1183 * in that case we will be called again as a result of
1184 * processing the interrupt from async_tx_channel_switch
1185 */
1186 for (; dep; dep = dep_next) {
caa20d97
DW
1187 txd_lock(dep);
1188 txd_clear_parent(dep);
1189 dep_next = txd_next(dep);
07f2211e 1190 if (dep_next && dep_next->chan == chan)
caa20d97 1191 txd_clear_next(dep); /* ->next will be submitted */
07f2211e
DW
1192 else
1193 dep_next = NULL; /* submit current dep and terminate */
caa20d97 1194 txd_unlock(dep);
07f2211e
DW
1195
1196 dep->tx_submit(dep);
1197 }
1198
1199 chan->device->device_issue_pending(chan);
1200}
1201EXPORT_SYMBOL_GPL(dma_run_dependencies);
1202
c13c8260
CL
1203static int __init dma_bus_init(void)
1204{
45c463ae
DW
1205 int err = dmaengine_init_unmap_pool();
1206
1207 if (err)
1208 return err;
c13c8260
CL
1209 return class_register(&dma_devclass);
1210}
652afc27 1211arch_initcall(dma_bus_init);
c13c8260 1212
bec08513 1213
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