Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/delay.h> |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/module.h> | |
3bfb1d20 HS |
24 | #include <linux/slab.h> |
25 | ||
61a76496 | 26 | #include "../dmaengine.h" |
9cade1a4 | 27 | #include "internal.h" |
3bfb1d20 HS |
28 | |
29 | /* | |
30 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
31 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
32 | * of which use ARM any more). See the "Databook" from Synopsys for | |
33 | * information beyond what licensees probably provide. | |
34 | * | |
dd5720b3 AS |
35 | * The driver has been tested with the Atmel AT32AP7000, which does not |
36 | * support descriptor writeback. | |
3bfb1d20 HS |
37 | */ |
38 | ||
327e6970 | 39 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
40 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
41 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 42 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 43 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 44 | DW_DMA_MSIZE_16; \ |
495aea4b | 45 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 46 | DW_DMA_MSIZE_16; \ |
f301c062 | 47 | \ |
327e6970 VK |
48 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
49 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
50 | | DWC_CTLL_LLP_D_EN \ |
51 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
52 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
53 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 54 | }) |
3bfb1d20 | 55 | |
3bfb1d20 HS |
56 | /* |
57 | * Number of descriptors to allocate for each channel. This should be | |
58 | * made configurable somehow; preferably, the clients (at least the | |
59 | * ones using slave transfers) should be able to give us a hint. | |
60 | */ | |
61 | #define NR_DESCS_PER_CHANNEL 64 | |
62 | ||
63 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 64 | |
41d5e59c DW |
65 | static struct device *chan2dev(struct dma_chan *chan) |
66 | { | |
67 | return &chan->dev->device; | |
68 | } | |
41d5e59c | 69 | |
3bfb1d20 HS |
70 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
71 | { | |
e63a47a3 | 72 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
73 | } |
74 | ||
3bfb1d20 HS |
75 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
76 | { | |
77 | struct dw_desc *desc, *_desc; | |
78 | struct dw_desc *ret = NULL; | |
79 | unsigned int i = 0; | |
69cea5a0 | 80 | unsigned long flags; |
3bfb1d20 | 81 | |
69cea5a0 | 82 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 83 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 84 | i++; |
3bfb1d20 HS |
85 | if (async_tx_test_ack(&desc->txd)) { |
86 | list_del(&desc->desc_node); | |
87 | ret = desc; | |
88 | break; | |
89 | } | |
41d5e59c | 90 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 91 | } |
69cea5a0 | 92 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 93 | |
41d5e59c | 94 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
95 | |
96 | return ret; | |
97 | } | |
98 | ||
3bfb1d20 HS |
99 | /* |
100 | * Move a descriptor, including any children, to the free list. | |
101 | * `desc' must not be on any lists. | |
102 | */ | |
103 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
104 | { | |
69cea5a0 VK |
105 | unsigned long flags; |
106 | ||
3bfb1d20 HS |
107 | if (desc) { |
108 | struct dw_desc *child; | |
109 | ||
69cea5a0 | 110 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 111 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 112 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
113 | "moving child desc %p to freelist\n", |
114 | child); | |
e0bd0f8c | 115 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 116 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 117 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 118 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
119 | } |
120 | } | |
121 | ||
61e183f8 VK |
122 | static void dwc_initialize(struct dw_dma_chan *dwc) |
123 | { | |
124 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
125 | struct dw_dma_slave *dws = dwc->chan.private; | |
126 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
127 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
128 | ||
129 | if (dwc->initialized == true) | |
130 | return; | |
131 | ||
f776076b | 132 | if (dws) { |
61e183f8 VK |
133 | /* |
134 | * We need controller-specific data to set up slave | |
135 | * transfers. | |
136 | */ | |
137 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
138 | ||
7e1e2f27 AS |
139 | cfghi |= DWC_CFGH_DST_PER(dws->dst_id); |
140 | cfghi |= DWC_CFGH_SRC_PER(dws->src_id); | |
8fccc5bf | 141 | } else { |
89500520 AS |
142 | cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); |
143 | cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); | |
61e183f8 VK |
144 | } |
145 | ||
146 | channel_writel(dwc, CFG_LO, cfglo); | |
147 | channel_writel(dwc, CFG_HI, cfghi); | |
148 | ||
149 | /* Enable interrupts */ | |
150 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
151 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
152 | ||
153 | dwc->initialized = true; | |
154 | } | |
155 | ||
3bfb1d20 HS |
156 | /*----------------------------------------------------------------------*/ |
157 | ||
4c2d56c5 AS |
158 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
159 | { | |
160 | /* | |
161 | * We can be a lot more clever here, but this should take care | |
162 | * of the most common optimization. | |
163 | */ | |
164 | if (!(v & 7)) | |
165 | return 3; | |
166 | else if (!(v & 3)) | |
167 | return 2; | |
168 | else if (!(v & 1)) | |
169 | return 1; | |
170 | return 0; | |
171 | } | |
172 | ||
f52b36d2 | 173 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
174 | { |
175 | dev_err(chan2dev(&dwc->chan), | |
176 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
177 | channel_readl(dwc, SAR), | |
178 | channel_readl(dwc, DAR), | |
179 | channel_readl(dwc, LLP), | |
180 | channel_readl(dwc, CTL_HI), | |
181 | channel_readl(dwc, CTL_LO)); | |
182 | } | |
183 | ||
3f936207 AS |
184 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
185 | { | |
186 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
187 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
188 | cpu_relax(); | |
189 | } | |
190 | ||
1d455437 AS |
191 | /*----------------------------------------------------------------------*/ |
192 | ||
fed2574b AS |
193 | /* Perform single block transfer */ |
194 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
195 | struct dw_desc *desc) | |
196 | { | |
197 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
198 | u32 ctllo; | |
199 | ||
1d566f11 AS |
200 | /* |
201 | * Software emulation of LLP mode relies on interrupts to continue | |
202 | * multi block transfer. | |
203 | */ | |
fed2574b AS |
204 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
205 | ||
206 | channel_writel(dwc, SAR, desc->lli.sar); | |
207 | channel_writel(dwc, DAR, desc->lli.dar); | |
208 | channel_writel(dwc, CTL_LO, ctllo); | |
209 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
210 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
211 | |
212 | /* Move pointer to next descriptor */ | |
213 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
214 | } |
215 | ||
3bfb1d20 HS |
216 | /* Called with dwc->lock held and bh disabled */ |
217 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
218 | { | |
219 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 220 | unsigned long was_soft_llp; |
3bfb1d20 HS |
221 | |
222 | /* ASSERT: channel is idle */ | |
223 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 224 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 225 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 226 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
227 | |
228 | /* The tasklet will hopefully advance the queue... */ | |
229 | return; | |
230 | } | |
231 | ||
fed2574b AS |
232 | if (dwc->nollp) { |
233 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
234 | &dwc->flags); | |
235 | if (was_soft_llp) { | |
236 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 237 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
238 | return; |
239 | } | |
240 | ||
241 | dwc_initialize(dwc); | |
242 | ||
4702d524 | 243 | dwc->residue = first->total_len; |
f5c6a7df | 244 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 245 | |
fdf475fa | 246 | /* Submit first block */ |
fed2574b AS |
247 | dwc_do_single_block(dwc, first); |
248 | ||
249 | return; | |
250 | } | |
251 | ||
61e183f8 VK |
252 | dwc_initialize(dwc); |
253 | ||
3bfb1d20 HS |
254 | channel_writel(dwc, LLP, first->txd.phys); |
255 | channel_writel(dwc, CTL_LO, | |
256 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
257 | channel_writel(dwc, CTL_HI, 0); | |
258 | channel_set_bit(dw, CH_EN, dwc->mask); | |
259 | } | |
260 | ||
e7637c6c AS |
261 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
262 | { | |
cba15617 AS |
263 | struct dw_desc *desc; |
264 | ||
e7637c6c AS |
265 | if (list_empty(&dwc->queue)) |
266 | return; | |
267 | ||
268 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
269 | desc = dwc_first_active(dwc); |
270 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
271 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
272 | } |
273 | ||
3bfb1d20 HS |
274 | /*----------------------------------------------------------------------*/ |
275 | ||
276 | static void | |
5fedefb8 VK |
277 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
278 | bool callback_required) | |
3bfb1d20 | 279 | { |
5fedefb8 VK |
280 | dma_async_tx_callback callback = NULL; |
281 | void *param = NULL; | |
3bfb1d20 | 282 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 283 | struct dw_desc *child; |
69cea5a0 | 284 | unsigned long flags; |
3bfb1d20 | 285 | |
41d5e59c | 286 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 287 | |
69cea5a0 | 288 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 289 | dma_cookie_complete(txd); |
5fedefb8 VK |
290 | if (callback_required) { |
291 | callback = txd->callback; | |
292 | param = txd->callback_param; | |
293 | } | |
3bfb1d20 | 294 | |
e518076e VK |
295 | /* async_tx_ack */ |
296 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
297 | async_tx_ack(&child->txd); | |
298 | async_tx_ack(&desc->txd); | |
299 | ||
e0bd0f8c | 300 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
301 | list_move(&desc->desc_node, &dwc->free_list); |
302 | ||
d38a8c62 | 303 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
304 | spin_unlock_irqrestore(&dwc->lock, flags); |
305 | ||
21e93c1e | 306 | if (callback) |
3bfb1d20 HS |
307 | callback(param); |
308 | } | |
309 | ||
310 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
311 | { | |
312 | struct dw_desc *desc, *_desc; | |
313 | LIST_HEAD(list); | |
69cea5a0 | 314 | unsigned long flags; |
3bfb1d20 | 315 | |
69cea5a0 | 316 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 317 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 318 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
319 | "BUG: XFER bit set, but channel not idle!\n"); |
320 | ||
321 | /* Try to continue after resetting the channel... */ | |
3f936207 | 322 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
323 | } |
324 | ||
325 | /* | |
326 | * Submit queued descriptors ASAP, i.e. before we go through | |
327 | * the completed ones. | |
328 | */ | |
3bfb1d20 | 329 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 330 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 331 | |
69cea5a0 VK |
332 | spin_unlock_irqrestore(&dwc->lock, flags); |
333 | ||
3bfb1d20 | 334 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 335 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
336 | } |
337 | ||
4702d524 AS |
338 | /* Returns how many bytes were already received from source */ |
339 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
340 | { | |
341 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
342 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
343 | ||
344 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
345 | } | |
346 | ||
3bfb1d20 HS |
347 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
348 | { | |
349 | dma_addr_t llp; | |
350 | struct dw_desc *desc, *_desc; | |
351 | struct dw_desc *child; | |
352 | u32 status_xfer; | |
69cea5a0 | 353 | unsigned long flags; |
3bfb1d20 | 354 | |
69cea5a0 | 355 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
356 | llp = channel_readl(dwc, LLP); |
357 | status_xfer = dma_readl(dw, RAW.XFER); | |
358 | ||
359 | if (status_xfer & dwc->mask) { | |
360 | /* Everything we've submitted is done */ | |
361 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
362 | |
363 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
364 | struct list_head *head, *active = dwc->tx_node_active; |
365 | ||
366 | /* | |
367 | * We are inside first active descriptor. | |
368 | * Otherwise something is really wrong. | |
369 | */ | |
370 | desc = dwc_first_active(dwc); | |
371 | ||
372 | head = &desc->tx_list; | |
373 | if (active != head) { | |
4702d524 AS |
374 | /* Update desc to reflect last sent one */ |
375 | if (active != head->next) | |
376 | desc = to_dw_desc(active->prev); | |
377 | ||
378 | dwc->residue -= desc->len; | |
379 | ||
fdf475fa | 380 | child = to_dw_desc(active); |
77bcc497 AS |
381 | |
382 | /* Submit next block */ | |
fdf475fa | 383 | dwc_do_single_block(dwc, child); |
77bcc497 | 384 | |
fdf475fa | 385 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
386 | return; |
387 | } | |
fdf475fa | 388 | |
77bcc497 AS |
389 | /* We are done here */ |
390 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
391 | } | |
4702d524 AS |
392 | |
393 | dwc->residue = 0; | |
394 | ||
69cea5a0 VK |
395 | spin_unlock_irqrestore(&dwc->lock, flags); |
396 | ||
3bfb1d20 HS |
397 | dwc_complete_all(dw, dwc); |
398 | return; | |
399 | } | |
400 | ||
69cea5a0 | 401 | if (list_empty(&dwc->active_list)) { |
4702d524 | 402 | dwc->residue = 0; |
69cea5a0 | 403 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 404 | return; |
69cea5a0 | 405 | } |
087809fc | 406 | |
77bcc497 AS |
407 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
408 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 409 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 410 | return; |
69cea5a0 | 411 | } |
087809fc | 412 | |
5a87f0e6 | 413 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
414 | |
415 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 416 | /* Initial residue value */ |
4702d524 AS |
417 | dwc->residue = desc->total_len; |
418 | ||
75c61225 | 419 | /* Check first descriptors addr */ |
69cea5a0 VK |
420 | if (desc->txd.phys == llp) { |
421 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 422 | return; |
69cea5a0 | 423 | } |
84adccfb | 424 | |
75c61225 | 425 | /* Check first descriptors llp */ |
69cea5a0 | 426 | if (desc->lli.llp == llp) { |
3bfb1d20 | 427 | /* This one is currently in progress */ |
4702d524 | 428 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 429 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 430 | return; |
69cea5a0 | 431 | } |
3bfb1d20 | 432 | |
4702d524 AS |
433 | dwc->residue -= desc->len; |
434 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 435 | if (child->lli.llp == llp) { |
3bfb1d20 | 436 | /* Currently in progress */ |
4702d524 | 437 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 438 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 439 | return; |
69cea5a0 | 440 | } |
4702d524 AS |
441 | dwc->residue -= child->len; |
442 | } | |
3bfb1d20 HS |
443 | |
444 | /* | |
445 | * No descriptors so far seem to be in progress, i.e. | |
446 | * this one must be done. | |
447 | */ | |
69cea5a0 | 448 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 449 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 450 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
451 | } |
452 | ||
41d5e59c | 453 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
454 | "BUG: All descriptors done, but channel not idle!\n"); |
455 | ||
456 | /* Try to continue after resetting the channel... */ | |
3f936207 | 457 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 458 | |
e7637c6c | 459 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 460 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
461 | } |
462 | ||
93aad1bc | 463 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 464 | { |
21d43f49 AS |
465 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
466 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
467 | } |
468 | ||
469 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
470 | { | |
471 | struct dw_desc *bad_desc; | |
472 | struct dw_desc *child; | |
69cea5a0 | 473 | unsigned long flags; |
3bfb1d20 HS |
474 | |
475 | dwc_scan_descriptors(dw, dwc); | |
476 | ||
69cea5a0 VK |
477 | spin_lock_irqsave(&dwc->lock, flags); |
478 | ||
3bfb1d20 HS |
479 | /* |
480 | * The descriptor currently at the head of the active list is | |
481 | * borked. Since we don't have any way to report errors, we'll | |
482 | * just have to scream loudly and try to carry on. | |
483 | */ | |
484 | bad_desc = dwc_first_active(dwc); | |
485 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 486 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
487 | |
488 | /* Clear the error flag and try to restart the controller */ | |
489 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
490 | if (!list_empty(&dwc->active_list)) | |
491 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
492 | ||
493 | /* | |
ba84bd71 | 494 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
495 | * when someone submits a bad physical address in a |
496 | * descriptor, we should consider ourselves lucky that the | |
497 | * controller flagged an error instead of scribbling over | |
498 | * random memory locations. | |
499 | */ | |
ba84bd71 AS |
500 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
501 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 502 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 503 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
504 | dwc_dump_lli(dwc, &child->lli); |
505 | ||
69cea5a0 VK |
506 | spin_unlock_irqrestore(&dwc->lock, flags); |
507 | ||
3bfb1d20 | 508 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 509 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
510 | } |
511 | ||
d9de4519 HCE |
512 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
513 | ||
8004cbb4 | 514 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
515 | { |
516 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
517 | return channel_readl(dwc, SAR); | |
518 | } | |
519 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
520 | ||
8004cbb4 | 521 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
522 | { |
523 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
524 | return channel_readl(dwc, DAR); | |
525 | } | |
526 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
527 | ||
75c61225 | 528 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 529 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 530 | u32 status_err, u32 status_xfer) |
d9de4519 | 531 | { |
69cea5a0 VK |
532 | unsigned long flags; |
533 | ||
ff7b05f2 | 534 | if (dwc->mask) { |
d9de4519 HCE |
535 | void (*callback)(void *param); |
536 | void *callback_param; | |
537 | ||
538 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
539 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
540 | |
541 | callback = dwc->cdesc->period_callback; | |
542 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
543 | |
544 | if (callback) | |
d9de4519 | 545 | callback(callback_param); |
d9de4519 HCE |
546 | } |
547 | ||
548 | /* | |
549 | * Error and transfer complete are highly unlikely, and will most | |
550 | * likely be due to a configuration error by the user. | |
551 | */ | |
552 | if (unlikely(status_err & dwc->mask) || | |
553 | unlikely(status_xfer & dwc->mask)) { | |
554 | int i; | |
555 | ||
fc61f6b4 AS |
556 | dev_err(chan2dev(&dwc->chan), |
557 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
558 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
559 | |
560 | spin_lock_irqsave(&dwc->lock, flags); | |
561 | ||
1d455437 | 562 | dwc_dump_chan_regs(dwc); |
d9de4519 | 563 | |
3f936207 | 564 | dwc_chan_disable(dw, dwc); |
d9de4519 | 565 | |
75c61225 | 566 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
567 | channel_writel(dwc, LLP, 0); |
568 | channel_writel(dwc, CTL_LO, 0); | |
569 | channel_writel(dwc, CTL_HI, 0); | |
570 | ||
d9de4519 HCE |
571 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
572 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
573 | ||
574 | for (i = 0; i < dwc->cdesc->periods; i++) | |
575 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
576 | |
577 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
578 | } |
579 | } | |
580 | ||
581 | /* ------------------------------------------------------------------------- */ | |
582 | ||
3bfb1d20 HS |
583 | static void dw_dma_tasklet(unsigned long data) |
584 | { | |
585 | struct dw_dma *dw = (struct dw_dma *)data; | |
586 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
587 | u32 status_xfer; |
588 | u32 status_err; | |
589 | int i; | |
590 | ||
7fe7b2f4 | 591 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
592 | status_err = dma_readl(dw, RAW.ERROR); |
593 | ||
2e4c364e | 594 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
595 | |
596 | for (i = 0; i < dw->dma.chancnt; i++) { | |
597 | dwc = &dw->chan[i]; | |
d9de4519 | 598 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 599 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 600 | else if (status_err & (1 << i)) |
3bfb1d20 | 601 | dwc_handle_error(dw, dwc); |
77bcc497 | 602 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 603 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
604 | } |
605 | ||
606 | /* | |
ff7b05f2 | 607 | * Re-enable interrupts. |
3bfb1d20 HS |
608 | */ |
609 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
610 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
611 | } | |
612 | ||
613 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
614 | { | |
615 | struct dw_dma *dw = dev_id; | |
3783cef8 | 616 | u32 status = dma_readl(dw, STATUS_INT); |
3bfb1d20 | 617 | |
3783cef8 AS |
618 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
619 | ||
620 | /* Check if we have any interrupt from the DMAC */ | |
621 | if (!status) | |
622 | return IRQ_NONE; | |
3bfb1d20 HS |
623 | |
624 | /* | |
625 | * Just disable the interrupts. We'll turn them back on in the | |
626 | * softirq handler. | |
627 | */ | |
628 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
629 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
630 | ||
631 | status = dma_readl(dw, STATUS_INT); | |
632 | if (status) { | |
633 | dev_err(dw->dma.dev, | |
634 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
635 | status); | |
636 | ||
637 | /* Try to recover */ | |
638 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
639 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
640 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
641 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
642 | } | |
643 | ||
644 | tasklet_schedule(&dw->tasklet); | |
645 | ||
646 | return IRQ_HANDLED; | |
647 | } | |
648 | ||
649 | /*----------------------------------------------------------------------*/ | |
650 | ||
651 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
652 | { | |
653 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
654 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
655 | dma_cookie_t cookie; | |
69cea5a0 | 656 | unsigned long flags; |
3bfb1d20 | 657 | |
69cea5a0 | 658 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 659 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
660 | |
661 | /* | |
662 | * REVISIT: We should attempt to chain as many descriptors as | |
663 | * possible, perhaps even appending to those already submitted | |
664 | * for DMA. But this is hard to do in a race-free manner. | |
665 | */ | |
3bfb1d20 | 666 | |
dd8ecfca AS |
667 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
668 | list_add_tail(&desc->desc_node, &dwc->queue); | |
3bfb1d20 | 669 | |
69cea5a0 | 670 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
671 | |
672 | return cookie; | |
673 | } | |
674 | ||
675 | static struct dma_async_tx_descriptor * | |
676 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
677 | size_t len, unsigned long flags) | |
678 | { | |
679 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 680 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
681 | struct dw_desc *desc; |
682 | struct dw_desc *first; | |
683 | struct dw_desc *prev; | |
684 | size_t xfer_count; | |
685 | size_t offset; | |
686 | unsigned int src_width; | |
687 | unsigned int dst_width; | |
3d4f8605 | 688 | unsigned int data_width; |
3bfb1d20 HS |
689 | u32 ctllo; |
690 | ||
2f45d613 | 691 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
692 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
693 | &dest, &src, len, flags); | |
3bfb1d20 HS |
694 | |
695 | if (unlikely(!len)) { | |
2e4c364e | 696 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
697 | return NULL; |
698 | } | |
699 | ||
0fdb567f AS |
700 | dwc->direction = DMA_MEM_TO_MEM; |
701 | ||
f776076b AB |
702 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
703 | dw->data_width[dwc->dst_master]); | |
a0982004 | 704 | |
3d4f8605 AS |
705 | src_width = dst_width = min_t(unsigned int, data_width, |
706 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 707 | |
327e6970 | 708 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
709 | | DWC_CTLL_DST_WIDTH(dst_width) |
710 | | DWC_CTLL_SRC_WIDTH(src_width) | |
711 | | DWC_CTLL_DST_INC | |
712 | | DWC_CTLL_SRC_INC | |
713 | | DWC_CTLL_FC_M2M; | |
714 | prev = first = NULL; | |
715 | ||
716 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
717 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 718 | dwc->block_size); |
3bfb1d20 HS |
719 | |
720 | desc = dwc_desc_get(dwc); | |
721 | if (!desc) | |
722 | goto err_desc_get; | |
723 | ||
724 | desc->lli.sar = src + offset; | |
725 | desc->lli.dar = dest + offset; | |
726 | desc->lli.ctllo = ctllo; | |
727 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 728 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
729 | |
730 | if (!first) { | |
731 | first = desc; | |
732 | } else { | |
733 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 734 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 735 | &first->tx_list); |
3bfb1d20 HS |
736 | } |
737 | prev = desc; | |
738 | } | |
739 | ||
3bfb1d20 HS |
740 | if (flags & DMA_PREP_INTERRUPT) |
741 | /* Trigger interrupt after last block */ | |
742 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
743 | ||
744 | prev->lli.llp = 0; | |
3bfb1d20 | 745 | first->txd.flags = flags; |
30d38a32 | 746 | first->total_len = len; |
3bfb1d20 HS |
747 | |
748 | return &first->txd; | |
749 | ||
750 | err_desc_get: | |
751 | dwc_desc_put(dwc, first); | |
752 | return NULL; | |
753 | } | |
754 | ||
755 | static struct dma_async_tx_descriptor * | |
756 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 757 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 758 | unsigned long flags, void *context) |
3bfb1d20 HS |
759 | { |
760 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 761 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 762 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
763 | struct dw_desc *prev; |
764 | struct dw_desc *first; | |
765 | u32 ctllo; | |
766 | dma_addr_t reg; | |
767 | unsigned int reg_width; | |
768 | unsigned int mem_width; | |
a0982004 | 769 | unsigned int data_width; |
3bfb1d20 HS |
770 | unsigned int i; |
771 | struct scatterlist *sg; | |
772 | size_t total_len = 0; | |
773 | ||
2e4c364e | 774 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 775 | |
495aea4b | 776 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
777 | return NULL; |
778 | ||
0fdb567f AS |
779 | dwc->direction = direction; |
780 | ||
3bfb1d20 HS |
781 | prev = first = NULL; |
782 | ||
3bfb1d20 | 783 | switch (direction) { |
db8196df | 784 | case DMA_MEM_TO_DEV: |
327e6970 VK |
785 | reg_width = __fls(sconfig->dst_addr_width); |
786 | reg = sconfig->dst_addr; | |
787 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
788 | | DWC_CTLL_DST_WIDTH(reg_width) |
789 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
790 | | DWC_CTLL_SRC_INC); |
791 | ||
792 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
793 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
794 | ||
f776076b | 795 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 796 | |
3bfb1d20 HS |
797 | for_each_sg(sgl, sg, sg_len, i) { |
798 | struct dw_desc *desc; | |
69dc14b5 | 799 | u32 len, dlen, mem; |
3bfb1d20 | 800 | |
cbb796cc | 801 | mem = sg_dma_address(sg); |
69dc14b5 | 802 | len = sg_dma_len(sg); |
6bc711f6 | 803 | |
a0982004 AS |
804 | mem_width = min_t(unsigned int, |
805 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 806 | |
69dc14b5 | 807 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
808 | desc = dwc_desc_get(dwc); |
809 | if (!desc) { | |
41d5e59c | 810 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
811 | "not enough descriptors available\n"); |
812 | goto err_desc_get; | |
813 | } | |
814 | ||
3bfb1d20 HS |
815 | desc->lli.sar = mem; |
816 | desc->lli.dar = reg; | |
817 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
818 | if ((len >> mem_width) > dwc->block_size) { |
819 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
820 | mem += dlen; |
821 | len -= dlen; | |
822 | } else { | |
823 | dlen = len; | |
824 | len = 0; | |
825 | } | |
826 | ||
827 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 828 | desc->len = dlen; |
3bfb1d20 HS |
829 | |
830 | if (!first) { | |
831 | first = desc; | |
832 | } else { | |
833 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 834 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 835 | &first->tx_list); |
3bfb1d20 HS |
836 | } |
837 | prev = desc; | |
69dc14b5 VK |
838 | total_len += dlen; |
839 | ||
840 | if (len) | |
841 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
842 | } |
843 | break; | |
db8196df | 844 | case DMA_DEV_TO_MEM: |
327e6970 VK |
845 | reg_width = __fls(sconfig->src_addr_width); |
846 | reg = sconfig->src_addr; | |
847 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
848 | | DWC_CTLL_SRC_WIDTH(reg_width) |
849 | | DWC_CTLL_DST_INC | |
327e6970 VK |
850 | | DWC_CTLL_SRC_FIX); |
851 | ||
852 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
853 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 854 | |
f776076b | 855 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 856 | |
3bfb1d20 HS |
857 | for_each_sg(sgl, sg, sg_len, i) { |
858 | struct dw_desc *desc; | |
69dc14b5 | 859 | u32 len, dlen, mem; |
3bfb1d20 | 860 | |
cbb796cc | 861 | mem = sg_dma_address(sg); |
3bfb1d20 | 862 | len = sg_dma_len(sg); |
6bc711f6 | 863 | |
a0982004 AS |
864 | mem_width = min_t(unsigned int, |
865 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 866 | |
69dc14b5 VK |
867 | slave_sg_fromdev_fill_desc: |
868 | desc = dwc_desc_get(dwc); | |
869 | if (!desc) { | |
870 | dev_err(chan2dev(chan), | |
871 | "not enough descriptors available\n"); | |
872 | goto err_desc_get; | |
873 | } | |
874 | ||
3bfb1d20 HS |
875 | desc->lli.sar = reg; |
876 | desc->lli.dar = mem; | |
877 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
878 | if ((len >> reg_width) > dwc->block_size) { |
879 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
880 | mem += dlen; |
881 | len -= dlen; | |
882 | } else { | |
883 | dlen = len; | |
884 | len = 0; | |
885 | } | |
886 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 887 | desc->len = dlen; |
3bfb1d20 HS |
888 | |
889 | if (!first) { | |
890 | first = desc; | |
891 | } else { | |
892 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 893 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 894 | &first->tx_list); |
3bfb1d20 HS |
895 | } |
896 | prev = desc; | |
69dc14b5 VK |
897 | total_len += dlen; |
898 | ||
899 | if (len) | |
900 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
901 | } |
902 | break; | |
903 | default: | |
904 | return NULL; | |
905 | } | |
906 | ||
907 | if (flags & DMA_PREP_INTERRUPT) | |
908 | /* Trigger interrupt after last block */ | |
909 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
910 | ||
911 | prev->lli.llp = 0; | |
30d38a32 | 912 | first->total_len = total_len; |
3bfb1d20 HS |
913 | |
914 | return &first->txd; | |
915 | ||
916 | err_desc_get: | |
917 | dwc_desc_put(dwc, first); | |
918 | return NULL; | |
919 | } | |
920 | ||
4d130de2 AS |
921 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
922 | { | |
923 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
924 | struct dw_dma_slave *dws = param; | |
925 | ||
926 | if (!dws || dws->dma_dev != chan->device->dev) | |
927 | return false; | |
928 | ||
929 | /* We have to copy data since dws can be temporary storage */ | |
930 | ||
931 | dwc->src_id = dws->src_id; | |
932 | dwc->dst_id = dws->dst_id; | |
933 | ||
934 | dwc->src_master = dws->src_master; | |
935 | dwc->dst_master = dws->dst_master; | |
936 | ||
937 | return true; | |
938 | } | |
939 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
940 | ||
327e6970 VK |
941 | /* |
942 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
943 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
944 | * | |
945 | * NOTE: burst size 2 is not supported by controller. | |
946 | * | |
947 | * This can be done by finding least significant bit set: n & (n - 1) | |
948 | */ | |
949 | static inline void convert_burst(u32 *maxburst) | |
950 | { | |
951 | if (*maxburst > 1) | |
952 | *maxburst = fls(*maxburst) - 2; | |
953 | else | |
954 | *maxburst = 0; | |
955 | } | |
956 | ||
957 | static int | |
958 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
959 | { | |
960 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
961 | ||
495aea4b AS |
962 | /* Check if chan will be configured for slave transfers */ |
963 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
964 | return -EINVAL; |
965 | ||
966 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 967 | dwc->direction = sconfig->direction; |
327e6970 VK |
968 | |
969 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
970 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
21fe3c52 AS |
975 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
976 | { | |
977 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 978 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
979 | |
980 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
981 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
982 | udelay(2); | |
21fe3c52 AS |
983 | |
984 | dwc->paused = true; | |
985 | } | |
986 | ||
987 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
988 | { | |
989 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
990 | ||
991 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
992 | ||
993 | dwc->paused = false; | |
994 | } | |
995 | ||
05827630 LW |
996 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
997 | unsigned long arg) | |
3bfb1d20 HS |
998 | { |
999 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1000 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1001 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1002 | unsigned long flags; |
3bfb1d20 HS |
1003 | LIST_HEAD(list); |
1004 | ||
a7c57cf7 LW |
1005 | if (cmd == DMA_PAUSE) { |
1006 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1007 | |
21fe3c52 | 1008 | dwc_chan_pause(dwc); |
3bfb1d20 | 1009 | |
a7c57cf7 LW |
1010 | spin_unlock_irqrestore(&dwc->lock, flags); |
1011 | } else if (cmd == DMA_RESUME) { | |
1012 | if (!dwc->paused) | |
1013 | return 0; | |
3bfb1d20 | 1014 | |
a7c57cf7 | 1015 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1016 | |
21fe3c52 | 1017 | dwc_chan_resume(dwc); |
3bfb1d20 | 1018 | |
a7c57cf7 LW |
1019 | spin_unlock_irqrestore(&dwc->lock, flags); |
1020 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1021 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1022 | |
fed2574b AS |
1023 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1024 | ||
3f936207 | 1025 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1026 | |
a5dbff11 | 1027 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1028 | |
1029 | /* active_list entries will end up before queued entries */ | |
1030 | list_splice_init(&dwc->queue, &list); | |
1031 | list_splice_init(&dwc->active_list, &list); | |
1032 | ||
1033 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1034 | ||
1035 | /* Flush all pending and queued descriptors */ | |
1036 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1037 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1038 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1039 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1040 | } else { | |
a7c57cf7 | 1041 | return -ENXIO; |
327e6970 | 1042 | } |
c3635c78 LW |
1043 | |
1044 | return 0; | |
3bfb1d20 HS |
1045 | } |
1046 | ||
4702d524 AS |
1047 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1048 | { | |
1049 | unsigned long flags; | |
1050 | u32 residue; | |
1051 | ||
1052 | spin_lock_irqsave(&dwc->lock, flags); | |
1053 | ||
1054 | residue = dwc->residue; | |
1055 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1056 | residue -= dwc_get_sent(dwc); | |
1057 | ||
1058 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1059 | return residue; | |
1060 | } | |
1061 | ||
3bfb1d20 | 1062 | static enum dma_status |
07934481 LW |
1063 | dwc_tx_status(struct dma_chan *chan, |
1064 | dma_cookie_t cookie, | |
1065 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1066 | { |
1067 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1068 | enum dma_status ret; |
3bfb1d20 | 1069 | |
96a2af41 | 1070 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1071 | if (ret == DMA_COMPLETE) |
12381dc0 | 1072 | return ret; |
3bfb1d20 | 1073 | |
12381dc0 | 1074 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1075 | |
12381dc0 | 1076 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1077 | if (ret != DMA_COMPLETE) |
4702d524 | 1078 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1079 | |
effd5cf6 | 1080 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1081 | return DMA_PAUSED; |
3bfb1d20 HS |
1082 | |
1083 | return ret; | |
1084 | } | |
1085 | ||
1086 | static void dwc_issue_pending(struct dma_chan *chan) | |
1087 | { | |
1088 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1089 | unsigned long flags; |
3bfb1d20 | 1090 | |
dd8ecfca AS |
1091 | spin_lock_irqsave(&dwc->lock, flags); |
1092 | if (list_empty(&dwc->active_list)) | |
1093 | dwc_dostart_first_queued(dwc); | |
1094 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1095 | } |
1096 | ||
aa1e6f1a | 1097 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1098 | { |
1099 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1100 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1101 | struct dw_desc *desc; | |
3bfb1d20 | 1102 | int i; |
69cea5a0 | 1103 | unsigned long flags; |
3bfb1d20 | 1104 | |
2e4c364e | 1105 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1106 | |
3bfb1d20 HS |
1107 | /* ASSERT: channel is idle */ |
1108 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1109 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1110 | return -EIO; |
1111 | } | |
1112 | ||
d3ee98cd | 1113 | dma_cookie_init(chan); |
3bfb1d20 | 1114 | |
3bfb1d20 HS |
1115 | /* |
1116 | * NOTE: some controllers may have additional features that we | |
1117 | * need to initialize here, like "scatter-gather" (which | |
1118 | * doesn't mean what you think it means), and status writeback. | |
1119 | */ | |
1120 | ||
69cea5a0 | 1121 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1122 | i = dwc->descs_allocated; |
1123 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1124 | dma_addr_t phys; |
1125 | ||
69cea5a0 | 1126 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1127 | |
f8122a82 | 1128 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1129 | if (!desc) |
1130 | goto err_desc_alloc; | |
3bfb1d20 | 1131 | |
f8122a82 | 1132 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1133 | |
e0bd0f8c | 1134 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1135 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1136 | desc->txd.tx_submit = dwc_tx_submit; | |
1137 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1138 | desc->txd.phys = phys; |
cbd65312 | 1139 | |
3bfb1d20 HS |
1140 | dwc_desc_put(dwc, desc); |
1141 | ||
69cea5a0 | 1142 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1143 | i = ++dwc->descs_allocated; |
1144 | } | |
1145 | ||
69cea5a0 | 1146 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1147 | |
2e4c364e | 1148 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1149 | |
cbd65312 AS |
1150 | return i; |
1151 | ||
1152 | err_desc_alloc: | |
cbd65312 AS |
1153 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1154 | ||
3bfb1d20 HS |
1155 | return i; |
1156 | } | |
1157 | ||
1158 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1159 | { | |
1160 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1161 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1162 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1163 | unsigned long flags; |
3bfb1d20 HS |
1164 | LIST_HEAD(list); |
1165 | ||
2e4c364e | 1166 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1167 | dwc->descs_allocated); |
1168 | ||
1169 | /* ASSERT: channel is idle */ | |
1170 | BUG_ON(!list_empty(&dwc->active_list)); | |
1171 | BUG_ON(!list_empty(&dwc->queue)); | |
1172 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1173 | ||
69cea5a0 | 1174 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1175 | list_splice_init(&dwc->free_list, &list); |
1176 | dwc->descs_allocated = 0; | |
61e183f8 | 1177 | dwc->initialized = false; |
3bfb1d20 HS |
1178 | |
1179 | /* Disable interrupts */ | |
1180 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1181 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1182 | ||
69cea5a0 | 1183 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1184 | |
1185 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1186 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1187 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1188 | } |
1189 | ||
2e4c364e | 1190 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1191 | } |
1192 | ||
d9de4519 HCE |
1193 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1194 | ||
1195 | /** | |
1196 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1197 | * @chan: the DMA channel to start | |
1198 | * | |
1199 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1200 | * -errno on failure. | |
1201 | */ | |
1202 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1203 | { | |
1204 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1205 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1206 | unsigned long flags; |
d9de4519 HCE |
1207 | |
1208 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1209 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1210 | return -ENODEV; | |
1211 | } | |
1212 | ||
69cea5a0 | 1213 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1214 | |
75c61225 | 1215 | /* Assert channel is idle */ |
d9de4519 HCE |
1216 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1217 | dev_err(chan2dev(&dwc->chan), | |
1218 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1219 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1220 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1221 | return -EBUSY; |
1222 | } | |
1223 | ||
d9de4519 HCE |
1224 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1225 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1226 | ||
75c61225 | 1227 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1228 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1229 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1230 | channel_writel(dwc, CTL_HI, 0); | |
1231 | ||
1232 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1233 | ||
69cea5a0 | 1234 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1239 | ||
1240 | /** | |
1241 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1242 | * @chan: the DMA channel to stop | |
1243 | * | |
1244 | * Must be called with soft interrupts disabled. | |
1245 | */ | |
1246 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1247 | { | |
1248 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1249 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1250 | unsigned long flags; |
d9de4519 | 1251 | |
69cea5a0 | 1252 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1253 | |
3f936207 | 1254 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1255 | |
69cea5a0 | 1256 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1257 | } |
1258 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1259 | ||
1260 | /** | |
1261 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1262 | * @chan: the DMA channel to prepare | |
1263 | * @buf_addr: physical DMA address where the buffer starts | |
1264 | * @buf_len: total number of bytes for the entire buffer | |
1265 | * @period_len: number of bytes for each period | |
1266 | * @direction: transfer direction, to or from device | |
1267 | * | |
1268 | * Must be called before trying to start the transfer. Returns a valid struct | |
1269 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1270 | */ | |
1271 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1272 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1273 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1274 | { |
1275 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1276 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1277 | struct dw_cyclic_desc *cdesc; |
1278 | struct dw_cyclic_desc *retval = NULL; | |
1279 | struct dw_desc *desc; | |
1280 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1281 | unsigned long was_cyclic; |
1282 | unsigned int reg_width; | |
1283 | unsigned int periods; | |
1284 | unsigned int i; | |
69cea5a0 | 1285 | unsigned long flags; |
d9de4519 | 1286 | |
69cea5a0 | 1287 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1288 | if (dwc->nollp) { |
1289 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1290 | dev_dbg(chan2dev(&dwc->chan), | |
1291 | "channel doesn't support LLP transfers\n"); | |
1292 | return ERR_PTR(-EINVAL); | |
1293 | } | |
1294 | ||
d9de4519 | 1295 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1296 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1297 | dev_dbg(chan2dev(&dwc->chan), |
1298 | "queue and/or active list are not empty\n"); | |
1299 | return ERR_PTR(-EBUSY); | |
1300 | } | |
1301 | ||
1302 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1303 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1304 | if (was_cyclic) { |
1305 | dev_dbg(chan2dev(&dwc->chan), | |
1306 | "channel already prepared for cyclic DMA\n"); | |
1307 | return ERR_PTR(-EBUSY); | |
1308 | } | |
1309 | ||
1310 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1311 | |
f44b92f4 AS |
1312 | if (unlikely(!is_slave_direction(direction))) |
1313 | goto out_err; | |
1314 | ||
0fdb567f AS |
1315 | dwc->direction = direction; |
1316 | ||
327e6970 VK |
1317 | if (direction == DMA_MEM_TO_DEV) |
1318 | reg_width = __ffs(sconfig->dst_addr_width); | |
1319 | else | |
1320 | reg_width = __ffs(sconfig->src_addr_width); | |
1321 | ||
d9de4519 HCE |
1322 | periods = buf_len / period_len; |
1323 | ||
1324 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1325 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1326 | goto out_err; |
1327 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1328 | goto out_err; | |
1329 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1330 | goto out_err; | |
d9de4519 HCE |
1331 | |
1332 | retval = ERR_PTR(-ENOMEM); | |
1333 | ||
1334 | if (periods > NR_DESCS_PER_CHANNEL) | |
1335 | goto out_err; | |
1336 | ||
1337 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1338 | if (!cdesc) | |
1339 | goto out_err; | |
1340 | ||
1341 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1342 | if (!cdesc->desc) | |
1343 | goto out_err_alloc; | |
1344 | ||
1345 | for (i = 0; i < periods; i++) { | |
1346 | desc = dwc_desc_get(dwc); | |
1347 | if (!desc) | |
1348 | goto out_err_desc_get; | |
1349 | ||
1350 | switch (direction) { | |
db8196df | 1351 | case DMA_MEM_TO_DEV: |
327e6970 | 1352 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1353 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1354 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1355 | | DWC_CTLL_DST_WIDTH(reg_width) |
1356 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1357 | | DWC_CTLL_DST_FIX | |
1358 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1359 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1360 | |
1361 | desc->lli.ctllo |= sconfig->device_fc ? | |
1362 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1363 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1364 | ||
d9de4519 | 1365 | break; |
db8196df | 1366 | case DMA_DEV_TO_MEM: |
d9de4519 | 1367 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1368 | desc->lli.sar = sconfig->src_addr; |
1369 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1370 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1371 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1372 | | DWC_CTLL_DST_INC | |
1373 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1374 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1375 | |
1376 | desc->lli.ctllo |= sconfig->device_fc ? | |
1377 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1378 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1379 | ||
d9de4519 HCE |
1380 | break; |
1381 | default: | |
1382 | break; | |
1383 | } | |
1384 | ||
1385 | desc->lli.ctlhi = (period_len >> reg_width); | |
1386 | cdesc->desc[i] = desc; | |
1387 | ||
f8122a82 | 1388 | if (last) |
d9de4519 | 1389 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1390 | |
1391 | last = desc; | |
1392 | } | |
1393 | ||
75c61225 | 1394 | /* Let's make a cyclic list */ |
d9de4519 | 1395 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1396 | |
5a87f0e6 AS |
1397 | dev_dbg(chan2dev(&dwc->chan), |
1398 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1399 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1400 | |
1401 | cdesc->periods = periods; | |
1402 | dwc->cdesc = cdesc; | |
1403 | ||
1404 | return cdesc; | |
1405 | ||
1406 | out_err_desc_get: | |
1407 | while (i--) | |
1408 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1409 | out_err_alloc: | |
1410 | kfree(cdesc); | |
1411 | out_err: | |
1412 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1413 | return (struct dw_cyclic_desc *)retval; | |
1414 | } | |
1415 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1416 | ||
1417 | /** | |
1418 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1419 | * @chan: the DMA channel to free | |
1420 | */ | |
1421 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1422 | { | |
1423 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1424 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1425 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1426 | int i; | |
69cea5a0 | 1427 | unsigned long flags; |
d9de4519 | 1428 | |
2e4c364e | 1429 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1430 | |
1431 | if (!cdesc) | |
1432 | return; | |
1433 | ||
69cea5a0 | 1434 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1435 | |
3f936207 | 1436 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1437 | |
d9de4519 HCE |
1438 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1439 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1440 | ||
69cea5a0 | 1441 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1442 | |
1443 | for (i = 0; i < cdesc->periods; i++) | |
1444 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1445 | ||
1446 | kfree(cdesc->desc); | |
1447 | kfree(cdesc); | |
1448 | ||
1449 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1450 | } | |
1451 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1452 | ||
3bfb1d20 HS |
1453 | /*----------------------------------------------------------------------*/ |
1454 | ||
1455 | static void dw_dma_off(struct dw_dma *dw) | |
1456 | { | |
61e183f8 VK |
1457 | int i; |
1458 | ||
3bfb1d20 HS |
1459 | dma_writel(dw, CFG, 0); |
1460 | ||
1461 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1462 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1463 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1464 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1465 | ||
1466 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1467 | cpu_relax(); | |
61e183f8 VK |
1468 | |
1469 | for (i = 0; i < dw->dma.chancnt; i++) | |
1470 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1471 | } |
1472 | ||
7a83c045 AS |
1473 | static void dw_dma_on(struct dw_dma *dw) |
1474 | { | |
1475 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1476 | } | |
1477 | ||
9cade1a4 | 1478 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1479 | { |
3bfb1d20 | 1480 | struct dw_dma *dw; |
482c67ea AS |
1481 | bool autocfg; |
1482 | unsigned int dw_params; | |
1483 | unsigned int nr_channels; | |
4a63a8b3 | 1484 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1485 | int err; |
1486 | int i; | |
1487 | ||
000871ce AS |
1488 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1489 | if (!dw) | |
1490 | return -ENOMEM; | |
1491 | ||
1492 | dw->regs = chip->regs; | |
1493 | chip->dw = dw; | |
1494 | ||
9cade1a4 | 1495 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1496 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1497 | ||
9cade1a4 | 1498 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1499 | |
1500 | if (!pdata && autocfg) { | |
9cade1a4 | 1501 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1502 | if (!pdata) { |
1503 | err = -ENOMEM; | |
1504 | goto err_pdata; | |
1505 | } | |
123de543 AS |
1506 | |
1507 | /* Fill platform data with the default values */ | |
1508 | pdata->is_private = true; | |
1509 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1510 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
8be4f523 AS |
1511 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
1512 | err = -EINVAL; | |
1513 | goto err_pdata; | |
1514 | } | |
123de543 | 1515 | |
482c67ea AS |
1516 | if (autocfg) |
1517 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1518 | else | |
1519 | nr_channels = pdata->nr_channels; | |
1520 | ||
000871ce AS |
1521 | dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), |
1522 | GFP_KERNEL); | |
8be4f523 AS |
1523 | if (!dw->chan) { |
1524 | err = -ENOMEM; | |
1525 | goto err_pdata; | |
1526 | } | |
3bfb1d20 | 1527 | |
75c61225 | 1528 | /* Get hardware configuration parameters */ |
a0982004 | 1529 | if (autocfg) { |
4a63a8b3 AS |
1530 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1531 | ||
a0982004 AS |
1532 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1533 | for (i = 0; i < dw->nr_masters; i++) { | |
1534 | dw->data_width[i] = | |
1535 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1536 | } | |
1537 | } else { | |
1538 | dw->nr_masters = pdata->nr_masters; | |
1539 | memcpy(dw->data_width, pdata->data_width, 4); | |
1540 | } | |
1541 | ||
11f932ec | 1542 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1543 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1544 | |
75c61225 | 1545 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1546 | dw_dma_off(dw); |
1547 | ||
75c61225 | 1548 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1549 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1550 | ||
75c61225 | 1551 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1552 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1553 | sizeof(struct dw_desc), 4, 0); |
1554 | if (!dw->desc_pool) { | |
9cade1a4 | 1555 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1556 | err = -ENOMEM; |
1557 | goto err_pdata; | |
f8122a82 AS |
1558 | } |
1559 | ||
3bfb1d20 HS |
1560 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1561 | ||
97977f75 AS |
1562 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1563 | "dw_dmac", dw); | |
1564 | if (err) | |
8be4f523 | 1565 | goto err_pdata; |
97977f75 | 1566 | |
3bfb1d20 | 1567 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1568 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1569 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1570 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1571 | |
1572 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1573 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1574 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1575 | list_add_tail(&dwc->chan.device_node, | |
1576 | &dw->dma.channels); | |
1577 | else | |
1578 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1579 | |
93317e8e VK |
1580 | /* 7 is highest priority & 0 is lowest. */ |
1581 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1582 | dwc->priority = r; |
93317e8e VK |
1583 | else |
1584 | dwc->priority = i; | |
1585 | ||
3bfb1d20 HS |
1586 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1587 | spin_lock_init(&dwc->lock); | |
1588 | dwc->mask = 1 << i; | |
1589 | ||
1590 | INIT_LIST_HEAD(&dwc->active_list); | |
1591 | INIT_LIST_HEAD(&dwc->queue); | |
1592 | INIT_LIST_HEAD(&dwc->free_list); | |
1593 | ||
1594 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1595 | |
0fdb567f | 1596 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1597 | |
75c61225 | 1598 | /* Hardware configuration */ |
fed2574b AS |
1599 | if (autocfg) { |
1600 | unsigned int dwc_params; | |
9cade1a4 | 1601 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1602 | |
9cade1a4 | 1603 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1604 | |
9cade1a4 AS |
1605 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1606 | dwc_params); | |
985a6c7d | 1607 | |
1d566f11 AS |
1608 | /* |
1609 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1610 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1611 | * up to 0x0a for 4095. |
1612 | */ | |
4a63a8b3 AS |
1613 | dwc->block_size = |
1614 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1615 | dwc->nollp = |
1616 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1617 | } else { | |
4a63a8b3 | 1618 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1619 | |
1620 | /* Check if channel supports multi block transfer */ | |
1621 | channel_writel(dwc, LLP, 0xfffffffc); | |
1622 | dwc->nollp = | |
1623 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1624 | channel_writel(dwc, LLP, 0); | |
1625 | } | |
3bfb1d20 HS |
1626 | } |
1627 | ||
11f932ec | 1628 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1629 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1630 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1631 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1632 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1633 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1634 | ||
3bfb1d20 HS |
1635 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1636 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1637 | if (pdata->is_private) |
1638 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1639 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1640 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1641 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1642 | ||
1643 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1644 | ||
1645 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1646 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1647 | |
07934481 | 1648 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1649 | dw->dma.device_issue_pending = dwc_issue_pending; |
1650 | ||
7a83c045 | 1651 | dw_dma_on(dw); |
3bfb1d20 | 1652 | |
1222934e AS |
1653 | err = dma_async_device_register(&dw->dma); |
1654 | if (err) | |
1655 | goto err_dma_register; | |
1656 | ||
9cade1a4 | 1657 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1658 | nr_channels); |
3bfb1d20 | 1659 | |
3bfb1d20 | 1660 | return 0; |
8be4f523 | 1661 | |
1222934e AS |
1662 | err_dma_register: |
1663 | free_irq(chip->irq, dw); | |
8be4f523 | 1664 | err_pdata: |
8be4f523 | 1665 | return err; |
3bfb1d20 | 1666 | } |
9cade1a4 | 1667 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1668 | |
9cade1a4 | 1669 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1670 | { |
9cade1a4 | 1671 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1672 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1673 | |
1674 | dw_dma_off(dw); | |
1675 | dma_async_device_unregister(&dw->dma); | |
1676 | ||
97977f75 | 1677 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1678 | tasklet_kill(&dw->tasklet); |
1679 | ||
1680 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1681 | chan.device_node) { | |
1682 | list_del(&dwc->chan.device_node); | |
1683 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1684 | } | |
1685 | ||
3bfb1d20 HS |
1686 | return 0; |
1687 | } | |
9cade1a4 | 1688 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1689 | |
9cade1a4 | 1690 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1691 | { |
9cade1a4 | 1692 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1693 | |
6168d567 | 1694 | dw_dma_off(dw); |
3bfb1d20 | 1695 | } |
9cade1a4 | 1696 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1697 | |
9cade1a4 AS |
1698 | #ifdef CONFIG_PM_SLEEP |
1699 | ||
1700 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1701 | { |
9cade1a4 | 1702 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1703 | |
6168d567 | 1704 | dw_dma_off(dw); |
3bfb1d20 HS |
1705 | return 0; |
1706 | } | |
9cade1a4 | 1707 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1708 | |
9cade1a4 | 1709 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1710 | { |
9cade1a4 | 1711 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1712 | |
7a83c045 | 1713 | dw_dma_on(dw); |
3bfb1d20 | 1714 | return 0; |
3bfb1d20 | 1715 | } |
9cade1a4 | 1716 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1717 | |
9cade1a4 | 1718 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1719 | |
1720 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1721 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1722 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1723 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |