Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
b801479b | 11 | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
d3f797d9 | 22 | #include <linux/of.h> |
f9c6a655 | 23 | #include <linux/of_dma.h> |
3bfb1d20 HS |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/slab.h> | |
42c91ee7 AS |
28 | #include <linux/acpi.h> |
29 | #include <linux/acpi_dma.h> | |
3bfb1d20 HS |
30 | |
31 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 32 | #include "dmaengine.h" |
3bfb1d20 HS |
33 | |
34 | /* | |
35 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
36 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
37 | * of which use ARM any more). See the "Databook" from Synopsys for | |
38 | * information beyond what licensees probably provide. | |
39 | * | |
40 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
41 | * which does not support descriptor writeback. | |
42 | */ | |
43 | ||
a0982004 AS |
44 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
45 | { | |
46 | return slave ? slave->dst_master : 0; | |
47 | } | |
48 | ||
49 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
50 | { | |
51 | return slave ? slave->src_master : 1; | |
52 | } | |
53 | ||
f776076b | 54 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 55 | { |
f776076b AB |
56 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
57 | struct dw_dma_slave *dws = dwc->chan.private; | |
58 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 59 | |
f776076b AB |
60 | if (dwc->request_line == ~0) { |
61 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
62 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
63 | } | |
5be10f34 AS |
64 | } |
65 | ||
327e6970 | 66 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
67 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
68 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 69 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 70 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 71 | DW_DMA_MSIZE_16; \ |
495aea4b | 72 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 73 | DW_DMA_MSIZE_16; \ |
f301c062 | 74 | \ |
327e6970 VK |
75 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
76 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
77 | | DWC_CTLL_LLP_D_EN \ |
78 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
79 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
80 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 81 | }) |
3bfb1d20 | 82 | |
3bfb1d20 HS |
83 | /* |
84 | * Number of descriptors to allocate for each channel. This should be | |
85 | * made configurable somehow; preferably, the clients (at least the | |
86 | * ones using slave transfers) should be able to give us a hint. | |
87 | */ | |
88 | #define NR_DESCS_PER_CHANNEL 64 | |
89 | ||
90 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 91 | |
41d5e59c DW |
92 | static struct device *chan2dev(struct dma_chan *chan) |
93 | { | |
94 | return &chan->dev->device; | |
95 | } | |
96 | static struct device *chan2parent(struct dma_chan *chan) | |
97 | { | |
98 | return chan->dev->device.parent; | |
99 | } | |
100 | ||
3bfb1d20 HS |
101 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
102 | { | |
e63a47a3 | 103 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
104 | } |
105 | ||
3bfb1d20 HS |
106 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
107 | { | |
108 | struct dw_desc *desc, *_desc; | |
109 | struct dw_desc *ret = NULL; | |
110 | unsigned int i = 0; | |
69cea5a0 | 111 | unsigned long flags; |
3bfb1d20 | 112 | |
69cea5a0 | 113 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 114 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 115 | i++; |
3bfb1d20 HS |
116 | if (async_tx_test_ack(&desc->txd)) { |
117 | list_del(&desc->desc_node); | |
118 | ret = desc; | |
119 | break; | |
120 | } | |
41d5e59c | 121 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 122 | } |
69cea5a0 | 123 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 124 | |
41d5e59c | 125 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
126 | |
127 | return ret; | |
128 | } | |
129 | ||
3bfb1d20 HS |
130 | /* |
131 | * Move a descriptor, including any children, to the free list. | |
132 | * `desc' must not be on any lists. | |
133 | */ | |
134 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
135 | { | |
69cea5a0 VK |
136 | unsigned long flags; |
137 | ||
3bfb1d20 HS |
138 | if (desc) { |
139 | struct dw_desc *child; | |
140 | ||
69cea5a0 | 141 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 142 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 143 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
144 | "moving child desc %p to freelist\n", |
145 | child); | |
e0bd0f8c | 146 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 147 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 148 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 149 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
150 | } |
151 | } | |
152 | ||
61e183f8 VK |
153 | static void dwc_initialize(struct dw_dma_chan *dwc) |
154 | { | |
155 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
156 | struct dw_dma_slave *dws = dwc->chan.private; | |
157 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
158 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
159 | ||
160 | if (dwc->initialized == true) | |
161 | return; | |
162 | ||
f776076b | 163 | if (dws) { |
61e183f8 VK |
164 | /* |
165 | * We need controller-specific data to set up slave | |
166 | * transfers. | |
167 | */ | |
168 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
169 | ||
170 | cfghi = dws->cfg_hi; | |
171 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 172 | } else { |
0fdb567f | 173 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 174 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 175 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 176 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
177 | } |
178 | ||
179 | channel_writel(dwc, CFG_LO, cfglo); | |
180 | channel_writel(dwc, CFG_HI, cfghi); | |
181 | ||
182 | /* Enable interrupts */ | |
183 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
184 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
185 | ||
186 | dwc->initialized = true; | |
187 | } | |
188 | ||
3bfb1d20 HS |
189 | /*----------------------------------------------------------------------*/ |
190 | ||
4c2d56c5 AS |
191 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
192 | { | |
193 | /* | |
194 | * We can be a lot more clever here, but this should take care | |
195 | * of the most common optimization. | |
196 | */ | |
197 | if (!(v & 7)) | |
198 | return 3; | |
199 | else if (!(v & 3)) | |
200 | return 2; | |
201 | else if (!(v & 1)) | |
202 | return 1; | |
203 | return 0; | |
204 | } | |
205 | ||
f52b36d2 | 206 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
207 | { |
208 | dev_err(chan2dev(&dwc->chan), | |
209 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
210 | channel_readl(dwc, SAR), | |
211 | channel_readl(dwc, DAR), | |
212 | channel_readl(dwc, LLP), | |
213 | channel_readl(dwc, CTL_HI), | |
214 | channel_readl(dwc, CTL_LO)); | |
215 | } | |
216 | ||
3f936207 AS |
217 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
218 | { | |
219 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
220 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
221 | cpu_relax(); | |
222 | } | |
223 | ||
1d455437 AS |
224 | /*----------------------------------------------------------------------*/ |
225 | ||
fed2574b AS |
226 | /* Perform single block transfer */ |
227 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
228 | struct dw_desc *desc) | |
229 | { | |
230 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
231 | u32 ctllo; | |
232 | ||
233 | /* Software emulation of LLP mode relies on interrupts to continue | |
234 | * multi block transfer. */ | |
235 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
236 | ||
237 | channel_writel(dwc, SAR, desc->lli.sar); | |
238 | channel_writel(dwc, DAR, desc->lli.dar); | |
239 | channel_writel(dwc, CTL_LO, ctllo); | |
240 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
241 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
242 | |
243 | /* Move pointer to next descriptor */ | |
244 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
245 | } |
246 | ||
3bfb1d20 HS |
247 | /* Called with dwc->lock held and bh disabled */ |
248 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
249 | { | |
250 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 251 | unsigned long was_soft_llp; |
3bfb1d20 HS |
252 | |
253 | /* ASSERT: channel is idle */ | |
254 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 255 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 256 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 257 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
258 | |
259 | /* The tasklet will hopefully advance the queue... */ | |
260 | return; | |
261 | } | |
262 | ||
fed2574b AS |
263 | if (dwc->nollp) { |
264 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
265 | &dwc->flags); | |
266 | if (was_soft_llp) { | |
267 | dev_err(chan2dev(&dwc->chan), | |
268 | "BUG: Attempted to start new LLP transfer " | |
269 | "inside ongoing one\n"); | |
270 | return; | |
271 | } | |
272 | ||
273 | dwc_initialize(dwc); | |
274 | ||
4702d524 | 275 | dwc->residue = first->total_len; |
f5c6a7df | 276 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 277 | |
fdf475fa | 278 | /* Submit first block */ |
fed2574b AS |
279 | dwc_do_single_block(dwc, first); |
280 | ||
281 | return; | |
282 | } | |
283 | ||
61e183f8 VK |
284 | dwc_initialize(dwc); |
285 | ||
3bfb1d20 HS |
286 | channel_writel(dwc, LLP, first->txd.phys); |
287 | channel_writel(dwc, CTL_LO, | |
288 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
289 | channel_writel(dwc, CTL_HI, 0); | |
290 | channel_set_bit(dw, CH_EN, dwc->mask); | |
291 | } | |
292 | ||
293 | /*----------------------------------------------------------------------*/ | |
294 | ||
295 | static void | |
5fedefb8 VK |
296 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
297 | bool callback_required) | |
3bfb1d20 | 298 | { |
5fedefb8 VK |
299 | dma_async_tx_callback callback = NULL; |
300 | void *param = NULL; | |
3bfb1d20 | 301 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 302 | struct dw_desc *child; |
69cea5a0 | 303 | unsigned long flags; |
3bfb1d20 | 304 | |
41d5e59c | 305 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 306 | |
69cea5a0 | 307 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 308 | dma_cookie_complete(txd); |
5fedefb8 VK |
309 | if (callback_required) { |
310 | callback = txd->callback; | |
311 | param = txd->callback_param; | |
312 | } | |
3bfb1d20 | 313 | |
e518076e VK |
314 | /* async_tx_ack */ |
315 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
316 | async_tx_ack(&child->txd); | |
317 | async_tx_ack(&desc->txd); | |
318 | ||
e0bd0f8c | 319 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
320 | list_move(&desc->desc_node, &dwc->free_list); |
321 | ||
495aea4b | 322 | if (!is_slave_direction(dwc->direction)) { |
657a77fa AN |
323 | struct device *parent = chan2parent(&dwc->chan); |
324 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
325 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
326 | dma_unmap_single(parent, desc->lli.dar, | |
30d38a32 | 327 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
328 | else |
329 | dma_unmap_page(parent, desc->lli.dar, | |
30d38a32 | 330 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
331 | } |
332 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
333 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
334 | dma_unmap_single(parent, desc->lli.sar, | |
30d38a32 | 335 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
336 | else |
337 | dma_unmap_page(parent, desc->lli.sar, | |
30d38a32 | 338 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
339 | } |
340 | } | |
3bfb1d20 | 341 | |
69cea5a0 VK |
342 | spin_unlock_irqrestore(&dwc->lock, flags); |
343 | ||
21e93c1e | 344 | if (callback) |
3bfb1d20 HS |
345 | callback(param); |
346 | } | |
347 | ||
348 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
349 | { | |
350 | struct dw_desc *desc, *_desc; | |
351 | LIST_HEAD(list); | |
69cea5a0 | 352 | unsigned long flags; |
3bfb1d20 | 353 | |
69cea5a0 | 354 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 355 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 356 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
357 | "BUG: XFER bit set, but channel not idle!\n"); |
358 | ||
359 | /* Try to continue after resetting the channel... */ | |
3f936207 | 360 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
361 | } |
362 | ||
363 | /* | |
364 | * Submit queued descriptors ASAP, i.e. before we go through | |
365 | * the completed ones. | |
366 | */ | |
3bfb1d20 | 367 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
368 | if (!list_empty(&dwc->queue)) { |
369 | list_move(dwc->queue.next, &dwc->active_list); | |
370 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
371 | } | |
3bfb1d20 | 372 | |
69cea5a0 VK |
373 | spin_unlock_irqrestore(&dwc->lock, flags); |
374 | ||
3bfb1d20 | 375 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 376 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
377 | } |
378 | ||
4702d524 AS |
379 | /* Returns how many bytes were already received from source */ |
380 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
381 | { | |
382 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
383 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
384 | ||
385 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
386 | } | |
387 | ||
3bfb1d20 HS |
388 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
389 | { | |
390 | dma_addr_t llp; | |
391 | struct dw_desc *desc, *_desc; | |
392 | struct dw_desc *child; | |
393 | u32 status_xfer; | |
69cea5a0 | 394 | unsigned long flags; |
3bfb1d20 | 395 | |
69cea5a0 | 396 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
397 | llp = channel_readl(dwc, LLP); |
398 | status_xfer = dma_readl(dw, RAW.XFER); | |
399 | ||
400 | if (status_xfer & dwc->mask) { | |
401 | /* Everything we've submitted is done */ | |
402 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
403 | |
404 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
405 | struct list_head *head, *active = dwc->tx_node_active; |
406 | ||
407 | /* | |
408 | * We are inside first active descriptor. | |
409 | * Otherwise something is really wrong. | |
410 | */ | |
411 | desc = dwc_first_active(dwc); | |
412 | ||
413 | head = &desc->tx_list; | |
414 | if (active != head) { | |
4702d524 AS |
415 | /* Update desc to reflect last sent one */ |
416 | if (active != head->next) | |
417 | desc = to_dw_desc(active->prev); | |
418 | ||
419 | dwc->residue -= desc->len; | |
420 | ||
fdf475fa | 421 | child = to_dw_desc(active); |
77bcc497 AS |
422 | |
423 | /* Submit next block */ | |
fdf475fa | 424 | dwc_do_single_block(dwc, child); |
77bcc497 | 425 | |
fdf475fa | 426 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
427 | return; |
428 | } | |
fdf475fa | 429 | |
77bcc497 AS |
430 | /* We are done here */ |
431 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
432 | } | |
4702d524 AS |
433 | |
434 | dwc->residue = 0; | |
435 | ||
69cea5a0 VK |
436 | spin_unlock_irqrestore(&dwc->lock, flags); |
437 | ||
3bfb1d20 HS |
438 | dwc_complete_all(dw, dwc); |
439 | return; | |
440 | } | |
441 | ||
69cea5a0 | 442 | if (list_empty(&dwc->active_list)) { |
4702d524 | 443 | dwc->residue = 0; |
69cea5a0 | 444 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 445 | return; |
69cea5a0 | 446 | } |
087809fc | 447 | |
77bcc497 AS |
448 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
449 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 450 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 451 | return; |
69cea5a0 | 452 | } |
087809fc | 453 | |
2e4c364e | 454 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 455 | (unsigned long long)llp); |
3bfb1d20 HS |
456 | |
457 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 458 | /* Initial residue value */ |
4702d524 AS |
459 | dwc->residue = desc->total_len; |
460 | ||
75c61225 | 461 | /* Check first descriptors addr */ |
69cea5a0 VK |
462 | if (desc->txd.phys == llp) { |
463 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 464 | return; |
69cea5a0 | 465 | } |
84adccfb | 466 | |
75c61225 | 467 | /* Check first descriptors llp */ |
69cea5a0 | 468 | if (desc->lli.llp == llp) { |
3bfb1d20 | 469 | /* This one is currently in progress */ |
4702d524 | 470 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 471 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 472 | return; |
69cea5a0 | 473 | } |
3bfb1d20 | 474 | |
4702d524 AS |
475 | dwc->residue -= desc->len; |
476 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 477 | if (child->lli.llp == llp) { |
3bfb1d20 | 478 | /* Currently in progress */ |
4702d524 | 479 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 480 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 481 | return; |
69cea5a0 | 482 | } |
4702d524 AS |
483 | dwc->residue -= child->len; |
484 | } | |
3bfb1d20 HS |
485 | |
486 | /* | |
487 | * No descriptors so far seem to be in progress, i.e. | |
488 | * this one must be done. | |
489 | */ | |
69cea5a0 | 490 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 491 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 492 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
493 | } |
494 | ||
41d5e59c | 495 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
496 | "BUG: All descriptors done, but channel not idle!\n"); |
497 | ||
498 | /* Try to continue after resetting the channel... */ | |
3f936207 | 499 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
500 | |
501 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
502 | list_move(dwc->queue.next, &dwc->active_list); |
503 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 504 | } |
69cea5a0 | 505 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
506 | } |
507 | ||
93aad1bc | 508 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 509 | { |
21d43f49 AS |
510 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
511 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
512 | } |
513 | ||
514 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
515 | { | |
516 | struct dw_desc *bad_desc; | |
517 | struct dw_desc *child; | |
69cea5a0 | 518 | unsigned long flags; |
3bfb1d20 HS |
519 | |
520 | dwc_scan_descriptors(dw, dwc); | |
521 | ||
69cea5a0 VK |
522 | spin_lock_irqsave(&dwc->lock, flags); |
523 | ||
3bfb1d20 HS |
524 | /* |
525 | * The descriptor currently at the head of the active list is | |
526 | * borked. Since we don't have any way to report errors, we'll | |
527 | * just have to scream loudly and try to carry on. | |
528 | */ | |
529 | bad_desc = dwc_first_active(dwc); | |
530 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 531 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
532 | |
533 | /* Clear the error flag and try to restart the controller */ | |
534 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
535 | if (!list_empty(&dwc->active_list)) | |
536 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
537 | ||
538 | /* | |
ba84bd71 | 539 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
540 | * when someone submits a bad physical address in a |
541 | * descriptor, we should consider ourselves lucky that the | |
542 | * controller flagged an error instead of scribbling over | |
543 | * random memory locations. | |
544 | */ | |
ba84bd71 AS |
545 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
546 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 547 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 548 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
549 | dwc_dump_lli(dwc, &child->lli); |
550 | ||
69cea5a0 VK |
551 | spin_unlock_irqrestore(&dwc->lock, flags); |
552 | ||
3bfb1d20 | 553 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 554 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
555 | } |
556 | ||
d9de4519 HCE |
557 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
558 | ||
8004cbb4 | 559 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
560 | { |
561 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
562 | return channel_readl(dwc, SAR); | |
563 | } | |
564 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
565 | ||
8004cbb4 | 566 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
567 | { |
568 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
569 | return channel_readl(dwc, DAR); | |
570 | } | |
571 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
572 | ||
75c61225 | 573 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 574 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 575 | u32 status_err, u32 status_xfer) |
d9de4519 | 576 | { |
69cea5a0 VK |
577 | unsigned long flags; |
578 | ||
ff7b05f2 | 579 | if (dwc->mask) { |
d9de4519 HCE |
580 | void (*callback)(void *param); |
581 | void *callback_param; | |
582 | ||
583 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
584 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
585 | |
586 | callback = dwc->cdesc->period_callback; | |
587 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
588 | |
589 | if (callback) | |
d9de4519 | 590 | callback(callback_param); |
d9de4519 HCE |
591 | } |
592 | ||
593 | /* | |
594 | * Error and transfer complete are highly unlikely, and will most | |
595 | * likely be due to a configuration error by the user. | |
596 | */ | |
597 | if (unlikely(status_err & dwc->mask) || | |
598 | unlikely(status_xfer & dwc->mask)) { | |
599 | int i; | |
600 | ||
601 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
602 | "interrupt, stopping DMA transfer\n", | |
603 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
604 | |
605 | spin_lock_irqsave(&dwc->lock, flags); | |
606 | ||
1d455437 | 607 | dwc_dump_chan_regs(dwc); |
d9de4519 | 608 | |
3f936207 | 609 | dwc_chan_disable(dw, dwc); |
d9de4519 | 610 | |
75c61225 | 611 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
612 | channel_writel(dwc, LLP, 0); |
613 | channel_writel(dwc, CTL_LO, 0); | |
614 | channel_writel(dwc, CTL_HI, 0); | |
615 | ||
d9de4519 HCE |
616 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
617 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
618 | ||
619 | for (i = 0; i < dwc->cdesc->periods; i++) | |
620 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
621 | |
622 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
623 | } |
624 | } | |
625 | ||
626 | /* ------------------------------------------------------------------------- */ | |
627 | ||
3bfb1d20 HS |
628 | static void dw_dma_tasklet(unsigned long data) |
629 | { | |
630 | struct dw_dma *dw = (struct dw_dma *)data; | |
631 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
632 | u32 status_xfer; |
633 | u32 status_err; | |
634 | int i; | |
635 | ||
7fe7b2f4 | 636 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
637 | status_err = dma_readl(dw, RAW.ERROR); |
638 | ||
2e4c364e | 639 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
640 | |
641 | for (i = 0; i < dw->dma.chancnt; i++) { | |
642 | dwc = &dw->chan[i]; | |
d9de4519 | 643 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 644 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 645 | else if (status_err & (1 << i)) |
3bfb1d20 | 646 | dwc_handle_error(dw, dwc); |
77bcc497 | 647 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 648 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
649 | } |
650 | ||
651 | /* | |
ff7b05f2 | 652 | * Re-enable interrupts. |
3bfb1d20 HS |
653 | */ |
654 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
655 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
656 | } | |
657 | ||
658 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
659 | { | |
660 | struct dw_dma *dw = dev_id; | |
661 | u32 status; | |
662 | ||
2e4c364e | 663 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
664 | dma_readl(dw, STATUS_INT)); |
665 | ||
666 | /* | |
667 | * Just disable the interrupts. We'll turn them back on in the | |
668 | * softirq handler. | |
669 | */ | |
670 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
671 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
672 | ||
673 | status = dma_readl(dw, STATUS_INT); | |
674 | if (status) { | |
675 | dev_err(dw->dma.dev, | |
676 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
677 | status); | |
678 | ||
679 | /* Try to recover */ | |
680 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
681 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
682 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
683 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
684 | } | |
685 | ||
686 | tasklet_schedule(&dw->tasklet); | |
687 | ||
688 | return IRQ_HANDLED; | |
689 | } | |
690 | ||
691 | /*----------------------------------------------------------------------*/ | |
692 | ||
693 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
694 | { | |
695 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
696 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
697 | dma_cookie_t cookie; | |
69cea5a0 | 698 | unsigned long flags; |
3bfb1d20 | 699 | |
69cea5a0 | 700 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 701 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
702 | |
703 | /* | |
704 | * REVISIT: We should attempt to chain as many descriptors as | |
705 | * possible, perhaps even appending to those already submitted | |
706 | * for DMA. But this is hard to do in a race-free manner. | |
707 | */ | |
708 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 709 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 710 | desc->txd.cookie); |
3bfb1d20 | 711 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 712 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 713 | } else { |
2e4c364e | 714 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
715 | desc->txd.cookie); |
716 | ||
717 | list_add_tail(&desc->desc_node, &dwc->queue); | |
718 | } | |
719 | ||
69cea5a0 | 720 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
721 | |
722 | return cookie; | |
723 | } | |
724 | ||
725 | static struct dma_async_tx_descriptor * | |
726 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
727 | size_t len, unsigned long flags) | |
728 | { | |
729 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 730 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
731 | struct dw_desc *desc; |
732 | struct dw_desc *first; | |
733 | struct dw_desc *prev; | |
734 | size_t xfer_count; | |
735 | size_t offset; | |
736 | unsigned int src_width; | |
737 | unsigned int dst_width; | |
3d4f8605 | 738 | unsigned int data_width; |
3bfb1d20 HS |
739 | u32 ctllo; |
740 | ||
2f45d613 | 741 | dev_vdbg(chan2dev(chan), |
2e4c364e | 742 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
743 | (unsigned long long)dest, (unsigned long long)src, |
744 | len, flags); | |
3bfb1d20 HS |
745 | |
746 | if (unlikely(!len)) { | |
2e4c364e | 747 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
748 | return NULL; |
749 | } | |
750 | ||
0fdb567f AS |
751 | dwc->direction = DMA_MEM_TO_MEM; |
752 | ||
f776076b AB |
753 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
754 | dw->data_width[dwc->dst_master]); | |
a0982004 | 755 | |
3d4f8605 AS |
756 | src_width = dst_width = min_t(unsigned int, data_width, |
757 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 758 | |
327e6970 | 759 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
760 | | DWC_CTLL_DST_WIDTH(dst_width) |
761 | | DWC_CTLL_SRC_WIDTH(src_width) | |
762 | | DWC_CTLL_DST_INC | |
763 | | DWC_CTLL_SRC_INC | |
764 | | DWC_CTLL_FC_M2M; | |
765 | prev = first = NULL; | |
766 | ||
767 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
768 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 769 | dwc->block_size); |
3bfb1d20 HS |
770 | |
771 | desc = dwc_desc_get(dwc); | |
772 | if (!desc) | |
773 | goto err_desc_get; | |
774 | ||
775 | desc->lli.sar = src + offset; | |
776 | desc->lli.dar = dest + offset; | |
777 | desc->lli.ctllo = ctllo; | |
778 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 779 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
780 | |
781 | if (!first) { | |
782 | first = desc; | |
783 | } else { | |
784 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 785 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 786 | &first->tx_list); |
3bfb1d20 HS |
787 | } |
788 | prev = desc; | |
789 | } | |
790 | ||
3bfb1d20 HS |
791 | if (flags & DMA_PREP_INTERRUPT) |
792 | /* Trigger interrupt after last block */ | |
793 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
794 | ||
795 | prev->lli.llp = 0; | |
3bfb1d20 | 796 | first->txd.flags = flags; |
30d38a32 | 797 | first->total_len = len; |
3bfb1d20 HS |
798 | |
799 | return &first->txd; | |
800 | ||
801 | err_desc_get: | |
802 | dwc_desc_put(dwc, first); | |
803 | return NULL; | |
804 | } | |
805 | ||
806 | static struct dma_async_tx_descriptor * | |
807 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 808 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 809 | unsigned long flags, void *context) |
3bfb1d20 HS |
810 | { |
811 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 812 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 813 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
814 | struct dw_desc *prev; |
815 | struct dw_desc *first; | |
816 | u32 ctllo; | |
817 | dma_addr_t reg; | |
818 | unsigned int reg_width; | |
819 | unsigned int mem_width; | |
a0982004 | 820 | unsigned int data_width; |
3bfb1d20 HS |
821 | unsigned int i; |
822 | struct scatterlist *sg; | |
823 | size_t total_len = 0; | |
824 | ||
2e4c364e | 825 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 826 | |
495aea4b | 827 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
828 | return NULL; |
829 | ||
0fdb567f AS |
830 | dwc->direction = direction; |
831 | ||
3bfb1d20 HS |
832 | prev = first = NULL; |
833 | ||
3bfb1d20 | 834 | switch (direction) { |
db8196df | 835 | case DMA_MEM_TO_DEV: |
327e6970 VK |
836 | reg_width = __fls(sconfig->dst_addr_width); |
837 | reg = sconfig->dst_addr; | |
838 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
839 | | DWC_CTLL_DST_WIDTH(reg_width) |
840 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
841 | | DWC_CTLL_SRC_INC); |
842 | ||
843 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
844 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
845 | ||
f776076b | 846 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 847 | |
3bfb1d20 HS |
848 | for_each_sg(sgl, sg, sg_len, i) { |
849 | struct dw_desc *desc; | |
69dc14b5 | 850 | u32 len, dlen, mem; |
3bfb1d20 | 851 | |
cbb796cc | 852 | mem = sg_dma_address(sg); |
69dc14b5 | 853 | len = sg_dma_len(sg); |
6bc711f6 | 854 | |
a0982004 AS |
855 | mem_width = min_t(unsigned int, |
856 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 857 | |
69dc14b5 | 858 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
859 | desc = dwc_desc_get(dwc); |
860 | if (!desc) { | |
41d5e59c | 861 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
862 | "not enough descriptors available\n"); |
863 | goto err_desc_get; | |
864 | } | |
865 | ||
3bfb1d20 HS |
866 | desc->lli.sar = mem; |
867 | desc->lli.dar = reg; | |
868 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
869 | if ((len >> mem_width) > dwc->block_size) { |
870 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
871 | mem += dlen; |
872 | len -= dlen; | |
873 | } else { | |
874 | dlen = len; | |
875 | len = 0; | |
876 | } | |
877 | ||
878 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 879 | desc->len = dlen; |
3bfb1d20 HS |
880 | |
881 | if (!first) { | |
882 | first = desc; | |
883 | } else { | |
884 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 885 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 886 | &first->tx_list); |
3bfb1d20 HS |
887 | } |
888 | prev = desc; | |
69dc14b5 VK |
889 | total_len += dlen; |
890 | ||
891 | if (len) | |
892 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
893 | } |
894 | break; | |
db8196df | 895 | case DMA_DEV_TO_MEM: |
327e6970 VK |
896 | reg_width = __fls(sconfig->src_addr_width); |
897 | reg = sconfig->src_addr; | |
898 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
899 | | DWC_CTLL_SRC_WIDTH(reg_width) |
900 | | DWC_CTLL_DST_INC | |
327e6970 VK |
901 | | DWC_CTLL_SRC_FIX); |
902 | ||
903 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
904 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 905 | |
f776076b | 906 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 907 | |
3bfb1d20 HS |
908 | for_each_sg(sgl, sg, sg_len, i) { |
909 | struct dw_desc *desc; | |
69dc14b5 | 910 | u32 len, dlen, mem; |
3bfb1d20 | 911 | |
cbb796cc | 912 | mem = sg_dma_address(sg); |
3bfb1d20 | 913 | len = sg_dma_len(sg); |
6bc711f6 | 914 | |
a0982004 AS |
915 | mem_width = min_t(unsigned int, |
916 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 917 | |
69dc14b5 VK |
918 | slave_sg_fromdev_fill_desc: |
919 | desc = dwc_desc_get(dwc); | |
920 | if (!desc) { | |
921 | dev_err(chan2dev(chan), | |
922 | "not enough descriptors available\n"); | |
923 | goto err_desc_get; | |
924 | } | |
925 | ||
3bfb1d20 HS |
926 | desc->lli.sar = reg; |
927 | desc->lli.dar = mem; | |
928 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
929 | if ((len >> reg_width) > dwc->block_size) { |
930 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
931 | mem += dlen; |
932 | len -= dlen; | |
933 | } else { | |
934 | dlen = len; | |
935 | len = 0; | |
936 | } | |
937 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 938 | desc->len = dlen; |
3bfb1d20 HS |
939 | |
940 | if (!first) { | |
941 | first = desc; | |
942 | } else { | |
943 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 944 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 945 | &first->tx_list); |
3bfb1d20 HS |
946 | } |
947 | prev = desc; | |
69dc14b5 VK |
948 | total_len += dlen; |
949 | ||
950 | if (len) | |
951 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
952 | } |
953 | break; | |
954 | default: | |
955 | return NULL; | |
956 | } | |
957 | ||
958 | if (flags & DMA_PREP_INTERRUPT) | |
959 | /* Trigger interrupt after last block */ | |
960 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
961 | ||
962 | prev->lli.llp = 0; | |
30d38a32 | 963 | first->total_len = total_len; |
3bfb1d20 HS |
964 | |
965 | return &first->txd; | |
966 | ||
967 | err_desc_get: | |
968 | dwc_desc_put(dwc, first); | |
969 | return NULL; | |
970 | } | |
971 | ||
327e6970 VK |
972 | /* |
973 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
974 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
975 | * | |
976 | * NOTE: burst size 2 is not supported by controller. | |
977 | * | |
978 | * This can be done by finding least significant bit set: n & (n - 1) | |
979 | */ | |
980 | static inline void convert_burst(u32 *maxburst) | |
981 | { | |
982 | if (*maxburst > 1) | |
983 | *maxburst = fls(*maxburst) - 2; | |
984 | else | |
985 | *maxburst = 0; | |
986 | } | |
987 | ||
988 | static int | |
989 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
990 | { | |
991 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
992 | ||
495aea4b AS |
993 | /* Check if chan will be configured for slave transfers */ |
994 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
995 | return -EINVAL; |
996 | ||
997 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 998 | dwc->direction = sconfig->direction; |
327e6970 | 999 | |
f776076b AB |
1000 | /* Take the request line from slave_id member */ |
1001 | if (dwc->request_line == ~0) | |
1002 | dwc->request_line = sconfig->slave_id; | |
1003 | ||
327e6970 VK |
1004 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
1005 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
21fe3c52 AS |
1010 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
1011 | { | |
1012 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 1013 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
1014 | |
1015 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
1016 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
1017 | udelay(2); | |
21fe3c52 AS |
1018 | |
1019 | dwc->paused = true; | |
1020 | } | |
1021 | ||
1022 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1023 | { | |
1024 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1025 | ||
1026 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1027 | ||
1028 | dwc->paused = false; | |
1029 | } | |
1030 | ||
05827630 LW |
1031 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1032 | unsigned long arg) | |
3bfb1d20 HS |
1033 | { |
1034 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1035 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1036 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1037 | unsigned long flags; |
3bfb1d20 HS |
1038 | LIST_HEAD(list); |
1039 | ||
a7c57cf7 LW |
1040 | if (cmd == DMA_PAUSE) { |
1041 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1042 | |
21fe3c52 | 1043 | dwc_chan_pause(dwc); |
3bfb1d20 | 1044 | |
a7c57cf7 LW |
1045 | spin_unlock_irqrestore(&dwc->lock, flags); |
1046 | } else if (cmd == DMA_RESUME) { | |
1047 | if (!dwc->paused) | |
1048 | return 0; | |
3bfb1d20 | 1049 | |
a7c57cf7 | 1050 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1051 | |
21fe3c52 | 1052 | dwc_chan_resume(dwc); |
3bfb1d20 | 1053 | |
a7c57cf7 LW |
1054 | spin_unlock_irqrestore(&dwc->lock, flags); |
1055 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1056 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1057 | |
fed2574b AS |
1058 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1059 | ||
3f936207 | 1060 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1061 | |
a5dbff11 | 1062 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1063 | |
1064 | /* active_list entries will end up before queued entries */ | |
1065 | list_splice_init(&dwc->queue, &list); | |
1066 | list_splice_init(&dwc->active_list, &list); | |
1067 | ||
1068 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1069 | ||
1070 | /* Flush all pending and queued descriptors */ | |
1071 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1072 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1073 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1074 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1075 | } else { | |
a7c57cf7 | 1076 | return -ENXIO; |
327e6970 | 1077 | } |
c3635c78 LW |
1078 | |
1079 | return 0; | |
3bfb1d20 HS |
1080 | } |
1081 | ||
4702d524 AS |
1082 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1083 | { | |
1084 | unsigned long flags; | |
1085 | u32 residue; | |
1086 | ||
1087 | spin_lock_irqsave(&dwc->lock, flags); | |
1088 | ||
1089 | residue = dwc->residue; | |
1090 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1091 | residue -= dwc_get_sent(dwc); | |
1092 | ||
1093 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1094 | return residue; | |
1095 | } | |
1096 | ||
3bfb1d20 | 1097 | static enum dma_status |
07934481 LW |
1098 | dwc_tx_status(struct dma_chan *chan, |
1099 | dma_cookie_t cookie, | |
1100 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1101 | { |
1102 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1103 | enum dma_status ret; |
3bfb1d20 | 1104 | |
96a2af41 | 1105 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1106 | if (ret != DMA_SUCCESS) { |
1107 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1108 | ||
96a2af41 | 1109 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1110 | } |
1111 | ||
abf53902 | 1112 | if (ret != DMA_SUCCESS) |
4702d524 | 1113 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1114 | |
a7c57cf7 LW |
1115 | if (dwc->paused) |
1116 | return DMA_PAUSED; | |
3bfb1d20 HS |
1117 | |
1118 | return ret; | |
1119 | } | |
1120 | ||
1121 | static void dwc_issue_pending(struct dma_chan *chan) | |
1122 | { | |
1123 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1124 | ||
3bfb1d20 HS |
1125 | if (!list_empty(&dwc->queue)) |
1126 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1127 | } |
1128 | ||
aa1e6f1a | 1129 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1130 | { |
1131 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1132 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1133 | struct dw_desc *desc; | |
3bfb1d20 | 1134 | int i; |
69cea5a0 | 1135 | unsigned long flags; |
3bfb1d20 | 1136 | |
2e4c364e | 1137 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1138 | |
3bfb1d20 HS |
1139 | /* ASSERT: channel is idle */ |
1140 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1141 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1142 | return -EIO; |
1143 | } | |
1144 | ||
d3ee98cd | 1145 | dma_cookie_init(chan); |
3bfb1d20 | 1146 | |
3bfb1d20 HS |
1147 | /* |
1148 | * NOTE: some controllers may have additional features that we | |
1149 | * need to initialize here, like "scatter-gather" (which | |
1150 | * doesn't mean what you think it means), and status writeback. | |
1151 | */ | |
1152 | ||
f776076b AB |
1153 | dwc_set_masters(dwc); |
1154 | ||
69cea5a0 | 1155 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1156 | i = dwc->descs_allocated; |
1157 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1158 | dma_addr_t phys; |
1159 | ||
69cea5a0 | 1160 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1161 | |
f8122a82 | 1162 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1163 | if (!desc) |
1164 | goto err_desc_alloc; | |
3bfb1d20 | 1165 | |
f8122a82 | 1166 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1167 | |
e0bd0f8c | 1168 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1169 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1170 | desc->txd.tx_submit = dwc_tx_submit; | |
1171 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1172 | desc->txd.phys = phys; |
cbd65312 | 1173 | |
3bfb1d20 HS |
1174 | dwc_desc_put(dwc, desc); |
1175 | ||
69cea5a0 | 1176 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1177 | i = ++dwc->descs_allocated; |
1178 | } | |
1179 | ||
69cea5a0 | 1180 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1181 | |
2e4c364e | 1182 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1183 | |
cbd65312 AS |
1184 | return i; |
1185 | ||
1186 | err_desc_alloc: | |
cbd65312 AS |
1187 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1188 | ||
3bfb1d20 HS |
1189 | return i; |
1190 | } | |
1191 | ||
1192 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1193 | { | |
1194 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1195 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1196 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1197 | unsigned long flags; |
3bfb1d20 HS |
1198 | LIST_HEAD(list); |
1199 | ||
2e4c364e | 1200 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1201 | dwc->descs_allocated); |
1202 | ||
1203 | /* ASSERT: channel is idle */ | |
1204 | BUG_ON(!list_empty(&dwc->active_list)); | |
1205 | BUG_ON(!list_empty(&dwc->queue)); | |
1206 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1207 | ||
69cea5a0 | 1208 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1209 | list_splice_init(&dwc->free_list, &list); |
1210 | dwc->descs_allocated = 0; | |
61e183f8 | 1211 | dwc->initialized = false; |
f776076b | 1212 | dwc->request_line = ~0; |
3bfb1d20 HS |
1213 | |
1214 | /* Disable interrupts */ | |
1215 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1216 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1217 | ||
69cea5a0 | 1218 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1219 | |
1220 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1221 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1222 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1223 | } |
1224 | ||
2e4c364e | 1225 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1226 | } |
1227 | ||
bd2e6b66 AS |
1228 | /*----------------------------------------------------------------------*/ |
1229 | ||
1230 | struct dw_dma_of_filter_args { | |
f9c6a655 AB |
1231 | struct dw_dma *dw; |
1232 | unsigned int req; | |
1233 | unsigned int src; | |
1234 | unsigned int dst; | |
1235 | }; | |
1236 | ||
bd2e6b66 | 1237 | static bool dw_dma_of_filter(struct dma_chan *chan, void *param) |
a9ddb575 | 1238 | { |
f9c6a655 | 1239 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
bd2e6b66 | 1240 | struct dw_dma_of_filter_args *fargs = param; |
a9ddb575 | 1241 | |
75c61225 | 1242 | /* Ensure the device matches our channel */ |
f9c6a655 AB |
1243 | if (chan->device != &fargs->dw->dma) |
1244 | return false; | |
a9ddb575 | 1245 | |
f9c6a655 | 1246 | dwc->request_line = fargs->req; |
f776076b AB |
1247 | dwc->src_master = fargs->src; |
1248 | dwc->dst_master = fargs->dst; | |
f9c6a655 AB |
1249 | |
1250 | return true; | |
1251 | } | |
1252 | ||
bd2e6b66 AS |
1253 | static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, |
1254 | struct of_dma *ofdma) | |
f9c6a655 AB |
1255 | { |
1256 | struct dw_dma *dw = ofdma->of_dma_data; | |
bd2e6b66 | 1257 | struct dw_dma_of_filter_args fargs = { |
f9c6a655 AB |
1258 | .dw = dw, |
1259 | }; | |
1260 | dma_cap_mask_t cap; | |
1261 | ||
1262 | if (dma_spec->args_count != 3) | |
1263 | return NULL; | |
1264 | ||
f73bb9b3 AB |
1265 | fargs.req = dma_spec->args[0]; |
1266 | fargs.src = dma_spec->args[1]; | |
1267 | fargs.dst = dma_spec->args[2]; | |
f9c6a655 AB |
1268 | |
1269 | if (WARN_ON(fargs.req >= DW_DMA_MAX_NR_REQUESTS || | |
1270 | fargs.src >= dw->nr_masters || | |
1271 | fargs.dst >= dw->nr_masters)) | |
1272 | return NULL; | |
a9ddb575 | 1273 | |
f9c6a655 AB |
1274 | dma_cap_zero(cap); |
1275 | dma_cap_set(DMA_SLAVE, cap); | |
1276 | ||
1277 | /* TODO: there should be a simpler way to do this */ | |
bd2e6b66 | 1278 | return dma_request_channel(cap, dw_dma_of_filter, &fargs); |
a9ddb575 | 1279 | } |
a9ddb575 | 1280 | |
42c91ee7 AS |
1281 | #ifdef CONFIG_ACPI |
1282 | static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param) | |
1283 | { | |
1284 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1285 | struct acpi_dma_spec *dma_spec = param; | |
1286 | ||
1287 | if (chan->device->dev != dma_spec->dev || | |
1288 | chan->chan_id != dma_spec->chan_id) | |
1289 | return false; | |
1290 | ||
1291 | dwc->request_line = dma_spec->slave_id; | |
1292 | dwc->src_master = dwc_get_sms(NULL); | |
1293 | dwc->dst_master = dwc_get_dms(NULL); | |
1294 | ||
1295 | return true; | |
1296 | } | |
1297 | ||
1298 | static void dw_dma_acpi_controller_register(struct dw_dma *dw) | |
1299 | { | |
1300 | struct device *dev = dw->dma.dev; | |
1301 | struct acpi_dma_filter_info *info; | |
1302 | int ret; | |
1303 | ||
1304 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
1305 | if (!info) | |
1306 | return; | |
1307 | ||
1308 | dma_cap_zero(info->dma_cap); | |
1309 | dma_cap_set(DMA_SLAVE, info->dma_cap); | |
1310 | info->filter_fn = dw_dma_acpi_filter; | |
1311 | ||
1312 | ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate, | |
1313 | info); | |
1314 | if (ret) | |
1315 | dev_err(dev, "could not register acpi_dma_controller\n"); | |
1316 | } | |
1317 | #else /* !CONFIG_ACPI */ | |
1318 | static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} | |
1319 | #endif /* !CONFIG_ACPI */ | |
1320 | ||
d9de4519 HCE |
1321 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1322 | ||
1323 | /** | |
1324 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1325 | * @chan: the DMA channel to start | |
1326 | * | |
1327 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1328 | * -errno on failure. | |
1329 | */ | |
1330 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1331 | { | |
1332 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1333 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1334 | unsigned long flags; |
d9de4519 HCE |
1335 | |
1336 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1337 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1338 | return -ENODEV; | |
1339 | } | |
1340 | ||
69cea5a0 | 1341 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1342 | |
75c61225 | 1343 | /* Assert channel is idle */ |
d9de4519 HCE |
1344 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1345 | dev_err(chan2dev(&dwc->chan), | |
1346 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1347 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1348 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1349 | return -EBUSY; |
1350 | } | |
1351 | ||
d9de4519 HCE |
1352 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1353 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1354 | ||
75c61225 | 1355 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1356 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1357 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1358 | channel_writel(dwc, CTL_HI, 0); | |
1359 | ||
1360 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1361 | ||
69cea5a0 | 1362 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1363 | |
1364 | return 0; | |
1365 | } | |
1366 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1367 | ||
1368 | /** | |
1369 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1370 | * @chan: the DMA channel to stop | |
1371 | * | |
1372 | * Must be called with soft interrupts disabled. | |
1373 | */ | |
1374 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1375 | { | |
1376 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1377 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1378 | unsigned long flags; |
d9de4519 | 1379 | |
69cea5a0 | 1380 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1381 | |
3f936207 | 1382 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1383 | |
69cea5a0 | 1384 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1385 | } |
1386 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1387 | ||
1388 | /** | |
1389 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1390 | * @chan: the DMA channel to prepare | |
1391 | * @buf_addr: physical DMA address where the buffer starts | |
1392 | * @buf_len: total number of bytes for the entire buffer | |
1393 | * @period_len: number of bytes for each period | |
1394 | * @direction: transfer direction, to or from device | |
1395 | * | |
1396 | * Must be called before trying to start the transfer. Returns a valid struct | |
1397 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1398 | */ | |
1399 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1400 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1401 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1402 | { |
1403 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1404 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1405 | struct dw_cyclic_desc *cdesc; |
1406 | struct dw_cyclic_desc *retval = NULL; | |
1407 | struct dw_desc *desc; | |
1408 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1409 | unsigned long was_cyclic; |
1410 | unsigned int reg_width; | |
1411 | unsigned int periods; | |
1412 | unsigned int i; | |
69cea5a0 | 1413 | unsigned long flags; |
d9de4519 | 1414 | |
69cea5a0 | 1415 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1416 | if (dwc->nollp) { |
1417 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1418 | dev_dbg(chan2dev(&dwc->chan), | |
1419 | "channel doesn't support LLP transfers\n"); | |
1420 | return ERR_PTR(-EINVAL); | |
1421 | } | |
1422 | ||
d9de4519 | 1423 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1424 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1425 | dev_dbg(chan2dev(&dwc->chan), |
1426 | "queue and/or active list are not empty\n"); | |
1427 | return ERR_PTR(-EBUSY); | |
1428 | } | |
1429 | ||
1430 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1431 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1432 | if (was_cyclic) { |
1433 | dev_dbg(chan2dev(&dwc->chan), | |
1434 | "channel already prepared for cyclic DMA\n"); | |
1435 | return ERR_PTR(-EBUSY); | |
1436 | } | |
1437 | ||
1438 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1439 | |
f44b92f4 AS |
1440 | if (unlikely(!is_slave_direction(direction))) |
1441 | goto out_err; | |
1442 | ||
0fdb567f AS |
1443 | dwc->direction = direction; |
1444 | ||
327e6970 VK |
1445 | if (direction == DMA_MEM_TO_DEV) |
1446 | reg_width = __ffs(sconfig->dst_addr_width); | |
1447 | else | |
1448 | reg_width = __ffs(sconfig->src_addr_width); | |
1449 | ||
d9de4519 HCE |
1450 | periods = buf_len / period_len; |
1451 | ||
1452 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1453 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1454 | goto out_err; |
1455 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1456 | goto out_err; | |
1457 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1458 | goto out_err; | |
d9de4519 HCE |
1459 | |
1460 | retval = ERR_PTR(-ENOMEM); | |
1461 | ||
1462 | if (periods > NR_DESCS_PER_CHANNEL) | |
1463 | goto out_err; | |
1464 | ||
1465 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1466 | if (!cdesc) | |
1467 | goto out_err; | |
1468 | ||
1469 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1470 | if (!cdesc->desc) | |
1471 | goto out_err_alloc; | |
1472 | ||
1473 | for (i = 0; i < periods; i++) { | |
1474 | desc = dwc_desc_get(dwc); | |
1475 | if (!desc) | |
1476 | goto out_err_desc_get; | |
1477 | ||
1478 | switch (direction) { | |
db8196df | 1479 | case DMA_MEM_TO_DEV: |
327e6970 | 1480 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1481 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1482 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1483 | | DWC_CTLL_DST_WIDTH(reg_width) |
1484 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1485 | | DWC_CTLL_DST_FIX | |
1486 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1487 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1488 | |
1489 | desc->lli.ctllo |= sconfig->device_fc ? | |
1490 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1491 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1492 | ||
d9de4519 | 1493 | break; |
db8196df | 1494 | case DMA_DEV_TO_MEM: |
d9de4519 | 1495 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1496 | desc->lli.sar = sconfig->src_addr; |
1497 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1498 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1499 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1500 | | DWC_CTLL_DST_INC | |
1501 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1502 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1503 | |
1504 | desc->lli.ctllo |= sconfig->device_fc ? | |
1505 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1506 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1507 | ||
d9de4519 HCE |
1508 | break; |
1509 | default: | |
1510 | break; | |
1511 | } | |
1512 | ||
1513 | desc->lli.ctlhi = (period_len >> reg_width); | |
1514 | cdesc->desc[i] = desc; | |
1515 | ||
f8122a82 | 1516 | if (last) |
d9de4519 | 1517 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1518 | |
1519 | last = desc; | |
1520 | } | |
1521 | ||
75c61225 | 1522 | /* Let's make a cyclic list */ |
d9de4519 | 1523 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1524 | |
2f45d613 AS |
1525 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1526 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1527 | buf_len, period_len, periods); | |
d9de4519 HCE |
1528 | |
1529 | cdesc->periods = periods; | |
1530 | dwc->cdesc = cdesc; | |
1531 | ||
1532 | return cdesc; | |
1533 | ||
1534 | out_err_desc_get: | |
1535 | while (i--) | |
1536 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1537 | out_err_alloc: | |
1538 | kfree(cdesc); | |
1539 | out_err: | |
1540 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1541 | return (struct dw_cyclic_desc *)retval; | |
1542 | } | |
1543 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1544 | ||
1545 | /** | |
1546 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1547 | * @chan: the DMA channel to free | |
1548 | */ | |
1549 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1550 | { | |
1551 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1552 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1553 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1554 | int i; | |
69cea5a0 | 1555 | unsigned long flags; |
d9de4519 | 1556 | |
2e4c364e | 1557 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1558 | |
1559 | if (!cdesc) | |
1560 | return; | |
1561 | ||
69cea5a0 | 1562 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1563 | |
3f936207 | 1564 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1565 | |
d9de4519 HCE |
1566 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1567 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1568 | ||
69cea5a0 | 1569 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1570 | |
1571 | for (i = 0; i < cdesc->periods; i++) | |
1572 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1573 | ||
1574 | kfree(cdesc->desc); | |
1575 | kfree(cdesc); | |
1576 | ||
1577 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1578 | } | |
1579 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1580 | ||
3bfb1d20 HS |
1581 | /*----------------------------------------------------------------------*/ |
1582 | ||
1583 | static void dw_dma_off(struct dw_dma *dw) | |
1584 | { | |
61e183f8 VK |
1585 | int i; |
1586 | ||
3bfb1d20 HS |
1587 | dma_writel(dw, CFG, 0); |
1588 | ||
1589 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1590 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1591 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1592 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1593 | ||
1594 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1595 | cpu_relax(); | |
61e183f8 VK |
1596 | |
1597 | for (i = 0; i < dw->dma.chancnt; i++) | |
1598 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1599 | } |
1600 | ||
a9ddb575 VK |
1601 | #ifdef CONFIG_OF |
1602 | static struct dw_dma_platform_data * | |
1603 | dw_dma_parse_dt(struct platform_device *pdev) | |
1604 | { | |
f9c6a655 | 1605 | struct device_node *np = pdev->dev.of_node; |
a9ddb575 | 1606 | struct dw_dma_platform_data *pdata; |
a9ddb575 VK |
1607 | u32 tmp, arr[4]; |
1608 | ||
1609 | if (!np) { | |
1610 | dev_err(&pdev->dev, "Missing DT data\n"); | |
1611 | return NULL; | |
1612 | } | |
1613 | ||
1614 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1615 | if (!pdata) | |
1616 | return NULL; | |
1617 | ||
f9c6a655 | 1618 | if (of_property_read_u32(np, "dma-channels", &pdata->nr_channels)) |
a9ddb575 VK |
1619 | return NULL; |
1620 | ||
1621 | if (of_property_read_bool(np, "is_private")) | |
1622 | pdata->is_private = true; | |
1623 | ||
1624 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) | |
1625 | pdata->chan_allocation_order = (unsigned char)tmp; | |
1626 | ||
1627 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
1628 | pdata->chan_priority = tmp; | |
1629 | ||
1630 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
1631 | pdata->block_size = tmp; | |
1632 | ||
f9c6a655 | 1633 | if (!of_property_read_u32(np, "dma-masters", &tmp)) { |
a9ddb575 VK |
1634 | if (tmp > 4) |
1635 | return NULL; | |
1636 | ||
1637 | pdata->nr_masters = tmp; | |
1638 | } | |
1639 | ||
1640 | if (!of_property_read_u32_array(np, "data_width", arr, | |
1641 | pdata->nr_masters)) | |
1642 | for (tmp = 0; tmp < pdata->nr_masters; tmp++) | |
1643 | pdata->data_width[tmp] = arr[tmp]; | |
1644 | ||
a9ddb575 VK |
1645 | return pdata; |
1646 | } | |
1647 | #else | |
1648 | static inline struct dw_dma_platform_data * | |
1649 | dw_dma_parse_dt(struct platform_device *pdev) | |
1650 | { | |
1651 | return NULL; | |
1652 | } | |
1653 | #endif | |
1654 | ||
463a1f8b | 1655 | static int dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1656 | { |
1657 | struct dw_dma_platform_data *pdata; | |
1658 | struct resource *io; | |
1659 | struct dw_dma *dw; | |
1660 | size_t size; | |
482c67ea AS |
1661 | void __iomem *regs; |
1662 | bool autocfg; | |
1663 | unsigned int dw_params; | |
1664 | unsigned int nr_channels; | |
4a63a8b3 | 1665 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1666 | int irq; |
1667 | int err; | |
1668 | int i; | |
1669 | ||
3bfb1d20 HS |
1670 | irq = platform_get_irq(pdev, 0); |
1671 | if (irq < 0) | |
1672 | return irq; | |
1673 | ||
0b95961e | 1674 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1675 | regs = devm_ioremap_resource(&pdev->dev, io); |
1676 | if (IS_ERR(regs)) | |
1677 | return PTR_ERR(regs); | |
482c67ea | 1678 | |
877e86f2 AS |
1679 | /* Apply default dma_mask if needed */ |
1680 | if (!pdev->dev.dma_mask) { | |
1681 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
1682 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
1683 | } | |
1684 | ||
482c67ea AS |
1685 | dw_params = dma_read_byaddr(regs, DW_PARAMS); |
1686 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1687 | ||
985a6c7d AS |
1688 | dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
1689 | ||
123de543 AS |
1690 | pdata = dev_get_platdata(&pdev->dev); |
1691 | if (!pdata) | |
1692 | pdata = dw_dma_parse_dt(pdev); | |
1693 | ||
1694 | if (!pdata && autocfg) { | |
1695 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1696 | if (!pdata) | |
1697 | return -ENOMEM; | |
1698 | ||
1699 | /* Fill platform data with the default values */ | |
1700 | pdata->is_private = true; | |
1701 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1702 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1703 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1704 | return -EINVAL; | |
1705 | ||
482c67ea AS |
1706 | if (autocfg) |
1707 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1708 | else | |
1709 | nr_channels = pdata->nr_channels; | |
1710 | ||
1711 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1712 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1713 | if (!dw) |
1714 | return -ENOMEM; | |
1715 | ||
dbde5c29 AS |
1716 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1717 | if (IS_ERR(dw->clk)) | |
1718 | return PTR_ERR(dw->clk); | |
3075528d | 1719 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1720 | |
482c67ea AS |
1721 | dw->regs = regs; |
1722 | ||
75c61225 | 1723 | /* Get hardware configuration parameters */ |
a0982004 | 1724 | if (autocfg) { |
4a63a8b3 AS |
1725 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1726 | ||
a0982004 AS |
1727 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1728 | for (i = 0; i < dw->nr_masters; i++) { | |
1729 | dw->data_width[i] = | |
1730 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1731 | } | |
1732 | } else { | |
1733 | dw->nr_masters = pdata->nr_masters; | |
1734 | memcpy(dw->data_width, pdata->data_width, 4); | |
1735 | } | |
1736 | ||
11f932ec | 1737 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1738 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1739 | |
75c61225 | 1740 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1741 | dw_dma_off(dw); |
1742 | ||
75c61225 | 1743 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1744 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1745 | ||
dbde5c29 AS |
1746 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1747 | "dw_dmac", dw); | |
3bfb1d20 | 1748 | if (err) |
dbde5c29 | 1749 | return err; |
3bfb1d20 HS |
1750 | |
1751 | platform_set_drvdata(pdev, dw); | |
1752 | ||
75c61225 | 1753 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
f8122a82 AS |
1754 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev, |
1755 | sizeof(struct dw_desc), 4, 0); | |
1756 | if (!dw->desc_pool) { | |
1757 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1758 | return -ENOMEM; | |
1759 | } | |
1760 | ||
3bfb1d20 HS |
1761 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1762 | ||
3bfb1d20 | 1763 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1764 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1765 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1766 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1767 | |
1768 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1769 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1770 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1771 | list_add_tail(&dwc->chan.device_node, | |
1772 | &dw->dma.channels); | |
1773 | else | |
1774 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1775 | |
93317e8e VK |
1776 | /* 7 is highest priority & 0 is lowest. */ |
1777 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1778 | dwc->priority = r; |
93317e8e VK |
1779 | else |
1780 | dwc->priority = i; | |
1781 | ||
3bfb1d20 HS |
1782 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1783 | spin_lock_init(&dwc->lock); | |
1784 | dwc->mask = 1 << i; | |
1785 | ||
1786 | INIT_LIST_HEAD(&dwc->active_list); | |
1787 | INIT_LIST_HEAD(&dwc->queue); | |
1788 | INIT_LIST_HEAD(&dwc->free_list); | |
1789 | ||
1790 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1791 | |
0fdb567f | 1792 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1793 | dwc->request_line = ~0; |
a0982004 | 1794 | |
75c61225 | 1795 | /* Hardware configuration */ |
fed2574b AS |
1796 | if (autocfg) { |
1797 | unsigned int dwc_params; | |
1798 | ||
1799 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1800 | DWC_PARAMS); | |
1801 | ||
985a6c7d AS |
1802 | dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1803 | dwc_params); | |
1804 | ||
4a63a8b3 AS |
1805 | /* Decode maximum block size for given channel. The |
1806 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1807 | * up to 0x0a for 4095. */ | |
1808 | dwc->block_size = | |
1809 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1810 | dwc->nollp = |
1811 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1812 | } else { | |
4a63a8b3 | 1813 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1814 | |
1815 | /* Check if channel supports multi block transfer */ | |
1816 | channel_writel(dwc, LLP, 0xfffffffc); | |
1817 | dwc->nollp = | |
1818 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1819 | channel_writel(dwc, LLP, 0); | |
1820 | } | |
3bfb1d20 HS |
1821 | } |
1822 | ||
11f932ec | 1823 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1824 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1825 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1826 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1827 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1828 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1829 | ||
3bfb1d20 HS |
1830 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1831 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1832 | if (pdata->is_private) |
1833 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1834 | dw->dma.dev = &pdev->dev; |
1835 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1836 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1837 | ||
1838 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1839 | ||
1840 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1841 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1842 | |
07934481 | 1843 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1844 | dw->dma.device_issue_pending = dwc_issue_pending; |
1845 | ||
1846 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1847 | ||
21d43f49 AS |
1848 | dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", |
1849 | nr_channels); | |
3bfb1d20 HS |
1850 | |
1851 | dma_async_device_register(&dw->dma); | |
1852 | ||
f9c6a655 AB |
1853 | if (pdev->dev.of_node) { |
1854 | err = of_dma_controller_register(pdev->dev.of_node, | |
bd2e6b66 | 1855 | dw_dma_of_xlate, dw); |
f5b9b77e | 1856 | if (err) |
f9c6a655 AB |
1857 | dev_err(&pdev->dev, |
1858 | "could not register of_dma_controller\n"); | |
1859 | } | |
1860 | ||
42c91ee7 AS |
1861 | if (ACPI_HANDLE(&pdev->dev)) |
1862 | dw_dma_acpi_controller_register(dw); | |
1863 | ||
3bfb1d20 | 1864 | return 0; |
3bfb1d20 HS |
1865 | } |
1866 | ||
4bf27b8b | 1867 | static int dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1868 | { |
1869 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1870 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 | 1871 | |
f9c6a655 AB |
1872 | if (pdev->dev.of_node) |
1873 | of_dma_controller_free(pdev->dev.of_node); | |
3bfb1d20 HS |
1874 | dw_dma_off(dw); |
1875 | dma_async_device_unregister(&dw->dma); | |
1876 | ||
3bfb1d20 HS |
1877 | tasklet_kill(&dw->tasklet); |
1878 | ||
1879 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1880 | chan.device_node) { | |
1881 | list_del(&dwc->chan.device_node); | |
1882 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1883 | } | |
1884 | ||
3bfb1d20 HS |
1885 | return 0; |
1886 | } | |
1887 | ||
1888 | static void dw_shutdown(struct platform_device *pdev) | |
1889 | { | |
1890 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1891 | ||
6168d567 | 1892 | dw_dma_off(dw); |
3075528d | 1893 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1894 | } |
1895 | ||
4a256b5f | 1896 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1897 | { |
4a256b5f | 1898 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1899 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1900 | ||
6168d567 | 1901 | dw_dma_off(dw); |
3075528d | 1902 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1903 | |
3bfb1d20 HS |
1904 | return 0; |
1905 | } | |
1906 | ||
4a256b5f | 1907 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1908 | { |
4a256b5f | 1909 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1910 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1911 | ||
3075528d | 1912 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1913 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1914 | |
3bfb1d20 | 1915 | return 0; |
3bfb1d20 HS |
1916 | } |
1917 | ||
47145210 | 1918 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1919 | .suspend_noirq = dw_suspend_noirq, |
1920 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1921 | .freeze_noirq = dw_suspend_noirq, |
1922 | .thaw_noirq = dw_resume_noirq, | |
1923 | .restore_noirq = dw_resume_noirq, | |
1924 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1925 | }; |
1926 | ||
d3f797d9 | 1927 | #ifdef CONFIG_OF |
bd2e6b66 | 1928 | static const struct of_device_id dw_dma_of_id_table[] = { |
d3f797d9 VK |
1929 | { .compatible = "snps,dma-spear1340" }, |
1930 | {} | |
1931 | }; | |
bd2e6b66 | 1932 | MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); |
d3f797d9 VK |
1933 | #endif |
1934 | ||
42c91ee7 AS |
1935 | #ifdef CONFIG_ACPI |
1936 | static const struct acpi_device_id dw_dma_acpi_id_table[] = { | |
1937 | { "INTL9C60", 0 }, | |
cfdf5b6c MW |
1938 | { } |
1939 | }; | |
42c91ee7 | 1940 | #endif |
cfdf5b6c | 1941 | |
3bfb1d20 | 1942 | static struct platform_driver dw_driver = { |
01126856 | 1943 | .probe = dw_probe, |
a7d6e3ec | 1944 | .remove = dw_remove, |
3bfb1d20 | 1945 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1946 | .driver = { |
1947 | .name = "dw_dmac", | |
4a256b5f | 1948 | .pm = &dw_dev_pm_ops, |
bd2e6b66 | 1949 | .of_match_table = of_match_ptr(dw_dma_of_id_table), |
42c91ee7 | 1950 | .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table), |
3bfb1d20 HS |
1951 | }, |
1952 | }; | |
1953 | ||
1954 | static int __init dw_init(void) | |
1955 | { | |
01126856 | 1956 | return platform_driver_register(&dw_driver); |
3bfb1d20 | 1957 | } |
cb689a70 | 1958 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1959 | |
1960 | static void __exit dw_exit(void) | |
1961 | { | |
1962 | platform_driver_unregister(&dw_driver); | |
1963 | } | |
1964 | module_exit(dw_exit); | |
1965 | ||
1966 | MODULE_LICENSE("GPL v2"); | |
1967 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1968 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1969 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |