Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
b801479b | 11 | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
3bfb1d20 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
d3f797d9 | 21 | #include <linux/of.h> |
3bfb1d20 HS |
22 | #include <linux/mm.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | ||
27 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 28 | #include "dmaengine.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
36 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
37 | * which does not support descriptor writeback. | |
38 | */ | |
39 | ||
a0982004 AS |
40 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
41 | { | |
42 | return slave ? slave->dst_master : 0; | |
43 | } | |
44 | ||
45 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
46 | { | |
47 | return slave ? slave->src_master : 1; | |
48 | } | |
49 | ||
5be10f34 AS |
50 | #define SRC_MASTER 0 |
51 | #define DST_MASTER 1 | |
52 | ||
53 | static inline unsigned int dwc_get_master(struct dma_chan *chan, int master) | |
54 | { | |
55 | struct dw_dma *dw = to_dw_dma(chan->device); | |
56 | struct dw_dma_slave *dws = chan->private; | |
57 | unsigned int m; | |
58 | ||
59 | if (master == SRC_MASTER) | |
60 | m = dwc_get_sms(dws); | |
61 | else | |
62 | m = dwc_get_dms(dws); | |
63 | ||
64 | return min_t(unsigned int, dw->nr_masters - 1, m); | |
65 | } | |
66 | ||
327e6970 | 67 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
68 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
69 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 70 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
5be10f34 AS |
71 | int _dms = dwc_get_master(_chan, DST_MASTER); \ |
72 | int _sms = dwc_get_master(_chan, SRC_MASTER); \ | |
495aea4b | 73 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 74 | DW_DMA_MSIZE_16; \ |
495aea4b | 75 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 76 | DW_DMA_MSIZE_16; \ |
f301c062 | 77 | \ |
327e6970 VK |
78 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
79 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
80 | | DWC_CTLL_LLP_D_EN \ |
81 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
82 | | DWC_CTLL_DMS(_dms) \ |
83 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 84 | }) |
3bfb1d20 | 85 | |
3bfb1d20 HS |
86 | /* |
87 | * Number of descriptors to allocate for each channel. This should be | |
88 | * made configurable somehow; preferably, the clients (at least the | |
89 | * ones using slave transfers) should be able to give us a hint. | |
90 | */ | |
91 | #define NR_DESCS_PER_CHANNEL 64 | |
92 | ||
23d5f4ec AS |
93 | static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master) |
94 | { | |
95 | struct dw_dma *dw = to_dw_dma(chan->device); | |
23d5f4ec | 96 | |
5be10f34 | 97 | return dw->data_width[dwc_get_master(chan, master)]; |
23d5f4ec AS |
98 | } |
99 | ||
3bfb1d20 HS |
100 | /*----------------------------------------------------------------------*/ |
101 | ||
41d5e59c DW |
102 | static struct device *chan2dev(struct dma_chan *chan) |
103 | { | |
104 | return &chan->dev->device; | |
105 | } | |
106 | static struct device *chan2parent(struct dma_chan *chan) | |
107 | { | |
108 | return chan->dev->device.parent; | |
109 | } | |
110 | ||
3bfb1d20 HS |
111 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
112 | { | |
e63a47a3 | 113 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
114 | } |
115 | ||
3bfb1d20 HS |
116 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
117 | { | |
118 | struct dw_desc *desc, *_desc; | |
119 | struct dw_desc *ret = NULL; | |
120 | unsigned int i = 0; | |
69cea5a0 | 121 | unsigned long flags; |
3bfb1d20 | 122 | |
69cea5a0 | 123 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 124 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 125 | i++; |
3bfb1d20 HS |
126 | if (async_tx_test_ack(&desc->txd)) { |
127 | list_del(&desc->desc_node); | |
128 | ret = desc; | |
129 | break; | |
130 | } | |
41d5e59c | 131 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 132 | } |
69cea5a0 | 133 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 134 | |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
136 | |
137 | return ret; | |
138 | } | |
139 | ||
3bfb1d20 HS |
140 | /* |
141 | * Move a descriptor, including any children, to the free list. | |
142 | * `desc' must not be on any lists. | |
143 | */ | |
144 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
145 | { | |
69cea5a0 VK |
146 | unsigned long flags; |
147 | ||
3bfb1d20 HS |
148 | if (desc) { |
149 | struct dw_desc *child; | |
150 | ||
69cea5a0 | 151 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 152 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 153 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
154 | "moving child desc %p to freelist\n", |
155 | child); | |
e0bd0f8c | 156 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 157 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 158 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 159 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
160 | } |
161 | } | |
162 | ||
61e183f8 VK |
163 | static void dwc_initialize(struct dw_dma_chan *dwc) |
164 | { | |
165 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
166 | struct dw_dma_slave *dws = dwc->chan.private; | |
167 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
168 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
169 | ||
170 | if (dwc->initialized == true) | |
171 | return; | |
172 | ||
173 | if (dws) { | |
174 | /* | |
175 | * We need controller-specific data to set up slave | |
176 | * transfers. | |
177 | */ | |
178 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
179 | ||
180 | cfghi = dws->cfg_hi; | |
181 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 182 | } else { |
0fdb567f | 183 | if (dwc->direction == DMA_MEM_TO_DEV) |
8fccc5bf | 184 | cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); |
0fdb567f | 185 | else if (dwc->direction == DMA_DEV_TO_MEM) |
8fccc5bf | 186 | cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); |
61e183f8 VK |
187 | } |
188 | ||
189 | channel_writel(dwc, CFG_LO, cfglo); | |
190 | channel_writel(dwc, CFG_HI, cfghi); | |
191 | ||
192 | /* Enable interrupts */ | |
193 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
194 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
195 | ||
196 | dwc->initialized = true; | |
197 | } | |
198 | ||
3bfb1d20 HS |
199 | /*----------------------------------------------------------------------*/ |
200 | ||
4c2d56c5 AS |
201 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
202 | { | |
203 | /* | |
204 | * We can be a lot more clever here, but this should take care | |
205 | * of the most common optimization. | |
206 | */ | |
207 | if (!(v & 7)) | |
208 | return 3; | |
209 | else if (!(v & 3)) | |
210 | return 2; | |
211 | else if (!(v & 1)) | |
212 | return 1; | |
213 | return 0; | |
214 | } | |
215 | ||
f52b36d2 | 216 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
217 | { |
218 | dev_err(chan2dev(&dwc->chan), | |
219 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
220 | channel_readl(dwc, SAR), | |
221 | channel_readl(dwc, DAR), | |
222 | channel_readl(dwc, LLP), | |
223 | channel_readl(dwc, CTL_HI), | |
224 | channel_readl(dwc, CTL_LO)); | |
225 | } | |
226 | ||
3f936207 AS |
227 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
228 | { | |
229 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
230 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
231 | cpu_relax(); | |
232 | } | |
233 | ||
1d455437 AS |
234 | /*----------------------------------------------------------------------*/ |
235 | ||
fed2574b AS |
236 | /* Perform single block transfer */ |
237 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
238 | struct dw_desc *desc) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
241 | u32 ctllo; | |
242 | ||
243 | /* Software emulation of LLP mode relies on interrupts to continue | |
244 | * multi block transfer. */ | |
245 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
246 | ||
247 | channel_writel(dwc, SAR, desc->lli.sar); | |
248 | channel_writel(dwc, DAR, desc->lli.dar); | |
249 | channel_writel(dwc, CTL_LO, ctllo); | |
250 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
251 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
252 | |
253 | /* Move pointer to next descriptor */ | |
254 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
255 | } |
256 | ||
3bfb1d20 HS |
257 | /* Called with dwc->lock held and bh disabled */ |
258 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
259 | { | |
260 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 261 | unsigned long was_soft_llp; |
3bfb1d20 HS |
262 | |
263 | /* ASSERT: channel is idle */ | |
264 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 265 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 266 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 267 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
268 | |
269 | /* The tasklet will hopefully advance the queue... */ | |
270 | return; | |
271 | } | |
272 | ||
fed2574b AS |
273 | if (dwc->nollp) { |
274 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
275 | &dwc->flags); | |
276 | if (was_soft_llp) { | |
277 | dev_err(chan2dev(&dwc->chan), | |
278 | "BUG: Attempted to start new LLP transfer " | |
279 | "inside ongoing one\n"); | |
280 | return; | |
281 | } | |
282 | ||
283 | dwc_initialize(dwc); | |
284 | ||
f5c6a7df | 285 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 286 | |
fdf475fa | 287 | /* Submit first block */ |
fed2574b AS |
288 | dwc_do_single_block(dwc, first); |
289 | ||
290 | return; | |
291 | } | |
292 | ||
61e183f8 VK |
293 | dwc_initialize(dwc); |
294 | ||
3bfb1d20 HS |
295 | channel_writel(dwc, LLP, first->txd.phys); |
296 | channel_writel(dwc, CTL_LO, | |
297 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
298 | channel_writel(dwc, CTL_HI, 0); | |
299 | channel_set_bit(dw, CH_EN, dwc->mask); | |
300 | } | |
301 | ||
302 | /*----------------------------------------------------------------------*/ | |
303 | ||
304 | static void | |
5fedefb8 VK |
305 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
306 | bool callback_required) | |
3bfb1d20 | 307 | { |
5fedefb8 VK |
308 | dma_async_tx_callback callback = NULL; |
309 | void *param = NULL; | |
3bfb1d20 | 310 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 311 | struct dw_desc *child; |
69cea5a0 | 312 | unsigned long flags; |
3bfb1d20 | 313 | |
41d5e59c | 314 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 315 | |
69cea5a0 | 316 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 317 | dma_cookie_complete(txd); |
5fedefb8 VK |
318 | if (callback_required) { |
319 | callback = txd->callback; | |
320 | param = txd->callback_param; | |
321 | } | |
3bfb1d20 | 322 | |
e518076e VK |
323 | /* async_tx_ack */ |
324 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
325 | async_tx_ack(&child->txd); | |
326 | async_tx_ack(&desc->txd); | |
327 | ||
e0bd0f8c | 328 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
329 | list_move(&desc->desc_node, &dwc->free_list); |
330 | ||
495aea4b | 331 | if (!is_slave_direction(dwc->direction)) { |
657a77fa AN |
332 | struct device *parent = chan2parent(&dwc->chan); |
333 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
334 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
335 | dma_unmap_single(parent, desc->lli.dar, | |
30d38a32 | 336 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
337 | else |
338 | dma_unmap_page(parent, desc->lli.dar, | |
30d38a32 | 339 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
340 | } |
341 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
342 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
343 | dma_unmap_single(parent, desc->lli.sar, | |
30d38a32 | 344 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
345 | else |
346 | dma_unmap_page(parent, desc->lli.sar, | |
30d38a32 | 347 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
348 | } |
349 | } | |
3bfb1d20 | 350 | |
69cea5a0 VK |
351 | spin_unlock_irqrestore(&dwc->lock, flags); |
352 | ||
21e93c1e | 353 | if (callback) |
3bfb1d20 HS |
354 | callback(param); |
355 | } | |
356 | ||
357 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
358 | { | |
359 | struct dw_desc *desc, *_desc; | |
360 | LIST_HEAD(list); | |
69cea5a0 | 361 | unsigned long flags; |
3bfb1d20 | 362 | |
69cea5a0 | 363 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 364 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 365 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
366 | "BUG: XFER bit set, but channel not idle!\n"); |
367 | ||
368 | /* Try to continue after resetting the channel... */ | |
3f936207 | 369 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
370 | } |
371 | ||
372 | /* | |
373 | * Submit queued descriptors ASAP, i.e. before we go through | |
374 | * the completed ones. | |
375 | */ | |
3bfb1d20 | 376 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
377 | if (!list_empty(&dwc->queue)) { |
378 | list_move(dwc->queue.next, &dwc->active_list); | |
379 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
380 | } | |
3bfb1d20 | 381 | |
69cea5a0 VK |
382 | spin_unlock_irqrestore(&dwc->lock, flags); |
383 | ||
3bfb1d20 | 384 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 385 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
386 | } |
387 | ||
388 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
389 | { | |
390 | dma_addr_t llp; | |
391 | struct dw_desc *desc, *_desc; | |
392 | struct dw_desc *child; | |
393 | u32 status_xfer; | |
69cea5a0 | 394 | unsigned long flags; |
3bfb1d20 | 395 | |
69cea5a0 | 396 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
397 | llp = channel_readl(dwc, LLP); |
398 | status_xfer = dma_readl(dw, RAW.XFER); | |
399 | ||
400 | if (status_xfer & dwc->mask) { | |
401 | /* Everything we've submitted is done */ | |
402 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
403 | |
404 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
405 | struct list_head *head, *active = dwc->tx_node_active; |
406 | ||
407 | /* | |
408 | * We are inside first active descriptor. | |
409 | * Otherwise something is really wrong. | |
410 | */ | |
411 | desc = dwc_first_active(dwc); | |
412 | ||
413 | head = &desc->tx_list; | |
414 | if (active != head) { | |
415 | child = to_dw_desc(active); | |
77bcc497 AS |
416 | |
417 | /* Submit next block */ | |
fdf475fa | 418 | dwc_do_single_block(dwc, child); |
77bcc497 | 419 | |
fdf475fa | 420 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
421 | return; |
422 | } | |
fdf475fa | 423 | |
77bcc497 AS |
424 | /* We are done here */ |
425 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
426 | } | |
69cea5a0 VK |
427 | spin_unlock_irqrestore(&dwc->lock, flags); |
428 | ||
3bfb1d20 HS |
429 | dwc_complete_all(dw, dwc); |
430 | return; | |
431 | } | |
432 | ||
69cea5a0 VK |
433 | if (list_empty(&dwc->active_list)) { |
434 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 435 | return; |
69cea5a0 | 436 | } |
087809fc | 437 | |
77bcc497 AS |
438 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
439 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
440 | spin_unlock_irqrestore(&dwc->lock, flags); | |
441 | return; | |
442 | } | |
443 | ||
2e4c364e | 444 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 445 | (unsigned long long)llp); |
3bfb1d20 HS |
446 | |
447 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb | 448 | /* check first descriptors addr */ |
69cea5a0 VK |
449 | if (desc->txd.phys == llp) { |
450 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 451 | return; |
69cea5a0 | 452 | } |
84adccfb VK |
453 | |
454 | /* check first descriptors llp */ | |
69cea5a0 | 455 | if (desc->lli.llp == llp) { |
3bfb1d20 | 456 | /* This one is currently in progress */ |
69cea5a0 | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 458 | return; |
69cea5a0 | 459 | } |
3bfb1d20 | 460 | |
e0bd0f8c | 461 | list_for_each_entry(child, &desc->tx_list, desc_node) |
69cea5a0 | 462 | if (child->lli.llp == llp) { |
3bfb1d20 | 463 | /* Currently in progress */ |
69cea5a0 | 464 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 465 | return; |
69cea5a0 | 466 | } |
3bfb1d20 HS |
467 | |
468 | /* | |
469 | * No descriptors so far seem to be in progress, i.e. | |
470 | * this one must be done. | |
471 | */ | |
69cea5a0 | 472 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 473 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 474 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
475 | } |
476 | ||
41d5e59c | 477 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
478 | "BUG: All descriptors done, but channel not idle!\n"); |
479 | ||
480 | /* Try to continue after resetting the channel... */ | |
3f936207 | 481 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
482 | |
483 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
484 | list_move(dwc->queue.next, &dwc->active_list); |
485 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 486 | } |
69cea5a0 | 487 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
488 | } |
489 | ||
93aad1bc | 490 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 491 | { |
21d43f49 AS |
492 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
493 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
494 | } |
495 | ||
496 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
497 | { | |
498 | struct dw_desc *bad_desc; | |
499 | struct dw_desc *child; | |
69cea5a0 | 500 | unsigned long flags; |
3bfb1d20 HS |
501 | |
502 | dwc_scan_descriptors(dw, dwc); | |
503 | ||
69cea5a0 VK |
504 | spin_lock_irqsave(&dwc->lock, flags); |
505 | ||
3bfb1d20 HS |
506 | /* |
507 | * The descriptor currently at the head of the active list is | |
508 | * borked. Since we don't have any way to report errors, we'll | |
509 | * just have to scream loudly and try to carry on. | |
510 | */ | |
511 | bad_desc = dwc_first_active(dwc); | |
512 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 513 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
514 | |
515 | /* Clear the error flag and try to restart the controller */ | |
516 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
517 | if (!list_empty(&dwc->active_list)) | |
518 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
519 | ||
520 | /* | |
ba84bd71 | 521 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
522 | * when someone submits a bad physical address in a |
523 | * descriptor, we should consider ourselves lucky that the | |
524 | * controller flagged an error instead of scribbling over | |
525 | * random memory locations. | |
526 | */ | |
ba84bd71 AS |
527 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
528 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 529 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 530 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
531 | dwc_dump_lli(dwc, &child->lli); |
532 | ||
69cea5a0 VK |
533 | spin_unlock_irqrestore(&dwc->lock, flags); |
534 | ||
3bfb1d20 | 535 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 536 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
537 | } |
538 | ||
d9de4519 HCE |
539 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
540 | ||
541 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
542 | { | |
543 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
544 | return channel_readl(dwc, SAR); | |
545 | } | |
546 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
547 | ||
548 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
549 | { | |
550 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
551 | return channel_readl(dwc, DAR); | |
552 | } | |
553 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
554 | ||
555 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
556 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 557 | u32 status_err, u32 status_xfer) |
d9de4519 | 558 | { |
69cea5a0 VK |
559 | unsigned long flags; |
560 | ||
ff7b05f2 | 561 | if (dwc->mask) { |
d9de4519 HCE |
562 | void (*callback)(void *param); |
563 | void *callback_param; | |
564 | ||
565 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
566 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
567 | |
568 | callback = dwc->cdesc->period_callback; | |
569 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
570 | |
571 | if (callback) | |
d9de4519 | 572 | callback(callback_param); |
d9de4519 HCE |
573 | } |
574 | ||
575 | /* | |
576 | * Error and transfer complete are highly unlikely, and will most | |
577 | * likely be due to a configuration error by the user. | |
578 | */ | |
579 | if (unlikely(status_err & dwc->mask) || | |
580 | unlikely(status_xfer & dwc->mask)) { | |
581 | int i; | |
582 | ||
583 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
584 | "interrupt, stopping DMA transfer\n", | |
585 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
586 | |
587 | spin_lock_irqsave(&dwc->lock, flags); | |
588 | ||
1d455437 | 589 | dwc_dump_chan_regs(dwc); |
d9de4519 | 590 | |
3f936207 | 591 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
592 | |
593 | /* make sure DMA does not restart by loading a new list */ | |
594 | channel_writel(dwc, LLP, 0); | |
595 | channel_writel(dwc, CTL_LO, 0); | |
596 | channel_writel(dwc, CTL_HI, 0); | |
597 | ||
d9de4519 HCE |
598 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
599 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
600 | ||
601 | for (i = 0; i < dwc->cdesc->periods; i++) | |
602 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
603 | |
604 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
605 | } |
606 | } | |
607 | ||
608 | /* ------------------------------------------------------------------------- */ | |
609 | ||
3bfb1d20 HS |
610 | static void dw_dma_tasklet(unsigned long data) |
611 | { | |
612 | struct dw_dma *dw = (struct dw_dma *)data; | |
613 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
614 | u32 status_xfer; |
615 | u32 status_err; | |
616 | int i; | |
617 | ||
7fe7b2f4 | 618 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
619 | status_err = dma_readl(dw, RAW.ERROR); |
620 | ||
2e4c364e | 621 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
622 | |
623 | for (i = 0; i < dw->dma.chancnt; i++) { | |
624 | dwc = &dw->chan[i]; | |
d9de4519 | 625 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 626 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 627 | else if (status_err & (1 << i)) |
3bfb1d20 | 628 | dwc_handle_error(dw, dwc); |
77bcc497 | 629 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 630 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
631 | } |
632 | ||
633 | /* | |
ff7b05f2 | 634 | * Re-enable interrupts. |
3bfb1d20 HS |
635 | */ |
636 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
637 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
638 | } | |
639 | ||
640 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
641 | { | |
642 | struct dw_dma *dw = dev_id; | |
643 | u32 status; | |
644 | ||
2e4c364e | 645 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
646 | dma_readl(dw, STATUS_INT)); |
647 | ||
648 | /* | |
649 | * Just disable the interrupts. We'll turn them back on in the | |
650 | * softirq handler. | |
651 | */ | |
652 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
653 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
654 | ||
655 | status = dma_readl(dw, STATUS_INT); | |
656 | if (status) { | |
657 | dev_err(dw->dma.dev, | |
658 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
659 | status); | |
660 | ||
661 | /* Try to recover */ | |
662 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
663 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
664 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
665 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
666 | } | |
667 | ||
668 | tasklet_schedule(&dw->tasklet); | |
669 | ||
670 | return IRQ_HANDLED; | |
671 | } | |
672 | ||
673 | /*----------------------------------------------------------------------*/ | |
674 | ||
675 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
676 | { | |
677 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
678 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
679 | dma_cookie_t cookie; | |
69cea5a0 | 680 | unsigned long flags; |
3bfb1d20 | 681 | |
69cea5a0 | 682 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 683 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
684 | |
685 | /* | |
686 | * REVISIT: We should attempt to chain as many descriptors as | |
687 | * possible, perhaps even appending to those already submitted | |
688 | * for DMA. But this is hard to do in a race-free manner. | |
689 | */ | |
690 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 691 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 692 | desc->txd.cookie); |
3bfb1d20 | 693 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 694 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 695 | } else { |
2e4c364e | 696 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
697 | desc->txd.cookie); |
698 | ||
699 | list_add_tail(&desc->desc_node, &dwc->queue); | |
700 | } | |
701 | ||
69cea5a0 | 702 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
703 | |
704 | return cookie; | |
705 | } | |
706 | ||
707 | static struct dma_async_tx_descriptor * | |
708 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
709 | size_t len, unsigned long flags) | |
710 | { | |
711 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
712 | struct dw_desc *desc; | |
713 | struct dw_desc *first; | |
714 | struct dw_desc *prev; | |
715 | size_t xfer_count; | |
716 | size_t offset; | |
717 | unsigned int src_width; | |
718 | unsigned int dst_width; | |
3d4f8605 | 719 | unsigned int data_width; |
3bfb1d20 HS |
720 | u32 ctllo; |
721 | ||
2f45d613 | 722 | dev_vdbg(chan2dev(chan), |
2e4c364e | 723 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
724 | (unsigned long long)dest, (unsigned long long)src, |
725 | len, flags); | |
3bfb1d20 HS |
726 | |
727 | if (unlikely(!len)) { | |
2e4c364e | 728 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
729 | return NULL; |
730 | } | |
731 | ||
0fdb567f AS |
732 | dwc->direction = DMA_MEM_TO_MEM; |
733 | ||
23d5f4ec AS |
734 | data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER), |
735 | dwc_get_data_width(chan, DST_MASTER)); | |
a0982004 | 736 | |
3d4f8605 AS |
737 | src_width = dst_width = min_t(unsigned int, data_width, |
738 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 739 | |
327e6970 | 740 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
741 | | DWC_CTLL_DST_WIDTH(dst_width) |
742 | | DWC_CTLL_SRC_WIDTH(src_width) | |
743 | | DWC_CTLL_DST_INC | |
744 | | DWC_CTLL_SRC_INC | |
745 | | DWC_CTLL_FC_M2M; | |
746 | prev = first = NULL; | |
747 | ||
748 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
749 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 750 | dwc->block_size); |
3bfb1d20 HS |
751 | |
752 | desc = dwc_desc_get(dwc); | |
753 | if (!desc) | |
754 | goto err_desc_get; | |
755 | ||
756 | desc->lli.sar = src + offset; | |
757 | desc->lli.dar = dest + offset; | |
758 | desc->lli.ctllo = ctllo; | |
759 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 760 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
761 | |
762 | if (!first) { | |
763 | first = desc; | |
764 | } else { | |
765 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 766 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 767 | &first->tx_list); |
3bfb1d20 HS |
768 | } |
769 | prev = desc; | |
770 | } | |
771 | ||
3bfb1d20 HS |
772 | if (flags & DMA_PREP_INTERRUPT) |
773 | /* Trigger interrupt after last block */ | |
774 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
775 | ||
776 | prev->lli.llp = 0; | |
3bfb1d20 | 777 | first->txd.flags = flags; |
30d38a32 | 778 | first->total_len = len; |
3bfb1d20 HS |
779 | |
780 | return &first->txd; | |
781 | ||
782 | err_desc_get: | |
783 | dwc_desc_put(dwc, first); | |
784 | return NULL; | |
785 | } | |
786 | ||
787 | static struct dma_async_tx_descriptor * | |
788 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 789 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 790 | unsigned long flags, void *context) |
3bfb1d20 HS |
791 | { |
792 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 793 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
794 | struct dw_desc *prev; |
795 | struct dw_desc *first; | |
796 | u32 ctllo; | |
797 | dma_addr_t reg; | |
798 | unsigned int reg_width; | |
799 | unsigned int mem_width; | |
a0982004 | 800 | unsigned int data_width; |
3bfb1d20 HS |
801 | unsigned int i; |
802 | struct scatterlist *sg; | |
803 | size_t total_len = 0; | |
804 | ||
2e4c364e | 805 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 806 | |
495aea4b | 807 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
808 | return NULL; |
809 | ||
0fdb567f AS |
810 | dwc->direction = direction; |
811 | ||
3bfb1d20 HS |
812 | prev = first = NULL; |
813 | ||
3bfb1d20 | 814 | switch (direction) { |
db8196df | 815 | case DMA_MEM_TO_DEV: |
327e6970 VK |
816 | reg_width = __fls(sconfig->dst_addr_width); |
817 | reg = sconfig->dst_addr; | |
818 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
819 | | DWC_CTLL_DST_WIDTH(reg_width) |
820 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
821 | | DWC_CTLL_SRC_INC); |
822 | ||
823 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
824 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
825 | ||
23d5f4ec | 826 | data_width = dwc_get_data_width(chan, SRC_MASTER); |
a0982004 | 827 | |
3bfb1d20 HS |
828 | for_each_sg(sgl, sg, sg_len, i) { |
829 | struct dw_desc *desc; | |
69dc14b5 | 830 | u32 len, dlen, mem; |
3bfb1d20 | 831 | |
cbb796cc | 832 | mem = sg_dma_address(sg); |
69dc14b5 | 833 | len = sg_dma_len(sg); |
6bc711f6 | 834 | |
a0982004 AS |
835 | mem_width = min_t(unsigned int, |
836 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 837 | |
69dc14b5 | 838 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
839 | desc = dwc_desc_get(dwc); |
840 | if (!desc) { | |
41d5e59c | 841 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
842 | "not enough descriptors available\n"); |
843 | goto err_desc_get; | |
844 | } | |
845 | ||
3bfb1d20 HS |
846 | desc->lli.sar = mem; |
847 | desc->lli.dar = reg; | |
848 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
849 | if ((len >> mem_width) > dwc->block_size) { |
850 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
851 | mem += dlen; |
852 | len -= dlen; | |
853 | } else { | |
854 | dlen = len; | |
855 | len = 0; | |
856 | } | |
857 | ||
858 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 859 | desc->len = dlen; |
3bfb1d20 HS |
860 | |
861 | if (!first) { | |
862 | first = desc; | |
863 | } else { | |
864 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 865 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 866 | &first->tx_list); |
3bfb1d20 HS |
867 | } |
868 | prev = desc; | |
69dc14b5 VK |
869 | total_len += dlen; |
870 | ||
871 | if (len) | |
872 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
873 | } |
874 | break; | |
db8196df | 875 | case DMA_DEV_TO_MEM: |
327e6970 VK |
876 | reg_width = __fls(sconfig->src_addr_width); |
877 | reg = sconfig->src_addr; | |
878 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
879 | | DWC_CTLL_SRC_WIDTH(reg_width) |
880 | | DWC_CTLL_DST_INC | |
327e6970 VK |
881 | | DWC_CTLL_SRC_FIX); |
882 | ||
883 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
884 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 885 | |
23d5f4ec | 886 | data_width = dwc_get_data_width(chan, DST_MASTER); |
a0982004 | 887 | |
3bfb1d20 HS |
888 | for_each_sg(sgl, sg, sg_len, i) { |
889 | struct dw_desc *desc; | |
69dc14b5 | 890 | u32 len, dlen, mem; |
3bfb1d20 | 891 | |
cbb796cc | 892 | mem = sg_dma_address(sg); |
3bfb1d20 | 893 | len = sg_dma_len(sg); |
6bc711f6 | 894 | |
a0982004 AS |
895 | mem_width = min_t(unsigned int, |
896 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 897 | |
69dc14b5 VK |
898 | slave_sg_fromdev_fill_desc: |
899 | desc = dwc_desc_get(dwc); | |
900 | if (!desc) { | |
901 | dev_err(chan2dev(chan), | |
902 | "not enough descriptors available\n"); | |
903 | goto err_desc_get; | |
904 | } | |
905 | ||
3bfb1d20 HS |
906 | desc->lli.sar = reg; |
907 | desc->lli.dar = mem; | |
908 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
909 | if ((len >> reg_width) > dwc->block_size) { |
910 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
911 | mem += dlen; |
912 | len -= dlen; | |
913 | } else { | |
914 | dlen = len; | |
915 | len = 0; | |
916 | } | |
917 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 918 | desc->len = dlen; |
3bfb1d20 HS |
919 | |
920 | if (!first) { | |
921 | first = desc; | |
922 | } else { | |
923 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 924 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 925 | &first->tx_list); |
3bfb1d20 HS |
926 | } |
927 | prev = desc; | |
69dc14b5 VK |
928 | total_len += dlen; |
929 | ||
930 | if (len) | |
931 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
932 | } |
933 | break; | |
934 | default: | |
935 | return NULL; | |
936 | } | |
937 | ||
938 | if (flags & DMA_PREP_INTERRUPT) | |
939 | /* Trigger interrupt after last block */ | |
940 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
941 | ||
942 | prev->lli.llp = 0; | |
30d38a32 | 943 | first->total_len = total_len; |
3bfb1d20 HS |
944 | |
945 | return &first->txd; | |
946 | ||
947 | err_desc_get: | |
948 | dwc_desc_put(dwc, first); | |
949 | return NULL; | |
950 | } | |
951 | ||
327e6970 VK |
952 | /* |
953 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
954 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
955 | * | |
956 | * NOTE: burst size 2 is not supported by controller. | |
957 | * | |
958 | * This can be done by finding least significant bit set: n & (n - 1) | |
959 | */ | |
960 | static inline void convert_burst(u32 *maxburst) | |
961 | { | |
962 | if (*maxburst > 1) | |
963 | *maxburst = fls(*maxburst) - 2; | |
964 | else | |
965 | *maxburst = 0; | |
966 | } | |
967 | ||
968 | static int | |
969 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
970 | { | |
971 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
972 | ||
495aea4b AS |
973 | /* Check if chan will be configured for slave transfers */ |
974 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
975 | return -EINVAL; |
976 | ||
977 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 978 | dwc->direction = sconfig->direction; |
327e6970 VK |
979 | |
980 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
981 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
21fe3c52 AS |
986 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
987 | { | |
988 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
989 | ||
990 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
991 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
992 | cpu_relax(); | |
993 | ||
994 | dwc->paused = true; | |
995 | } | |
996 | ||
997 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
998 | { | |
999 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1000 | ||
1001 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1002 | ||
1003 | dwc->paused = false; | |
1004 | } | |
1005 | ||
05827630 LW |
1006 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1007 | unsigned long arg) | |
3bfb1d20 HS |
1008 | { |
1009 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1010 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1011 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1012 | unsigned long flags; |
3bfb1d20 HS |
1013 | LIST_HEAD(list); |
1014 | ||
a7c57cf7 LW |
1015 | if (cmd == DMA_PAUSE) { |
1016 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1017 | |
21fe3c52 | 1018 | dwc_chan_pause(dwc); |
3bfb1d20 | 1019 | |
a7c57cf7 LW |
1020 | spin_unlock_irqrestore(&dwc->lock, flags); |
1021 | } else if (cmd == DMA_RESUME) { | |
1022 | if (!dwc->paused) | |
1023 | return 0; | |
3bfb1d20 | 1024 | |
a7c57cf7 | 1025 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1026 | |
21fe3c52 | 1027 | dwc_chan_resume(dwc); |
3bfb1d20 | 1028 | |
a7c57cf7 LW |
1029 | spin_unlock_irqrestore(&dwc->lock, flags); |
1030 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1031 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1032 | |
fed2574b AS |
1033 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1034 | ||
3f936207 | 1035 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1036 | |
a5dbff11 | 1037 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1038 | |
1039 | /* active_list entries will end up before queued entries */ | |
1040 | list_splice_init(&dwc->queue, &list); | |
1041 | list_splice_init(&dwc->active_list, &list); | |
1042 | ||
1043 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1044 | ||
1045 | /* Flush all pending and queued descriptors */ | |
1046 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1047 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1048 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1049 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1050 | } else { | |
a7c57cf7 | 1051 | return -ENXIO; |
327e6970 | 1052 | } |
c3635c78 LW |
1053 | |
1054 | return 0; | |
3bfb1d20 HS |
1055 | } |
1056 | ||
1057 | static enum dma_status | |
07934481 LW |
1058 | dwc_tx_status(struct dma_chan *chan, |
1059 | dma_cookie_t cookie, | |
1060 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1061 | { |
1062 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1063 | enum dma_status ret; |
3bfb1d20 | 1064 | |
96a2af41 | 1065 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1066 | if (ret != DMA_SUCCESS) { |
1067 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1068 | ||
96a2af41 | 1069 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1070 | } |
1071 | ||
abf53902 | 1072 | if (ret != DMA_SUCCESS) |
96a2af41 | 1073 | dma_set_residue(txstate, dwc_first_active(dwc)->len); |
3bfb1d20 | 1074 | |
a7c57cf7 LW |
1075 | if (dwc->paused) |
1076 | return DMA_PAUSED; | |
3bfb1d20 HS |
1077 | |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | static void dwc_issue_pending(struct dma_chan *chan) | |
1082 | { | |
1083 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1084 | ||
3bfb1d20 HS |
1085 | if (!list_empty(&dwc->queue)) |
1086 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1087 | } |
1088 | ||
aa1e6f1a | 1089 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1090 | { |
1091 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1092 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1093 | struct dw_desc *desc; | |
3bfb1d20 | 1094 | int i; |
69cea5a0 | 1095 | unsigned long flags; |
3bfb1d20 | 1096 | |
2e4c364e | 1097 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1098 | |
3bfb1d20 HS |
1099 | /* ASSERT: channel is idle */ |
1100 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1101 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1102 | return -EIO; |
1103 | } | |
1104 | ||
d3ee98cd | 1105 | dma_cookie_init(chan); |
3bfb1d20 | 1106 | |
3bfb1d20 HS |
1107 | /* |
1108 | * NOTE: some controllers may have additional features that we | |
1109 | * need to initialize here, like "scatter-gather" (which | |
1110 | * doesn't mean what you think it means), and status writeback. | |
1111 | */ | |
1112 | ||
69cea5a0 | 1113 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1114 | i = dwc->descs_allocated; |
1115 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1116 | dma_addr_t phys; |
1117 | ||
69cea5a0 | 1118 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1119 | |
f8122a82 | 1120 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1121 | if (!desc) |
1122 | goto err_desc_alloc; | |
3bfb1d20 | 1123 | |
f8122a82 AS |
1124 | memset(desc, 0, sizeof(struct dw_desc)); |
1125 | ||
e0bd0f8c | 1126 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1127 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1128 | desc->txd.tx_submit = dwc_tx_submit; | |
1129 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1130 | desc->txd.phys = phys; |
cbd65312 | 1131 | |
3bfb1d20 HS |
1132 | dwc_desc_put(dwc, desc); |
1133 | ||
69cea5a0 | 1134 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1135 | i = ++dwc->descs_allocated; |
1136 | } | |
1137 | ||
69cea5a0 | 1138 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1139 | |
2e4c364e | 1140 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1141 | |
cbd65312 AS |
1142 | return i; |
1143 | ||
1144 | err_desc_alloc: | |
cbd65312 AS |
1145 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1146 | ||
3bfb1d20 HS |
1147 | return i; |
1148 | } | |
1149 | ||
1150 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1151 | { | |
1152 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1153 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1154 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1155 | unsigned long flags; |
3bfb1d20 HS |
1156 | LIST_HEAD(list); |
1157 | ||
2e4c364e | 1158 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1159 | dwc->descs_allocated); |
1160 | ||
1161 | /* ASSERT: channel is idle */ | |
1162 | BUG_ON(!list_empty(&dwc->active_list)); | |
1163 | BUG_ON(!list_empty(&dwc->queue)); | |
1164 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1165 | ||
69cea5a0 | 1166 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1167 | list_splice_init(&dwc->free_list, &list); |
1168 | dwc->descs_allocated = 0; | |
61e183f8 | 1169 | dwc->initialized = false; |
3bfb1d20 HS |
1170 | |
1171 | /* Disable interrupts */ | |
1172 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1173 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1174 | ||
69cea5a0 | 1175 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1176 | |
1177 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1178 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1179 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1180 | } |
1181 | ||
2e4c364e | 1182 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1183 | } |
1184 | ||
a9ddb575 VK |
1185 | bool dw_dma_generic_filter(struct dma_chan *chan, void *param) |
1186 | { | |
1187 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1188 | static struct dw_dma *last_dw; | |
1189 | static char *last_bus_id; | |
1190 | int i = -1; | |
1191 | ||
1192 | /* | |
1193 | * dmaengine framework calls this routine for all channels of all dma | |
1194 | * controller, until true is returned. If 'param' bus_id is not | |
1195 | * registered with a dma controller (dw), then there is no need of | |
1196 | * running below function for all channels of dw. | |
1197 | * | |
1198 | * This block of code does this by saving the parameters of last | |
1199 | * failure. If dw and param are same, i.e. trying on same dw with | |
1200 | * different channel, return false. | |
1201 | */ | |
1202 | if ((last_dw == dw) && (last_bus_id == param)) | |
1203 | return false; | |
1204 | /* | |
1205 | * Return true: | |
1206 | * - If dw_dma's platform data is not filled with slave info, then all | |
1207 | * dma controllers are fine for transfer. | |
1208 | * - Or if param is NULL | |
1209 | */ | |
1210 | if (!dw->sd || !param) | |
1211 | return true; | |
1212 | ||
1213 | while (++i < dw->sd_count) { | |
1214 | if (!strcmp(dw->sd[i].bus_id, param)) { | |
1215 | chan->private = &dw->sd[i]; | |
1216 | last_dw = NULL; | |
1217 | last_bus_id = NULL; | |
1218 | ||
1219 | return true; | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | last_dw = dw; | |
1224 | last_bus_id = param; | |
1225 | return false; | |
1226 | } | |
1227 | EXPORT_SYMBOL(dw_dma_generic_filter); | |
1228 | ||
d9de4519 HCE |
1229 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1230 | ||
1231 | /** | |
1232 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1233 | * @chan: the DMA channel to start | |
1234 | * | |
1235 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1236 | * -errno on failure. | |
1237 | */ | |
1238 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1239 | { | |
1240 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1241 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1242 | unsigned long flags; |
d9de4519 HCE |
1243 | |
1244 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1245 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1246 | return -ENODEV; | |
1247 | } | |
1248 | ||
69cea5a0 | 1249 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1250 | |
1251 | /* assert channel is idle */ | |
1252 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1253 | dev_err(chan2dev(&dwc->chan), | |
1254 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1255 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1256 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1257 | return -EBUSY; |
1258 | } | |
1259 | ||
d9de4519 HCE |
1260 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1261 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1262 | ||
1263 | /* setup DMAC channel registers */ | |
1264 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1265 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1266 | channel_writel(dwc, CTL_HI, 0); | |
1267 | ||
1268 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1269 | ||
69cea5a0 | 1270 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1271 | |
1272 | return 0; | |
1273 | } | |
1274 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1275 | ||
1276 | /** | |
1277 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1278 | * @chan: the DMA channel to stop | |
1279 | * | |
1280 | * Must be called with soft interrupts disabled. | |
1281 | */ | |
1282 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1283 | { | |
1284 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1285 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1286 | unsigned long flags; |
d9de4519 | 1287 | |
69cea5a0 | 1288 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1289 | |
3f936207 | 1290 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1291 | |
69cea5a0 | 1292 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1293 | } |
1294 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1295 | ||
1296 | /** | |
1297 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1298 | * @chan: the DMA channel to prepare | |
1299 | * @buf_addr: physical DMA address where the buffer starts | |
1300 | * @buf_len: total number of bytes for the entire buffer | |
1301 | * @period_len: number of bytes for each period | |
1302 | * @direction: transfer direction, to or from device | |
1303 | * | |
1304 | * Must be called before trying to start the transfer. Returns a valid struct | |
1305 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1306 | */ | |
1307 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1308 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1309 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1310 | { |
1311 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1312 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1313 | struct dw_cyclic_desc *cdesc; |
1314 | struct dw_cyclic_desc *retval = NULL; | |
1315 | struct dw_desc *desc; | |
1316 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1317 | unsigned long was_cyclic; |
1318 | unsigned int reg_width; | |
1319 | unsigned int periods; | |
1320 | unsigned int i; | |
69cea5a0 | 1321 | unsigned long flags; |
d9de4519 | 1322 | |
69cea5a0 | 1323 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1324 | if (dwc->nollp) { |
1325 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1326 | dev_dbg(chan2dev(&dwc->chan), | |
1327 | "channel doesn't support LLP transfers\n"); | |
1328 | return ERR_PTR(-EINVAL); | |
1329 | } | |
1330 | ||
d9de4519 | 1331 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1332 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1333 | dev_dbg(chan2dev(&dwc->chan), |
1334 | "queue and/or active list are not empty\n"); | |
1335 | return ERR_PTR(-EBUSY); | |
1336 | } | |
1337 | ||
1338 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1339 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1340 | if (was_cyclic) { |
1341 | dev_dbg(chan2dev(&dwc->chan), | |
1342 | "channel already prepared for cyclic DMA\n"); | |
1343 | return ERR_PTR(-EBUSY); | |
1344 | } | |
1345 | ||
1346 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1347 | |
f44b92f4 AS |
1348 | if (unlikely(!is_slave_direction(direction))) |
1349 | goto out_err; | |
1350 | ||
0fdb567f AS |
1351 | dwc->direction = direction; |
1352 | ||
327e6970 VK |
1353 | if (direction == DMA_MEM_TO_DEV) |
1354 | reg_width = __ffs(sconfig->dst_addr_width); | |
1355 | else | |
1356 | reg_width = __ffs(sconfig->src_addr_width); | |
1357 | ||
d9de4519 HCE |
1358 | periods = buf_len / period_len; |
1359 | ||
1360 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1361 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1362 | goto out_err; |
1363 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1364 | goto out_err; | |
1365 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1366 | goto out_err; | |
d9de4519 HCE |
1367 | |
1368 | retval = ERR_PTR(-ENOMEM); | |
1369 | ||
1370 | if (periods > NR_DESCS_PER_CHANNEL) | |
1371 | goto out_err; | |
1372 | ||
1373 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1374 | if (!cdesc) | |
1375 | goto out_err; | |
1376 | ||
1377 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1378 | if (!cdesc->desc) | |
1379 | goto out_err_alloc; | |
1380 | ||
1381 | for (i = 0; i < periods; i++) { | |
1382 | desc = dwc_desc_get(dwc); | |
1383 | if (!desc) | |
1384 | goto out_err_desc_get; | |
1385 | ||
1386 | switch (direction) { | |
db8196df | 1387 | case DMA_MEM_TO_DEV: |
327e6970 | 1388 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1389 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1390 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1391 | | DWC_CTLL_DST_WIDTH(reg_width) |
1392 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1393 | | DWC_CTLL_DST_FIX | |
1394 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1395 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1396 | |
1397 | desc->lli.ctllo |= sconfig->device_fc ? | |
1398 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1399 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1400 | ||
d9de4519 | 1401 | break; |
db8196df | 1402 | case DMA_DEV_TO_MEM: |
d9de4519 | 1403 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1404 | desc->lli.sar = sconfig->src_addr; |
1405 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1406 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1407 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1408 | | DWC_CTLL_DST_INC | |
1409 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1410 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1411 | |
1412 | desc->lli.ctllo |= sconfig->device_fc ? | |
1413 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1414 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1415 | ||
d9de4519 HCE |
1416 | break; |
1417 | default: | |
1418 | break; | |
1419 | } | |
1420 | ||
1421 | desc->lli.ctlhi = (period_len >> reg_width); | |
1422 | cdesc->desc[i] = desc; | |
1423 | ||
f8122a82 | 1424 | if (last) |
d9de4519 | 1425 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1426 | |
1427 | last = desc; | |
1428 | } | |
1429 | ||
1430 | /* lets make a cyclic list */ | |
1431 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
d9de4519 | 1432 | |
2f45d613 AS |
1433 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1434 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1435 | buf_len, period_len, periods); | |
d9de4519 HCE |
1436 | |
1437 | cdesc->periods = periods; | |
1438 | dwc->cdesc = cdesc; | |
1439 | ||
1440 | return cdesc; | |
1441 | ||
1442 | out_err_desc_get: | |
1443 | while (i--) | |
1444 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1445 | out_err_alloc: | |
1446 | kfree(cdesc); | |
1447 | out_err: | |
1448 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1449 | return (struct dw_cyclic_desc *)retval; | |
1450 | } | |
1451 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1452 | ||
1453 | /** | |
1454 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1455 | * @chan: the DMA channel to free | |
1456 | */ | |
1457 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1458 | { | |
1459 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1460 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1461 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1462 | int i; | |
69cea5a0 | 1463 | unsigned long flags; |
d9de4519 | 1464 | |
2e4c364e | 1465 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1466 | |
1467 | if (!cdesc) | |
1468 | return; | |
1469 | ||
69cea5a0 | 1470 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1471 | |
3f936207 | 1472 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1473 | |
d9de4519 HCE |
1474 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1475 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1476 | ||
69cea5a0 | 1477 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1478 | |
1479 | for (i = 0; i < cdesc->periods; i++) | |
1480 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1481 | ||
1482 | kfree(cdesc->desc); | |
1483 | kfree(cdesc); | |
1484 | ||
1485 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1486 | } | |
1487 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1488 | ||
3bfb1d20 HS |
1489 | /*----------------------------------------------------------------------*/ |
1490 | ||
1491 | static void dw_dma_off(struct dw_dma *dw) | |
1492 | { | |
61e183f8 VK |
1493 | int i; |
1494 | ||
3bfb1d20 HS |
1495 | dma_writel(dw, CFG, 0); |
1496 | ||
1497 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1498 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1499 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1500 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1501 | ||
1502 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1503 | cpu_relax(); | |
61e183f8 VK |
1504 | |
1505 | for (i = 0; i < dw->dma.chancnt; i++) | |
1506 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1507 | } |
1508 | ||
a9ddb575 VK |
1509 | #ifdef CONFIG_OF |
1510 | static struct dw_dma_platform_data * | |
1511 | dw_dma_parse_dt(struct platform_device *pdev) | |
1512 | { | |
1513 | struct device_node *sn, *cn, *np = pdev->dev.of_node; | |
1514 | struct dw_dma_platform_data *pdata; | |
1515 | struct dw_dma_slave *sd; | |
1516 | u32 tmp, arr[4]; | |
1517 | ||
1518 | if (!np) { | |
1519 | dev_err(&pdev->dev, "Missing DT data\n"); | |
1520 | return NULL; | |
1521 | } | |
1522 | ||
1523 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1524 | if (!pdata) | |
1525 | return NULL; | |
1526 | ||
1527 | if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels)) | |
1528 | return NULL; | |
1529 | ||
1530 | if (of_property_read_bool(np, "is_private")) | |
1531 | pdata->is_private = true; | |
1532 | ||
1533 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) | |
1534 | pdata->chan_allocation_order = (unsigned char)tmp; | |
1535 | ||
1536 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
1537 | pdata->chan_priority = tmp; | |
1538 | ||
1539 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
1540 | pdata->block_size = tmp; | |
1541 | ||
1542 | if (!of_property_read_u32(np, "nr_masters", &tmp)) { | |
1543 | if (tmp > 4) | |
1544 | return NULL; | |
1545 | ||
1546 | pdata->nr_masters = tmp; | |
1547 | } | |
1548 | ||
1549 | if (!of_property_read_u32_array(np, "data_width", arr, | |
1550 | pdata->nr_masters)) | |
1551 | for (tmp = 0; tmp < pdata->nr_masters; tmp++) | |
1552 | pdata->data_width[tmp] = arr[tmp]; | |
1553 | ||
1554 | /* parse slave data */ | |
1555 | sn = of_find_node_by_name(np, "slave_info"); | |
1556 | if (!sn) | |
1557 | return pdata; | |
1558 | ||
1559 | /* calculate number of slaves */ | |
1560 | tmp = of_get_child_count(sn); | |
1561 | if (!tmp) | |
1562 | return NULL; | |
1563 | ||
1564 | sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL); | |
1565 | if (!sd) | |
1566 | return NULL; | |
1567 | ||
1568 | pdata->sd = sd; | |
1569 | pdata->sd_count = tmp; | |
1570 | ||
1571 | for_each_child_of_node(sn, cn) { | |
1572 | sd->dma_dev = &pdev->dev; | |
1573 | of_property_read_string(cn, "bus_id", &sd->bus_id); | |
1574 | of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi); | |
1575 | of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo); | |
1576 | if (!of_property_read_u32(cn, "src_master", &tmp)) | |
1577 | sd->src_master = tmp; | |
1578 | ||
1579 | if (!of_property_read_u32(cn, "dst_master", &tmp)) | |
1580 | sd->dst_master = tmp; | |
1581 | sd++; | |
1582 | } | |
1583 | ||
1584 | return pdata; | |
1585 | } | |
1586 | #else | |
1587 | static inline struct dw_dma_platform_data * | |
1588 | dw_dma_parse_dt(struct platform_device *pdev) | |
1589 | { | |
1590 | return NULL; | |
1591 | } | |
1592 | #endif | |
1593 | ||
463a1f8b | 1594 | static int dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1595 | { |
1596 | struct dw_dma_platform_data *pdata; | |
1597 | struct resource *io; | |
1598 | struct dw_dma *dw; | |
1599 | size_t size; | |
482c67ea AS |
1600 | void __iomem *regs; |
1601 | bool autocfg; | |
1602 | unsigned int dw_params; | |
1603 | unsigned int nr_channels; | |
4a63a8b3 | 1604 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1605 | int irq; |
1606 | int err; | |
1607 | int i; | |
1608 | ||
3bfb1d20 HS |
1609 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1610 | if (!io) | |
1611 | return -EINVAL; | |
1612 | ||
1613 | irq = platform_get_irq(pdev, 0); | |
1614 | if (irq < 0) | |
1615 | return irq; | |
1616 | ||
482c67ea AS |
1617 | regs = devm_request_and_ioremap(&pdev->dev, io); |
1618 | if (!regs) | |
1619 | return -EBUSY; | |
1620 | ||
1621 | dw_params = dma_read_byaddr(regs, DW_PARAMS); | |
1622 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1623 | ||
985a6c7d AS |
1624 | dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
1625 | ||
123de543 AS |
1626 | pdata = dev_get_platdata(&pdev->dev); |
1627 | if (!pdata) | |
1628 | pdata = dw_dma_parse_dt(pdev); | |
1629 | ||
1630 | if (!pdata && autocfg) { | |
1631 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1632 | if (!pdata) | |
1633 | return -ENOMEM; | |
1634 | ||
1635 | /* Fill platform data with the default values */ | |
1636 | pdata->is_private = true; | |
1637 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1638 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1639 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1640 | return -EINVAL; | |
1641 | ||
482c67ea AS |
1642 | if (autocfg) |
1643 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1644 | else | |
1645 | nr_channels = pdata->nr_channels; | |
1646 | ||
1647 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1648 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1649 | if (!dw) |
1650 | return -ENOMEM; | |
1651 | ||
dbde5c29 AS |
1652 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1653 | if (IS_ERR(dw->clk)) | |
1654 | return PTR_ERR(dw->clk); | |
3075528d | 1655 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1656 | |
482c67ea | 1657 | dw->regs = regs; |
a9ddb575 VK |
1658 | dw->sd = pdata->sd; |
1659 | dw->sd_count = pdata->sd_count; | |
482c67ea | 1660 | |
4a63a8b3 | 1661 | /* get hardware configuration parameters */ |
a0982004 | 1662 | if (autocfg) { |
4a63a8b3 AS |
1663 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1664 | ||
a0982004 AS |
1665 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1666 | for (i = 0; i < dw->nr_masters; i++) { | |
1667 | dw->data_width[i] = | |
1668 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1669 | } | |
1670 | } else { | |
1671 | dw->nr_masters = pdata->nr_masters; | |
1672 | memcpy(dw->data_width, pdata->data_width, 4); | |
1673 | } | |
1674 | ||
11f932ec | 1675 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1676 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1677 | |
3bfb1d20 HS |
1678 | /* force dma off, just in case */ |
1679 | dw_dma_off(dw); | |
1680 | ||
236b106f AS |
1681 | /* disable BLOCK interrupts as well */ |
1682 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1683 | ||
dbde5c29 AS |
1684 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1685 | "dw_dmac", dw); | |
3bfb1d20 | 1686 | if (err) |
dbde5c29 | 1687 | return err; |
3bfb1d20 HS |
1688 | |
1689 | platform_set_drvdata(pdev, dw); | |
1690 | ||
f8122a82 AS |
1691 | /* create a pool of consistent memory blocks for hardware descriptors */ |
1692 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev, | |
1693 | sizeof(struct dw_desc), 4, 0); | |
1694 | if (!dw->desc_pool) { | |
1695 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1696 | return -ENOMEM; | |
1697 | } | |
1698 | ||
3bfb1d20 HS |
1699 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1700 | ||
3bfb1d20 | 1701 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1702 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1703 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1704 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1705 | |
1706 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1707 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1708 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1709 | list_add_tail(&dwc->chan.device_node, | |
1710 | &dw->dma.channels); | |
1711 | else | |
1712 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1713 | |
93317e8e VK |
1714 | /* 7 is highest priority & 0 is lowest. */ |
1715 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1716 | dwc->priority = r; |
93317e8e VK |
1717 | else |
1718 | dwc->priority = i; | |
1719 | ||
3bfb1d20 HS |
1720 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1721 | spin_lock_init(&dwc->lock); | |
1722 | dwc->mask = 1 << i; | |
1723 | ||
1724 | INIT_LIST_HEAD(&dwc->active_list); | |
1725 | INIT_LIST_HEAD(&dwc->queue); | |
1726 | INIT_LIST_HEAD(&dwc->free_list); | |
1727 | ||
1728 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1729 | |
0fdb567f | 1730 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1731 | |
4a63a8b3 | 1732 | /* hardware configuration */ |
fed2574b AS |
1733 | if (autocfg) { |
1734 | unsigned int dwc_params; | |
1735 | ||
1736 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1737 | DWC_PARAMS); | |
1738 | ||
985a6c7d AS |
1739 | dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1740 | dwc_params); | |
1741 | ||
4a63a8b3 AS |
1742 | /* Decode maximum block size for given channel. The |
1743 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1744 | * up to 0x0a for 4095. */ | |
1745 | dwc->block_size = | |
1746 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1747 | dwc->nollp = |
1748 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1749 | } else { | |
4a63a8b3 | 1750 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1751 | |
1752 | /* Check if channel supports multi block transfer */ | |
1753 | channel_writel(dwc, LLP, 0xfffffffc); | |
1754 | dwc->nollp = | |
1755 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1756 | channel_writel(dwc, LLP, 0); | |
1757 | } | |
3bfb1d20 HS |
1758 | } |
1759 | ||
11f932ec | 1760 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1761 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1762 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1763 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1764 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1765 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1766 | ||
3bfb1d20 HS |
1767 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1768 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1769 | if (pdata->is_private) |
1770 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1771 | dw->dma.dev = &pdev->dev; |
1772 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1773 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1774 | ||
1775 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1776 | ||
1777 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1778 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1779 | |
07934481 | 1780 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1781 | dw->dma.device_issue_pending = dwc_issue_pending; |
1782 | ||
1783 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1784 | ||
21d43f49 AS |
1785 | dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", |
1786 | nr_channels); | |
3bfb1d20 HS |
1787 | |
1788 | dma_async_device_register(&dw->dma); | |
1789 | ||
1790 | return 0; | |
3bfb1d20 HS |
1791 | } |
1792 | ||
0272e93f | 1793 | static int __devexit dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1794 | { |
1795 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1796 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 HS |
1797 | |
1798 | dw_dma_off(dw); | |
1799 | dma_async_device_unregister(&dw->dma); | |
1800 | ||
3bfb1d20 HS |
1801 | tasklet_kill(&dw->tasklet); |
1802 | ||
1803 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1804 | chan.device_node) { | |
1805 | list_del(&dwc->chan.device_node); | |
1806 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1807 | } | |
1808 | ||
3bfb1d20 HS |
1809 | return 0; |
1810 | } | |
1811 | ||
1812 | static void dw_shutdown(struct platform_device *pdev) | |
1813 | { | |
1814 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1815 | ||
6168d567 | 1816 | dw_dma_off(dw); |
3075528d | 1817 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1818 | } |
1819 | ||
4a256b5f | 1820 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1821 | { |
4a256b5f | 1822 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1823 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1824 | ||
6168d567 | 1825 | dw_dma_off(dw); |
3075528d | 1826 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1827 | |
3bfb1d20 HS |
1828 | return 0; |
1829 | } | |
1830 | ||
4a256b5f | 1831 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1832 | { |
4a256b5f | 1833 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1834 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1835 | ||
3075528d | 1836 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1837 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1838 | |
3bfb1d20 | 1839 | return 0; |
3bfb1d20 HS |
1840 | } |
1841 | ||
47145210 | 1842 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1843 | .suspend_noirq = dw_suspend_noirq, |
1844 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1845 | .freeze_noirq = dw_suspend_noirq, |
1846 | .thaw_noirq = dw_resume_noirq, | |
1847 | .restore_noirq = dw_resume_noirq, | |
1848 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1849 | }; |
1850 | ||
d3f797d9 VK |
1851 | #ifdef CONFIG_OF |
1852 | static const struct of_device_id dw_dma_id_table[] = { | |
1853 | { .compatible = "snps,dma-spear1340" }, | |
1854 | {} | |
1855 | }; | |
1856 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1857 | #endif | |
1858 | ||
3bfb1d20 | 1859 | static struct platform_driver dw_driver = { |
01126856 | 1860 | .probe = dw_probe, |
a7d6e3ec | 1861 | .remove = dw_remove, |
3bfb1d20 | 1862 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1863 | .driver = { |
1864 | .name = "dw_dmac", | |
4a256b5f | 1865 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1866 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 HS |
1867 | }, |
1868 | }; | |
1869 | ||
1870 | static int __init dw_init(void) | |
1871 | { | |
01126856 | 1872 | return platform_driver_register(&dw_driver); |
3bfb1d20 | 1873 | } |
cb689a70 | 1874 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1875 | |
1876 | static void __exit dw_exit(void) | |
1877 | { | |
1878 | platform_driver_unregister(&dw_driver); | |
1879 | } | |
1880 | module_exit(dw_exit); | |
1881 | ||
1882 | MODULE_LICENSE("GPL v2"); | |
1883 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1884 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1885 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |