Commit | Line | Data |
---|---|---|
3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
d3f797d9 | 20 | #include <linux/of.h> |
3bfb1d20 HS |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | ||
26 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 27 | #include "dmaengine.h" |
3bfb1d20 HS |
28 | |
29 | /* | |
30 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
31 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
32 | * of which use ARM any more). See the "Databook" from Synopsys for | |
33 | * information beyond what licensees probably provide. | |
34 | * | |
35 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
36 | * which does not support descriptor writeback. | |
37 | */ | |
38 | ||
327e6970 VK |
39 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
40 | struct dw_dma_slave *__slave = (_chan->private); \ | |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ | |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
43 | int _dms = __slave ? __slave->dst_master : 0; \ | |
44 | int _sms = __slave ? __slave->src_master : 1; \ | |
45 | u8 _smsize = __slave ? _sconfig->src_maxburst : \ | |
46 | DW_DMA_MSIZE_16; \ | |
47 | u8 _dmsize = __slave ? _sconfig->dst_maxburst : \ | |
48 | DW_DMA_MSIZE_16; \ | |
f301c062 | 49 | \ |
327e6970 VK |
50 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
51 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
52 | | DWC_CTLL_LLP_D_EN \ |
53 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
54 | | DWC_CTLL_DMS(_dms) \ |
55 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 56 | }) |
3bfb1d20 HS |
57 | |
58 | /* | |
59 | * This is configuration-dependent and usually a funny size like 4095. | |
3bfb1d20 HS |
60 | * |
61 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
418e7407 | 62 | * words, we can do 16380 bytes per descriptor. |
3bfb1d20 HS |
63 | * |
64 | * This parameter is also system-specific. | |
65 | */ | |
418e7407 | 66 | #define DWC_MAX_COUNT 4095U |
3bfb1d20 HS |
67 | |
68 | /* | |
69 | * Number of descriptors to allocate for each channel. This should be | |
70 | * made configurable somehow; preferably, the clients (at least the | |
71 | * ones using slave transfers) should be able to give us a hint. | |
72 | */ | |
73 | #define NR_DESCS_PER_CHANNEL 64 | |
74 | ||
75 | /*----------------------------------------------------------------------*/ | |
76 | ||
77 | /* | |
78 | * Because we're not relying on writeback from the controller (it may not | |
79 | * even be configured into the core!) we don't need to use dma_pool. These | |
80 | * descriptors -- and associated data -- are cacheable. We do need to make | |
81 | * sure their dcache entries are written back before handing them off to | |
82 | * the controller, though. | |
83 | */ | |
84 | ||
41d5e59c DW |
85 | static struct device *chan2dev(struct dma_chan *chan) |
86 | { | |
87 | return &chan->dev->device; | |
88 | } | |
89 | static struct device *chan2parent(struct dma_chan *chan) | |
90 | { | |
91 | return chan->dev->device.parent; | |
92 | } | |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
95 | { | |
96 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
97 | } | |
98 | ||
3bfb1d20 HS |
99 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
100 | { | |
101 | struct dw_desc *desc, *_desc; | |
102 | struct dw_desc *ret = NULL; | |
103 | unsigned int i = 0; | |
69cea5a0 | 104 | unsigned long flags; |
3bfb1d20 | 105 | |
69cea5a0 | 106 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 107 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 108 | i++; |
3bfb1d20 HS |
109 | if (async_tx_test_ack(&desc->txd)) { |
110 | list_del(&desc->desc_node); | |
111 | ret = desc; | |
112 | break; | |
113 | } | |
41d5e59c | 114 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 115 | } |
69cea5a0 | 116 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 117 | |
41d5e59c | 118 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
119 | |
120 | return ret; | |
121 | } | |
122 | ||
123 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
124 | { | |
125 | struct dw_desc *child; | |
126 | ||
e0bd0f8c | 127 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 128 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
129 | child->txd.phys, sizeof(child->lli), |
130 | DMA_TO_DEVICE); | |
41d5e59c | 131 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
132 | desc->txd.phys, sizeof(desc->lli), |
133 | DMA_TO_DEVICE); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Move a descriptor, including any children, to the free list. | |
138 | * `desc' must not be on any lists. | |
139 | */ | |
140 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
141 | { | |
69cea5a0 VK |
142 | unsigned long flags; |
143 | ||
3bfb1d20 HS |
144 | if (desc) { |
145 | struct dw_desc *child; | |
146 | ||
147 | dwc_sync_desc_for_cpu(dwc, desc); | |
148 | ||
69cea5a0 | 149 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 150 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 151 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
152 | "moving child desc %p to freelist\n", |
153 | child); | |
e0bd0f8c | 154 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 155 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 156 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 157 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
158 | } |
159 | } | |
160 | ||
61e183f8 VK |
161 | static void dwc_initialize(struct dw_dma_chan *dwc) |
162 | { | |
163 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
164 | struct dw_dma_slave *dws = dwc->chan.private; | |
165 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
166 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
167 | ||
168 | if (dwc->initialized == true) | |
169 | return; | |
170 | ||
171 | if (dws) { | |
172 | /* | |
173 | * We need controller-specific data to set up slave | |
174 | * transfers. | |
175 | */ | |
176 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
177 | ||
178 | cfghi = dws->cfg_hi; | |
179 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
180 | } | |
181 | ||
182 | channel_writel(dwc, CFG_LO, cfglo); | |
183 | channel_writel(dwc, CFG_HI, cfghi); | |
184 | ||
185 | /* Enable interrupts */ | |
186 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
187 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
188 | ||
189 | dwc->initialized = true; | |
190 | } | |
191 | ||
3bfb1d20 HS |
192 | /*----------------------------------------------------------------------*/ |
193 | ||
4c2d56c5 AS |
194 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
195 | { | |
196 | /* | |
197 | * We can be a lot more clever here, but this should take care | |
198 | * of the most common optimization. | |
199 | */ | |
200 | if (!(v & 7)) | |
201 | return 3; | |
202 | else if (!(v & 3)) | |
203 | return 2; | |
204 | else if (!(v & 1)) | |
205 | return 1; | |
206 | return 0; | |
207 | } | |
208 | ||
1d455437 AS |
209 | static void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
210 | { | |
211 | dev_err(chan2dev(&dwc->chan), | |
212 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
213 | channel_readl(dwc, SAR), | |
214 | channel_readl(dwc, DAR), | |
215 | channel_readl(dwc, LLP), | |
216 | channel_readl(dwc, CTL_HI), | |
217 | channel_readl(dwc, CTL_LO)); | |
218 | } | |
219 | ||
3f936207 AS |
220 | |
221 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
222 | { | |
223 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
224 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
225 | cpu_relax(); | |
226 | } | |
227 | ||
1d455437 AS |
228 | /*----------------------------------------------------------------------*/ |
229 | ||
3bfb1d20 HS |
230 | /* Called with dwc->lock held and bh disabled */ |
231 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
232 | { | |
233 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
234 | ||
235 | /* ASSERT: channel is idle */ | |
236 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 237 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 238 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 239 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
240 | |
241 | /* The tasklet will hopefully advance the queue... */ | |
242 | return; | |
243 | } | |
244 | ||
61e183f8 VK |
245 | dwc_initialize(dwc); |
246 | ||
3bfb1d20 HS |
247 | channel_writel(dwc, LLP, first->txd.phys); |
248 | channel_writel(dwc, CTL_LO, | |
249 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
250 | channel_writel(dwc, CTL_HI, 0); | |
251 | channel_set_bit(dw, CH_EN, dwc->mask); | |
252 | } | |
253 | ||
254 | /*----------------------------------------------------------------------*/ | |
255 | ||
256 | static void | |
5fedefb8 VK |
257 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
258 | bool callback_required) | |
3bfb1d20 | 259 | { |
5fedefb8 VK |
260 | dma_async_tx_callback callback = NULL; |
261 | void *param = NULL; | |
3bfb1d20 | 262 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 263 | struct dw_desc *child; |
69cea5a0 | 264 | unsigned long flags; |
3bfb1d20 | 265 | |
41d5e59c | 266 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 267 | |
69cea5a0 | 268 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 269 | dma_cookie_complete(txd); |
5fedefb8 VK |
270 | if (callback_required) { |
271 | callback = txd->callback; | |
272 | param = txd->callback_param; | |
273 | } | |
3bfb1d20 HS |
274 | |
275 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
276 | |
277 | /* async_tx_ack */ | |
278 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
279 | async_tx_ack(&child->txd); | |
280 | async_tx_ack(&desc->txd); | |
281 | ||
e0bd0f8c | 282 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
283 | list_move(&desc->desc_node, &dwc->free_list); |
284 | ||
657a77fa AN |
285 | if (!dwc->chan.private) { |
286 | struct device *parent = chan2parent(&dwc->chan); | |
287 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
288 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
289 | dma_unmap_single(parent, desc->lli.dar, | |
290 | desc->len, DMA_FROM_DEVICE); | |
291 | else | |
292 | dma_unmap_page(parent, desc->lli.dar, | |
293 | desc->len, DMA_FROM_DEVICE); | |
294 | } | |
295 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
296 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
297 | dma_unmap_single(parent, desc->lli.sar, | |
298 | desc->len, DMA_TO_DEVICE); | |
299 | else | |
300 | dma_unmap_page(parent, desc->lli.sar, | |
301 | desc->len, DMA_TO_DEVICE); | |
302 | } | |
303 | } | |
3bfb1d20 | 304 | |
69cea5a0 VK |
305 | spin_unlock_irqrestore(&dwc->lock, flags); |
306 | ||
5fedefb8 | 307 | if (callback_required && callback) |
3bfb1d20 HS |
308 | callback(param); |
309 | } | |
310 | ||
311 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
312 | { | |
313 | struct dw_desc *desc, *_desc; | |
314 | LIST_HEAD(list); | |
69cea5a0 | 315 | unsigned long flags; |
3bfb1d20 | 316 | |
69cea5a0 | 317 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 318 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 319 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
320 | "BUG: XFER bit set, but channel not idle!\n"); |
321 | ||
322 | /* Try to continue after resetting the channel... */ | |
3f936207 | 323 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
324 | } |
325 | ||
326 | /* | |
327 | * Submit queued descriptors ASAP, i.e. before we go through | |
328 | * the completed ones. | |
329 | */ | |
3bfb1d20 | 330 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
331 | if (!list_empty(&dwc->queue)) { |
332 | list_move(dwc->queue.next, &dwc->active_list); | |
333 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
334 | } | |
3bfb1d20 | 335 | |
69cea5a0 VK |
336 | spin_unlock_irqrestore(&dwc->lock, flags); |
337 | ||
3bfb1d20 | 338 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 339 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
340 | } |
341 | ||
342 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
343 | { | |
344 | dma_addr_t llp; | |
345 | struct dw_desc *desc, *_desc; | |
346 | struct dw_desc *child; | |
347 | u32 status_xfer; | |
69cea5a0 | 348 | unsigned long flags; |
3bfb1d20 | 349 | |
69cea5a0 | 350 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
351 | llp = channel_readl(dwc, LLP); |
352 | status_xfer = dma_readl(dw, RAW.XFER); | |
353 | ||
354 | if (status_xfer & dwc->mask) { | |
355 | /* Everything we've submitted is done */ | |
356 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
69cea5a0 VK |
357 | spin_unlock_irqrestore(&dwc->lock, flags); |
358 | ||
3bfb1d20 HS |
359 | dwc_complete_all(dw, dwc); |
360 | return; | |
361 | } | |
362 | ||
69cea5a0 VK |
363 | if (list_empty(&dwc->active_list)) { |
364 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 365 | return; |
69cea5a0 | 366 | } |
087809fc | 367 | |
2e4c364e | 368 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 369 | (unsigned long long)llp); |
3bfb1d20 HS |
370 | |
371 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb | 372 | /* check first descriptors addr */ |
69cea5a0 VK |
373 | if (desc->txd.phys == llp) { |
374 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 375 | return; |
69cea5a0 | 376 | } |
84adccfb VK |
377 | |
378 | /* check first descriptors llp */ | |
69cea5a0 | 379 | if (desc->lli.llp == llp) { |
3bfb1d20 | 380 | /* This one is currently in progress */ |
69cea5a0 | 381 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 382 | return; |
69cea5a0 | 383 | } |
3bfb1d20 | 384 | |
e0bd0f8c | 385 | list_for_each_entry(child, &desc->tx_list, desc_node) |
69cea5a0 | 386 | if (child->lli.llp == llp) { |
3bfb1d20 | 387 | /* Currently in progress */ |
69cea5a0 | 388 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 389 | return; |
69cea5a0 | 390 | } |
3bfb1d20 HS |
391 | |
392 | /* | |
393 | * No descriptors so far seem to be in progress, i.e. | |
394 | * this one must be done. | |
395 | */ | |
69cea5a0 | 396 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 397 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 398 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
399 | } |
400 | ||
41d5e59c | 401 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
402 | "BUG: All descriptors done, but channel not idle!\n"); |
403 | ||
404 | /* Try to continue after resetting the channel... */ | |
3f936207 | 405 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
406 | |
407 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
408 | list_move(dwc->queue.next, &dwc->active_list); |
409 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 410 | } |
69cea5a0 | 411 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
412 | } |
413 | ||
414 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
415 | { | |
41d5e59c | 416 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
2f45d613 AS |
417 | " desc: s0x%llx d0x%llx l0x%llx c0x%x:%x\n", |
418 | (unsigned long long)lli->sar, | |
419 | (unsigned long long)lli->dar, | |
420 | (unsigned long long)lli->llp, | |
3bfb1d20 HS |
421 | lli->ctlhi, lli->ctllo); |
422 | } | |
423 | ||
424 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
425 | { | |
426 | struct dw_desc *bad_desc; | |
427 | struct dw_desc *child; | |
69cea5a0 | 428 | unsigned long flags; |
3bfb1d20 HS |
429 | |
430 | dwc_scan_descriptors(dw, dwc); | |
431 | ||
69cea5a0 VK |
432 | spin_lock_irqsave(&dwc->lock, flags); |
433 | ||
3bfb1d20 HS |
434 | /* |
435 | * The descriptor currently at the head of the active list is | |
436 | * borked. Since we don't have any way to report errors, we'll | |
437 | * just have to scream loudly and try to carry on. | |
438 | */ | |
439 | bad_desc = dwc_first_active(dwc); | |
440 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 441 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
442 | |
443 | /* Clear the error flag and try to restart the controller */ | |
444 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
445 | if (!list_empty(&dwc->active_list)) | |
446 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
447 | ||
448 | /* | |
449 | * KERN_CRITICAL may seem harsh, but since this only happens | |
450 | * when someone submits a bad physical address in a | |
451 | * descriptor, we should consider ourselves lucky that the | |
452 | * controller flagged an error instead of scribbling over | |
453 | * random memory locations. | |
454 | */ | |
41d5e59c | 455 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 456 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 457 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
458 | " cookie: %d\n", bad_desc->txd.cookie); |
459 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 460 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
461 | dwc_dump_lli(dwc, &child->lli); |
462 | ||
69cea5a0 VK |
463 | spin_unlock_irqrestore(&dwc->lock, flags); |
464 | ||
3bfb1d20 | 465 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 466 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
467 | } |
468 | ||
d9de4519 HCE |
469 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
470 | ||
471 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
472 | { | |
473 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
474 | return channel_readl(dwc, SAR); | |
475 | } | |
476 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
477 | ||
478 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
479 | { | |
480 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
481 | return channel_readl(dwc, DAR); | |
482 | } | |
483 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
484 | ||
485 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
486 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 487 | u32 status_err, u32 status_xfer) |
d9de4519 | 488 | { |
69cea5a0 VK |
489 | unsigned long flags; |
490 | ||
ff7b05f2 | 491 | if (dwc->mask) { |
d9de4519 HCE |
492 | void (*callback)(void *param); |
493 | void *callback_param; | |
494 | ||
495 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
496 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
497 | |
498 | callback = dwc->cdesc->period_callback; | |
499 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
500 | |
501 | if (callback) | |
d9de4519 | 502 | callback(callback_param); |
d9de4519 HCE |
503 | } |
504 | ||
505 | /* | |
506 | * Error and transfer complete are highly unlikely, and will most | |
507 | * likely be due to a configuration error by the user. | |
508 | */ | |
509 | if (unlikely(status_err & dwc->mask) || | |
510 | unlikely(status_xfer & dwc->mask)) { | |
511 | int i; | |
512 | ||
513 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
514 | "interrupt, stopping DMA transfer\n", | |
515 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
516 | |
517 | spin_lock_irqsave(&dwc->lock, flags); | |
518 | ||
1d455437 | 519 | dwc_dump_chan_regs(dwc); |
d9de4519 | 520 | |
3f936207 | 521 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
522 | |
523 | /* make sure DMA does not restart by loading a new list */ | |
524 | channel_writel(dwc, LLP, 0); | |
525 | channel_writel(dwc, CTL_LO, 0); | |
526 | channel_writel(dwc, CTL_HI, 0); | |
527 | ||
d9de4519 HCE |
528 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
529 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
530 | ||
531 | for (i = 0; i < dwc->cdesc->periods; i++) | |
532 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
533 | |
534 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
535 | } |
536 | } | |
537 | ||
538 | /* ------------------------------------------------------------------------- */ | |
539 | ||
3bfb1d20 HS |
540 | static void dw_dma_tasklet(unsigned long data) |
541 | { | |
542 | struct dw_dma *dw = (struct dw_dma *)data; | |
543 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
544 | u32 status_xfer; |
545 | u32 status_err; | |
546 | int i; | |
547 | ||
7fe7b2f4 | 548 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
549 | status_err = dma_readl(dw, RAW.ERROR); |
550 | ||
2e4c364e | 551 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
552 | |
553 | for (i = 0; i < dw->dma.chancnt; i++) { | |
554 | dwc = &dw->chan[i]; | |
d9de4519 | 555 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 556 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 557 | else if (status_err & (1 << i)) |
3bfb1d20 | 558 | dwc_handle_error(dw, dwc); |
ff7b05f2 | 559 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 560 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
561 | } |
562 | ||
563 | /* | |
ff7b05f2 | 564 | * Re-enable interrupts. |
3bfb1d20 HS |
565 | */ |
566 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
567 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
568 | } | |
569 | ||
570 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
571 | { | |
572 | struct dw_dma *dw = dev_id; | |
573 | u32 status; | |
574 | ||
2e4c364e | 575 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
576 | dma_readl(dw, STATUS_INT)); |
577 | ||
578 | /* | |
579 | * Just disable the interrupts. We'll turn them back on in the | |
580 | * softirq handler. | |
581 | */ | |
582 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
583 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
584 | ||
585 | status = dma_readl(dw, STATUS_INT); | |
586 | if (status) { | |
587 | dev_err(dw->dma.dev, | |
588 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
589 | status); | |
590 | ||
591 | /* Try to recover */ | |
592 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
593 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
594 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
595 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
596 | } | |
597 | ||
598 | tasklet_schedule(&dw->tasklet); | |
599 | ||
600 | return IRQ_HANDLED; | |
601 | } | |
602 | ||
603 | /*----------------------------------------------------------------------*/ | |
604 | ||
605 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
606 | { | |
607 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
608 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
609 | dma_cookie_t cookie; | |
69cea5a0 | 610 | unsigned long flags; |
3bfb1d20 | 611 | |
69cea5a0 | 612 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 613 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
614 | |
615 | /* | |
616 | * REVISIT: We should attempt to chain as many descriptors as | |
617 | * possible, perhaps even appending to those already submitted | |
618 | * for DMA. But this is hard to do in a race-free manner. | |
619 | */ | |
620 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 621 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 622 | desc->txd.cookie); |
3bfb1d20 | 623 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 624 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 625 | } else { |
2e4c364e | 626 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
627 | desc->txd.cookie); |
628 | ||
629 | list_add_tail(&desc->desc_node, &dwc->queue); | |
630 | } | |
631 | ||
69cea5a0 | 632 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
633 | |
634 | return cookie; | |
635 | } | |
636 | ||
637 | static struct dma_async_tx_descriptor * | |
638 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
639 | size_t len, unsigned long flags) | |
640 | { | |
641 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
642 | struct dw_desc *desc; | |
643 | struct dw_desc *first; | |
644 | struct dw_desc *prev; | |
645 | size_t xfer_count; | |
646 | size_t offset; | |
647 | unsigned int src_width; | |
648 | unsigned int dst_width; | |
649 | u32 ctllo; | |
650 | ||
2f45d613 | 651 | dev_vdbg(chan2dev(chan), |
2e4c364e | 652 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
653 | (unsigned long long)dest, (unsigned long long)src, |
654 | len, flags); | |
3bfb1d20 HS |
655 | |
656 | if (unlikely(!len)) { | |
2e4c364e | 657 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
658 | return NULL; |
659 | } | |
660 | ||
4c2d56c5 | 661 | src_width = dst_width = dwc_fast_fls(src | dest | len); |
3bfb1d20 | 662 | |
327e6970 | 663 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
664 | | DWC_CTLL_DST_WIDTH(dst_width) |
665 | | DWC_CTLL_SRC_WIDTH(src_width) | |
666 | | DWC_CTLL_DST_INC | |
667 | | DWC_CTLL_SRC_INC | |
668 | | DWC_CTLL_FC_M2M; | |
669 | prev = first = NULL; | |
670 | ||
671 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
672 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
673 | DWC_MAX_COUNT); | |
674 | ||
675 | desc = dwc_desc_get(dwc); | |
676 | if (!desc) | |
677 | goto err_desc_get; | |
678 | ||
679 | desc->lli.sar = src + offset; | |
680 | desc->lli.dar = dest + offset; | |
681 | desc->lli.ctllo = ctllo; | |
682 | desc->lli.ctlhi = xfer_count; | |
683 | ||
684 | if (!first) { | |
685 | first = desc; | |
686 | } else { | |
687 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 688 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
689 | prev->txd.phys, sizeof(prev->lli), |
690 | DMA_TO_DEVICE); | |
691 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 692 | &first->tx_list); |
3bfb1d20 HS |
693 | } |
694 | prev = desc; | |
695 | } | |
696 | ||
697 | ||
698 | if (flags & DMA_PREP_INTERRUPT) | |
699 | /* Trigger interrupt after last block */ | |
700 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
701 | ||
702 | prev->lli.llp = 0; | |
41d5e59c | 703 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
704 | prev->txd.phys, sizeof(prev->lli), |
705 | DMA_TO_DEVICE); | |
706 | ||
707 | first->txd.flags = flags; | |
708 | first->len = len; | |
709 | ||
710 | return &first->txd; | |
711 | ||
712 | err_desc_get: | |
713 | dwc_desc_put(dwc, first); | |
714 | return NULL; | |
715 | } | |
716 | ||
717 | static struct dma_async_tx_descriptor * | |
718 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 719 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 720 | unsigned long flags, void *context) |
3bfb1d20 HS |
721 | { |
722 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 723 | struct dw_dma_slave *dws = chan->private; |
327e6970 | 724 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
725 | struct dw_desc *prev; |
726 | struct dw_desc *first; | |
727 | u32 ctllo; | |
728 | dma_addr_t reg; | |
729 | unsigned int reg_width; | |
730 | unsigned int mem_width; | |
731 | unsigned int i; | |
732 | struct scatterlist *sg; | |
733 | size_t total_len = 0; | |
734 | ||
2e4c364e | 735 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 HS |
736 | |
737 | if (unlikely(!dws || !sg_len)) | |
738 | return NULL; | |
739 | ||
3bfb1d20 HS |
740 | prev = first = NULL; |
741 | ||
3bfb1d20 | 742 | switch (direction) { |
db8196df | 743 | case DMA_MEM_TO_DEV: |
327e6970 VK |
744 | reg_width = __fls(sconfig->dst_addr_width); |
745 | reg = sconfig->dst_addr; | |
746 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
747 | | DWC_CTLL_DST_WIDTH(reg_width) |
748 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
749 | | DWC_CTLL_SRC_INC); |
750 | ||
751 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
752 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
753 | ||
3bfb1d20 HS |
754 | for_each_sg(sgl, sg, sg_len, i) { |
755 | struct dw_desc *desc; | |
69dc14b5 | 756 | u32 len, dlen, mem; |
3bfb1d20 | 757 | |
cbb796cc | 758 | mem = sg_dma_address(sg); |
69dc14b5 | 759 | len = sg_dma_len(sg); |
6bc711f6 | 760 | |
4c2d56c5 | 761 | mem_width = dwc_fast_fls(mem | len); |
3bfb1d20 | 762 | |
69dc14b5 | 763 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
764 | desc = dwc_desc_get(dwc); |
765 | if (!desc) { | |
41d5e59c | 766 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
767 | "not enough descriptors available\n"); |
768 | goto err_desc_get; | |
769 | } | |
770 | ||
3bfb1d20 HS |
771 | desc->lli.sar = mem; |
772 | desc->lli.dar = reg; | |
773 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
69dc14b5 VK |
774 | if ((len >> mem_width) > DWC_MAX_COUNT) { |
775 | dlen = DWC_MAX_COUNT << mem_width; | |
776 | mem += dlen; | |
777 | len -= dlen; | |
778 | } else { | |
779 | dlen = len; | |
780 | len = 0; | |
781 | } | |
782 | ||
783 | desc->lli.ctlhi = dlen >> mem_width; | |
3bfb1d20 HS |
784 | |
785 | if (!first) { | |
786 | first = desc; | |
787 | } else { | |
788 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 789 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
790 | prev->txd.phys, |
791 | sizeof(prev->lli), | |
792 | DMA_TO_DEVICE); | |
793 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 794 | &first->tx_list); |
3bfb1d20 HS |
795 | } |
796 | prev = desc; | |
69dc14b5 VK |
797 | total_len += dlen; |
798 | ||
799 | if (len) | |
800 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
801 | } |
802 | break; | |
db8196df | 803 | case DMA_DEV_TO_MEM: |
327e6970 VK |
804 | reg_width = __fls(sconfig->src_addr_width); |
805 | reg = sconfig->src_addr; | |
806 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
807 | | DWC_CTLL_SRC_WIDTH(reg_width) |
808 | | DWC_CTLL_DST_INC | |
327e6970 VK |
809 | | DWC_CTLL_SRC_FIX); |
810 | ||
811 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
812 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 813 | |
3bfb1d20 HS |
814 | for_each_sg(sgl, sg, sg_len, i) { |
815 | struct dw_desc *desc; | |
69dc14b5 | 816 | u32 len, dlen, mem; |
3bfb1d20 | 817 | |
cbb796cc | 818 | mem = sg_dma_address(sg); |
3bfb1d20 | 819 | len = sg_dma_len(sg); |
6bc711f6 | 820 | |
4c2d56c5 | 821 | mem_width = dwc_fast_fls(mem | len); |
3bfb1d20 | 822 | |
69dc14b5 VK |
823 | slave_sg_fromdev_fill_desc: |
824 | desc = dwc_desc_get(dwc); | |
825 | if (!desc) { | |
826 | dev_err(chan2dev(chan), | |
827 | "not enough descriptors available\n"); | |
828 | goto err_desc_get; | |
829 | } | |
830 | ||
3bfb1d20 HS |
831 | desc->lli.sar = reg; |
832 | desc->lli.dar = mem; | |
833 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
69dc14b5 VK |
834 | if ((len >> reg_width) > DWC_MAX_COUNT) { |
835 | dlen = DWC_MAX_COUNT << reg_width; | |
836 | mem += dlen; | |
837 | len -= dlen; | |
838 | } else { | |
839 | dlen = len; | |
840 | len = 0; | |
841 | } | |
842 | desc->lli.ctlhi = dlen >> reg_width; | |
3bfb1d20 HS |
843 | |
844 | if (!first) { | |
845 | first = desc; | |
846 | } else { | |
847 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 848 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
849 | prev->txd.phys, |
850 | sizeof(prev->lli), | |
851 | DMA_TO_DEVICE); | |
852 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 853 | &first->tx_list); |
3bfb1d20 HS |
854 | } |
855 | prev = desc; | |
69dc14b5 VK |
856 | total_len += dlen; |
857 | ||
858 | if (len) | |
859 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
860 | } |
861 | break; | |
862 | default: | |
863 | return NULL; | |
864 | } | |
865 | ||
866 | if (flags & DMA_PREP_INTERRUPT) | |
867 | /* Trigger interrupt after last block */ | |
868 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
869 | ||
870 | prev->lli.llp = 0; | |
41d5e59c | 871 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
872 | prev->txd.phys, sizeof(prev->lli), |
873 | DMA_TO_DEVICE); | |
874 | ||
875 | first->len = total_len; | |
876 | ||
877 | return &first->txd; | |
878 | ||
879 | err_desc_get: | |
880 | dwc_desc_put(dwc, first); | |
881 | return NULL; | |
882 | } | |
883 | ||
327e6970 VK |
884 | /* |
885 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
886 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
887 | * | |
888 | * NOTE: burst size 2 is not supported by controller. | |
889 | * | |
890 | * This can be done by finding least significant bit set: n & (n - 1) | |
891 | */ | |
892 | static inline void convert_burst(u32 *maxburst) | |
893 | { | |
894 | if (*maxburst > 1) | |
895 | *maxburst = fls(*maxburst) - 2; | |
896 | else | |
897 | *maxburst = 0; | |
898 | } | |
899 | ||
900 | static int | |
901 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
902 | { | |
903 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
904 | ||
905 | /* Check if it is chan is configured for slave transfers */ | |
906 | if (!chan->private) | |
907 | return -EINVAL; | |
908 | ||
909 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
910 | ||
911 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
912 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
05827630 LW |
917 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
918 | unsigned long arg) | |
3bfb1d20 HS |
919 | { |
920 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
921 | struct dw_dma *dw = to_dw_dma(chan->device); | |
922 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 923 | unsigned long flags; |
a7c57cf7 | 924 | u32 cfglo; |
3bfb1d20 HS |
925 | LIST_HEAD(list); |
926 | ||
a7c57cf7 LW |
927 | if (cmd == DMA_PAUSE) { |
928 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 929 | |
a7c57cf7 LW |
930 | cfglo = channel_readl(dwc, CFG_LO); |
931 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
932 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
933 | cpu_relax(); | |
3bfb1d20 | 934 | |
a7c57cf7 LW |
935 | dwc->paused = true; |
936 | spin_unlock_irqrestore(&dwc->lock, flags); | |
937 | } else if (cmd == DMA_RESUME) { | |
938 | if (!dwc->paused) | |
939 | return 0; | |
3bfb1d20 | 940 | |
a7c57cf7 | 941 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 942 | |
a7c57cf7 LW |
943 | cfglo = channel_readl(dwc, CFG_LO); |
944 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
945 | dwc->paused = false; | |
3bfb1d20 | 946 | |
a7c57cf7 LW |
947 | spin_unlock_irqrestore(&dwc->lock, flags); |
948 | } else if (cmd == DMA_TERMINATE_ALL) { | |
949 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 950 | |
3f936207 | 951 | dwc_chan_disable(dw, dwc); |
a7c57cf7 LW |
952 | |
953 | dwc->paused = false; | |
954 | ||
955 | /* active_list entries will end up before queued entries */ | |
956 | list_splice_init(&dwc->queue, &list); | |
957 | list_splice_init(&dwc->active_list, &list); | |
958 | ||
959 | spin_unlock_irqrestore(&dwc->lock, flags); | |
960 | ||
961 | /* Flush all pending and queued descriptors */ | |
962 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
963 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
964 | } else if (cmd == DMA_SLAVE_CONFIG) { |
965 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
966 | } else { | |
a7c57cf7 | 967 | return -ENXIO; |
327e6970 | 968 | } |
c3635c78 LW |
969 | |
970 | return 0; | |
3bfb1d20 HS |
971 | } |
972 | ||
973 | static enum dma_status | |
07934481 LW |
974 | dwc_tx_status(struct dma_chan *chan, |
975 | dma_cookie_t cookie, | |
976 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
977 | { |
978 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 979 | enum dma_status ret; |
3bfb1d20 | 980 | |
96a2af41 | 981 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
982 | if (ret != DMA_SUCCESS) { |
983 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
984 | ||
96a2af41 | 985 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
986 | } |
987 | ||
abf53902 | 988 | if (ret != DMA_SUCCESS) |
96a2af41 | 989 | dma_set_residue(txstate, dwc_first_active(dwc)->len); |
3bfb1d20 | 990 | |
a7c57cf7 LW |
991 | if (dwc->paused) |
992 | return DMA_PAUSED; | |
3bfb1d20 HS |
993 | |
994 | return ret; | |
995 | } | |
996 | ||
997 | static void dwc_issue_pending(struct dma_chan *chan) | |
998 | { | |
999 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1000 | ||
3bfb1d20 HS |
1001 | if (!list_empty(&dwc->queue)) |
1002 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1003 | } |
1004 | ||
aa1e6f1a | 1005 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1006 | { |
1007 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1008 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1009 | struct dw_desc *desc; | |
3bfb1d20 | 1010 | int i; |
69cea5a0 | 1011 | unsigned long flags; |
3bfb1d20 | 1012 | |
2e4c364e | 1013 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1014 | |
3bfb1d20 HS |
1015 | /* ASSERT: channel is idle */ |
1016 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1017 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1018 | return -EIO; |
1019 | } | |
1020 | ||
d3ee98cd | 1021 | dma_cookie_init(chan); |
3bfb1d20 | 1022 | |
3bfb1d20 HS |
1023 | /* |
1024 | * NOTE: some controllers may have additional features that we | |
1025 | * need to initialize here, like "scatter-gather" (which | |
1026 | * doesn't mean what you think it means), and status writeback. | |
1027 | */ | |
1028 | ||
69cea5a0 | 1029 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1030 | i = dwc->descs_allocated; |
1031 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
69cea5a0 | 1032 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1033 | |
1034 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
1035 | if (!desc) { | |
41d5e59c | 1036 | dev_info(chan2dev(chan), |
3bfb1d20 | 1037 | "only allocated %d descriptors\n", i); |
69cea5a0 | 1038 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1039 | break; |
1040 | } | |
1041 | ||
e0bd0f8c | 1042 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1043 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1044 | desc->txd.tx_submit = dwc_tx_submit; | |
1045 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 1046 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
1047 | sizeof(desc->lli), DMA_TO_DEVICE); |
1048 | dwc_desc_put(dwc, desc); | |
1049 | ||
69cea5a0 | 1050 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1051 | i = ++dwc->descs_allocated; |
1052 | } | |
1053 | ||
69cea5a0 | 1054 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1055 | |
2e4c364e | 1056 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 HS |
1057 | |
1058 | return i; | |
1059 | } | |
1060 | ||
1061 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1062 | { | |
1063 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1064 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1065 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1066 | unsigned long flags; |
3bfb1d20 HS |
1067 | LIST_HEAD(list); |
1068 | ||
2e4c364e | 1069 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1070 | dwc->descs_allocated); |
1071 | ||
1072 | /* ASSERT: channel is idle */ | |
1073 | BUG_ON(!list_empty(&dwc->active_list)); | |
1074 | BUG_ON(!list_empty(&dwc->queue)); | |
1075 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1076 | ||
69cea5a0 | 1077 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1078 | list_splice_init(&dwc->free_list, &list); |
1079 | dwc->descs_allocated = 0; | |
61e183f8 | 1080 | dwc->initialized = false; |
3bfb1d20 HS |
1081 | |
1082 | /* Disable interrupts */ | |
1083 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1084 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1085 | ||
69cea5a0 | 1086 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1087 | |
1088 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
1089 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
1090 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
1091 | sizeof(desc->lli), DMA_TO_DEVICE); |
1092 | kfree(desc); | |
1093 | } | |
1094 | ||
2e4c364e | 1095 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1096 | } |
1097 | ||
d9de4519 HCE |
1098 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1099 | ||
1100 | /** | |
1101 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1102 | * @chan: the DMA channel to start | |
1103 | * | |
1104 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1105 | * -errno on failure. | |
1106 | */ | |
1107 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1108 | { | |
1109 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1110 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1111 | unsigned long flags; |
d9de4519 HCE |
1112 | |
1113 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1114 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1115 | return -ENODEV; | |
1116 | } | |
1117 | ||
69cea5a0 | 1118 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1119 | |
1120 | /* assert channel is idle */ | |
1121 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1122 | dev_err(chan2dev(&dwc->chan), | |
1123 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1124 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1125 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1126 | return -EBUSY; |
1127 | } | |
1128 | ||
d9de4519 HCE |
1129 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1130 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1131 | ||
1132 | /* setup DMAC channel registers */ | |
1133 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1134 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1135 | channel_writel(dwc, CTL_HI, 0); | |
1136 | ||
1137 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1138 | ||
69cea5a0 | 1139 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1140 | |
1141 | return 0; | |
1142 | } | |
1143 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1144 | ||
1145 | /** | |
1146 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1147 | * @chan: the DMA channel to stop | |
1148 | * | |
1149 | * Must be called with soft interrupts disabled. | |
1150 | */ | |
1151 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1152 | { | |
1153 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1154 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1155 | unsigned long flags; |
d9de4519 | 1156 | |
69cea5a0 | 1157 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1158 | |
3f936207 | 1159 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1160 | |
69cea5a0 | 1161 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1162 | } |
1163 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1164 | ||
1165 | /** | |
1166 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1167 | * @chan: the DMA channel to prepare | |
1168 | * @buf_addr: physical DMA address where the buffer starts | |
1169 | * @buf_len: total number of bytes for the entire buffer | |
1170 | * @period_len: number of bytes for each period | |
1171 | * @direction: transfer direction, to or from device | |
1172 | * | |
1173 | * Must be called before trying to start the transfer. Returns a valid struct | |
1174 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1175 | */ | |
1176 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1177 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1178 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1179 | { |
1180 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1181 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1182 | struct dw_cyclic_desc *cdesc; |
1183 | struct dw_cyclic_desc *retval = NULL; | |
1184 | struct dw_desc *desc; | |
1185 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1186 | unsigned long was_cyclic; |
1187 | unsigned int reg_width; | |
1188 | unsigned int periods; | |
1189 | unsigned int i; | |
69cea5a0 | 1190 | unsigned long flags; |
d9de4519 | 1191 | |
69cea5a0 | 1192 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1193 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1194 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1195 | dev_dbg(chan2dev(&dwc->chan), |
1196 | "queue and/or active list are not empty\n"); | |
1197 | return ERR_PTR(-EBUSY); | |
1198 | } | |
1199 | ||
1200 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1201 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1202 | if (was_cyclic) { |
1203 | dev_dbg(chan2dev(&dwc->chan), | |
1204 | "channel already prepared for cyclic DMA\n"); | |
1205 | return ERR_PTR(-EBUSY); | |
1206 | } | |
1207 | ||
1208 | retval = ERR_PTR(-EINVAL); | |
327e6970 VK |
1209 | |
1210 | if (direction == DMA_MEM_TO_DEV) | |
1211 | reg_width = __ffs(sconfig->dst_addr_width); | |
1212 | else | |
1213 | reg_width = __ffs(sconfig->src_addr_width); | |
1214 | ||
d9de4519 HCE |
1215 | periods = buf_len / period_len; |
1216 | ||
1217 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
1218 | if (period_len > (DWC_MAX_COUNT << reg_width)) | |
1219 | goto out_err; | |
1220 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1221 | goto out_err; | |
1222 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1223 | goto out_err; | |
db8196df | 1224 | if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM)))) |
d9de4519 HCE |
1225 | goto out_err; |
1226 | ||
1227 | retval = ERR_PTR(-ENOMEM); | |
1228 | ||
1229 | if (periods > NR_DESCS_PER_CHANNEL) | |
1230 | goto out_err; | |
1231 | ||
1232 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1233 | if (!cdesc) | |
1234 | goto out_err; | |
1235 | ||
1236 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1237 | if (!cdesc->desc) | |
1238 | goto out_err_alloc; | |
1239 | ||
1240 | for (i = 0; i < periods; i++) { | |
1241 | desc = dwc_desc_get(dwc); | |
1242 | if (!desc) | |
1243 | goto out_err_desc_get; | |
1244 | ||
1245 | switch (direction) { | |
db8196df | 1246 | case DMA_MEM_TO_DEV: |
327e6970 | 1247 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1248 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1249 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1250 | | DWC_CTLL_DST_WIDTH(reg_width) |
1251 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1252 | | DWC_CTLL_DST_FIX | |
1253 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1254 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1255 | |
1256 | desc->lli.ctllo |= sconfig->device_fc ? | |
1257 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1258 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1259 | ||
d9de4519 | 1260 | break; |
db8196df | 1261 | case DMA_DEV_TO_MEM: |
d9de4519 | 1262 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1263 | desc->lli.sar = sconfig->src_addr; |
1264 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1265 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1266 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1267 | | DWC_CTLL_DST_INC | |
1268 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1269 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1270 | |
1271 | desc->lli.ctllo |= sconfig->device_fc ? | |
1272 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1273 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1274 | ||
d9de4519 HCE |
1275 | break; |
1276 | default: | |
1277 | break; | |
1278 | } | |
1279 | ||
1280 | desc->lli.ctlhi = (period_len >> reg_width); | |
1281 | cdesc->desc[i] = desc; | |
1282 | ||
1283 | if (last) { | |
1284 | last->lli.llp = desc->txd.phys; | |
1285 | dma_sync_single_for_device(chan2parent(chan), | |
1286 | last->txd.phys, sizeof(last->lli), | |
1287 | DMA_TO_DEVICE); | |
1288 | } | |
1289 | ||
1290 | last = desc; | |
1291 | } | |
1292 | ||
1293 | /* lets make a cyclic list */ | |
1294 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1295 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1296 | sizeof(last->lli), DMA_TO_DEVICE); | |
1297 | ||
2f45d613 AS |
1298 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1299 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1300 | buf_len, period_len, periods); | |
d9de4519 HCE |
1301 | |
1302 | cdesc->periods = periods; | |
1303 | dwc->cdesc = cdesc; | |
1304 | ||
1305 | return cdesc; | |
1306 | ||
1307 | out_err_desc_get: | |
1308 | while (i--) | |
1309 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1310 | out_err_alloc: | |
1311 | kfree(cdesc); | |
1312 | out_err: | |
1313 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1314 | return (struct dw_cyclic_desc *)retval; | |
1315 | } | |
1316 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1317 | ||
1318 | /** | |
1319 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1320 | * @chan: the DMA channel to free | |
1321 | */ | |
1322 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1323 | { | |
1324 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1325 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1326 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1327 | int i; | |
69cea5a0 | 1328 | unsigned long flags; |
d9de4519 | 1329 | |
2e4c364e | 1330 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1331 | |
1332 | if (!cdesc) | |
1333 | return; | |
1334 | ||
69cea5a0 | 1335 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1336 | |
3f936207 | 1337 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1338 | |
d9de4519 HCE |
1339 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1340 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1341 | ||
69cea5a0 | 1342 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1343 | |
1344 | for (i = 0; i < cdesc->periods; i++) | |
1345 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1346 | ||
1347 | kfree(cdesc->desc); | |
1348 | kfree(cdesc); | |
1349 | ||
1350 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1351 | } | |
1352 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1353 | ||
3bfb1d20 HS |
1354 | /*----------------------------------------------------------------------*/ |
1355 | ||
1356 | static void dw_dma_off(struct dw_dma *dw) | |
1357 | { | |
61e183f8 VK |
1358 | int i; |
1359 | ||
3bfb1d20 HS |
1360 | dma_writel(dw, CFG, 0); |
1361 | ||
1362 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1363 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1364 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1365 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1366 | ||
1367 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1368 | cpu_relax(); | |
61e183f8 VK |
1369 | |
1370 | for (i = 0; i < dw->dma.chancnt; i++) | |
1371 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1372 | } |
1373 | ||
0272e93f | 1374 | static int __devinit dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1375 | { |
1376 | struct dw_dma_platform_data *pdata; | |
1377 | struct resource *io; | |
1378 | struct dw_dma *dw; | |
1379 | size_t size; | |
1380 | int irq; | |
1381 | int err; | |
1382 | int i; | |
1383 | ||
6c618c9d | 1384 | pdata = dev_get_platdata(&pdev->dev); |
3bfb1d20 HS |
1385 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) |
1386 | return -EINVAL; | |
1387 | ||
1388 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1389 | if (!io) | |
1390 | return -EINVAL; | |
1391 | ||
1392 | irq = platform_get_irq(pdev, 0); | |
1393 | if (irq < 0) | |
1394 | return irq; | |
1395 | ||
1396 | size = sizeof(struct dw_dma); | |
1397 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
1398 | dw = kzalloc(size, GFP_KERNEL); | |
1399 | if (!dw) | |
1400 | return -ENOMEM; | |
1401 | ||
1402 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
1403 | err = -EBUSY; | |
1404 | goto err_kfree; | |
1405 | } | |
1406 | ||
3bfb1d20 HS |
1407 | dw->regs = ioremap(io->start, DW_REGLEN); |
1408 | if (!dw->regs) { | |
1409 | err = -ENOMEM; | |
1410 | goto err_release_r; | |
1411 | } | |
1412 | ||
1413 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
1414 | if (IS_ERR(dw->clk)) { | |
1415 | err = PTR_ERR(dw->clk); | |
1416 | goto err_clk; | |
1417 | } | |
3075528d | 1418 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1419 | |
11f932ec AS |
1420 | /* Calculate all channel mask before DMA setup */ |
1421 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1422 | ||
3bfb1d20 HS |
1423 | /* force dma off, just in case */ |
1424 | dw_dma_off(dw); | |
1425 | ||
236b106f AS |
1426 | /* disable BLOCK interrupts as well */ |
1427 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1428 | ||
3bfb1d20 HS |
1429 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); |
1430 | if (err) | |
1431 | goto err_irq; | |
1432 | ||
1433 | platform_set_drvdata(pdev, dw); | |
1434 | ||
1435 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1436 | ||
3bfb1d20 | 1437 | INIT_LIST_HEAD(&dw->dma.channels); |
46389470 | 1438 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1439 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1440 | ||
1441 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1442 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1443 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1444 | list_add_tail(&dwc->chan.device_node, | |
1445 | &dw->dma.channels); | |
1446 | else | |
1447 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1448 | |
93317e8e VK |
1449 | /* 7 is highest priority & 0 is lowest. */ |
1450 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
e8d9f875 | 1451 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1452 | else |
1453 | dwc->priority = i; | |
1454 | ||
3bfb1d20 HS |
1455 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1456 | spin_lock_init(&dwc->lock); | |
1457 | dwc->mask = 1 << i; | |
1458 | ||
1459 | INIT_LIST_HEAD(&dwc->active_list); | |
1460 | INIT_LIST_HEAD(&dwc->queue); | |
1461 | INIT_LIST_HEAD(&dwc->free_list); | |
1462 | ||
1463 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1464 | } | |
1465 | ||
11f932ec | 1466 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1467 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1468 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1469 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1470 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1471 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1472 | ||
3bfb1d20 HS |
1473 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1474 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1475 | if (pdata->is_private) |
1476 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1477 | dw->dma.dev = &pdev->dev; |
1478 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1479 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1480 | ||
1481 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1482 | ||
1483 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1484 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1485 | |
07934481 | 1486 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1487 | dw->dma.device_issue_pending = dwc_issue_pending; |
1488 | ||
1489 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1490 | ||
1491 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
46389470 | 1492 | dev_name(&pdev->dev), pdata->nr_channels); |
3bfb1d20 HS |
1493 | |
1494 | dma_async_device_register(&dw->dma); | |
1495 | ||
1496 | return 0; | |
1497 | ||
1498 | err_irq: | |
3075528d | 1499 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1500 | clk_put(dw->clk); |
1501 | err_clk: | |
1502 | iounmap(dw->regs); | |
1503 | dw->regs = NULL; | |
1504 | err_release_r: | |
1505 | release_resource(io); | |
1506 | err_kfree: | |
1507 | kfree(dw); | |
1508 | return err; | |
1509 | } | |
1510 | ||
0272e93f | 1511 | static int __devexit dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1512 | { |
1513 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1514 | struct dw_dma_chan *dwc, *_dwc; | |
1515 | struct resource *io; | |
1516 | ||
1517 | dw_dma_off(dw); | |
1518 | dma_async_device_unregister(&dw->dma); | |
1519 | ||
1520 | free_irq(platform_get_irq(pdev, 0), dw); | |
1521 | tasklet_kill(&dw->tasklet); | |
1522 | ||
1523 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1524 | chan.device_node) { | |
1525 | list_del(&dwc->chan.device_node); | |
1526 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1527 | } | |
1528 | ||
3075528d | 1529 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1530 | clk_put(dw->clk); |
1531 | ||
1532 | iounmap(dw->regs); | |
1533 | dw->regs = NULL; | |
1534 | ||
1535 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1536 | release_mem_region(io->start, DW_REGLEN); | |
1537 | ||
1538 | kfree(dw); | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static void dw_shutdown(struct platform_device *pdev) | |
1544 | { | |
1545 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1546 | ||
1547 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1548 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1549 | } |
1550 | ||
4a256b5f | 1551 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1552 | { |
4a256b5f | 1553 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1554 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1555 | ||
1556 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1557 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1558 | |
3bfb1d20 HS |
1559 | return 0; |
1560 | } | |
1561 | ||
4a256b5f | 1562 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1563 | { |
4a256b5f | 1564 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1565 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1566 | ||
3075528d | 1567 | clk_prepare_enable(dw->clk); |
3bfb1d20 HS |
1568 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
1569 | return 0; | |
3bfb1d20 HS |
1570 | } |
1571 | ||
47145210 | 1572 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1573 | .suspend_noirq = dw_suspend_noirq, |
1574 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1575 | .freeze_noirq = dw_suspend_noirq, |
1576 | .thaw_noirq = dw_resume_noirq, | |
1577 | .restore_noirq = dw_resume_noirq, | |
1578 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1579 | }; |
1580 | ||
d3f797d9 VK |
1581 | #ifdef CONFIG_OF |
1582 | static const struct of_device_id dw_dma_id_table[] = { | |
1583 | { .compatible = "snps,dma-spear1340" }, | |
1584 | {} | |
1585 | }; | |
1586 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1587 | #endif | |
1588 | ||
3bfb1d20 | 1589 | static struct platform_driver dw_driver = { |
0272e93f | 1590 | .remove = __devexit_p(dw_remove), |
3bfb1d20 | 1591 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1592 | .driver = { |
1593 | .name = "dw_dmac", | |
4a256b5f | 1594 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1595 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 HS |
1596 | }, |
1597 | }; | |
1598 | ||
1599 | static int __init dw_init(void) | |
1600 | { | |
1601 | return platform_driver_probe(&dw_driver, dw_probe); | |
1602 | } | |
cb689a70 | 1603 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1604 | |
1605 | static void __exit dw_exit(void) | |
1606 | { | |
1607 | platform_driver_unregister(&dw_driver); | |
1608 | } | |
1609 | module_exit(dw_exit); | |
1610 | ||
1611 | MODULE_LICENSE("GPL v2"); | |
1612 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1613 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
aecb7b64 | 1614 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); |