Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
b801479b | 11 | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
3bfb1d20 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
d3f797d9 | 21 | #include <linux/of.h> |
3bfb1d20 HS |
22 | #include <linux/mm.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | ||
27 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 28 | #include "dmaengine.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
36 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
37 | * which does not support descriptor writeback. | |
38 | */ | |
39 | ||
a0982004 AS |
40 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
41 | { | |
42 | return slave ? slave->dst_master : 0; | |
43 | } | |
44 | ||
45 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
46 | { | |
47 | return slave ? slave->src_master : 1; | |
48 | } | |
49 | ||
5be10f34 AS |
50 | #define SRC_MASTER 0 |
51 | #define DST_MASTER 1 | |
52 | ||
53 | static inline unsigned int dwc_get_master(struct dma_chan *chan, int master) | |
54 | { | |
55 | struct dw_dma *dw = to_dw_dma(chan->device); | |
56 | struct dw_dma_slave *dws = chan->private; | |
57 | unsigned int m; | |
58 | ||
59 | if (master == SRC_MASTER) | |
60 | m = dwc_get_sms(dws); | |
61 | else | |
62 | m = dwc_get_dms(dws); | |
63 | ||
64 | return min_t(unsigned int, dw->nr_masters - 1, m); | |
65 | } | |
66 | ||
327e6970 | 67 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
68 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
69 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 70 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
5be10f34 AS |
71 | int _dms = dwc_get_master(_chan, DST_MASTER); \ |
72 | int _sms = dwc_get_master(_chan, SRC_MASTER); \ | |
495aea4b | 73 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 74 | DW_DMA_MSIZE_16; \ |
495aea4b | 75 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 76 | DW_DMA_MSIZE_16; \ |
f301c062 | 77 | \ |
327e6970 VK |
78 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
79 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
80 | | DWC_CTLL_LLP_D_EN \ |
81 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
82 | | DWC_CTLL_DMS(_dms) \ |
83 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 84 | }) |
3bfb1d20 | 85 | |
3bfb1d20 HS |
86 | /* |
87 | * Number of descriptors to allocate for each channel. This should be | |
88 | * made configurable somehow; preferably, the clients (at least the | |
89 | * ones using slave transfers) should be able to give us a hint. | |
90 | */ | |
91 | #define NR_DESCS_PER_CHANNEL 64 | |
92 | ||
23d5f4ec AS |
93 | static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master) |
94 | { | |
95 | struct dw_dma *dw = to_dw_dma(chan->device); | |
23d5f4ec | 96 | |
5be10f34 | 97 | return dw->data_width[dwc_get_master(chan, master)]; |
23d5f4ec AS |
98 | } |
99 | ||
3bfb1d20 HS |
100 | /*----------------------------------------------------------------------*/ |
101 | ||
41d5e59c DW |
102 | static struct device *chan2dev(struct dma_chan *chan) |
103 | { | |
104 | return &chan->dev->device; | |
105 | } | |
106 | static struct device *chan2parent(struct dma_chan *chan) | |
107 | { | |
108 | return chan->dev->device.parent; | |
109 | } | |
110 | ||
3bfb1d20 HS |
111 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
112 | { | |
e63a47a3 | 113 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
114 | } |
115 | ||
3bfb1d20 HS |
116 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
117 | { | |
118 | struct dw_desc *desc, *_desc; | |
119 | struct dw_desc *ret = NULL; | |
120 | unsigned int i = 0; | |
69cea5a0 | 121 | unsigned long flags; |
3bfb1d20 | 122 | |
69cea5a0 | 123 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 124 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 125 | i++; |
3bfb1d20 HS |
126 | if (async_tx_test_ack(&desc->txd)) { |
127 | list_del(&desc->desc_node); | |
128 | ret = desc; | |
129 | break; | |
130 | } | |
41d5e59c | 131 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 132 | } |
69cea5a0 | 133 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 134 | |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
136 | |
137 | return ret; | |
138 | } | |
139 | ||
3bfb1d20 HS |
140 | /* |
141 | * Move a descriptor, including any children, to the free list. | |
142 | * `desc' must not be on any lists. | |
143 | */ | |
144 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
145 | { | |
69cea5a0 VK |
146 | unsigned long flags; |
147 | ||
3bfb1d20 HS |
148 | if (desc) { |
149 | struct dw_desc *child; | |
150 | ||
69cea5a0 | 151 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 152 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 153 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
154 | "moving child desc %p to freelist\n", |
155 | child); | |
e0bd0f8c | 156 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 157 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 158 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 159 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
160 | } |
161 | } | |
162 | ||
61e183f8 VK |
163 | static void dwc_initialize(struct dw_dma_chan *dwc) |
164 | { | |
165 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
166 | struct dw_dma_slave *dws = dwc->chan.private; | |
167 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
168 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
169 | ||
170 | if (dwc->initialized == true) | |
171 | return; | |
172 | ||
173 | if (dws) { | |
174 | /* | |
175 | * We need controller-specific data to set up slave | |
176 | * transfers. | |
177 | */ | |
178 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
179 | ||
180 | cfghi = dws->cfg_hi; | |
181 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 182 | } else { |
0fdb567f | 183 | if (dwc->direction == DMA_MEM_TO_DEV) |
8fccc5bf | 184 | cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); |
0fdb567f | 185 | else if (dwc->direction == DMA_DEV_TO_MEM) |
8fccc5bf | 186 | cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); |
61e183f8 VK |
187 | } |
188 | ||
189 | channel_writel(dwc, CFG_LO, cfglo); | |
190 | channel_writel(dwc, CFG_HI, cfghi); | |
191 | ||
192 | /* Enable interrupts */ | |
193 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
194 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
195 | ||
196 | dwc->initialized = true; | |
197 | } | |
198 | ||
3bfb1d20 HS |
199 | /*----------------------------------------------------------------------*/ |
200 | ||
4c2d56c5 AS |
201 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
202 | { | |
203 | /* | |
204 | * We can be a lot more clever here, but this should take care | |
205 | * of the most common optimization. | |
206 | */ | |
207 | if (!(v & 7)) | |
208 | return 3; | |
209 | else if (!(v & 3)) | |
210 | return 2; | |
211 | else if (!(v & 1)) | |
212 | return 1; | |
213 | return 0; | |
214 | } | |
215 | ||
f52b36d2 | 216 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
217 | { |
218 | dev_err(chan2dev(&dwc->chan), | |
219 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
220 | channel_readl(dwc, SAR), | |
221 | channel_readl(dwc, DAR), | |
222 | channel_readl(dwc, LLP), | |
223 | channel_readl(dwc, CTL_HI), | |
224 | channel_readl(dwc, CTL_LO)); | |
225 | } | |
226 | ||
3f936207 AS |
227 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
228 | { | |
229 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
230 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
231 | cpu_relax(); | |
232 | } | |
233 | ||
1d455437 AS |
234 | /*----------------------------------------------------------------------*/ |
235 | ||
fed2574b AS |
236 | /* Perform single block transfer */ |
237 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
238 | struct dw_desc *desc) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
241 | u32 ctllo; | |
242 | ||
243 | /* Software emulation of LLP mode relies on interrupts to continue | |
244 | * multi block transfer. */ | |
245 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
246 | ||
247 | channel_writel(dwc, SAR, desc->lli.sar); | |
248 | channel_writel(dwc, DAR, desc->lli.dar); | |
249 | channel_writel(dwc, CTL_LO, ctllo); | |
250 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
251 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
252 | |
253 | /* Move pointer to next descriptor */ | |
254 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
255 | } |
256 | ||
3bfb1d20 HS |
257 | /* Called with dwc->lock held and bh disabled */ |
258 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
259 | { | |
260 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 261 | unsigned long was_soft_llp; |
3bfb1d20 HS |
262 | |
263 | /* ASSERT: channel is idle */ | |
264 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 265 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 266 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 267 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
268 | |
269 | /* The tasklet will hopefully advance the queue... */ | |
270 | return; | |
271 | } | |
272 | ||
fed2574b AS |
273 | if (dwc->nollp) { |
274 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
275 | &dwc->flags); | |
276 | if (was_soft_llp) { | |
277 | dev_err(chan2dev(&dwc->chan), | |
278 | "BUG: Attempted to start new LLP transfer " | |
279 | "inside ongoing one\n"); | |
280 | return; | |
281 | } | |
282 | ||
283 | dwc_initialize(dwc); | |
284 | ||
4702d524 | 285 | dwc->residue = first->total_len; |
f5c6a7df | 286 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 287 | |
fdf475fa | 288 | /* Submit first block */ |
fed2574b AS |
289 | dwc_do_single_block(dwc, first); |
290 | ||
291 | return; | |
292 | } | |
293 | ||
61e183f8 VK |
294 | dwc_initialize(dwc); |
295 | ||
3bfb1d20 HS |
296 | channel_writel(dwc, LLP, first->txd.phys); |
297 | channel_writel(dwc, CTL_LO, | |
298 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
299 | channel_writel(dwc, CTL_HI, 0); | |
300 | channel_set_bit(dw, CH_EN, dwc->mask); | |
301 | } | |
302 | ||
303 | /*----------------------------------------------------------------------*/ | |
304 | ||
305 | static void | |
5fedefb8 VK |
306 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
307 | bool callback_required) | |
3bfb1d20 | 308 | { |
5fedefb8 VK |
309 | dma_async_tx_callback callback = NULL; |
310 | void *param = NULL; | |
3bfb1d20 | 311 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 312 | struct dw_desc *child; |
69cea5a0 | 313 | unsigned long flags; |
3bfb1d20 | 314 | |
41d5e59c | 315 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 316 | |
69cea5a0 | 317 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 318 | dma_cookie_complete(txd); |
5fedefb8 VK |
319 | if (callback_required) { |
320 | callback = txd->callback; | |
321 | param = txd->callback_param; | |
322 | } | |
3bfb1d20 | 323 | |
e518076e VK |
324 | /* async_tx_ack */ |
325 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
326 | async_tx_ack(&child->txd); | |
327 | async_tx_ack(&desc->txd); | |
328 | ||
e0bd0f8c | 329 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
330 | list_move(&desc->desc_node, &dwc->free_list); |
331 | ||
495aea4b | 332 | if (!is_slave_direction(dwc->direction)) { |
657a77fa AN |
333 | struct device *parent = chan2parent(&dwc->chan); |
334 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
335 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
336 | dma_unmap_single(parent, desc->lli.dar, | |
30d38a32 | 337 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
338 | else |
339 | dma_unmap_page(parent, desc->lli.dar, | |
30d38a32 | 340 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
341 | } |
342 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
343 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
344 | dma_unmap_single(parent, desc->lli.sar, | |
30d38a32 | 345 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
346 | else |
347 | dma_unmap_page(parent, desc->lli.sar, | |
30d38a32 | 348 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
349 | } |
350 | } | |
3bfb1d20 | 351 | |
69cea5a0 VK |
352 | spin_unlock_irqrestore(&dwc->lock, flags); |
353 | ||
21e93c1e | 354 | if (callback) |
3bfb1d20 HS |
355 | callback(param); |
356 | } | |
357 | ||
358 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
359 | { | |
360 | struct dw_desc *desc, *_desc; | |
361 | LIST_HEAD(list); | |
69cea5a0 | 362 | unsigned long flags; |
3bfb1d20 | 363 | |
69cea5a0 | 364 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 365 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 366 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
367 | "BUG: XFER bit set, but channel not idle!\n"); |
368 | ||
369 | /* Try to continue after resetting the channel... */ | |
3f936207 | 370 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
371 | } |
372 | ||
373 | /* | |
374 | * Submit queued descriptors ASAP, i.e. before we go through | |
375 | * the completed ones. | |
376 | */ | |
3bfb1d20 | 377 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
378 | if (!list_empty(&dwc->queue)) { |
379 | list_move(dwc->queue.next, &dwc->active_list); | |
380 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
381 | } | |
3bfb1d20 | 382 | |
69cea5a0 VK |
383 | spin_unlock_irqrestore(&dwc->lock, flags); |
384 | ||
3bfb1d20 | 385 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 386 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
387 | } |
388 | ||
4702d524 AS |
389 | /* Returns how many bytes were already received from source */ |
390 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
391 | { | |
392 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
393 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
394 | ||
395 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
396 | } | |
397 | ||
3bfb1d20 HS |
398 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
399 | { | |
400 | dma_addr_t llp; | |
401 | struct dw_desc *desc, *_desc; | |
402 | struct dw_desc *child; | |
403 | u32 status_xfer; | |
69cea5a0 | 404 | unsigned long flags; |
3bfb1d20 | 405 | |
69cea5a0 | 406 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
407 | llp = channel_readl(dwc, LLP); |
408 | status_xfer = dma_readl(dw, RAW.XFER); | |
409 | ||
410 | if (status_xfer & dwc->mask) { | |
411 | /* Everything we've submitted is done */ | |
412 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
413 | |
414 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
415 | struct list_head *head, *active = dwc->tx_node_active; |
416 | ||
417 | /* | |
418 | * We are inside first active descriptor. | |
419 | * Otherwise something is really wrong. | |
420 | */ | |
421 | desc = dwc_first_active(dwc); | |
422 | ||
423 | head = &desc->tx_list; | |
424 | if (active != head) { | |
4702d524 AS |
425 | /* Update desc to reflect last sent one */ |
426 | if (active != head->next) | |
427 | desc = to_dw_desc(active->prev); | |
428 | ||
429 | dwc->residue -= desc->len; | |
430 | ||
fdf475fa | 431 | child = to_dw_desc(active); |
77bcc497 AS |
432 | |
433 | /* Submit next block */ | |
fdf475fa | 434 | dwc_do_single_block(dwc, child); |
77bcc497 | 435 | |
fdf475fa | 436 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
437 | return; |
438 | } | |
fdf475fa | 439 | |
77bcc497 AS |
440 | /* We are done here */ |
441 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
442 | } | |
4702d524 AS |
443 | |
444 | dwc->residue = 0; | |
445 | ||
69cea5a0 VK |
446 | spin_unlock_irqrestore(&dwc->lock, flags); |
447 | ||
3bfb1d20 HS |
448 | dwc_complete_all(dw, dwc); |
449 | return; | |
450 | } | |
451 | ||
69cea5a0 | 452 | if (list_empty(&dwc->active_list)) { |
4702d524 | 453 | dwc->residue = 0; |
69cea5a0 | 454 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 455 | return; |
69cea5a0 | 456 | } |
087809fc | 457 | |
77bcc497 AS |
458 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
459 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
460 | spin_unlock_irqrestore(&dwc->lock, flags); | |
461 | return; | |
462 | } | |
463 | ||
2e4c364e | 464 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 465 | (unsigned long long)llp); |
3bfb1d20 HS |
466 | |
467 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
4702d524 AS |
468 | /* initial residue value */ |
469 | dwc->residue = desc->total_len; | |
470 | ||
84adccfb | 471 | /* check first descriptors addr */ |
69cea5a0 VK |
472 | if (desc->txd.phys == llp) { |
473 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 474 | return; |
69cea5a0 | 475 | } |
84adccfb VK |
476 | |
477 | /* check first descriptors llp */ | |
69cea5a0 | 478 | if (desc->lli.llp == llp) { |
3bfb1d20 | 479 | /* This one is currently in progress */ |
4702d524 | 480 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 481 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 482 | return; |
69cea5a0 | 483 | } |
3bfb1d20 | 484 | |
4702d524 AS |
485 | dwc->residue -= desc->len; |
486 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 487 | if (child->lli.llp == llp) { |
3bfb1d20 | 488 | /* Currently in progress */ |
4702d524 | 489 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 490 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 491 | return; |
69cea5a0 | 492 | } |
4702d524 AS |
493 | dwc->residue -= child->len; |
494 | } | |
3bfb1d20 HS |
495 | |
496 | /* | |
497 | * No descriptors so far seem to be in progress, i.e. | |
498 | * this one must be done. | |
499 | */ | |
69cea5a0 | 500 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 501 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 502 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
503 | } |
504 | ||
41d5e59c | 505 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
506 | "BUG: All descriptors done, but channel not idle!\n"); |
507 | ||
508 | /* Try to continue after resetting the channel... */ | |
3f936207 | 509 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
510 | |
511 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
512 | list_move(dwc->queue.next, &dwc->active_list); |
513 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 514 | } |
69cea5a0 | 515 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
516 | } |
517 | ||
93aad1bc | 518 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 519 | { |
21d43f49 AS |
520 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
521 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
522 | } |
523 | ||
524 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
525 | { | |
526 | struct dw_desc *bad_desc; | |
527 | struct dw_desc *child; | |
69cea5a0 | 528 | unsigned long flags; |
3bfb1d20 HS |
529 | |
530 | dwc_scan_descriptors(dw, dwc); | |
531 | ||
69cea5a0 VK |
532 | spin_lock_irqsave(&dwc->lock, flags); |
533 | ||
3bfb1d20 HS |
534 | /* |
535 | * The descriptor currently at the head of the active list is | |
536 | * borked. Since we don't have any way to report errors, we'll | |
537 | * just have to scream loudly and try to carry on. | |
538 | */ | |
539 | bad_desc = dwc_first_active(dwc); | |
540 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 541 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
542 | |
543 | /* Clear the error flag and try to restart the controller */ | |
544 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
545 | if (!list_empty(&dwc->active_list)) | |
546 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
547 | ||
548 | /* | |
ba84bd71 | 549 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
550 | * when someone submits a bad physical address in a |
551 | * descriptor, we should consider ourselves lucky that the | |
552 | * controller flagged an error instead of scribbling over | |
553 | * random memory locations. | |
554 | */ | |
ba84bd71 AS |
555 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
556 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 557 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 558 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
559 | dwc_dump_lli(dwc, &child->lli); |
560 | ||
69cea5a0 VK |
561 | spin_unlock_irqrestore(&dwc->lock, flags); |
562 | ||
3bfb1d20 | 563 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 564 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
565 | } |
566 | ||
d9de4519 HCE |
567 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
568 | ||
569 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
570 | { | |
571 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
572 | return channel_readl(dwc, SAR); | |
573 | } | |
574 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
575 | ||
576 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
577 | { | |
578 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
579 | return channel_readl(dwc, DAR); | |
580 | } | |
581 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
582 | ||
583 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
584 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 585 | u32 status_err, u32 status_xfer) |
d9de4519 | 586 | { |
69cea5a0 VK |
587 | unsigned long flags; |
588 | ||
ff7b05f2 | 589 | if (dwc->mask) { |
d9de4519 HCE |
590 | void (*callback)(void *param); |
591 | void *callback_param; | |
592 | ||
593 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
594 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
595 | |
596 | callback = dwc->cdesc->period_callback; | |
597 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
598 | |
599 | if (callback) | |
d9de4519 | 600 | callback(callback_param); |
d9de4519 HCE |
601 | } |
602 | ||
603 | /* | |
604 | * Error and transfer complete are highly unlikely, and will most | |
605 | * likely be due to a configuration error by the user. | |
606 | */ | |
607 | if (unlikely(status_err & dwc->mask) || | |
608 | unlikely(status_xfer & dwc->mask)) { | |
609 | int i; | |
610 | ||
611 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
612 | "interrupt, stopping DMA transfer\n", | |
613 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
614 | |
615 | spin_lock_irqsave(&dwc->lock, flags); | |
616 | ||
1d455437 | 617 | dwc_dump_chan_regs(dwc); |
d9de4519 | 618 | |
3f936207 | 619 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
620 | |
621 | /* make sure DMA does not restart by loading a new list */ | |
622 | channel_writel(dwc, LLP, 0); | |
623 | channel_writel(dwc, CTL_LO, 0); | |
624 | channel_writel(dwc, CTL_HI, 0); | |
625 | ||
d9de4519 HCE |
626 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
627 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
628 | ||
629 | for (i = 0; i < dwc->cdesc->periods; i++) | |
630 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
631 | |
632 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
633 | } |
634 | } | |
635 | ||
636 | /* ------------------------------------------------------------------------- */ | |
637 | ||
3bfb1d20 HS |
638 | static void dw_dma_tasklet(unsigned long data) |
639 | { | |
640 | struct dw_dma *dw = (struct dw_dma *)data; | |
641 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
642 | u32 status_xfer; |
643 | u32 status_err; | |
644 | int i; | |
645 | ||
7fe7b2f4 | 646 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
647 | status_err = dma_readl(dw, RAW.ERROR); |
648 | ||
2e4c364e | 649 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
650 | |
651 | for (i = 0; i < dw->dma.chancnt; i++) { | |
652 | dwc = &dw->chan[i]; | |
d9de4519 | 653 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 654 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 655 | else if (status_err & (1 << i)) |
3bfb1d20 | 656 | dwc_handle_error(dw, dwc); |
77bcc497 | 657 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 658 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
659 | } |
660 | ||
661 | /* | |
ff7b05f2 | 662 | * Re-enable interrupts. |
3bfb1d20 HS |
663 | */ |
664 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
665 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
666 | } | |
667 | ||
668 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
669 | { | |
670 | struct dw_dma *dw = dev_id; | |
671 | u32 status; | |
672 | ||
2e4c364e | 673 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
674 | dma_readl(dw, STATUS_INT)); |
675 | ||
676 | /* | |
677 | * Just disable the interrupts. We'll turn them back on in the | |
678 | * softirq handler. | |
679 | */ | |
680 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
681 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
682 | ||
683 | status = dma_readl(dw, STATUS_INT); | |
684 | if (status) { | |
685 | dev_err(dw->dma.dev, | |
686 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
687 | status); | |
688 | ||
689 | /* Try to recover */ | |
690 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
691 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
692 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
693 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
694 | } | |
695 | ||
696 | tasklet_schedule(&dw->tasklet); | |
697 | ||
698 | return IRQ_HANDLED; | |
699 | } | |
700 | ||
701 | /*----------------------------------------------------------------------*/ | |
702 | ||
703 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
704 | { | |
705 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
706 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
707 | dma_cookie_t cookie; | |
69cea5a0 | 708 | unsigned long flags; |
3bfb1d20 | 709 | |
69cea5a0 | 710 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 711 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
712 | |
713 | /* | |
714 | * REVISIT: We should attempt to chain as many descriptors as | |
715 | * possible, perhaps even appending to those already submitted | |
716 | * for DMA. But this is hard to do in a race-free manner. | |
717 | */ | |
718 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 719 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 720 | desc->txd.cookie); |
3bfb1d20 | 721 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 722 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 723 | } else { |
2e4c364e | 724 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
725 | desc->txd.cookie); |
726 | ||
727 | list_add_tail(&desc->desc_node, &dwc->queue); | |
728 | } | |
729 | ||
69cea5a0 | 730 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
731 | |
732 | return cookie; | |
733 | } | |
734 | ||
735 | static struct dma_async_tx_descriptor * | |
736 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
737 | size_t len, unsigned long flags) | |
738 | { | |
739 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
740 | struct dw_desc *desc; | |
741 | struct dw_desc *first; | |
742 | struct dw_desc *prev; | |
743 | size_t xfer_count; | |
744 | size_t offset; | |
745 | unsigned int src_width; | |
746 | unsigned int dst_width; | |
3d4f8605 | 747 | unsigned int data_width; |
3bfb1d20 HS |
748 | u32 ctllo; |
749 | ||
2f45d613 | 750 | dev_vdbg(chan2dev(chan), |
2e4c364e | 751 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
752 | (unsigned long long)dest, (unsigned long long)src, |
753 | len, flags); | |
3bfb1d20 HS |
754 | |
755 | if (unlikely(!len)) { | |
2e4c364e | 756 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
757 | return NULL; |
758 | } | |
759 | ||
0fdb567f AS |
760 | dwc->direction = DMA_MEM_TO_MEM; |
761 | ||
23d5f4ec AS |
762 | data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER), |
763 | dwc_get_data_width(chan, DST_MASTER)); | |
a0982004 | 764 | |
3d4f8605 AS |
765 | src_width = dst_width = min_t(unsigned int, data_width, |
766 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 767 | |
327e6970 | 768 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
769 | | DWC_CTLL_DST_WIDTH(dst_width) |
770 | | DWC_CTLL_SRC_WIDTH(src_width) | |
771 | | DWC_CTLL_DST_INC | |
772 | | DWC_CTLL_SRC_INC | |
773 | | DWC_CTLL_FC_M2M; | |
774 | prev = first = NULL; | |
775 | ||
776 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
777 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 778 | dwc->block_size); |
3bfb1d20 HS |
779 | |
780 | desc = dwc_desc_get(dwc); | |
781 | if (!desc) | |
782 | goto err_desc_get; | |
783 | ||
784 | desc->lli.sar = src + offset; | |
785 | desc->lli.dar = dest + offset; | |
786 | desc->lli.ctllo = ctllo; | |
787 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 788 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
789 | |
790 | if (!first) { | |
791 | first = desc; | |
792 | } else { | |
793 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 794 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 795 | &first->tx_list); |
3bfb1d20 HS |
796 | } |
797 | prev = desc; | |
798 | } | |
799 | ||
3bfb1d20 HS |
800 | if (flags & DMA_PREP_INTERRUPT) |
801 | /* Trigger interrupt after last block */ | |
802 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
803 | ||
804 | prev->lli.llp = 0; | |
3bfb1d20 | 805 | first->txd.flags = flags; |
30d38a32 | 806 | first->total_len = len; |
3bfb1d20 HS |
807 | |
808 | return &first->txd; | |
809 | ||
810 | err_desc_get: | |
811 | dwc_desc_put(dwc, first); | |
812 | return NULL; | |
813 | } | |
814 | ||
815 | static struct dma_async_tx_descriptor * | |
816 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 817 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 818 | unsigned long flags, void *context) |
3bfb1d20 HS |
819 | { |
820 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 821 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
822 | struct dw_desc *prev; |
823 | struct dw_desc *first; | |
824 | u32 ctllo; | |
825 | dma_addr_t reg; | |
826 | unsigned int reg_width; | |
827 | unsigned int mem_width; | |
a0982004 | 828 | unsigned int data_width; |
3bfb1d20 HS |
829 | unsigned int i; |
830 | struct scatterlist *sg; | |
831 | size_t total_len = 0; | |
832 | ||
2e4c364e | 833 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 834 | |
495aea4b | 835 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
836 | return NULL; |
837 | ||
0fdb567f AS |
838 | dwc->direction = direction; |
839 | ||
3bfb1d20 HS |
840 | prev = first = NULL; |
841 | ||
3bfb1d20 | 842 | switch (direction) { |
db8196df | 843 | case DMA_MEM_TO_DEV: |
327e6970 VK |
844 | reg_width = __fls(sconfig->dst_addr_width); |
845 | reg = sconfig->dst_addr; | |
846 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
847 | | DWC_CTLL_DST_WIDTH(reg_width) |
848 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
849 | | DWC_CTLL_SRC_INC); |
850 | ||
851 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
852 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
853 | ||
23d5f4ec | 854 | data_width = dwc_get_data_width(chan, SRC_MASTER); |
a0982004 | 855 | |
3bfb1d20 HS |
856 | for_each_sg(sgl, sg, sg_len, i) { |
857 | struct dw_desc *desc; | |
69dc14b5 | 858 | u32 len, dlen, mem; |
3bfb1d20 | 859 | |
cbb796cc | 860 | mem = sg_dma_address(sg); |
69dc14b5 | 861 | len = sg_dma_len(sg); |
6bc711f6 | 862 | |
a0982004 AS |
863 | mem_width = min_t(unsigned int, |
864 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 865 | |
69dc14b5 | 866 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
867 | desc = dwc_desc_get(dwc); |
868 | if (!desc) { | |
41d5e59c | 869 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
870 | "not enough descriptors available\n"); |
871 | goto err_desc_get; | |
872 | } | |
873 | ||
3bfb1d20 HS |
874 | desc->lli.sar = mem; |
875 | desc->lli.dar = reg; | |
876 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
877 | if ((len >> mem_width) > dwc->block_size) { |
878 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
879 | mem += dlen; |
880 | len -= dlen; | |
881 | } else { | |
882 | dlen = len; | |
883 | len = 0; | |
884 | } | |
885 | ||
886 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 887 | desc->len = dlen; |
3bfb1d20 HS |
888 | |
889 | if (!first) { | |
890 | first = desc; | |
891 | } else { | |
892 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 893 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 894 | &first->tx_list); |
3bfb1d20 HS |
895 | } |
896 | prev = desc; | |
69dc14b5 VK |
897 | total_len += dlen; |
898 | ||
899 | if (len) | |
900 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
901 | } |
902 | break; | |
db8196df | 903 | case DMA_DEV_TO_MEM: |
327e6970 VK |
904 | reg_width = __fls(sconfig->src_addr_width); |
905 | reg = sconfig->src_addr; | |
906 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
907 | | DWC_CTLL_SRC_WIDTH(reg_width) |
908 | | DWC_CTLL_DST_INC | |
327e6970 VK |
909 | | DWC_CTLL_SRC_FIX); |
910 | ||
911 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
912 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 913 | |
23d5f4ec | 914 | data_width = dwc_get_data_width(chan, DST_MASTER); |
a0982004 | 915 | |
3bfb1d20 HS |
916 | for_each_sg(sgl, sg, sg_len, i) { |
917 | struct dw_desc *desc; | |
69dc14b5 | 918 | u32 len, dlen, mem; |
3bfb1d20 | 919 | |
cbb796cc | 920 | mem = sg_dma_address(sg); |
3bfb1d20 | 921 | len = sg_dma_len(sg); |
6bc711f6 | 922 | |
a0982004 AS |
923 | mem_width = min_t(unsigned int, |
924 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 925 | |
69dc14b5 VK |
926 | slave_sg_fromdev_fill_desc: |
927 | desc = dwc_desc_get(dwc); | |
928 | if (!desc) { | |
929 | dev_err(chan2dev(chan), | |
930 | "not enough descriptors available\n"); | |
931 | goto err_desc_get; | |
932 | } | |
933 | ||
3bfb1d20 HS |
934 | desc->lli.sar = reg; |
935 | desc->lli.dar = mem; | |
936 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
937 | if ((len >> reg_width) > dwc->block_size) { |
938 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
939 | mem += dlen; |
940 | len -= dlen; | |
941 | } else { | |
942 | dlen = len; | |
943 | len = 0; | |
944 | } | |
945 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 946 | desc->len = dlen; |
3bfb1d20 HS |
947 | |
948 | if (!first) { | |
949 | first = desc; | |
950 | } else { | |
951 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 952 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 953 | &first->tx_list); |
3bfb1d20 HS |
954 | } |
955 | prev = desc; | |
69dc14b5 VK |
956 | total_len += dlen; |
957 | ||
958 | if (len) | |
959 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
960 | } |
961 | break; | |
962 | default: | |
963 | return NULL; | |
964 | } | |
965 | ||
966 | if (flags & DMA_PREP_INTERRUPT) | |
967 | /* Trigger interrupt after last block */ | |
968 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
969 | ||
970 | prev->lli.llp = 0; | |
30d38a32 | 971 | first->total_len = total_len; |
3bfb1d20 HS |
972 | |
973 | return &first->txd; | |
974 | ||
975 | err_desc_get: | |
976 | dwc_desc_put(dwc, first); | |
977 | return NULL; | |
978 | } | |
979 | ||
327e6970 VK |
980 | /* |
981 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
982 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
983 | * | |
984 | * NOTE: burst size 2 is not supported by controller. | |
985 | * | |
986 | * This can be done by finding least significant bit set: n & (n - 1) | |
987 | */ | |
988 | static inline void convert_burst(u32 *maxburst) | |
989 | { | |
990 | if (*maxburst > 1) | |
991 | *maxburst = fls(*maxburst) - 2; | |
992 | else | |
993 | *maxburst = 0; | |
994 | } | |
995 | ||
996 | static int | |
997 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
998 | { | |
999 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1000 | ||
495aea4b AS |
1001 | /* Check if chan will be configured for slave transfers */ |
1002 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
1003 | return -EINVAL; |
1004 | ||
1005 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 1006 | dwc->direction = sconfig->direction; |
327e6970 VK |
1007 | |
1008 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
1009 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
21fe3c52 AS |
1014 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
1015 | { | |
1016 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1017 | ||
1018 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
1019 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
1020 | cpu_relax(); | |
1021 | ||
1022 | dwc->paused = true; | |
1023 | } | |
1024 | ||
1025 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1026 | { | |
1027 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1028 | ||
1029 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1030 | ||
1031 | dwc->paused = false; | |
1032 | } | |
1033 | ||
05827630 LW |
1034 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1035 | unsigned long arg) | |
3bfb1d20 HS |
1036 | { |
1037 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1038 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1039 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1040 | unsigned long flags; |
3bfb1d20 HS |
1041 | LIST_HEAD(list); |
1042 | ||
a7c57cf7 LW |
1043 | if (cmd == DMA_PAUSE) { |
1044 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1045 | |
21fe3c52 | 1046 | dwc_chan_pause(dwc); |
3bfb1d20 | 1047 | |
a7c57cf7 LW |
1048 | spin_unlock_irqrestore(&dwc->lock, flags); |
1049 | } else if (cmd == DMA_RESUME) { | |
1050 | if (!dwc->paused) | |
1051 | return 0; | |
3bfb1d20 | 1052 | |
a7c57cf7 | 1053 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1054 | |
21fe3c52 | 1055 | dwc_chan_resume(dwc); |
3bfb1d20 | 1056 | |
a7c57cf7 LW |
1057 | spin_unlock_irqrestore(&dwc->lock, flags); |
1058 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1059 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1060 | |
fed2574b AS |
1061 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1062 | ||
3f936207 | 1063 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1064 | |
a5dbff11 | 1065 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1066 | |
1067 | /* active_list entries will end up before queued entries */ | |
1068 | list_splice_init(&dwc->queue, &list); | |
1069 | list_splice_init(&dwc->active_list, &list); | |
1070 | ||
1071 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1072 | ||
1073 | /* Flush all pending and queued descriptors */ | |
1074 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1075 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1076 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1077 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1078 | } else { | |
a7c57cf7 | 1079 | return -ENXIO; |
327e6970 | 1080 | } |
c3635c78 LW |
1081 | |
1082 | return 0; | |
3bfb1d20 HS |
1083 | } |
1084 | ||
4702d524 AS |
1085 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1086 | { | |
1087 | unsigned long flags; | |
1088 | u32 residue; | |
1089 | ||
1090 | spin_lock_irqsave(&dwc->lock, flags); | |
1091 | ||
1092 | residue = dwc->residue; | |
1093 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1094 | residue -= dwc_get_sent(dwc); | |
1095 | ||
1096 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1097 | return residue; | |
1098 | } | |
1099 | ||
3bfb1d20 | 1100 | static enum dma_status |
07934481 LW |
1101 | dwc_tx_status(struct dma_chan *chan, |
1102 | dma_cookie_t cookie, | |
1103 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1104 | { |
1105 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1106 | enum dma_status ret; |
3bfb1d20 | 1107 | |
96a2af41 | 1108 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1109 | if (ret != DMA_SUCCESS) { |
1110 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1111 | ||
96a2af41 | 1112 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1113 | } |
1114 | ||
abf53902 | 1115 | if (ret != DMA_SUCCESS) |
4702d524 | 1116 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1117 | |
a7c57cf7 LW |
1118 | if (dwc->paused) |
1119 | return DMA_PAUSED; | |
3bfb1d20 HS |
1120 | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | static void dwc_issue_pending(struct dma_chan *chan) | |
1125 | { | |
1126 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1127 | ||
3bfb1d20 HS |
1128 | if (!list_empty(&dwc->queue)) |
1129 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1130 | } |
1131 | ||
aa1e6f1a | 1132 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1133 | { |
1134 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1135 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1136 | struct dw_desc *desc; | |
3bfb1d20 | 1137 | int i; |
69cea5a0 | 1138 | unsigned long flags; |
3bfb1d20 | 1139 | |
2e4c364e | 1140 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1141 | |
3bfb1d20 HS |
1142 | /* ASSERT: channel is idle */ |
1143 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1144 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1145 | return -EIO; |
1146 | } | |
1147 | ||
d3ee98cd | 1148 | dma_cookie_init(chan); |
3bfb1d20 | 1149 | |
3bfb1d20 HS |
1150 | /* |
1151 | * NOTE: some controllers may have additional features that we | |
1152 | * need to initialize here, like "scatter-gather" (which | |
1153 | * doesn't mean what you think it means), and status writeback. | |
1154 | */ | |
1155 | ||
69cea5a0 | 1156 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1157 | i = dwc->descs_allocated; |
1158 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1159 | dma_addr_t phys; |
1160 | ||
69cea5a0 | 1161 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1162 | |
f8122a82 | 1163 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1164 | if (!desc) |
1165 | goto err_desc_alloc; | |
3bfb1d20 | 1166 | |
f8122a82 AS |
1167 | memset(desc, 0, sizeof(struct dw_desc)); |
1168 | ||
e0bd0f8c | 1169 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1170 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1171 | desc->txd.tx_submit = dwc_tx_submit; | |
1172 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1173 | desc->txd.phys = phys; |
cbd65312 | 1174 | |
3bfb1d20 HS |
1175 | dwc_desc_put(dwc, desc); |
1176 | ||
69cea5a0 | 1177 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1178 | i = ++dwc->descs_allocated; |
1179 | } | |
1180 | ||
69cea5a0 | 1181 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1182 | |
2e4c364e | 1183 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1184 | |
cbd65312 AS |
1185 | return i; |
1186 | ||
1187 | err_desc_alloc: | |
cbd65312 AS |
1188 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1189 | ||
3bfb1d20 HS |
1190 | return i; |
1191 | } | |
1192 | ||
1193 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1194 | { | |
1195 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1196 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1197 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1198 | unsigned long flags; |
3bfb1d20 HS |
1199 | LIST_HEAD(list); |
1200 | ||
2e4c364e | 1201 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1202 | dwc->descs_allocated); |
1203 | ||
1204 | /* ASSERT: channel is idle */ | |
1205 | BUG_ON(!list_empty(&dwc->active_list)); | |
1206 | BUG_ON(!list_empty(&dwc->queue)); | |
1207 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1208 | ||
69cea5a0 | 1209 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1210 | list_splice_init(&dwc->free_list, &list); |
1211 | dwc->descs_allocated = 0; | |
61e183f8 | 1212 | dwc->initialized = false; |
3bfb1d20 HS |
1213 | |
1214 | /* Disable interrupts */ | |
1215 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1216 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1217 | ||
69cea5a0 | 1218 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1219 | |
1220 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1221 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1222 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1223 | } |
1224 | ||
2e4c364e | 1225 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1226 | } |
1227 | ||
a9ddb575 VK |
1228 | bool dw_dma_generic_filter(struct dma_chan *chan, void *param) |
1229 | { | |
1230 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1231 | static struct dw_dma *last_dw; | |
1232 | static char *last_bus_id; | |
1233 | int i = -1; | |
1234 | ||
1235 | /* | |
1236 | * dmaengine framework calls this routine for all channels of all dma | |
1237 | * controller, until true is returned. If 'param' bus_id is not | |
1238 | * registered with a dma controller (dw), then there is no need of | |
1239 | * running below function for all channels of dw. | |
1240 | * | |
1241 | * This block of code does this by saving the parameters of last | |
1242 | * failure. If dw and param are same, i.e. trying on same dw with | |
1243 | * different channel, return false. | |
1244 | */ | |
1245 | if ((last_dw == dw) && (last_bus_id == param)) | |
1246 | return false; | |
1247 | /* | |
1248 | * Return true: | |
1249 | * - If dw_dma's platform data is not filled with slave info, then all | |
1250 | * dma controllers are fine for transfer. | |
1251 | * - Or if param is NULL | |
1252 | */ | |
1253 | if (!dw->sd || !param) | |
1254 | return true; | |
1255 | ||
1256 | while (++i < dw->sd_count) { | |
1257 | if (!strcmp(dw->sd[i].bus_id, param)) { | |
1258 | chan->private = &dw->sd[i]; | |
1259 | last_dw = NULL; | |
1260 | last_bus_id = NULL; | |
1261 | ||
1262 | return true; | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | last_dw = dw; | |
1267 | last_bus_id = param; | |
1268 | return false; | |
1269 | } | |
1270 | EXPORT_SYMBOL(dw_dma_generic_filter); | |
1271 | ||
d9de4519 HCE |
1272 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1273 | ||
1274 | /** | |
1275 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1276 | * @chan: the DMA channel to start | |
1277 | * | |
1278 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1279 | * -errno on failure. | |
1280 | */ | |
1281 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1282 | { | |
1283 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1284 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1285 | unsigned long flags; |
d9de4519 HCE |
1286 | |
1287 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1288 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1289 | return -ENODEV; | |
1290 | } | |
1291 | ||
69cea5a0 | 1292 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1293 | |
1294 | /* assert channel is idle */ | |
1295 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1296 | dev_err(chan2dev(&dwc->chan), | |
1297 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1298 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1299 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1300 | return -EBUSY; |
1301 | } | |
1302 | ||
d9de4519 HCE |
1303 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1304 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1305 | ||
1306 | /* setup DMAC channel registers */ | |
1307 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1308 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1309 | channel_writel(dwc, CTL_HI, 0); | |
1310 | ||
1311 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1312 | ||
69cea5a0 | 1313 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1314 | |
1315 | return 0; | |
1316 | } | |
1317 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1318 | ||
1319 | /** | |
1320 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1321 | * @chan: the DMA channel to stop | |
1322 | * | |
1323 | * Must be called with soft interrupts disabled. | |
1324 | */ | |
1325 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1326 | { | |
1327 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1328 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1329 | unsigned long flags; |
d9de4519 | 1330 | |
69cea5a0 | 1331 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1332 | |
3f936207 | 1333 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1334 | |
69cea5a0 | 1335 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1336 | } |
1337 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1338 | ||
1339 | /** | |
1340 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1341 | * @chan: the DMA channel to prepare | |
1342 | * @buf_addr: physical DMA address where the buffer starts | |
1343 | * @buf_len: total number of bytes for the entire buffer | |
1344 | * @period_len: number of bytes for each period | |
1345 | * @direction: transfer direction, to or from device | |
1346 | * | |
1347 | * Must be called before trying to start the transfer. Returns a valid struct | |
1348 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1349 | */ | |
1350 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1351 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1352 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1353 | { |
1354 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1355 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1356 | struct dw_cyclic_desc *cdesc; |
1357 | struct dw_cyclic_desc *retval = NULL; | |
1358 | struct dw_desc *desc; | |
1359 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1360 | unsigned long was_cyclic; |
1361 | unsigned int reg_width; | |
1362 | unsigned int periods; | |
1363 | unsigned int i; | |
69cea5a0 | 1364 | unsigned long flags; |
d9de4519 | 1365 | |
69cea5a0 | 1366 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1367 | if (dwc->nollp) { |
1368 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1369 | dev_dbg(chan2dev(&dwc->chan), | |
1370 | "channel doesn't support LLP transfers\n"); | |
1371 | return ERR_PTR(-EINVAL); | |
1372 | } | |
1373 | ||
d9de4519 | 1374 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1375 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1376 | dev_dbg(chan2dev(&dwc->chan), |
1377 | "queue and/or active list are not empty\n"); | |
1378 | return ERR_PTR(-EBUSY); | |
1379 | } | |
1380 | ||
1381 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1382 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1383 | if (was_cyclic) { |
1384 | dev_dbg(chan2dev(&dwc->chan), | |
1385 | "channel already prepared for cyclic DMA\n"); | |
1386 | return ERR_PTR(-EBUSY); | |
1387 | } | |
1388 | ||
1389 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1390 | |
f44b92f4 AS |
1391 | if (unlikely(!is_slave_direction(direction))) |
1392 | goto out_err; | |
1393 | ||
0fdb567f AS |
1394 | dwc->direction = direction; |
1395 | ||
327e6970 VK |
1396 | if (direction == DMA_MEM_TO_DEV) |
1397 | reg_width = __ffs(sconfig->dst_addr_width); | |
1398 | else | |
1399 | reg_width = __ffs(sconfig->src_addr_width); | |
1400 | ||
d9de4519 HCE |
1401 | periods = buf_len / period_len; |
1402 | ||
1403 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1404 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1405 | goto out_err; |
1406 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1407 | goto out_err; | |
1408 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1409 | goto out_err; | |
d9de4519 HCE |
1410 | |
1411 | retval = ERR_PTR(-ENOMEM); | |
1412 | ||
1413 | if (periods > NR_DESCS_PER_CHANNEL) | |
1414 | goto out_err; | |
1415 | ||
1416 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1417 | if (!cdesc) | |
1418 | goto out_err; | |
1419 | ||
1420 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1421 | if (!cdesc->desc) | |
1422 | goto out_err_alloc; | |
1423 | ||
1424 | for (i = 0; i < periods; i++) { | |
1425 | desc = dwc_desc_get(dwc); | |
1426 | if (!desc) | |
1427 | goto out_err_desc_get; | |
1428 | ||
1429 | switch (direction) { | |
db8196df | 1430 | case DMA_MEM_TO_DEV: |
327e6970 | 1431 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1432 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1433 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1434 | | DWC_CTLL_DST_WIDTH(reg_width) |
1435 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1436 | | DWC_CTLL_DST_FIX | |
1437 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1438 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1439 | |
1440 | desc->lli.ctllo |= sconfig->device_fc ? | |
1441 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1442 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1443 | ||
d9de4519 | 1444 | break; |
db8196df | 1445 | case DMA_DEV_TO_MEM: |
d9de4519 | 1446 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1447 | desc->lli.sar = sconfig->src_addr; |
1448 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1449 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1450 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1451 | | DWC_CTLL_DST_INC | |
1452 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1453 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1454 | |
1455 | desc->lli.ctllo |= sconfig->device_fc ? | |
1456 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1457 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1458 | ||
d9de4519 HCE |
1459 | break; |
1460 | default: | |
1461 | break; | |
1462 | } | |
1463 | ||
1464 | desc->lli.ctlhi = (period_len >> reg_width); | |
1465 | cdesc->desc[i] = desc; | |
1466 | ||
f8122a82 | 1467 | if (last) |
d9de4519 | 1468 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1469 | |
1470 | last = desc; | |
1471 | } | |
1472 | ||
1473 | /* lets make a cyclic list */ | |
1474 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
d9de4519 | 1475 | |
2f45d613 AS |
1476 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1477 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1478 | buf_len, period_len, periods); | |
d9de4519 HCE |
1479 | |
1480 | cdesc->periods = periods; | |
1481 | dwc->cdesc = cdesc; | |
1482 | ||
1483 | return cdesc; | |
1484 | ||
1485 | out_err_desc_get: | |
1486 | while (i--) | |
1487 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1488 | out_err_alloc: | |
1489 | kfree(cdesc); | |
1490 | out_err: | |
1491 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1492 | return (struct dw_cyclic_desc *)retval; | |
1493 | } | |
1494 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1495 | ||
1496 | /** | |
1497 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1498 | * @chan: the DMA channel to free | |
1499 | */ | |
1500 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1501 | { | |
1502 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1503 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1504 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1505 | int i; | |
69cea5a0 | 1506 | unsigned long flags; |
d9de4519 | 1507 | |
2e4c364e | 1508 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1509 | |
1510 | if (!cdesc) | |
1511 | return; | |
1512 | ||
69cea5a0 | 1513 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1514 | |
3f936207 | 1515 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1516 | |
d9de4519 HCE |
1517 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1518 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1519 | ||
69cea5a0 | 1520 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1521 | |
1522 | for (i = 0; i < cdesc->periods; i++) | |
1523 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1524 | ||
1525 | kfree(cdesc->desc); | |
1526 | kfree(cdesc); | |
1527 | ||
1528 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1529 | } | |
1530 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1531 | ||
3bfb1d20 HS |
1532 | /*----------------------------------------------------------------------*/ |
1533 | ||
1534 | static void dw_dma_off(struct dw_dma *dw) | |
1535 | { | |
61e183f8 VK |
1536 | int i; |
1537 | ||
3bfb1d20 HS |
1538 | dma_writel(dw, CFG, 0); |
1539 | ||
1540 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1541 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1542 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1543 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1544 | ||
1545 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1546 | cpu_relax(); | |
61e183f8 VK |
1547 | |
1548 | for (i = 0; i < dw->dma.chancnt; i++) | |
1549 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1550 | } |
1551 | ||
a9ddb575 VK |
1552 | #ifdef CONFIG_OF |
1553 | static struct dw_dma_platform_data * | |
1554 | dw_dma_parse_dt(struct platform_device *pdev) | |
1555 | { | |
1556 | struct device_node *sn, *cn, *np = pdev->dev.of_node; | |
1557 | struct dw_dma_platform_data *pdata; | |
1558 | struct dw_dma_slave *sd; | |
1559 | u32 tmp, arr[4]; | |
1560 | ||
1561 | if (!np) { | |
1562 | dev_err(&pdev->dev, "Missing DT data\n"); | |
1563 | return NULL; | |
1564 | } | |
1565 | ||
1566 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1567 | if (!pdata) | |
1568 | return NULL; | |
1569 | ||
1570 | if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels)) | |
1571 | return NULL; | |
1572 | ||
1573 | if (of_property_read_bool(np, "is_private")) | |
1574 | pdata->is_private = true; | |
1575 | ||
1576 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) | |
1577 | pdata->chan_allocation_order = (unsigned char)tmp; | |
1578 | ||
1579 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
1580 | pdata->chan_priority = tmp; | |
1581 | ||
1582 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
1583 | pdata->block_size = tmp; | |
1584 | ||
1585 | if (!of_property_read_u32(np, "nr_masters", &tmp)) { | |
1586 | if (tmp > 4) | |
1587 | return NULL; | |
1588 | ||
1589 | pdata->nr_masters = tmp; | |
1590 | } | |
1591 | ||
1592 | if (!of_property_read_u32_array(np, "data_width", arr, | |
1593 | pdata->nr_masters)) | |
1594 | for (tmp = 0; tmp < pdata->nr_masters; tmp++) | |
1595 | pdata->data_width[tmp] = arr[tmp]; | |
1596 | ||
1597 | /* parse slave data */ | |
1598 | sn = of_find_node_by_name(np, "slave_info"); | |
1599 | if (!sn) | |
1600 | return pdata; | |
1601 | ||
1602 | /* calculate number of slaves */ | |
1603 | tmp = of_get_child_count(sn); | |
1604 | if (!tmp) | |
1605 | return NULL; | |
1606 | ||
1607 | sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL); | |
1608 | if (!sd) | |
1609 | return NULL; | |
1610 | ||
1611 | pdata->sd = sd; | |
1612 | pdata->sd_count = tmp; | |
1613 | ||
1614 | for_each_child_of_node(sn, cn) { | |
1615 | sd->dma_dev = &pdev->dev; | |
1616 | of_property_read_string(cn, "bus_id", &sd->bus_id); | |
1617 | of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi); | |
1618 | of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo); | |
1619 | if (!of_property_read_u32(cn, "src_master", &tmp)) | |
1620 | sd->src_master = tmp; | |
1621 | ||
1622 | if (!of_property_read_u32(cn, "dst_master", &tmp)) | |
1623 | sd->dst_master = tmp; | |
1624 | sd++; | |
1625 | } | |
1626 | ||
1627 | return pdata; | |
1628 | } | |
1629 | #else | |
1630 | static inline struct dw_dma_platform_data * | |
1631 | dw_dma_parse_dt(struct platform_device *pdev) | |
1632 | { | |
1633 | return NULL; | |
1634 | } | |
1635 | #endif | |
1636 | ||
463a1f8b | 1637 | static int dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1638 | { |
1639 | struct dw_dma_platform_data *pdata; | |
1640 | struct resource *io; | |
1641 | struct dw_dma *dw; | |
1642 | size_t size; | |
482c67ea AS |
1643 | void __iomem *regs; |
1644 | bool autocfg; | |
1645 | unsigned int dw_params; | |
1646 | unsigned int nr_channels; | |
4a63a8b3 | 1647 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1648 | int irq; |
1649 | int err; | |
1650 | int i; | |
1651 | ||
3bfb1d20 HS |
1652 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1653 | if (!io) | |
1654 | return -EINVAL; | |
1655 | ||
1656 | irq = platform_get_irq(pdev, 0); | |
1657 | if (irq < 0) | |
1658 | return irq; | |
1659 | ||
482c67ea AS |
1660 | regs = devm_request_and_ioremap(&pdev->dev, io); |
1661 | if (!regs) | |
1662 | return -EBUSY; | |
1663 | ||
1664 | dw_params = dma_read_byaddr(regs, DW_PARAMS); | |
1665 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1666 | ||
985a6c7d AS |
1667 | dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
1668 | ||
123de543 AS |
1669 | pdata = dev_get_platdata(&pdev->dev); |
1670 | if (!pdata) | |
1671 | pdata = dw_dma_parse_dt(pdev); | |
1672 | ||
1673 | if (!pdata && autocfg) { | |
1674 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1675 | if (!pdata) | |
1676 | return -ENOMEM; | |
1677 | ||
1678 | /* Fill platform data with the default values */ | |
1679 | pdata->is_private = true; | |
1680 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1681 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1682 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1683 | return -EINVAL; | |
1684 | ||
482c67ea AS |
1685 | if (autocfg) |
1686 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1687 | else | |
1688 | nr_channels = pdata->nr_channels; | |
1689 | ||
1690 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1691 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1692 | if (!dw) |
1693 | return -ENOMEM; | |
1694 | ||
dbde5c29 AS |
1695 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1696 | if (IS_ERR(dw->clk)) | |
1697 | return PTR_ERR(dw->clk); | |
3075528d | 1698 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1699 | |
482c67ea | 1700 | dw->regs = regs; |
a9ddb575 VK |
1701 | dw->sd = pdata->sd; |
1702 | dw->sd_count = pdata->sd_count; | |
482c67ea | 1703 | |
4a63a8b3 | 1704 | /* get hardware configuration parameters */ |
a0982004 | 1705 | if (autocfg) { |
4a63a8b3 AS |
1706 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1707 | ||
a0982004 AS |
1708 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1709 | for (i = 0; i < dw->nr_masters; i++) { | |
1710 | dw->data_width[i] = | |
1711 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1712 | } | |
1713 | } else { | |
1714 | dw->nr_masters = pdata->nr_masters; | |
1715 | memcpy(dw->data_width, pdata->data_width, 4); | |
1716 | } | |
1717 | ||
11f932ec | 1718 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1719 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1720 | |
3bfb1d20 HS |
1721 | /* force dma off, just in case */ |
1722 | dw_dma_off(dw); | |
1723 | ||
236b106f AS |
1724 | /* disable BLOCK interrupts as well */ |
1725 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1726 | ||
dbde5c29 AS |
1727 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1728 | "dw_dmac", dw); | |
3bfb1d20 | 1729 | if (err) |
dbde5c29 | 1730 | return err; |
3bfb1d20 HS |
1731 | |
1732 | platform_set_drvdata(pdev, dw); | |
1733 | ||
f8122a82 AS |
1734 | /* create a pool of consistent memory blocks for hardware descriptors */ |
1735 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev, | |
1736 | sizeof(struct dw_desc), 4, 0); | |
1737 | if (!dw->desc_pool) { | |
1738 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1739 | return -ENOMEM; | |
1740 | } | |
1741 | ||
3bfb1d20 HS |
1742 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1743 | ||
3bfb1d20 | 1744 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1745 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1746 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1747 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1748 | |
1749 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1750 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1751 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1752 | list_add_tail(&dwc->chan.device_node, | |
1753 | &dw->dma.channels); | |
1754 | else | |
1755 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1756 | |
93317e8e VK |
1757 | /* 7 is highest priority & 0 is lowest. */ |
1758 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1759 | dwc->priority = r; |
93317e8e VK |
1760 | else |
1761 | dwc->priority = i; | |
1762 | ||
3bfb1d20 HS |
1763 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1764 | spin_lock_init(&dwc->lock); | |
1765 | dwc->mask = 1 << i; | |
1766 | ||
1767 | INIT_LIST_HEAD(&dwc->active_list); | |
1768 | INIT_LIST_HEAD(&dwc->queue); | |
1769 | INIT_LIST_HEAD(&dwc->free_list); | |
1770 | ||
1771 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1772 | |
0fdb567f | 1773 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1774 | |
4a63a8b3 | 1775 | /* hardware configuration */ |
fed2574b AS |
1776 | if (autocfg) { |
1777 | unsigned int dwc_params; | |
1778 | ||
1779 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1780 | DWC_PARAMS); | |
1781 | ||
985a6c7d AS |
1782 | dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1783 | dwc_params); | |
1784 | ||
4a63a8b3 AS |
1785 | /* Decode maximum block size for given channel. The |
1786 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1787 | * up to 0x0a for 4095. */ | |
1788 | dwc->block_size = | |
1789 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1790 | dwc->nollp = |
1791 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1792 | } else { | |
4a63a8b3 | 1793 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1794 | |
1795 | /* Check if channel supports multi block transfer */ | |
1796 | channel_writel(dwc, LLP, 0xfffffffc); | |
1797 | dwc->nollp = | |
1798 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1799 | channel_writel(dwc, LLP, 0); | |
1800 | } | |
3bfb1d20 HS |
1801 | } |
1802 | ||
11f932ec | 1803 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1804 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1805 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1806 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1807 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1808 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1809 | ||
3bfb1d20 HS |
1810 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1811 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1812 | if (pdata->is_private) |
1813 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1814 | dw->dma.dev = &pdev->dev; |
1815 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1816 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1817 | ||
1818 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1819 | ||
1820 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1821 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1822 | |
07934481 | 1823 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1824 | dw->dma.device_issue_pending = dwc_issue_pending; |
1825 | ||
1826 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1827 | ||
21d43f49 AS |
1828 | dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", |
1829 | nr_channels); | |
3bfb1d20 HS |
1830 | |
1831 | dma_async_device_register(&dw->dma); | |
1832 | ||
1833 | return 0; | |
3bfb1d20 HS |
1834 | } |
1835 | ||
0272e93f | 1836 | static int __devexit dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1837 | { |
1838 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1839 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 HS |
1840 | |
1841 | dw_dma_off(dw); | |
1842 | dma_async_device_unregister(&dw->dma); | |
1843 | ||
3bfb1d20 HS |
1844 | tasklet_kill(&dw->tasklet); |
1845 | ||
1846 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1847 | chan.device_node) { | |
1848 | list_del(&dwc->chan.device_node); | |
1849 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1850 | } | |
1851 | ||
3bfb1d20 HS |
1852 | return 0; |
1853 | } | |
1854 | ||
1855 | static void dw_shutdown(struct platform_device *pdev) | |
1856 | { | |
1857 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1858 | ||
6168d567 | 1859 | dw_dma_off(dw); |
3075528d | 1860 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1861 | } |
1862 | ||
4a256b5f | 1863 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1864 | { |
4a256b5f | 1865 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1866 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1867 | ||
6168d567 | 1868 | dw_dma_off(dw); |
3075528d | 1869 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1870 | |
3bfb1d20 HS |
1871 | return 0; |
1872 | } | |
1873 | ||
4a256b5f | 1874 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1875 | { |
4a256b5f | 1876 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1877 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1878 | ||
3075528d | 1879 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1880 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1881 | |
3bfb1d20 | 1882 | return 0; |
3bfb1d20 HS |
1883 | } |
1884 | ||
47145210 | 1885 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1886 | .suspend_noirq = dw_suspend_noirq, |
1887 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1888 | .freeze_noirq = dw_suspend_noirq, |
1889 | .thaw_noirq = dw_resume_noirq, | |
1890 | .restore_noirq = dw_resume_noirq, | |
1891 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1892 | }; |
1893 | ||
d3f797d9 VK |
1894 | #ifdef CONFIG_OF |
1895 | static const struct of_device_id dw_dma_id_table[] = { | |
1896 | { .compatible = "snps,dma-spear1340" }, | |
1897 | {} | |
1898 | }; | |
1899 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1900 | #endif | |
1901 | ||
cfdf5b6c MW |
1902 | static const struct platform_device_id dw_dma_ids[] = { |
1903 | { "INTL9C60", 0 }, | |
1904 | { } | |
1905 | }; | |
1906 | ||
3bfb1d20 | 1907 | static struct platform_driver dw_driver = { |
01126856 | 1908 | .probe = dw_probe, |
a7d6e3ec | 1909 | .remove = dw_remove, |
3bfb1d20 | 1910 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1911 | .driver = { |
1912 | .name = "dw_dmac", | |
4a256b5f | 1913 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1914 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 | 1915 | }, |
cfdf5b6c | 1916 | .id_table = dw_dma_ids, |
3bfb1d20 HS |
1917 | }; |
1918 | ||
1919 | static int __init dw_init(void) | |
1920 | { | |
01126856 | 1921 | return platform_driver_register(&dw_driver); |
3bfb1d20 | 1922 | } |
cb689a70 | 1923 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1924 | |
1925 | static void __exit dw_exit(void) | |
1926 | { | |
1927 | platform_driver_unregister(&dw_driver); | |
1928 | } | |
1929 | module_exit(dw_exit); | |
1930 | ||
1931 | MODULE_LICENSE("GPL v2"); | |
1932 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1933 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1934 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |