Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
3ad7a42d | 27 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
28 | |
29 | #include "dmaengine.h" | |
30 | #include "virt-dma.h" | |
31 | ||
32 | /* | |
33 | * This will go away when the private EDMA API is folded | |
34 | * into this driver and the platform device(s) are | |
35 | * instantiated in the arch code. We can only get away | |
36 | * with this simplification because DA8XX may not be built | |
37 | * in the same kernel image with other DaVinci parts. This | |
38 | * avoids having to sprinkle dmaengine driver platform devices | |
39 | * and data throughout all the existing board files. | |
40 | */ | |
41 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
42 | #define EDMA_CTLRS 2 | |
43 | #define EDMA_CHANS 32 | |
44 | #else | |
45 | #define EDMA_CTLRS 1 | |
46 | #define EDMA_CHANS 64 | |
47 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
48 | ||
2abd5f1b JF |
49 | /* |
50 | * Max of 20 segments per channel to conserve PaRAM slots | |
51 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
52 | * that are required for ASoC, otherwise DMA prep calls will | |
53 | * fail. Today davinci-pcm is the only user of this driver and | |
54 | * requires atleast 17 slots, so we setup the default to 20. | |
55 | */ | |
56 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
57 | #define EDMA_MAX_SLOTS MAX_NR_SG |
58 | #define EDMA_DESCRIPTORS 16 | |
59 | ||
b5088ad9 | 60 | struct edma_pset { |
c2da2340 TG |
61 | u32 len; |
62 | dma_addr_t addr; | |
b5088ad9 TG |
63 | struct edmacc_param param; |
64 | }; | |
65 | ||
c2dde5f8 MP |
66 | struct edma_desc { |
67 | struct virt_dma_desc vdesc; | |
68 | struct list_head node; | |
c2da2340 | 69 | enum dma_transfer_direction direction; |
50a9c707 | 70 | int cyclic; |
c2dde5f8 MP |
71 | int absync; |
72 | int pset_nr; | |
04361d88 | 73 | struct edma_chan *echan; |
53407062 | 74 | int processed; |
04361d88 JF |
75 | |
76 | /* | |
77 | * The following 4 elements are used for residue accounting. | |
78 | * | |
79 | * - processed_stat: the number of SG elements we have traversed | |
80 | * so far to cover accounting. This is updated directly to processed | |
81 | * during edma_callback and is always <= processed, because processed | |
82 | * refers to the number of pending transfer (programmed to EDMA | |
83 | * controller), where as processed_stat tracks number of transfers | |
84 | * accounted for so far. | |
85 | * | |
86 | * - residue: The amount of bytes we have left to transfer for this desc | |
87 | * | |
88 | * - residue_stat: The residue in bytes of data we have covered | |
89 | * so far for accounting. This is updated directly to residue | |
90 | * during callbacks to keep it current. | |
91 | * | |
92 | * - sg_len: Tracks the length of the current intermediate transfer, | |
93 | * this is required to update the residue during intermediate transfer | |
94 | * completion callback. | |
95 | */ | |
740b41f7 | 96 | int processed_stat; |
740b41f7 | 97 | u32 sg_len; |
04361d88 | 98 | u32 residue; |
740b41f7 | 99 | u32 residue_stat; |
04361d88 | 100 | |
b5088ad9 | 101 | struct edma_pset pset[0]; |
c2dde5f8 MP |
102 | }; |
103 | ||
104 | struct edma_cc; | |
105 | ||
106 | struct edma_chan { | |
107 | struct virt_dma_chan vchan; | |
108 | struct list_head node; | |
109 | struct edma_desc *edesc; | |
110 | struct edma_cc *ecc; | |
111 | int ch_num; | |
112 | bool alloced; | |
113 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 114 | int missed; |
661f7cb5 | 115 | struct dma_slave_config cfg; |
c2dde5f8 MP |
116 | }; |
117 | ||
118 | struct edma_cc { | |
119 | int ctlr; | |
120 | struct dma_device dma_slave; | |
121 | struct edma_chan slave_chans[EDMA_CHANS]; | |
122 | int num_slave_chans; | |
123 | int dummy_slot; | |
124 | }; | |
125 | ||
126 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
127 | { | |
128 | return container_of(d, struct edma_cc, dma_slave); | |
129 | } | |
130 | ||
131 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
132 | { | |
133 | return container_of(c, struct edma_chan, vchan.chan); | |
134 | } | |
135 | ||
136 | static inline struct edma_desc | |
137 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
138 | { | |
139 | return container_of(tx, struct edma_desc, vdesc.tx); | |
140 | } | |
141 | ||
142 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
143 | { | |
144 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
145 | } | |
146 | ||
147 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
148 | static void edma_execute(struct edma_chan *echan) | |
149 | { | |
53407062 | 150 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 151 | struct edma_desc *edesc; |
53407062 JF |
152 | struct device *dev = echan->vchan.chan.device->dev; |
153 | int i, j, left, nslots; | |
154 | ||
155 | /* If either we processed all psets or we're still not started */ | |
156 | if (!echan->edesc || | |
157 | echan->edesc->pset_nr == echan->edesc->processed) { | |
158 | /* Get next vdesc */ | |
159 | vdesc = vchan_next_desc(&echan->vchan); | |
160 | if (!vdesc) { | |
161 | echan->edesc = NULL; | |
162 | return; | |
163 | } | |
164 | list_del(&vdesc->node); | |
165 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
166 | } |
167 | ||
53407062 | 168 | edesc = echan->edesc; |
c2dde5f8 | 169 | |
53407062 JF |
170 | /* Find out how many left */ |
171 | left = edesc->pset_nr - edesc->processed; | |
172 | nslots = min(MAX_NR_SG, left); | |
740b41f7 | 173 | edesc->sg_len = 0; |
c2dde5f8 MP |
174 | |
175 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
176 | for (i = 0; i < nslots; i++) { |
177 | j = i + edesc->processed; | |
b5088ad9 | 178 | edma_write_slot(echan->slot[i], &edesc->pset[j].param); |
740b41f7 | 179 | edesc->sg_len += edesc->pset[j].len; |
83bb3126 | 180 | dev_vdbg(echan->vchan.chan.device->dev, |
c2dde5f8 MP |
181 | "\n pset[%d]:\n" |
182 | " chnum\t%d\n" | |
183 | " slot\t%d\n" | |
184 | " opt\t%08x\n" | |
185 | " src\t%08x\n" | |
186 | " dst\t%08x\n" | |
187 | " abcnt\t%08x\n" | |
188 | " ccnt\t%08x\n" | |
189 | " bidx\t%08x\n" | |
190 | " cidx\t%08x\n" | |
191 | " lkrld\t%08x\n", | |
53407062 | 192 | j, echan->ch_num, echan->slot[i], |
b5088ad9 TG |
193 | edesc->pset[j].param.opt, |
194 | edesc->pset[j].param.src, | |
195 | edesc->pset[j].param.dst, | |
196 | edesc->pset[j].param.a_b_cnt, | |
197 | edesc->pset[j].param.ccnt, | |
198 | edesc->pset[j].param.src_dst_bidx, | |
199 | edesc->pset[j].param.src_dst_cidx, | |
200 | edesc->pset[j].param.link_bcntrld); | |
c2dde5f8 | 201 | /* Link to the previous slot if not the last set */ |
53407062 | 202 | if (i != (nslots - 1)) |
c2dde5f8 | 203 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
204 | } |
205 | ||
53407062 JF |
206 | edesc->processed += nslots; |
207 | ||
b267b3bc JF |
208 | /* |
209 | * If this is either the last set in a set of SG-list transactions | |
210 | * then setup a link to the dummy slot, this results in all future | |
211 | * events being absorbed and that's OK because we're done | |
212 | */ | |
50a9c707 JF |
213 | if (edesc->processed == edesc->pset_nr) { |
214 | if (edesc->cyclic) | |
215 | edma_link(echan->slot[nslots-1], echan->slot[1]); | |
216 | else | |
217 | edma_link(echan->slot[nslots-1], | |
218 | echan->ecc->dummy_slot); | |
219 | } | |
b267b3bc | 220 | |
53407062 | 221 | if (edesc->processed <= MAX_NR_SG) { |
9aac9096 PU |
222 | dev_dbg(dev, "first transfer starting on channel %d\n", |
223 | echan->ch_num); | |
53407062 | 224 | edma_start(echan->ch_num); |
5fc68a6c SN |
225 | } else { |
226 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
227 | echan->ch_num, edesc->processed); | |
228 | edma_resume(echan->ch_num); | |
53407062 | 229 | } |
c5f47990 JF |
230 | |
231 | /* | |
232 | * This happens due to setup times between intermediate transfers | |
233 | * in long SG lists which have to be broken up into transfers of | |
234 | * MAX_NR_SG | |
235 | */ | |
236 | if (echan->missed) { | |
9aac9096 | 237 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
c5f47990 JF |
238 | edma_clean_channel(echan->ch_num); |
239 | edma_stop(echan->ch_num); | |
240 | edma_start(echan->ch_num); | |
241 | edma_trigger_channel(echan->ch_num); | |
242 | echan->missed = 0; | |
243 | } | |
c2dde5f8 MP |
244 | } |
245 | ||
246 | static int edma_terminate_all(struct edma_chan *echan) | |
247 | { | |
248 | unsigned long flags; | |
249 | LIST_HEAD(head); | |
250 | ||
251 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
252 | ||
253 | /* | |
254 | * Stop DMA activity: we assume the callback will not be called | |
255 | * after edma_dma() returns (even if it does, it will see | |
256 | * echan->edesc is NULL and exit.) | |
257 | */ | |
258 | if (echan->edesc) { | |
8e8805d5 | 259 | int cyclic = echan->edesc->cyclic; |
c2dde5f8 MP |
260 | echan->edesc = NULL; |
261 | edma_stop(echan->ch_num); | |
8e8805d5 PU |
262 | /* Move the cyclic channel back to default queue */ |
263 | if (cyclic) | |
264 | edma_assign_channel_eventq(echan->ch_num, | |
265 | EVENTQ_DEFAULT); | |
c2dde5f8 MP |
266 | } |
267 | ||
268 | vchan_get_all_descriptors(&echan->vchan, &head); | |
269 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
270 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
c2dde5f8 | 275 | static int edma_slave_config(struct edma_chan *echan, |
661f7cb5 | 276 | struct dma_slave_config *cfg) |
c2dde5f8 | 277 | { |
661f7cb5 MP |
278 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
279 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
280 | return -EINVAL; |
281 | ||
661f7cb5 | 282 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
72c7b67a PU |
287 | static int edma_dma_pause(struct edma_chan *echan) |
288 | { | |
289 | /* Pause/Resume only allowed with cyclic mode */ | |
290 | if (!echan->edesc->cyclic) | |
291 | return -EINVAL; | |
292 | ||
293 | edma_pause(echan->ch_num); | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int edma_dma_resume(struct edma_chan *echan) | |
298 | { | |
299 | /* Pause/Resume only allowed with cyclic mode */ | |
300 | if (!echan->edesc->cyclic) | |
301 | return -EINVAL; | |
302 | ||
303 | edma_resume(echan->ch_num); | |
304 | return 0; | |
305 | } | |
306 | ||
c2dde5f8 MP |
307 | static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
308 | unsigned long arg) | |
309 | { | |
310 | int ret = 0; | |
311 | struct dma_slave_config *config; | |
312 | struct edma_chan *echan = to_edma_chan(chan); | |
313 | ||
314 | switch (cmd) { | |
315 | case DMA_TERMINATE_ALL: | |
316 | edma_terminate_all(echan); | |
317 | break; | |
318 | case DMA_SLAVE_CONFIG: | |
319 | config = (struct dma_slave_config *)arg; | |
320 | ret = edma_slave_config(echan, config); | |
321 | break; | |
72c7b67a PU |
322 | case DMA_PAUSE: |
323 | ret = edma_dma_pause(echan); | |
324 | break; | |
325 | ||
326 | case DMA_RESUME: | |
327 | ret = edma_dma_resume(echan); | |
328 | break; | |
329 | ||
c2dde5f8 MP |
330 | default: |
331 | ret = -ENOSYS; | |
332 | } | |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
fd009035 JF |
337 | /* |
338 | * A PaRAM set configuration abstraction used by other modes | |
339 | * @chan: Channel who's PaRAM set we're configuring | |
340 | * @pset: PaRAM set to initialize and setup. | |
341 | * @src_addr: Source address of the DMA | |
342 | * @dst_addr: Destination address of the DMA | |
343 | * @burst: In units of dev_width, how much to send | |
344 | * @dev_width: How much is the dev_width | |
345 | * @dma_length: Total length of the DMA transfer | |
346 | * @direction: Direction of the transfer | |
347 | */ | |
b5088ad9 | 348 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
fd009035 JF |
349 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
350 | enum dma_slave_buswidth dev_width, unsigned int dma_length, | |
351 | enum dma_transfer_direction direction) | |
352 | { | |
353 | struct edma_chan *echan = to_edma_chan(chan); | |
354 | struct device *dev = chan->device->dev; | |
b5088ad9 | 355 | struct edmacc_param *param = &epset->param; |
fd009035 JF |
356 | int acnt, bcnt, ccnt, cidx; |
357 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
358 | int absync; | |
359 | ||
360 | acnt = dev_width; | |
b2b617de PU |
361 | |
362 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ | |
363 | if (!burst) | |
364 | burst = 1; | |
fd009035 JF |
365 | /* |
366 | * If the maxburst is equal to the fifo width, use | |
367 | * A-synced transfers. This allows for large contiguous | |
368 | * buffer transfers using only one PaRAM set. | |
369 | */ | |
370 | if (burst == 1) { | |
371 | /* | |
372 | * For the A-sync case, bcnt and ccnt are the remainder | |
373 | * and quotient respectively of the division of: | |
374 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
375 | * that in case bcnt over flows, we have ccnt to use. | |
376 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
377 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
378 | * In this case, the best way adopted is- bccnt for the | |
379 | * first frame will be the remainder below. Then for | |
380 | * every successive frame, bcnt will be SZ_64K-1. This | |
381 | * is assured as bcntrld = 0xffff in end of function. | |
382 | */ | |
383 | absync = false; | |
384 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
385 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
386 | /* | |
387 | * If bcnt is non-zero, we have a remainder and hence an | |
388 | * extra frame to transfer, so increment ccnt. | |
389 | */ | |
390 | if (bcnt) | |
391 | ccnt++; | |
392 | else | |
393 | bcnt = SZ_64K - 1; | |
394 | cidx = acnt; | |
395 | } else { | |
396 | /* | |
397 | * If maxburst is greater than the fifo address_width, | |
398 | * use AB-synced transfers where A count is the fifo | |
399 | * address_width and B count is the maxburst. In this | |
400 | * case, we are limited to transfers of C count frames | |
401 | * of (address_width * maxburst) where C count is limited | |
402 | * to SZ_64K-1. This places an upper bound on the length | |
403 | * of an SG segment that can be handled. | |
404 | */ | |
405 | absync = true; | |
406 | bcnt = burst; | |
407 | ccnt = dma_length / (acnt * bcnt); | |
408 | if (ccnt > (SZ_64K - 1)) { | |
409 | dev_err(dev, "Exceeded max SG segment size\n"); | |
410 | return -EINVAL; | |
411 | } | |
412 | cidx = acnt * bcnt; | |
413 | } | |
414 | ||
c2da2340 TG |
415 | epset->len = dma_length; |
416 | ||
fd009035 JF |
417 | if (direction == DMA_MEM_TO_DEV) { |
418 | src_bidx = acnt; | |
419 | src_cidx = cidx; | |
420 | dst_bidx = 0; | |
421 | dst_cidx = 0; | |
c2da2340 | 422 | epset->addr = src_addr; |
fd009035 JF |
423 | } else if (direction == DMA_DEV_TO_MEM) { |
424 | src_bidx = 0; | |
425 | src_cidx = 0; | |
426 | dst_bidx = acnt; | |
427 | dst_cidx = cidx; | |
c2da2340 | 428 | epset->addr = dst_addr; |
8cc3e30b JF |
429 | } else if (direction == DMA_MEM_TO_MEM) { |
430 | src_bidx = acnt; | |
431 | src_cidx = cidx; | |
432 | dst_bidx = acnt; | |
433 | dst_cidx = cidx; | |
fd009035 JF |
434 | } else { |
435 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
b5088ad9 | 439 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
fd009035 JF |
440 | /* Configure A or AB synchronized transfers */ |
441 | if (absync) | |
b5088ad9 | 442 | param->opt |= SYNCDIM; |
fd009035 | 443 | |
b5088ad9 TG |
444 | param->src = src_addr; |
445 | param->dst = dst_addr; | |
fd009035 | 446 | |
b5088ad9 TG |
447 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
448 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
fd009035 | 449 | |
b5088ad9 TG |
450 | param->a_b_cnt = bcnt << 16 | acnt; |
451 | param->ccnt = ccnt; | |
fd009035 JF |
452 | /* |
453 | * Only time when (bcntrld) auto reload is required is for | |
454 | * A-sync case, and in this case, a requirement of reload value | |
455 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
456 | * and then later will be populated by edma_execute. | |
457 | */ | |
b5088ad9 | 458 | param->link_bcntrld = 0xffffffff; |
fd009035 JF |
459 | return absync; |
460 | } | |
461 | ||
c2dde5f8 MP |
462 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
463 | struct dma_chan *chan, struct scatterlist *sgl, | |
464 | unsigned int sg_len, enum dma_transfer_direction direction, | |
465 | unsigned long tx_flags, void *context) | |
466 | { | |
467 | struct edma_chan *echan = to_edma_chan(chan); | |
468 | struct device *dev = chan->device->dev; | |
469 | struct edma_desc *edesc; | |
fd009035 | 470 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
471 | enum dma_slave_buswidth dev_width; |
472 | u32 burst; | |
c2dde5f8 | 473 | struct scatterlist *sg; |
fd009035 | 474 | int i, nslots, ret; |
c2dde5f8 MP |
475 | |
476 | if (unlikely(!echan || !sgl || !sg_len)) | |
477 | return NULL; | |
478 | ||
661f7cb5 | 479 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 480 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
481 | dev_width = echan->cfg.src_addr_width; |
482 | burst = echan->cfg.src_maxburst; | |
483 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 484 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
485 | dev_width = echan->cfg.dst_addr_width; |
486 | burst = echan->cfg.dst_maxburst; | |
487 | } else { | |
e6fad592 | 488 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
661f7cb5 MP |
489 | return NULL; |
490 | } | |
491 | ||
492 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 493 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
494 | return NULL; |
495 | } | |
496 | ||
c2dde5f8 MP |
497 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
498 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
499 | if (!edesc) { | |
c594c891 | 500 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
c2dde5f8 MP |
501 | return NULL; |
502 | } | |
503 | ||
504 | edesc->pset_nr = sg_len; | |
b6205c39 | 505 | edesc->residue = 0; |
c2da2340 | 506 | edesc->direction = direction; |
740b41f7 | 507 | edesc->echan = echan; |
c2dde5f8 | 508 | |
6fbe24da JF |
509 | /* Allocate a PaRAM slot, if needed */ |
510 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
511 | ||
512 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
513 | if (echan->slot[i] < 0) { |
514 | echan->slot[i] = | |
515 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
516 | EDMA_SLOT_ANY); | |
517 | if (echan->slot[i] < 0) { | |
4b6271a6 | 518 | kfree(edesc); |
c594c891 PU |
519 | dev_err(dev, "%s: Failed to allocate slot\n", |
520 | __func__); | |
c2dde5f8 MP |
521 | return NULL; |
522 | } | |
523 | } | |
6fbe24da JF |
524 | } |
525 | ||
526 | /* Configure PaRAM sets for each SG */ | |
527 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
528 | /* Get address for each SG */ |
529 | if (direction == DMA_DEV_TO_MEM) | |
530 | dst_addr = sg_dma_address(sg); | |
531 | else | |
532 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 533 | |
fd009035 JF |
534 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
535 | dst_addr, burst, dev_width, | |
536 | sg_dma_len(sg), direction); | |
b967aecf VK |
537 | if (ret < 0) { |
538 | kfree(edesc); | |
fd009035 | 539 | return NULL; |
c2dde5f8 MP |
540 | } |
541 | ||
fd009035 | 542 | edesc->absync = ret; |
b6205c39 | 543 | edesc->residue += sg_dma_len(sg); |
6fbe24da JF |
544 | |
545 | /* If this is the last in a current SG set of transactions, | |
546 | enable interrupts so that next set is processed */ | |
547 | if (!((i+1) % MAX_NR_SG)) | |
b5088ad9 | 548 | edesc->pset[i].param.opt |= TCINTEN; |
6fbe24da | 549 | |
c2dde5f8 MP |
550 | /* If this is the last set, enable completion interrupt flag */ |
551 | if (i == sg_len - 1) | |
b5088ad9 | 552 | edesc->pset[i].param.opt |= TCINTEN; |
c2dde5f8 | 553 | } |
740b41f7 | 554 | edesc->residue_stat = edesc->residue; |
c2dde5f8 | 555 | |
c2dde5f8 MP |
556 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
557 | } | |
c2dde5f8 | 558 | |
8cc3e30b JF |
559 | struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
560 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
561 | size_t len, unsigned long tx_flags) | |
562 | { | |
563 | int ret; | |
564 | struct edma_desc *edesc; | |
565 | struct device *dev = chan->device->dev; | |
566 | struct edma_chan *echan = to_edma_chan(chan); | |
567 | ||
568 | if (unlikely(!echan || !len)) | |
569 | return NULL; | |
570 | ||
571 | edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC); | |
572 | if (!edesc) { | |
573 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
574 | return NULL; | |
575 | } | |
576 | ||
577 | edesc->pset_nr = 1; | |
578 | ||
579 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, | |
580 | DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM); | |
581 | if (ret < 0) | |
582 | return NULL; | |
583 | ||
584 | edesc->absync = ret; | |
585 | ||
586 | /* | |
587 | * Enable intermediate transfer chaining to re-trigger channel | |
588 | * on completion of every TR, and enable transfer-completion | |
589 | * interrupt on completion of the whole transfer. | |
590 | */ | |
b0cce4ca JF |
591 | edesc->pset[0].param.opt |= ITCCHEN; |
592 | edesc->pset[0].param.opt |= TCINTEN; | |
8cc3e30b JF |
593 | |
594 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
595 | } | |
596 | ||
50a9c707 JF |
597 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
598 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
599 | size_t period_len, enum dma_transfer_direction direction, | |
600 | unsigned long tx_flags, void *context) | |
601 | { | |
602 | struct edma_chan *echan = to_edma_chan(chan); | |
603 | struct device *dev = chan->device->dev; | |
604 | struct edma_desc *edesc; | |
605 | dma_addr_t src_addr, dst_addr; | |
606 | enum dma_slave_buswidth dev_width; | |
607 | u32 burst; | |
608 | int i, ret, nslots; | |
609 | ||
610 | if (unlikely(!echan || !buf_len || !period_len)) | |
611 | return NULL; | |
612 | ||
613 | if (direction == DMA_DEV_TO_MEM) { | |
614 | src_addr = echan->cfg.src_addr; | |
615 | dst_addr = buf_addr; | |
616 | dev_width = echan->cfg.src_addr_width; | |
617 | burst = echan->cfg.src_maxburst; | |
618 | } else if (direction == DMA_MEM_TO_DEV) { | |
619 | src_addr = buf_addr; | |
620 | dst_addr = echan->cfg.dst_addr; | |
621 | dev_width = echan->cfg.dst_addr_width; | |
622 | burst = echan->cfg.dst_maxburst; | |
623 | } else { | |
e6fad592 | 624 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
50a9c707 JF |
625 | return NULL; |
626 | } | |
627 | ||
628 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 629 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
630 | return NULL; |
631 | } | |
632 | ||
633 | if (unlikely(buf_len % period_len)) { | |
634 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
635 | return NULL; | |
636 | } | |
637 | ||
638 | nslots = (buf_len / period_len) + 1; | |
639 | ||
640 | /* | |
641 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
642 | * by cases where the number of periods is more than the maximum | |
643 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
644 | * such as Slave SGs, such delays are tolerable and synchronized, | |
645 | * but the synchronization is difficult to achieve with Cyclic and | |
646 | * cannot be guaranteed, so we error out early. | |
647 | */ | |
648 | if (nslots > MAX_NR_SG) | |
649 | return NULL; | |
650 | ||
651 | edesc = kzalloc(sizeof(*edesc) + nslots * | |
652 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
653 | if (!edesc) { | |
c594c891 | 654 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
50a9c707 JF |
655 | return NULL; |
656 | } | |
657 | ||
658 | edesc->cyclic = 1; | |
659 | edesc->pset_nr = nslots; | |
740b41f7 | 660 | edesc->residue = edesc->residue_stat = buf_len; |
c2da2340 | 661 | edesc->direction = direction; |
740b41f7 | 662 | edesc->echan = echan; |
50a9c707 | 663 | |
83bb3126 PU |
664 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
665 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
666 | |
667 | for (i = 0; i < nslots; i++) { | |
668 | /* Allocate a PaRAM slot, if needed */ | |
669 | if (echan->slot[i] < 0) { | |
670 | echan->slot[i] = | |
671 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
672 | EDMA_SLOT_ANY); | |
673 | if (echan->slot[i] < 0) { | |
e3ddc979 | 674 | kfree(edesc); |
c594c891 PU |
675 | dev_err(dev, "%s: Failed to allocate slot\n", |
676 | __func__); | |
50a9c707 JF |
677 | return NULL; |
678 | } | |
679 | } | |
680 | ||
681 | if (i == nslots - 1) { | |
682 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
683 | sizeof(edesc->pset[0])); | |
684 | break; | |
685 | } | |
686 | ||
687 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
688 | dst_addr, burst, dev_width, period_len, | |
689 | direction); | |
e3ddc979 CE |
690 | if (ret < 0) { |
691 | kfree(edesc); | |
50a9c707 | 692 | return NULL; |
e3ddc979 | 693 | } |
c2dde5f8 | 694 | |
50a9c707 JF |
695 | if (direction == DMA_DEV_TO_MEM) |
696 | dst_addr += period_len; | |
697 | else | |
698 | src_addr += period_len; | |
c2dde5f8 | 699 | |
83bb3126 PU |
700 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
701 | dev_vdbg(dev, | |
50a9c707 JF |
702 | "\n pset[%d]:\n" |
703 | " chnum\t%d\n" | |
704 | " slot\t%d\n" | |
705 | " opt\t%08x\n" | |
706 | " src\t%08x\n" | |
707 | " dst\t%08x\n" | |
708 | " abcnt\t%08x\n" | |
709 | " ccnt\t%08x\n" | |
710 | " bidx\t%08x\n" | |
711 | " cidx\t%08x\n" | |
712 | " lkrld\t%08x\n", | |
713 | i, echan->ch_num, echan->slot[i], | |
b5088ad9 TG |
714 | edesc->pset[i].param.opt, |
715 | edesc->pset[i].param.src, | |
716 | edesc->pset[i].param.dst, | |
717 | edesc->pset[i].param.a_b_cnt, | |
718 | edesc->pset[i].param.ccnt, | |
719 | edesc->pset[i].param.src_dst_bidx, | |
720 | edesc->pset[i].param.src_dst_cidx, | |
721 | edesc->pset[i].param.link_bcntrld); | |
50a9c707 JF |
722 | |
723 | edesc->absync = ret; | |
724 | ||
725 | /* | |
a1f146f3 | 726 | * Enable period interrupt only if it is requested |
50a9c707 | 727 | */ |
a1f146f3 PU |
728 | if (tx_flags & DMA_PREP_INTERRUPT) |
729 | edesc->pset[i].param.opt |= TCINTEN; | |
c2dde5f8 MP |
730 | } |
731 | ||
8e8805d5 PU |
732 | /* Place the cyclic channel to highest priority queue */ |
733 | edma_assign_channel_eventq(echan->ch_num, EVENTQ_0); | |
734 | ||
c2dde5f8 MP |
735 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
736 | } | |
737 | ||
738 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
739 | { | |
740 | struct edma_chan *echan = data; | |
741 | struct device *dev = echan->vchan.chan.device->dev; | |
742 | struct edma_desc *edesc; | |
c5f47990 | 743 | struct edmacc_param p; |
c2dde5f8 | 744 | |
50a9c707 JF |
745 | edesc = echan->edesc; |
746 | ||
747 | /* Pause the channel for non-cyclic */ | |
748 | if (!edesc || (edesc && !edesc->cyclic)) | |
749 | edma_pause(echan->ch_num); | |
c2dde5f8 MP |
750 | |
751 | switch (ch_status) { | |
db60d8da | 752 | case EDMA_DMA_COMPLETE: |
406efb1a | 753 | spin_lock(&echan->vchan.lock); |
c2dde5f8 | 754 | |
c2dde5f8 | 755 | if (edesc) { |
50a9c707 JF |
756 | if (edesc->cyclic) { |
757 | vchan_cyclic_callback(&edesc->vdesc); | |
758 | } else if (edesc->processed == edesc->pset_nr) { | |
53407062 | 759 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); |
b6205c39 | 760 | edesc->residue = 0; |
53407062 JF |
761 | edma_stop(echan->ch_num); |
762 | vchan_cookie_complete(&edesc->vdesc); | |
50a9c707 | 763 | edma_execute(echan); |
53407062 JF |
764 | } else { |
765 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
740b41f7 TG |
766 | |
767 | /* Update statistics for tx_status */ | |
768 | edesc->residue -= edesc->sg_len; | |
769 | edesc->residue_stat = edesc->residue; | |
770 | edesc->processed_stat = edesc->processed; | |
771 | ||
50a9c707 | 772 | edma_execute(echan); |
53407062 | 773 | } |
c2dde5f8 MP |
774 | } |
775 | ||
406efb1a | 776 | spin_unlock(&echan->vchan.lock); |
c2dde5f8 MP |
777 | |
778 | break; | |
db60d8da | 779 | case EDMA_DMA_CC_ERROR: |
406efb1a | 780 | spin_lock(&echan->vchan.lock); |
c5f47990 JF |
781 | |
782 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); | |
783 | ||
784 | /* | |
785 | * Issue later based on missed flag which will be sure | |
786 | * to happen as: | |
787 | * (1) we finished transmitting an intermediate slot and | |
788 | * edma_execute is coming up. | |
789 | * (2) or we finished current transfer and issue will | |
790 | * call edma_execute. | |
791 | * | |
792 | * Important note: issuing can be dangerous here and | |
793 | * lead to some nasty recursion when we are in a NULL | |
794 | * slot. So we avoid doing so and set the missed flag. | |
795 | */ | |
796 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
797 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
798 | echan->missed = 1; | |
799 | } else { | |
800 | /* | |
801 | * The slot is already programmed but the event got | |
802 | * missed, so its safe to issue it here. | |
803 | */ | |
804 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
805 | edma_clean_channel(echan->ch_num); | |
806 | edma_stop(echan->ch_num); | |
807 | edma_start(echan->ch_num); | |
808 | edma_trigger_channel(echan->ch_num); | |
809 | } | |
810 | ||
406efb1a | 811 | spin_unlock(&echan->vchan.lock); |
c5f47990 | 812 | |
c2dde5f8 MP |
813 | break; |
814 | default: | |
815 | break; | |
816 | } | |
817 | } | |
818 | ||
819 | /* Alloc channel resources */ | |
820 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
821 | { | |
822 | struct edma_chan *echan = to_edma_chan(chan); | |
823 | struct device *dev = chan->device->dev; | |
824 | int ret; | |
825 | int a_ch_num; | |
826 | LIST_HEAD(descs); | |
827 | ||
828 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
829 | chan, EVENTQ_DEFAULT); | |
830 | ||
831 | if (a_ch_num < 0) { | |
832 | ret = -ENODEV; | |
833 | goto err_no_chan; | |
834 | } | |
835 | ||
836 | if (a_ch_num != echan->ch_num) { | |
837 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
838 | EDMA_CTLR(echan->ch_num), | |
839 | EDMA_CHAN_SLOT(echan->ch_num)); | |
840 | ret = -ENODEV; | |
841 | goto err_wrong_chan; | |
842 | } | |
843 | ||
844 | echan->alloced = true; | |
845 | echan->slot[0] = echan->ch_num; | |
846 | ||
9aac9096 | 847 | dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, |
0e772c67 | 848 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); |
c2dde5f8 MP |
849 | |
850 | return 0; | |
851 | ||
852 | err_wrong_chan: | |
853 | edma_free_channel(a_ch_num); | |
854 | err_no_chan: | |
855 | return ret; | |
856 | } | |
857 | ||
858 | /* Free channel resources */ | |
859 | static void edma_free_chan_resources(struct dma_chan *chan) | |
860 | { | |
861 | struct edma_chan *echan = to_edma_chan(chan); | |
862 | struct device *dev = chan->device->dev; | |
863 | int i; | |
864 | ||
865 | /* Terminate transfers */ | |
866 | edma_stop(echan->ch_num); | |
867 | ||
868 | vchan_free_chan_resources(&echan->vchan); | |
869 | ||
870 | /* Free EDMA PaRAM slots */ | |
871 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
872 | if (echan->slot[i] >= 0) { | |
873 | edma_free_slot(echan->slot[i]); | |
874 | echan->slot[i] = -1; | |
875 | } | |
876 | } | |
877 | ||
878 | /* Free EDMA channel */ | |
879 | if (echan->alloced) { | |
880 | edma_free_channel(echan->ch_num); | |
881 | echan->alloced = false; | |
882 | } | |
883 | ||
0e772c67 | 884 | dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); |
c2dde5f8 MP |
885 | } |
886 | ||
887 | /* Send pending descriptor to hardware */ | |
888 | static void edma_issue_pending(struct dma_chan *chan) | |
889 | { | |
890 | struct edma_chan *echan = to_edma_chan(chan); | |
891 | unsigned long flags; | |
892 | ||
893 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
894 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
895 | edma_execute(echan); | |
896 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
897 | } | |
898 | ||
740b41f7 TG |
899 | static u32 edma_residue(struct edma_desc *edesc) |
900 | { | |
901 | bool dst = edesc->direction == DMA_DEV_TO_MEM; | |
902 | struct edma_pset *pset = edesc->pset; | |
903 | dma_addr_t done, pos; | |
904 | int i; | |
905 | ||
906 | /* | |
907 | * We always read the dst/src position from the first RamPar | |
908 | * pset. That's the one which is active now. | |
909 | */ | |
910 | pos = edma_get_position(edesc->echan->slot[0], dst); | |
911 | ||
912 | /* | |
913 | * Cyclic is simple. Just subtract pset[0].addr from pos. | |
914 | * | |
915 | * We never update edesc->residue in the cyclic case, so we | |
916 | * can tell the remaining room to the end of the circular | |
917 | * buffer. | |
918 | */ | |
919 | if (edesc->cyclic) { | |
920 | done = pos - pset->addr; | |
921 | edesc->residue_stat = edesc->residue - done; | |
922 | return edesc->residue_stat; | |
923 | } | |
924 | ||
925 | /* | |
926 | * For SG operation we catch up with the last processed | |
927 | * status. | |
928 | */ | |
929 | pset += edesc->processed_stat; | |
930 | ||
931 | for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { | |
932 | /* | |
933 | * If we are inside this pset address range, we know | |
934 | * this is the active one. Get the current delta and | |
935 | * stop walking the psets. | |
936 | */ | |
937 | if (pos >= pset->addr && pos < pset->addr + pset->len) | |
938 | return edesc->residue_stat - (pos - pset->addr); | |
939 | ||
940 | /* Otherwise mark it done and update residue_stat. */ | |
941 | edesc->processed_stat++; | |
942 | edesc->residue_stat -= pset->len; | |
943 | } | |
944 | return edesc->residue_stat; | |
945 | } | |
946 | ||
c2dde5f8 MP |
947 | /* Check request completion status */ |
948 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
949 | dma_cookie_t cookie, | |
950 | struct dma_tx_state *txstate) | |
951 | { | |
952 | struct edma_chan *echan = to_edma_chan(chan); | |
953 | struct virt_dma_desc *vdesc; | |
954 | enum dma_status ret; | |
955 | unsigned long flags; | |
956 | ||
957 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 958 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
959 | return ret; |
960 | ||
961 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
de135939 | 962 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
740b41f7 | 963 | txstate->residue = edma_residue(echan->edesc); |
de135939 TG |
964 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
965 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; | |
c2dde5f8 MP |
966 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
967 | ||
968 | return ret; | |
969 | } | |
970 | ||
971 | static void __init edma_chan_init(struct edma_cc *ecc, | |
972 | struct dma_device *dma, | |
973 | struct edma_chan *echans) | |
974 | { | |
975 | int i, j; | |
976 | ||
977 | for (i = 0; i < EDMA_CHANS; i++) { | |
978 | struct edma_chan *echan = &echans[i]; | |
979 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
980 | echan->ecc = ecc; | |
981 | echan->vchan.desc_free = edma_desc_free; | |
982 | ||
983 | vchan_init(&echan->vchan, dma); | |
984 | ||
985 | INIT_LIST_HEAD(&echan->node); | |
986 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
987 | echan->slot[j] = -1; | |
988 | } | |
989 | } | |
990 | ||
2c88ee6b PU |
991 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
992 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
993 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
994 | ||
995 | static int edma_dma_device_slave_caps(struct dma_chan *dchan, | |
996 | struct dma_slave_caps *caps) | |
997 | { | |
998 | caps->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
999 | caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1000 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1001 | caps->cmd_pause = true; | |
1002 | caps->cmd_terminate = true; | |
b7f9bc52 | 1003 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
2c88ee6b PU |
1004 | |
1005 | return 0; | |
1006 | } | |
1007 | ||
c2dde5f8 MP |
1008 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, |
1009 | struct device *dev) | |
1010 | { | |
1011 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
50a9c707 | 1012 | dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; |
8cc3e30b | 1013 | dma->device_prep_dma_memcpy = edma_prep_dma_memcpy; |
c2dde5f8 MP |
1014 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; |
1015 | dma->device_free_chan_resources = edma_free_chan_resources; | |
1016 | dma->device_issue_pending = edma_issue_pending; | |
1017 | dma->device_tx_status = edma_tx_status; | |
1018 | dma->device_control = edma_control; | |
2c88ee6b | 1019 | dma->device_slave_caps = edma_dma_device_slave_caps; |
c2dde5f8 MP |
1020 | dma->dev = dev; |
1021 | ||
8cc3e30b JF |
1022 | /* |
1023 | * code using dma memcpy must make sure alignment of | |
1024 | * length is at dma->copy_align boundary. | |
1025 | */ | |
1026 | dma->copy_align = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1027 | ||
c2dde5f8 MP |
1028 | INIT_LIST_HEAD(&dma->channels); |
1029 | } | |
1030 | ||
463a1f8b | 1031 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
1032 | { |
1033 | struct edma_cc *ecc; | |
1034 | int ret; | |
1035 | ||
94cb0e79 RK |
1036 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
1037 | if (ret) | |
1038 | return ret; | |
1039 | ||
c2dde5f8 MP |
1040 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); |
1041 | if (!ecc) { | |
1042 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
1043 | return -ENOMEM; | |
1044 | } | |
1045 | ||
1046 | ecc->ctlr = pdev->id; | |
1047 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
1048 | if (ecc->dummy_slot < 0) { | |
1049 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
1050 | return -EIO; | |
1051 | } | |
1052 | ||
1053 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
1054 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
232b223d | 1055 | dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); |
8cc3e30b | 1056 | dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); |
c2dde5f8 MP |
1057 | |
1058 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
1059 | ||
1060 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
1061 | ||
1062 | ret = dma_async_device_register(&ecc->dma_slave); | |
1063 | if (ret) | |
1064 | goto err_reg1; | |
1065 | ||
1066 | platform_set_drvdata(pdev, ecc); | |
1067 | ||
1068 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
1069 | ||
1070 | return 0; | |
1071 | ||
1072 | err_reg1: | |
1073 | edma_free_slot(ecc->dummy_slot); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
4bf27b8b | 1077 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
1078 | { |
1079 | struct device *dev = &pdev->dev; | |
1080 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
1081 | ||
1082 | dma_async_device_unregister(&ecc->dma_slave); | |
1083 | edma_free_slot(ecc->dummy_slot); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static struct platform_driver edma_driver = { | |
1089 | .probe = edma_probe, | |
a7d6e3ec | 1090 | .remove = edma_remove, |
c2dde5f8 MP |
1091 | .driver = { |
1092 | .name = "edma-dma-engine", | |
1093 | .owner = THIS_MODULE, | |
1094 | }, | |
1095 | }; | |
1096 | ||
1097 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
1098 | { | |
1099 | if (chan->device->dev->driver == &edma_driver.driver) { | |
1100 | struct edma_chan *echan = to_edma_chan(chan); | |
1101 | unsigned ch_req = *(unsigned *)param; | |
1102 | return ch_req == echan->ch_num; | |
1103 | } | |
1104 | return false; | |
1105 | } | |
1106 | EXPORT_SYMBOL(edma_filter_fn); | |
1107 | ||
1108 | static struct platform_device *pdev0, *pdev1; | |
1109 | ||
1110 | static const struct platform_device_info edma_dev_info0 = { | |
1111 | .name = "edma-dma-engine", | |
1112 | .id = 0, | |
94cb0e79 | 1113 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
1114 | }; |
1115 | ||
1116 | static const struct platform_device_info edma_dev_info1 = { | |
1117 | .name = "edma-dma-engine", | |
1118 | .id = 1, | |
94cb0e79 | 1119 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
1120 | }; |
1121 | ||
1122 | static int edma_init(void) | |
1123 | { | |
1124 | int ret = platform_driver_register(&edma_driver); | |
1125 | ||
1126 | if (ret == 0) { | |
1127 | pdev0 = platform_device_register_full(&edma_dev_info0); | |
1128 | if (IS_ERR(pdev0)) { | |
1129 | platform_driver_unregister(&edma_driver); | |
1130 | ret = PTR_ERR(pdev0); | |
1131 | goto out; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | if (EDMA_CTLRS == 2) { | |
1136 | pdev1 = platform_device_register_full(&edma_dev_info1); | |
1137 | if (IS_ERR(pdev1)) { | |
1138 | platform_driver_unregister(&edma_driver); | |
1139 | platform_device_unregister(pdev0); | |
1140 | ret = PTR_ERR(pdev1); | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | out: | |
1145 | return ret; | |
1146 | } | |
1147 | subsys_initcall(edma_init); | |
1148 | ||
1149 | static void __exit edma_exit(void) | |
1150 | { | |
1151 | platform_device_unregister(pdev0); | |
1152 | if (pdev1) | |
1153 | platform_device_unregister(pdev1); | |
1154 | platform_driver_unregister(&edma_driver); | |
1155 | } | |
1156 | module_exit(edma_exit); | |
1157 | ||
d71505b6 | 1158 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
1159 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
1160 | MODULE_LICENSE("GPL v2"); |