Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
5af50730 RH |
36 | #include <linux/of_address.h> |
37 | #include <linux/of_irq.h> | |
173acc7c | 38 | #include <linux/of_platform.h> |
0a5642be | 39 | #include <linux/fsldma.h> |
d2ebfb33 | 40 | #include "dmaengine.h" |
173acc7c ZW |
41 | #include "fsldma.h" |
42 | ||
b158471e IS |
43 | #define chan_dbg(chan, fmt, arg...) \ |
44 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
45 | #define chan_err(chan, fmt, arg...) \ | |
46 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 47 | |
b158471e | 48 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 49 | |
e8bd84df IS |
50 | /* |
51 | * Register Helpers | |
52 | */ | |
173acc7c | 53 | |
a1c03319 | 54 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 55 | { |
a1c03319 | 56 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
57 | } |
58 | ||
a1c03319 | 59 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 60 | { |
a1c03319 | 61 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
62 | } |
63 | ||
ccdce9a0 HZ |
64 | static void set_mr(struct fsldma_chan *chan, u32 val) |
65 | { | |
66 | DMA_OUT(chan, &chan->regs->mr, val, 32); | |
67 | } | |
68 | ||
69 | static u32 get_mr(struct fsldma_chan *chan) | |
70 | { | |
71 | return DMA_IN(chan, &chan->regs->mr, 32); | |
72 | } | |
73 | ||
e8bd84df IS |
74 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
75 | { | |
76 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
77 | } | |
78 | ||
79 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
80 | { | |
81 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
82 | } | |
83 | ||
ccdce9a0 HZ |
84 | static void set_bcr(struct fsldma_chan *chan, u32 val) |
85 | { | |
86 | DMA_OUT(chan, &chan->regs->bcr, val, 32); | |
87 | } | |
88 | ||
e8bd84df IS |
89 | static u32 get_bcr(struct fsldma_chan *chan) |
90 | { | |
91 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
92 | } | |
93 | ||
94 | /* | |
95 | * Descriptor Helpers | |
96 | */ | |
97 | ||
a1c03319 | 98 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
99 | struct fsl_dma_ld_hw *hw, u32 count) |
100 | { | |
a1c03319 | 101 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
102 | } |
103 | ||
a1c03319 | 104 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 105 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
106 | { |
107 | u64 snoop_bits; | |
108 | ||
a1c03319 | 109 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 110 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 111 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
112 | } |
113 | ||
a1c03319 | 114 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 115 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
116 | { |
117 | u64 snoop_bits; | |
118 | ||
a1c03319 | 119 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 120 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 121 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
122 | } |
123 | ||
a1c03319 | 124 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 125 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
126 | { |
127 | u64 snoop_bits; | |
128 | ||
a1c03319 | 129 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 130 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 131 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
132 | } |
133 | ||
31f4306c | 134 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 135 | { |
e8bd84df | 136 | u64 snoop_bits; |
173acc7c | 137 | |
e8bd84df IS |
138 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
139 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 140 | |
e8bd84df IS |
141 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
142 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
143 | | snoop_bits, 64); | |
173acc7c ZW |
144 | } |
145 | ||
e8bd84df IS |
146 | /* |
147 | * DMA Engine Hardware Control Helpers | |
148 | */ | |
149 | ||
150 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 151 | { |
e8bd84df | 152 | /* Reset the channel */ |
ccdce9a0 | 153 | set_mr(chan, 0); |
e8bd84df IS |
154 | |
155 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
156 | case FSL_DMA_IP_85XX: | |
157 | /* Set the channel to below modes: | |
158 | * EIE - Error interrupt enable | |
e8bd84df IS |
159 | * EOLNIE - End of links interrupt enable |
160 | * BWC - Bandwidth sharing among channels | |
161 | */ | |
ccdce9a0 HZ |
162 | set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE |
163 | | FSL_DMA_MR_EOLNIE); | |
e8bd84df IS |
164 | break; |
165 | case FSL_DMA_IP_83XX: | |
166 | /* Set the channel to below modes: | |
167 | * EOTIE - End-of-transfer interrupt enable | |
168 | * PRC_RM - PCI read multiple | |
169 | */ | |
ccdce9a0 | 170 | set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM); |
e8bd84df IS |
171 | break; |
172 | } | |
f79abb62 ZW |
173 | } |
174 | ||
a1c03319 | 175 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 176 | { |
a1c03319 | 177 | u32 sr = get_sr(chan); |
173acc7c ZW |
178 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
179 | } | |
180 | ||
f04cd407 IS |
181 | /* |
182 | * Start the DMA controller | |
183 | * | |
184 | * Preconditions: | |
185 | * - the CDAR register must point to the start descriptor | |
186 | * - the MRn[CS] bit must be cleared | |
187 | */ | |
a1c03319 | 188 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 189 | { |
272ca655 IS |
190 | u32 mode; |
191 | ||
ccdce9a0 | 192 | mode = get_mr(chan); |
272ca655 | 193 | |
f04cd407 | 194 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
ccdce9a0 | 195 | set_bcr(chan, 0); |
f04cd407 IS |
196 | mode |= FSL_DMA_MR_EMP_EN; |
197 | } else { | |
198 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 199 | } |
173acc7c | 200 | |
f04cd407 | 201 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 202 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
203 | } else { |
204 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 205 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 206 | } |
173acc7c | 207 | |
ccdce9a0 | 208 | set_mr(chan, mode); |
173acc7c ZW |
209 | } |
210 | ||
a1c03319 | 211 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 212 | { |
272ca655 | 213 | u32 mode; |
900325a6 DW |
214 | int i; |
215 | ||
a00ae34a | 216 | /* read the mode register */ |
ccdce9a0 | 217 | mode = get_mr(chan); |
272ca655 | 218 | |
a00ae34a IS |
219 | /* |
220 | * The 85xx controller supports channel abort, which will stop | |
221 | * the current transfer. On 83xx, this bit is the transfer error | |
222 | * mask bit, which should not be changed. | |
223 | */ | |
224 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
225 | mode |= FSL_DMA_MR_CA; | |
ccdce9a0 | 226 | set_mr(chan, mode); |
a00ae34a IS |
227 | |
228 | mode &= ~FSL_DMA_MR_CA; | |
229 | } | |
230 | ||
231 | /* stop the DMA controller */ | |
232 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
ccdce9a0 | 233 | set_mr(chan, mode); |
173acc7c | 234 | |
a00ae34a | 235 | /* wait for the DMA controller to become idle */ |
900325a6 | 236 | for (i = 0; i < 100; i++) { |
a1c03319 | 237 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
238 | return; |
239 | ||
173acc7c | 240 | udelay(10); |
900325a6 | 241 | } |
272ca655 | 242 | |
9c3a50b7 | 243 | if (!dma_is_idle(chan)) |
b158471e | 244 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
245 | } |
246 | ||
173acc7c ZW |
247 | /** |
248 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 249 | * @chan : Freescale DMA channel |
173acc7c ZW |
250 | * @size : Address loop size, 0 for disable loop |
251 | * | |
252 | * The set source address hold transfer size. The source | |
253 | * address hold or loop transfer size is when the DMA transfer | |
254 | * data from source address (SA), if the loop size is 4, the DMA will | |
255 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
256 | * SA + 1 ... and so on. | |
257 | */ | |
a1c03319 | 258 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 259 | { |
272ca655 IS |
260 | u32 mode; |
261 | ||
ccdce9a0 | 262 | mode = get_mr(chan); |
272ca655 | 263 | |
173acc7c ZW |
264 | switch (size) { |
265 | case 0: | |
272ca655 | 266 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
267 | break; |
268 | case 1: | |
269 | case 2: | |
270 | case 4: | |
271 | case 8: | |
272ca655 | 272 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
273 | break; |
274 | } | |
272ca655 | 275 | |
ccdce9a0 | 276 | set_mr(chan, mode); |
173acc7c ZW |
277 | } |
278 | ||
279 | /** | |
738f5f7e | 280 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 281 | * @chan : Freescale DMA channel |
173acc7c ZW |
282 | * @size : Address loop size, 0 for disable loop |
283 | * | |
284 | * The set destination address hold transfer size. The destination | |
285 | * address hold or loop transfer size is when the DMA transfer | |
286 | * data to destination address (TA), if the loop size is 4, the DMA will | |
287 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
288 | * TA + 1 ... and so on. | |
289 | */ | |
a1c03319 | 290 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 291 | { |
272ca655 IS |
292 | u32 mode; |
293 | ||
ccdce9a0 | 294 | mode = get_mr(chan); |
272ca655 | 295 | |
173acc7c ZW |
296 | switch (size) { |
297 | case 0: | |
272ca655 | 298 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
299 | break; |
300 | case 1: | |
301 | case 2: | |
302 | case 4: | |
303 | case 8: | |
272ca655 | 304 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
305 | break; |
306 | } | |
272ca655 | 307 | |
ccdce9a0 | 308 | set_mr(chan, mode); |
173acc7c ZW |
309 | } |
310 | ||
311 | /** | |
e6c7ecb6 | 312 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 313 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
314 | * @size : Number of bytes to transfer in a single request |
315 | * | |
316 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
317 | * The DMA request count is how many bytes are allowed to transfer before | |
318 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
319 | * operation. | |
173acc7c | 320 | * |
e6c7ecb6 | 321 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 322 | */ |
a1c03319 | 323 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 324 | { |
272ca655 IS |
325 | u32 mode; |
326 | ||
e6c7ecb6 | 327 | BUG_ON(size > 1024); |
272ca655 | 328 | |
ccdce9a0 | 329 | mode = get_mr(chan); |
272ca655 IS |
330 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
331 | ||
ccdce9a0 | 332 | set_mr(chan, mode); |
e6c7ecb6 | 333 | } |
173acc7c | 334 | |
e6c7ecb6 IS |
335 | /** |
336 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 337 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
338 | * @enable : 0 is disabled, 1 is enabled. |
339 | * | |
340 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
341 | * The DMA Request Count feature should be used in addition to this feature | |
342 | * to set the number of bytes to transfer before pausing the channel. | |
343 | */ | |
a1c03319 | 344 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
345 | { |
346 | if (enable) | |
a1c03319 | 347 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 348 | else |
a1c03319 | 349 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
350 | } |
351 | ||
352 | /** | |
353 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 354 | * @chan : Freescale DMA channel |
173acc7c ZW |
355 | * @enable : 0 is disabled, 1 is enabled. |
356 | * | |
357 | * If enable the external start, the channel can be started by an | |
358 | * external DMA start pin. So the dma_start() does not start the | |
359 | * transfer immediately. The DMA channel will wait for the | |
360 | * control pin asserted. | |
361 | */ | |
a1c03319 | 362 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
363 | { |
364 | if (enable) | |
a1c03319 | 365 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 366 | else |
a1c03319 | 367 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
368 | } |
369 | ||
0a5642be VK |
370 | int fsl_dma_external_start(struct dma_chan *dchan, int enable) |
371 | { | |
372 | struct fsldma_chan *chan; | |
373 | ||
374 | if (!dchan) | |
375 | return -EINVAL; | |
376 | ||
377 | chan = to_fsl_chan(dchan); | |
378 | ||
379 | fsl_chan_toggle_ext_start(chan, enable); | |
380 | return 0; | |
381 | } | |
382 | EXPORT_SYMBOL_GPL(fsl_dma_external_start); | |
383 | ||
31f4306c | 384 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
385 | { |
386 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
387 | ||
388 | if (list_empty(&chan->ld_pending)) | |
389 | goto out_splice; | |
390 | ||
391 | /* | |
392 | * Add the hardware descriptor to the chain of hardware descriptors | |
393 | * that already exists in memory. | |
394 | * | |
395 | * This will un-set the EOL bit of the existing transaction, and the | |
396 | * last link in this transaction will become the EOL descriptor. | |
397 | */ | |
398 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
399 | ||
400 | /* | |
401 | * Add the software descriptor and all children to the list | |
402 | * of pending transactions | |
403 | */ | |
404 | out_splice: | |
405 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
406 | } | |
407 | ||
173acc7c ZW |
408 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
409 | { | |
a1c03319 | 410 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
411 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
412 | struct fsl_desc_sw *child; | |
bbc76560 | 413 | dma_cookie_t cookie = -EINVAL; |
173acc7c | 414 | |
2baff570 | 415 | spin_lock_bh(&chan->desc_lock); |
173acc7c | 416 | |
14c6a333 HZ |
417 | #ifdef CONFIG_PM |
418 | if (unlikely(chan->pm_state != RUNNING)) { | |
419 | chan_dbg(chan, "cannot submit due to suspend\n"); | |
420 | spin_unlock_bh(&chan->desc_lock); | |
421 | return -1; | |
422 | } | |
423 | #endif | |
424 | ||
9c3a50b7 IS |
425 | /* |
426 | * assign cookies to all of the software descriptors | |
427 | * that make up this transaction | |
428 | */ | |
eda34234 | 429 | list_for_each_entry(child, &desc->tx_list, node) { |
884485e1 | 430 | cookie = dma_cookie_assign(&child->async_tx); |
bcfb7465 IS |
431 | } |
432 | ||
9c3a50b7 | 433 | /* put this transaction onto the tail of the pending queue */ |
a1c03319 | 434 | append_ld_queue(chan, desc); |
173acc7c | 435 | |
2baff570 | 436 | spin_unlock_bh(&chan->desc_lock); |
173acc7c ZW |
437 | |
438 | return cookie; | |
439 | } | |
440 | ||
86d19a54 HZ |
441 | /** |
442 | * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool. | |
443 | * @chan : Freescale DMA channel | |
444 | * @desc: descriptor to be freed | |
445 | */ | |
446 | static void fsl_dma_free_descriptor(struct fsldma_chan *chan, | |
447 | struct fsl_desc_sw *desc) | |
448 | { | |
449 | list_del(&desc->node); | |
450 | chan_dbg(chan, "LD %p free\n", desc); | |
451 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
452 | } | |
453 | ||
173acc7c ZW |
454 | /** |
455 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 456 | * @chan : Freescale DMA channel |
173acc7c ZW |
457 | * |
458 | * Return - The descriptor allocated. NULL for failed. | |
459 | */ | |
31f4306c | 460 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 461 | { |
9c3a50b7 | 462 | struct fsl_desc_sw *desc; |
173acc7c | 463 | dma_addr_t pdesc; |
9c3a50b7 IS |
464 | |
465 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
466 | if (!desc) { | |
b158471e | 467 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 468 | return NULL; |
173acc7c ZW |
469 | } |
470 | ||
9c3a50b7 IS |
471 | memset(desc, 0, sizeof(*desc)); |
472 | INIT_LIST_HEAD(&desc->tx_list); | |
473 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
474 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
475 | desc->async_tx.phys = pdesc; | |
476 | ||
0ab09c36 | 477 | chan_dbg(chan, "LD %p allocated\n", desc); |
0ab09c36 | 478 | |
9c3a50b7 | 479 | return desc; |
173acc7c ZW |
480 | } |
481 | ||
43452fad HZ |
482 | /** |
483 | * fsldma_clean_completed_descriptor - free all descriptors which | |
484 | * has been completed and acked | |
485 | * @chan: Freescale DMA channel | |
486 | * | |
487 | * This function is used on all completed and acked descriptors. | |
488 | * All descriptors should only be freed in this function. | |
489 | */ | |
490 | static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan) | |
491 | { | |
492 | struct fsl_desc_sw *desc, *_desc; | |
493 | ||
494 | /* Run the callback for each descriptor, in order */ | |
495 | list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) | |
496 | if (async_tx_test_ack(&desc->async_tx)) | |
497 | fsl_dma_free_descriptor(chan, desc); | |
498 | } | |
499 | ||
500 | /** | |
501 | * fsldma_run_tx_complete_actions - cleanup a single link descriptor | |
502 | * @chan: Freescale DMA channel | |
503 | * @desc: descriptor to cleanup and free | |
504 | * @cookie: Freescale DMA transaction identifier | |
505 | * | |
506 | * This function is used on a descriptor which has been executed by the DMA | |
507 | * controller. It will run any callbacks, submit any dependencies. | |
508 | */ | |
509 | static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan, | |
510 | struct fsl_desc_sw *desc, dma_cookie_t cookie) | |
511 | { | |
512 | struct dma_async_tx_descriptor *txd = &desc->async_tx; | |
513 | dma_cookie_t ret = cookie; | |
514 | ||
515 | BUG_ON(txd->cookie < 0); | |
516 | ||
517 | if (txd->cookie > 0) { | |
518 | ret = txd->cookie; | |
519 | ||
520 | /* Run the link descriptor callback function */ | |
521 | if (txd->callback) { | |
522 | chan_dbg(chan, "LD %p callback\n", desc); | |
523 | txd->callback(txd->callback_param); | |
524 | } | |
525 | } | |
526 | ||
527 | /* Run any dependencies */ | |
528 | dma_run_dependencies(txd); | |
529 | ||
530 | return ret; | |
531 | } | |
532 | ||
533 | /** | |
534 | * fsldma_clean_running_descriptor - move the completed descriptor from | |
535 | * ld_running to ld_completed | |
536 | * @chan: Freescale DMA channel | |
537 | * @desc: the descriptor which is completed | |
538 | * | |
539 | * Free the descriptor directly if acked by async_tx api, or move it to | |
540 | * queue ld_completed. | |
541 | */ | |
542 | static void fsldma_clean_running_descriptor(struct fsldma_chan *chan, | |
543 | struct fsl_desc_sw *desc) | |
544 | { | |
545 | /* Remove from the list of transactions */ | |
546 | list_del(&desc->node); | |
547 | ||
548 | /* | |
549 | * the client is allowed to attach dependent operations | |
550 | * until 'ack' is set | |
551 | */ | |
552 | if (!async_tx_test_ack(&desc->async_tx)) { | |
553 | /* | |
554 | * Move this descriptor to the list of descriptors which is | |
555 | * completed, but still awaiting the 'ack' bit to be set. | |
556 | */ | |
557 | list_add_tail(&desc->node, &chan->ld_completed); | |
558 | return; | |
559 | } | |
560 | ||
561 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
562 | } | |
563 | ||
2a5ecb79 HZ |
564 | /** |
565 | * fsl_chan_xfer_ld_queue - transfer any pending transactions | |
566 | * @chan : Freescale DMA channel | |
567 | * | |
568 | * HARDWARE STATE: idle | |
569 | * LOCKING: must hold chan->desc_lock | |
570 | */ | |
571 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) | |
572 | { | |
573 | struct fsl_desc_sw *desc; | |
574 | ||
575 | /* | |
576 | * If the list of pending descriptors is empty, then we | |
577 | * don't need to do any work at all | |
578 | */ | |
579 | if (list_empty(&chan->ld_pending)) { | |
580 | chan_dbg(chan, "no pending LDs\n"); | |
581 | return; | |
582 | } | |
583 | ||
584 | /* | |
585 | * The DMA controller is not idle, which means that the interrupt | |
586 | * handler will start any queued transactions when it runs after | |
587 | * this transaction finishes | |
588 | */ | |
589 | if (!chan->idle) { | |
590 | chan_dbg(chan, "DMA controller still busy\n"); | |
591 | return; | |
592 | } | |
593 | ||
594 | /* | |
595 | * If there are some link descriptors which have not been | |
596 | * transferred, we need to start the controller | |
597 | */ | |
598 | ||
599 | /* | |
600 | * Move all elements from the queue of pending transactions | |
601 | * onto the list of running transactions | |
602 | */ | |
603 | chan_dbg(chan, "idle, starting controller\n"); | |
604 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
605 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
606 | ||
607 | /* | |
608 | * The 85xx DMA controller doesn't clear the channel start bit | |
609 | * automatically at the end of a transfer. Therefore we must clear | |
610 | * it in software before starting the transfer. | |
611 | */ | |
612 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
613 | u32 mode; | |
614 | ||
615 | mode = get_mr(chan); | |
616 | mode &= ~FSL_DMA_MR_CS; | |
617 | set_mr(chan, mode); | |
618 | } | |
619 | ||
620 | /* | |
621 | * Program the descriptor's address into the DMA controller, | |
622 | * then start the DMA transaction | |
623 | */ | |
624 | set_cdar(chan, desc->async_tx.phys); | |
625 | get_cdar(chan); | |
626 | ||
627 | dma_start(chan); | |
628 | chan->idle = false; | |
629 | } | |
630 | ||
631 | /** | |
43452fad HZ |
632 | * fsldma_cleanup_descriptors - cleanup link descriptors which are completed |
633 | * and move them to ld_completed to free until flag 'ack' is set | |
2a5ecb79 | 634 | * @chan: Freescale DMA channel |
2a5ecb79 | 635 | * |
43452fad HZ |
636 | * This function is used on descriptors which have been executed by the DMA |
637 | * controller. It will run any callbacks, submit any dependencies, then | |
638 | * free these descriptors if flag 'ack' is set. | |
2a5ecb79 | 639 | */ |
43452fad | 640 | static void fsldma_cleanup_descriptors(struct fsldma_chan *chan) |
2a5ecb79 | 641 | { |
43452fad HZ |
642 | struct fsl_desc_sw *desc, *_desc; |
643 | dma_cookie_t cookie = 0; | |
644 | dma_addr_t curr_phys = get_cdar(chan); | |
645 | int seen_current = 0; | |
2a5ecb79 | 646 | |
43452fad HZ |
647 | fsldma_clean_completed_descriptor(chan); |
648 | ||
649 | /* Run the callback for each descriptor, in order */ | |
650 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { | |
651 | /* | |
652 | * do not advance past the current descriptor loaded into the | |
653 | * hardware channel, subsequent descriptors are either in | |
654 | * process or have not been submitted | |
655 | */ | |
656 | if (seen_current) | |
657 | break; | |
658 | ||
659 | /* | |
660 | * stop the search if we reach the current descriptor and the | |
661 | * channel is busy | |
662 | */ | |
663 | if (desc->async_tx.phys == curr_phys) { | |
664 | seen_current = 1; | |
665 | if (!dma_is_idle(chan)) | |
666 | break; | |
667 | } | |
668 | ||
669 | cookie = fsldma_run_tx_complete_actions(chan, desc, cookie); | |
670 | ||
671 | fsldma_clean_running_descriptor(chan, desc); | |
2a5ecb79 HZ |
672 | } |
673 | ||
43452fad HZ |
674 | /* |
675 | * Start any pending transactions automatically | |
676 | * | |
677 | * In the ideal case, we keep the DMA controller busy while we go | |
678 | * ahead and free the descriptors below. | |
679 | */ | |
680 | fsl_chan_xfer_ld_queue(chan); | |
2a5ecb79 | 681 | |
43452fad HZ |
682 | if (cookie > 0) |
683 | chan->common.completed_cookie = cookie; | |
2a5ecb79 HZ |
684 | } |
685 | ||
173acc7c ZW |
686 | /** |
687 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 688 | * @chan : Freescale DMA channel |
173acc7c ZW |
689 | * |
690 | * This function will create a dma pool for descriptor allocation. | |
691 | * | |
692 | * Return - The number of descriptors allocated. | |
693 | */ | |
a1c03319 | 694 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 695 | { |
a1c03319 | 696 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
697 | |
698 | /* Has this channel already been allocated? */ | |
a1c03319 | 699 | if (chan->desc_pool) |
77cd62e8 | 700 | return 1; |
173acc7c | 701 | |
9c3a50b7 IS |
702 | /* |
703 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
704 | * for meeting FSL DMA specification requirement. |
705 | */ | |
b158471e | 706 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
707 | sizeof(struct fsl_desc_sw), |
708 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 709 | if (!chan->desc_pool) { |
b158471e | 710 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 711 | return -ENOMEM; |
173acc7c ZW |
712 | } |
713 | ||
9c3a50b7 | 714 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
715 | return 1; |
716 | } | |
717 | ||
9c3a50b7 IS |
718 | /** |
719 | * fsldma_free_desc_list - Free all descriptors in a queue | |
720 | * @chan: Freescae DMA channel | |
721 | * @list: the list to free | |
722 | * | |
723 | * LOCKING: must hold chan->desc_lock | |
724 | */ | |
725 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
726 | struct list_head *list) | |
727 | { | |
728 | struct fsl_desc_sw *desc, *_desc; | |
729 | ||
86d19a54 HZ |
730 | list_for_each_entry_safe(desc, _desc, list, node) |
731 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
732 | } |
733 | ||
734 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
735 | struct list_head *list) | |
736 | { | |
737 | struct fsl_desc_sw *desc, *_desc; | |
738 | ||
86d19a54 HZ |
739 | list_for_each_entry_safe_reverse(desc, _desc, list, node) |
740 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
741 | } |
742 | ||
173acc7c ZW |
743 | /** |
744 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 745 | * @chan : Freescale DMA channel |
173acc7c | 746 | */ |
a1c03319 | 747 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 748 | { |
a1c03319 | 749 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c | 750 | |
b158471e | 751 | chan_dbg(chan, "free all channel resources\n"); |
2baff570 | 752 | spin_lock_bh(&chan->desc_lock); |
43452fad | 753 | fsldma_cleanup_descriptors(chan); |
9c3a50b7 IS |
754 | fsldma_free_desc_list(chan, &chan->ld_pending); |
755 | fsldma_free_desc_list(chan, &chan->ld_running); | |
43452fad | 756 | fsldma_free_desc_list(chan, &chan->ld_completed); |
2baff570 | 757 | spin_unlock_bh(&chan->desc_lock); |
77cd62e8 | 758 | |
9c3a50b7 | 759 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 760 | chan->desc_pool = NULL; |
173acc7c ZW |
761 | } |
762 | ||
31f4306c IS |
763 | static struct dma_async_tx_descriptor * |
764 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
765 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
766 | size_t len, unsigned long flags) |
767 | { | |
a1c03319 | 768 | struct fsldma_chan *chan; |
173acc7c ZW |
769 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
770 | size_t copy; | |
173acc7c | 771 | |
a1c03319 | 772 | if (!dchan) |
173acc7c ZW |
773 | return NULL; |
774 | ||
775 | if (!len) | |
776 | return NULL; | |
777 | ||
a1c03319 | 778 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
779 | |
780 | do { | |
781 | ||
782 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 783 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 784 | if (!new) { |
b158471e | 785 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 786 | goto fail; |
173acc7c | 787 | } |
173acc7c | 788 | |
56822843 | 789 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 790 | |
a1c03319 IS |
791 | set_desc_cnt(chan, &new->hw, copy); |
792 | set_desc_src(chan, &new->hw, dma_src); | |
793 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
794 | |
795 | if (!first) | |
796 | first = new; | |
797 | else | |
a1c03319 | 798 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
799 | |
800 | new->async_tx.cookie = 0; | |
636bdeaa | 801 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
802 | |
803 | prev = new; | |
804 | len -= copy; | |
805 | dma_src += copy; | |
738f5f7e | 806 | dma_dst += copy; |
173acc7c ZW |
807 | |
808 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 809 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
810 | } while (len); |
811 | ||
636bdeaa | 812 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
813 | new->async_tx.cookie = -EBUSY; |
814 | ||
31f4306c | 815 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 816 | set_ld_eol(chan, new); |
173acc7c | 817 | |
2e077f8e IS |
818 | return &first->async_tx; |
819 | ||
820 | fail: | |
821 | if (!first) | |
822 | return NULL; | |
823 | ||
9c3a50b7 | 824 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 825 | return NULL; |
173acc7c ZW |
826 | } |
827 | ||
c1433041 IS |
828 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
829 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
830 | struct scatterlist *src_sg, unsigned int src_nents, | |
831 | unsigned long flags) | |
832 | { | |
833 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
834 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
835 | size_t dst_avail, src_avail; | |
836 | dma_addr_t dst, src; | |
837 | size_t len; | |
838 | ||
839 | /* basic sanity checks */ | |
840 | if (dst_nents == 0 || src_nents == 0) | |
841 | return NULL; | |
842 | ||
843 | if (dst_sg == NULL || src_sg == NULL) | |
844 | return NULL; | |
845 | ||
846 | /* | |
847 | * TODO: should we check that both scatterlists have the same | |
848 | * TODO: number of bytes in total? Is that really an error? | |
849 | */ | |
850 | ||
851 | /* get prepared for the loop */ | |
852 | dst_avail = sg_dma_len(dst_sg); | |
853 | src_avail = sg_dma_len(src_sg); | |
854 | ||
855 | /* run until we are out of scatterlist entries */ | |
856 | while (true) { | |
857 | ||
858 | /* create the largest transaction possible */ | |
859 | len = min_t(size_t, src_avail, dst_avail); | |
860 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
861 | if (len == 0) | |
862 | goto fetch; | |
863 | ||
864 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
865 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
866 | ||
867 | /* allocate and populate the descriptor */ | |
868 | new = fsl_dma_alloc_descriptor(chan); | |
869 | if (!new) { | |
b158471e | 870 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
871 | goto fail; |
872 | } | |
c1433041 IS |
873 | |
874 | set_desc_cnt(chan, &new->hw, len); | |
875 | set_desc_src(chan, &new->hw, src); | |
876 | set_desc_dst(chan, &new->hw, dst); | |
877 | ||
878 | if (!first) | |
879 | first = new; | |
880 | else | |
881 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
882 | ||
883 | new->async_tx.cookie = 0; | |
884 | async_tx_ack(&new->async_tx); | |
885 | prev = new; | |
886 | ||
887 | /* Insert the link descriptor to the LD ring */ | |
888 | list_add_tail(&new->node, &first->tx_list); | |
889 | ||
890 | /* update metadata */ | |
891 | dst_avail -= len; | |
892 | src_avail -= len; | |
893 | ||
894 | fetch: | |
895 | /* fetch the next dst scatterlist entry */ | |
896 | if (dst_avail == 0) { | |
897 | ||
898 | /* no more entries: we're done */ | |
899 | if (dst_nents == 0) | |
900 | break; | |
901 | ||
902 | /* fetch the next entry: if there are no more: done */ | |
903 | dst_sg = sg_next(dst_sg); | |
904 | if (dst_sg == NULL) | |
905 | break; | |
906 | ||
907 | dst_nents--; | |
908 | dst_avail = sg_dma_len(dst_sg); | |
909 | } | |
910 | ||
911 | /* fetch the next src scatterlist entry */ | |
912 | if (src_avail == 0) { | |
913 | ||
914 | /* no more entries: we're done */ | |
915 | if (src_nents == 0) | |
916 | break; | |
917 | ||
918 | /* fetch the next entry: if there are no more: done */ | |
919 | src_sg = sg_next(src_sg); | |
920 | if (src_sg == NULL) | |
921 | break; | |
922 | ||
923 | src_nents--; | |
924 | src_avail = sg_dma_len(src_sg); | |
925 | } | |
926 | } | |
927 | ||
928 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
929 | new->async_tx.cookie = -EBUSY; | |
930 | ||
931 | /* Set End-of-link to the last link descriptor of new list */ | |
932 | set_ld_eol(chan, new); | |
933 | ||
934 | return &first->async_tx; | |
935 | ||
936 | fail: | |
937 | if (!first) | |
938 | return NULL; | |
939 | ||
940 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
941 | return NULL; | |
942 | } | |
943 | ||
bbea0b6e IS |
944 | /** |
945 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
946 | * @chan: DMA channel | |
947 | * @sgl: scatterlist to transfer to/from | |
948 | * @sg_len: number of entries in @scatterlist | |
949 | * @direction: DMA direction | |
950 | * @flags: DMAEngine flags | |
185ecb5f | 951 | * @context: transaction context (ignored) |
bbea0b6e IS |
952 | * |
953 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
954 | * DMA_SLAVE API, this gets the device-specific information from the | |
955 | * chan->private variable. | |
956 | */ | |
957 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 958 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
185ecb5f AB |
959 | enum dma_transfer_direction direction, unsigned long flags, |
960 | void *context) | |
bbea0b6e | 961 | { |
bbea0b6e | 962 | /* |
968f19ae | 963 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 964 | * |
968f19ae IS |
965 | * However, we need to provide the function pointer to allow the |
966 | * device_control() method to work. | |
bbea0b6e | 967 | */ |
bbea0b6e IS |
968 | return NULL; |
969 | } | |
970 | ||
c3635c78 | 971 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 972 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 973 | { |
968f19ae | 974 | struct dma_slave_config *config; |
a1c03319 | 975 | struct fsldma_chan *chan; |
968f19ae | 976 | int size; |
c3635c78 | 977 | |
a1c03319 | 978 | if (!dchan) |
c3635c78 | 979 | return -EINVAL; |
bbea0b6e | 980 | |
a1c03319 | 981 | chan = to_fsl_chan(dchan); |
bbea0b6e | 982 | |
968f19ae IS |
983 | switch (cmd) { |
984 | case DMA_TERMINATE_ALL: | |
2baff570 | 985 | spin_lock_bh(&chan->desc_lock); |
f04cd407 | 986 | |
968f19ae IS |
987 | /* Halt the DMA engine */ |
988 | dma_halt(chan); | |
bbea0b6e | 989 | |
968f19ae IS |
990 | /* Remove and free all of the descriptors in the LD queue */ |
991 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
992 | fsldma_free_desc_list(chan, &chan->ld_running); | |
43452fad | 993 | fsldma_free_desc_list(chan, &chan->ld_completed); |
f04cd407 | 994 | chan->idle = true; |
bbea0b6e | 995 | |
2baff570 | 996 | spin_unlock_bh(&chan->desc_lock); |
968f19ae IS |
997 | return 0; |
998 | ||
999 | case DMA_SLAVE_CONFIG: | |
1000 | config = (struct dma_slave_config *)arg; | |
1001 | ||
1002 | /* make sure the channel supports setting burst size */ | |
1003 | if (!chan->set_request_count) | |
1004 | return -ENXIO; | |
1005 | ||
1006 | /* we set the controller burst size depending on direction */ | |
db8196df | 1007 | if (config->direction == DMA_MEM_TO_DEV) |
968f19ae IS |
1008 | size = config->dst_addr_width * config->dst_maxburst; |
1009 | else | |
1010 | size = config->src_addr_width * config->src_maxburst; | |
1011 | ||
1012 | chan->set_request_count(chan, size); | |
1013 | return 0; | |
1014 | ||
968f19ae IS |
1015 | default: |
1016 | return -ENXIO; | |
1017 | } | |
c3635c78 LW |
1018 | |
1019 | return 0; | |
bbea0b6e IS |
1020 | } |
1021 | ||
173acc7c ZW |
1022 | /** |
1023 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 1024 | * @chan : Freescale DMA channel |
173acc7c | 1025 | */ |
a1c03319 | 1026 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 1027 | { |
a1c03319 | 1028 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 | 1029 | |
2baff570 | 1030 | spin_lock_bh(&chan->desc_lock); |
a1c03319 | 1031 | fsl_chan_xfer_ld_queue(chan); |
2baff570 | 1032 | spin_unlock_bh(&chan->desc_lock); |
173acc7c ZW |
1033 | } |
1034 | ||
173acc7c | 1035 | /** |
07934481 | 1036 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 1037 | * @chan : Freescale DMA channel |
173acc7c | 1038 | */ |
07934481 | 1039 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 1040 | dma_cookie_t cookie, |
07934481 | 1041 | struct dma_tx_state *txstate) |
173acc7c | 1042 | { |
43452fad HZ |
1043 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
1044 | enum dma_status ret; | |
1045 | ||
1046 | ret = dma_cookie_status(dchan, cookie, txstate); | |
1047 | if (ret == DMA_COMPLETE) | |
1048 | return ret; | |
1049 | ||
1050 | spin_lock_bh(&chan->desc_lock); | |
1051 | fsldma_cleanup_descriptors(chan); | |
1052 | spin_unlock_bh(&chan->desc_lock); | |
1053 | ||
9b0b0bdc | 1054 | return dma_cookie_status(dchan, cookie, txstate); |
173acc7c ZW |
1055 | } |
1056 | ||
d3f620b2 IS |
1057 | /*----------------------------------------------------------------------------*/ |
1058 | /* Interrupt Handling */ | |
1059 | /*----------------------------------------------------------------------------*/ | |
1060 | ||
e7a29151 | 1061 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 1062 | { |
a1c03319 | 1063 | struct fsldma_chan *chan = data; |
a1c03319 | 1064 | u32 stat; |
173acc7c | 1065 | |
9c3a50b7 | 1066 | /* save and clear the status register */ |
a1c03319 | 1067 | stat = get_sr(chan); |
9c3a50b7 | 1068 | set_sr(chan, stat); |
b158471e | 1069 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 1070 | |
f04cd407 | 1071 | /* check that this was really our device */ |
173acc7c ZW |
1072 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
1073 | if (!stat) | |
1074 | return IRQ_NONE; | |
1075 | ||
1076 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 1077 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 1078 | |
9c3a50b7 IS |
1079 | /* |
1080 | * Programming Error | |
f79abb62 | 1081 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
d73111c6 | 1082 | * trigger a PE interrupt. |
f79abb62 ZW |
1083 | */ |
1084 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 1085 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 1086 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
1087 | if (get_bcr(chan) != 0) |
1088 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
1089 | } |
1090 | ||
9c3a50b7 IS |
1091 | /* |
1092 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1093 | * and start the next transfer if it exist. |
1094 | */ | |
1095 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 1096 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 1097 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
1098 | } |
1099 | ||
9c3a50b7 IS |
1100 | /* |
1101 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1102 | * we should clear the Channel Start bit for |
1103 | * prepare next transfer. | |
1104 | */ | |
1c62979e | 1105 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 1106 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 1107 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
1108 | } |
1109 | ||
f04cd407 IS |
1110 | /* check that the DMA controller is really idle */ |
1111 | if (!dma_is_idle(chan)) | |
1112 | chan_err(chan, "irq: controller not idle!\n"); | |
1113 | ||
1114 | /* check that we handled all of the bits */ | |
173acc7c | 1115 | if (stat) |
f04cd407 | 1116 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1117 | |
f04cd407 IS |
1118 | /* |
1119 | * Schedule the tasklet to handle all cleanup of the current | |
1120 | * transaction. It will start a new transaction if there is | |
1121 | * one pending. | |
1122 | */ | |
a1c03319 | 1123 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 1124 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
1125 | return IRQ_HANDLED; |
1126 | } | |
1127 | ||
d3f620b2 IS |
1128 | static void dma_do_tasklet(unsigned long data) |
1129 | { | |
a1c03319 | 1130 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
f04cd407 IS |
1131 | |
1132 | chan_dbg(chan, "tasklet entry\n"); | |
1133 | ||
2baff570 | 1134 | spin_lock_bh(&chan->desc_lock); |
dc8d4091 | 1135 | |
dc8d4091 | 1136 | /* the hardware is now idle and ready for more */ |
f04cd407 | 1137 | chan->idle = true; |
f04cd407 | 1138 | |
43452fad HZ |
1139 | /* Run all cleanup for descriptors which have been completed */ |
1140 | fsldma_cleanup_descriptors(chan); | |
dc8d4091 | 1141 | |
43452fad | 1142 | spin_unlock_bh(&chan->desc_lock); |
dc8d4091 | 1143 | |
f04cd407 | 1144 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1145 | } |
1146 | ||
1147 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1148 | { |
a4f56d4b | 1149 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1150 | struct fsldma_chan *chan; |
1151 | unsigned int handled = 0; | |
1152 | u32 gsr, mask; | |
1153 | int i; | |
173acc7c | 1154 | |
e7a29151 | 1155 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1156 | : in_le32(fdev->regs); |
1157 | mask = 0xff000000; | |
1158 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1159 | |
d3f620b2 IS |
1160 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1161 | chan = fdev->chan[i]; | |
1162 | if (!chan) | |
1163 | continue; | |
1164 | ||
1165 | if (gsr & mask) { | |
1166 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1167 | fsldma_chan_irq(irq, chan); | |
1168 | handled++; | |
1169 | } | |
1170 | ||
1171 | gsr &= ~mask; | |
1172 | mask >>= 8; | |
1173 | } | |
1174 | ||
1175 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1176 | } |
1177 | ||
d3f620b2 | 1178 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1179 | { |
d3f620b2 IS |
1180 | struct fsldma_chan *chan; |
1181 | int i; | |
1182 | ||
1183 | if (fdev->irq != NO_IRQ) { | |
1184 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1185 | free_irq(fdev->irq, fdev); | |
1186 | return; | |
1187 | } | |
1188 | ||
1189 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1190 | chan = fdev->chan[i]; | |
1191 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1192 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1193 | free_irq(chan->irq, chan); |
1194 | } | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1199 | { | |
1200 | struct fsldma_chan *chan; | |
1201 | int ret; | |
1202 | int i; | |
1203 | ||
1204 | /* if we have a per-controller IRQ, use that */ | |
1205 | if (fdev->irq != NO_IRQ) { | |
1206 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1207 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1208 | "fsldma-controller", fdev); | |
1209 | return ret; | |
1210 | } | |
1211 | ||
1212 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1213 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1214 | chan = fdev->chan[i]; | |
1215 | if (!chan) | |
1216 | continue; | |
1217 | ||
1218 | if (chan->irq == NO_IRQ) { | |
b158471e | 1219 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1220 | ret = -ENODEV; |
1221 | goto out_unwind; | |
1222 | } | |
1223 | ||
b158471e | 1224 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1225 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1226 | "fsldma-chan", chan); | |
1227 | if (ret) { | |
b158471e | 1228 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1229 | goto out_unwind; |
1230 | } | |
1231 | } | |
1232 | ||
1233 | return 0; | |
1234 | ||
1235 | out_unwind: | |
1236 | for (/* none */; i >= 0; i--) { | |
1237 | chan = fdev->chan[i]; | |
1238 | if (!chan) | |
1239 | continue; | |
1240 | ||
1241 | if (chan->irq == NO_IRQ) | |
1242 | continue; | |
1243 | ||
1244 | free_irq(chan->irq, chan); | |
1245 | } | |
1246 | ||
1247 | return ret; | |
173acc7c ZW |
1248 | } |
1249 | ||
a4f56d4b IS |
1250 | /*----------------------------------------------------------------------------*/ |
1251 | /* OpenFirmware Subsystem */ | |
1252 | /*----------------------------------------------------------------------------*/ | |
1253 | ||
463a1f8b | 1254 | static int fsl_dma_chan_probe(struct fsldma_device *fdev, |
77cd62e8 | 1255 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1256 | { |
a1c03319 | 1257 | struct fsldma_chan *chan; |
4ce0e953 | 1258 | struct resource res; |
173acc7c ZW |
1259 | int err; |
1260 | ||
173acc7c | 1261 | /* alloc channel */ |
a1c03319 IS |
1262 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1263 | if (!chan) { | |
e7a29151 IS |
1264 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1265 | err = -ENOMEM; | |
1266 | goto out_return; | |
1267 | } | |
1268 | ||
1269 | /* ioremap registers for use */ | |
a1c03319 IS |
1270 | chan->regs = of_iomap(node, 0); |
1271 | if (!chan->regs) { | |
e7a29151 IS |
1272 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1273 | err = -ENOMEM; | |
a1c03319 | 1274 | goto out_free_chan; |
173acc7c ZW |
1275 | } |
1276 | ||
4ce0e953 | 1277 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1278 | if (err) { |
e7a29151 IS |
1279 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1280 | goto out_iounmap_regs; | |
173acc7c ZW |
1281 | } |
1282 | ||
a1c03319 | 1283 | chan->feature = feature; |
173acc7c | 1284 | if (!fdev->feature) |
a1c03319 | 1285 | fdev->feature = chan->feature; |
173acc7c | 1286 | |
e7a29151 IS |
1287 | /* |
1288 | * If the DMA device's feature is different than the feature | |
1289 | * of its channels, report the bug | |
173acc7c | 1290 | */ |
a1c03319 | 1291 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1292 | |
a1c03319 | 1293 | chan->dev = fdev->dev; |
8de7a7d9 HZ |
1294 | chan->id = (res.start & 0xfff) < 0x300 ? |
1295 | ((res.start - 0x100) & 0xfff) >> 7 : | |
1296 | ((res.start - 0x200) & 0xfff) >> 7; | |
a1c03319 | 1297 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
e7a29151 | 1298 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1299 | err = -EINVAL; |
e7a29151 | 1300 | goto out_iounmap_regs; |
173acc7c | 1301 | } |
173acc7c | 1302 | |
a1c03319 IS |
1303 | fdev->chan[chan->id] = chan; |
1304 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1305 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1306 | |
1307 | /* Initialize the channel */ | |
a1c03319 | 1308 | dma_init(chan); |
173acc7c ZW |
1309 | |
1310 | /* Clear cdar registers */ | |
a1c03319 | 1311 | set_cdar(chan, 0); |
173acc7c | 1312 | |
a1c03319 | 1313 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1314 | case FSL_DMA_IP_85XX: |
a1c03319 | 1315 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1316 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1317 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1318 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1319 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1320 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1321 | } |
1322 | ||
a1c03319 | 1323 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1324 | INIT_LIST_HEAD(&chan->ld_pending); |
1325 | INIT_LIST_HEAD(&chan->ld_running); | |
43452fad | 1326 | INIT_LIST_HEAD(&chan->ld_completed); |
f04cd407 | 1327 | chan->idle = true; |
14c6a333 HZ |
1328 | #ifdef CONFIG_PM |
1329 | chan->pm_state = RUNNING; | |
1330 | #endif | |
173acc7c | 1331 | |
a1c03319 | 1332 | chan->common.device = &fdev->common; |
8ac69546 | 1333 | dma_cookie_init(&chan->common); |
173acc7c | 1334 | |
d3f620b2 | 1335 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1336 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1337 | |
173acc7c | 1338 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1339 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1340 | fdev->common.chancnt++; |
1341 | ||
a1c03319 IS |
1342 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1343 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1344 | |
1345 | return 0; | |
51ee87f2 | 1346 | |
e7a29151 | 1347 | out_iounmap_regs: |
a1c03319 IS |
1348 | iounmap(chan->regs); |
1349 | out_free_chan: | |
1350 | kfree(chan); | |
e7a29151 | 1351 | out_return: |
173acc7c ZW |
1352 | return err; |
1353 | } | |
1354 | ||
a1c03319 | 1355 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1356 | { |
a1c03319 IS |
1357 | irq_dispose_mapping(chan->irq); |
1358 | list_del(&chan->common.device_node); | |
1359 | iounmap(chan->regs); | |
1360 | kfree(chan); | |
173acc7c ZW |
1361 | } |
1362 | ||
463a1f8b | 1363 | static int fsldma_of_probe(struct platform_device *op) |
173acc7c | 1364 | { |
a4f56d4b | 1365 | struct fsldma_device *fdev; |
77cd62e8 | 1366 | struct device_node *child; |
e7a29151 | 1367 | int err; |
173acc7c | 1368 | |
a4f56d4b | 1369 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1370 | if (!fdev) { |
e7a29151 IS |
1371 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1372 | err = -ENOMEM; | |
1373 | goto out_return; | |
173acc7c | 1374 | } |
e7a29151 IS |
1375 | |
1376 | fdev->dev = &op->dev; | |
173acc7c ZW |
1377 | INIT_LIST_HEAD(&fdev->common.channels); |
1378 | ||
e7a29151 | 1379 | /* ioremap the registers for use */ |
61c7a080 | 1380 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1381 | if (!fdev->regs) { |
1382 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1383 | err = -ENOMEM; | |
1384 | goto out_free_fdev; | |
173acc7c ZW |
1385 | } |
1386 | ||
d3f620b2 | 1387 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1388 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1389 | |
173acc7c | 1390 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
c1433041 | 1391 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1392 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1393 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1394 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
1395 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; | |
c1433041 | 1396 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1397 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1398 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1399 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1400 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1401 | fdev->common.dev = &op->dev; |
173acc7c | 1402 | |
e2c8e425 LY |
1403 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1404 | ||
dd3daca1 | 1405 | platform_set_drvdata(op, fdev); |
77cd62e8 | 1406 | |
e7a29151 IS |
1407 | /* |
1408 | * We cannot use of_platform_bus_probe() because there is no | |
1409 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1410 | * channel object. |
1411 | */ | |
61c7a080 | 1412 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1413 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1414 | fsl_dma_chan_probe(fdev, child, |
1415 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1416 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1417 | } |
1418 | ||
1419 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1420 | fsl_dma_chan_probe(fdev, child, |
1421 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1422 | "fsl,elo-dma-channel"); | |
e7a29151 | 1423 | } |
77cd62e8 | 1424 | } |
173acc7c | 1425 | |
d3f620b2 IS |
1426 | /* |
1427 | * Hookup the IRQ handler(s) | |
1428 | * | |
1429 | * If we have a per-controller interrupt, we prefer that to the | |
1430 | * per-channel interrupts to reduce the number of shared interrupt | |
1431 | * handlers on the same IRQ line | |
1432 | */ | |
1433 | err = fsldma_request_irqs(fdev); | |
1434 | if (err) { | |
1435 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1436 | goto out_free_fdev; | |
1437 | } | |
1438 | ||
173acc7c ZW |
1439 | dma_async_device_register(&fdev->common); |
1440 | return 0; | |
1441 | ||
e7a29151 | 1442 | out_free_fdev: |
d3f620b2 | 1443 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1444 | kfree(fdev); |
e7a29151 | 1445 | out_return: |
173acc7c ZW |
1446 | return err; |
1447 | } | |
1448 | ||
2dc11581 | 1449 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1450 | { |
a4f56d4b | 1451 | struct fsldma_device *fdev; |
77cd62e8 TT |
1452 | unsigned int i; |
1453 | ||
dd3daca1 | 1454 | fdev = platform_get_drvdata(op); |
77cd62e8 TT |
1455 | dma_async_device_unregister(&fdev->common); |
1456 | ||
d3f620b2 IS |
1457 | fsldma_free_irqs(fdev); |
1458 | ||
e7a29151 | 1459 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1460 | if (fdev->chan[i]) |
1461 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1462 | } |
77cd62e8 | 1463 | |
e7a29151 | 1464 | iounmap(fdev->regs); |
77cd62e8 | 1465 | kfree(fdev); |
77cd62e8 TT |
1466 | |
1467 | return 0; | |
1468 | } | |
1469 | ||
14c6a333 HZ |
1470 | #ifdef CONFIG_PM |
1471 | static int fsldma_suspend_late(struct device *dev) | |
1472 | { | |
1473 | struct platform_device *pdev = to_platform_device(dev); | |
1474 | struct fsldma_device *fdev = platform_get_drvdata(pdev); | |
1475 | struct fsldma_chan *chan; | |
1476 | int i; | |
1477 | ||
1478 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1479 | chan = fdev->chan[i]; | |
1480 | if (!chan) | |
1481 | continue; | |
1482 | ||
1483 | spin_lock_bh(&chan->desc_lock); | |
1484 | if (unlikely(!chan->idle)) | |
1485 | goto out; | |
1486 | chan->regs_save.mr = get_mr(chan); | |
1487 | chan->pm_state = SUSPENDED; | |
1488 | spin_unlock_bh(&chan->desc_lock); | |
1489 | } | |
1490 | return 0; | |
1491 | ||
1492 | out: | |
1493 | for (; i >= 0; i--) { | |
1494 | chan = fdev->chan[i]; | |
1495 | if (!chan) | |
1496 | continue; | |
1497 | chan->pm_state = RUNNING; | |
1498 | spin_unlock_bh(&chan->desc_lock); | |
1499 | } | |
1500 | return -EBUSY; | |
1501 | } | |
1502 | ||
1503 | static int fsldma_resume_early(struct device *dev) | |
1504 | { | |
1505 | struct platform_device *pdev = to_platform_device(dev); | |
1506 | struct fsldma_device *fdev = platform_get_drvdata(pdev); | |
1507 | struct fsldma_chan *chan; | |
1508 | u32 mode; | |
1509 | int i; | |
1510 | ||
1511 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1512 | chan = fdev->chan[i]; | |
1513 | if (!chan) | |
1514 | continue; | |
1515 | ||
1516 | spin_lock_bh(&chan->desc_lock); | |
1517 | mode = chan->regs_save.mr | |
1518 | & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA; | |
1519 | set_mr(chan, mode); | |
1520 | chan->pm_state = RUNNING; | |
1521 | spin_unlock_bh(&chan->desc_lock); | |
1522 | } | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | static const struct dev_pm_ops fsldma_pm_ops = { | |
1528 | .suspend_late = fsldma_suspend_late, | |
1529 | .resume_early = fsldma_resume_early, | |
1530 | }; | |
1531 | #endif | |
1532 | ||
4b1cf1fa | 1533 | static const struct of_device_id fsldma_of_ids[] = { |
8de7a7d9 | 1534 | { .compatible = "fsl,elo3-dma", }, |
049c9d45 KG |
1535 | { .compatible = "fsl,eloplus-dma", }, |
1536 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1537 | {} |
1538 | }; | |
1539 | ||
8faa7cf8 | 1540 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1541 | .driver = { |
1542 | .name = "fsl-elo-dma", | |
1543 | .owner = THIS_MODULE, | |
1544 | .of_match_table = fsldma_of_ids, | |
14c6a333 HZ |
1545 | #ifdef CONFIG_PM |
1546 | .pm = &fsldma_pm_ops, | |
1547 | #endif | |
4018294b GL |
1548 | }, |
1549 | .probe = fsldma_of_probe, | |
1550 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1551 | }; |
1552 | ||
a4f56d4b IS |
1553 | /*----------------------------------------------------------------------------*/ |
1554 | /* Module Init / Exit */ | |
1555 | /*----------------------------------------------------------------------------*/ | |
1556 | ||
1557 | static __init int fsldma_init(void) | |
173acc7c | 1558 | { |
8de7a7d9 | 1559 | pr_info("Freescale Elo series DMA driver\n"); |
00006124 | 1560 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1561 | } |
1562 | ||
a4f56d4b | 1563 | static void __exit fsldma_exit(void) |
77cd62e8 | 1564 | { |
00006124 | 1565 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1566 | } |
1567 | ||
a4f56d4b IS |
1568 | subsys_initcall(fsldma_init); |
1569 | module_exit(fsldma_exit); | |
77cd62e8 | 1570 | |
8de7a7d9 | 1571 | MODULE_DESCRIPTION("Freescale Elo series DMA driver"); |
77cd62e8 | 1572 | MODULE_LICENSE("GPL"); |