Commit | Line | Data |
---|---|---|
173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
38 | #include "fsldma.h" | |
39 | ||
b158471e IS |
40 | #define chan_dbg(chan, fmt, arg...) \ |
41 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
42 | #define chan_err(chan, fmt, arg...) \ | |
43 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
44 | ||
45 | static const char msg_ld_oom[] = "No free memory for link descriptor"; | |
c1433041 | 46 | |
e8bd84df IS |
47 | /* |
48 | * Register Helpers | |
49 | */ | |
173acc7c | 50 | |
a1c03319 | 51 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 52 | { |
a1c03319 | 53 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
54 | } |
55 | ||
a1c03319 | 56 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 57 | { |
a1c03319 | 58 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
59 | } |
60 | ||
e8bd84df IS |
61 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
62 | { | |
63 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
64 | } | |
65 | ||
66 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
67 | { | |
68 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
69 | } | |
70 | ||
e8bd84df IS |
71 | static u32 get_bcr(struct fsldma_chan *chan) |
72 | { | |
73 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
74 | } | |
75 | ||
76 | /* | |
77 | * Descriptor Helpers | |
78 | */ | |
79 | ||
a1c03319 | 80 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
81 | struct fsl_dma_ld_hw *hw, u32 count) |
82 | { | |
a1c03319 | 83 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
84 | } |
85 | ||
a1c03319 | 86 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 87 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
88 | { |
89 | u64 snoop_bits; | |
90 | ||
a1c03319 | 91 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 92 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 93 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
94 | } |
95 | ||
a1c03319 | 96 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 97 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
98 | { |
99 | u64 snoop_bits; | |
100 | ||
a1c03319 | 101 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 102 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 103 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
104 | } |
105 | ||
a1c03319 | 106 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 107 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
108 | { |
109 | u64 snoop_bits; | |
110 | ||
a1c03319 | 111 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 112 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 113 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
114 | } |
115 | ||
31f4306c | 116 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 117 | { |
e8bd84df | 118 | u64 snoop_bits; |
173acc7c | 119 | |
e8bd84df IS |
120 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
121 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 122 | |
e8bd84df IS |
123 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
124 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
125 | | snoop_bits, 64); | |
173acc7c ZW |
126 | } |
127 | ||
e8bd84df IS |
128 | /* |
129 | * DMA Engine Hardware Control Helpers | |
130 | */ | |
131 | ||
132 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 133 | { |
e8bd84df IS |
134 | /* Reset the channel */ |
135 | DMA_OUT(chan, &chan->regs->mr, 0, 32); | |
136 | ||
137 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
138 | case FSL_DMA_IP_85XX: | |
139 | /* Set the channel to below modes: | |
140 | * EIE - Error interrupt enable | |
e8bd84df IS |
141 | * EOLNIE - End of links interrupt enable |
142 | * BWC - Bandwidth sharing among channels | |
143 | */ | |
144 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC | |
f04cd407 | 145 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); |
e8bd84df IS |
146 | break; |
147 | case FSL_DMA_IP_83XX: | |
148 | /* Set the channel to below modes: | |
149 | * EOTIE - End-of-transfer interrupt enable | |
150 | * PRC_RM - PCI read multiple | |
151 | */ | |
152 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | |
153 | | FSL_DMA_MR_PRC_RM, 32); | |
154 | break; | |
155 | } | |
f79abb62 ZW |
156 | } |
157 | ||
a1c03319 | 158 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 159 | { |
a1c03319 | 160 | u32 sr = get_sr(chan); |
173acc7c ZW |
161 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
162 | } | |
163 | ||
f04cd407 IS |
164 | /* |
165 | * Start the DMA controller | |
166 | * | |
167 | * Preconditions: | |
168 | * - the CDAR register must point to the start descriptor | |
169 | * - the MRn[CS] bit must be cleared | |
170 | */ | |
a1c03319 | 171 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 172 | { |
272ca655 IS |
173 | u32 mode; |
174 | ||
a1c03319 | 175 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 176 | |
f04cd407 IS |
177 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
178 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
179 | mode |= FSL_DMA_MR_EMP_EN; | |
180 | } else { | |
181 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 182 | } |
173acc7c | 183 | |
f04cd407 | 184 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 185 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
186 | } else { |
187 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 188 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 189 | } |
173acc7c | 190 | |
a1c03319 | 191 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
192 | } |
193 | ||
a1c03319 | 194 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 195 | { |
272ca655 | 196 | u32 mode; |
900325a6 DW |
197 | int i; |
198 | ||
a1c03319 | 199 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 200 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 201 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
202 | |
203 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 204 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 205 | |
900325a6 | 206 | for (i = 0; i < 100; i++) { |
a1c03319 | 207 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
208 | return; |
209 | ||
173acc7c | 210 | udelay(10); |
900325a6 | 211 | } |
272ca655 | 212 | |
9c3a50b7 | 213 | if (!dma_is_idle(chan)) |
b158471e | 214 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
215 | } |
216 | ||
173acc7c ZW |
217 | /** |
218 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 219 | * @chan : Freescale DMA channel |
173acc7c ZW |
220 | * @size : Address loop size, 0 for disable loop |
221 | * | |
222 | * The set source address hold transfer size. The source | |
223 | * address hold or loop transfer size is when the DMA transfer | |
224 | * data from source address (SA), if the loop size is 4, the DMA will | |
225 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
226 | * SA + 1 ... and so on. | |
227 | */ | |
a1c03319 | 228 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 229 | { |
272ca655 IS |
230 | u32 mode; |
231 | ||
a1c03319 | 232 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 233 | |
173acc7c ZW |
234 | switch (size) { |
235 | case 0: | |
272ca655 | 236 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
237 | break; |
238 | case 1: | |
239 | case 2: | |
240 | case 4: | |
241 | case 8: | |
272ca655 | 242 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
243 | break; |
244 | } | |
272ca655 | 245 | |
a1c03319 | 246 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
247 | } |
248 | ||
249 | /** | |
738f5f7e | 250 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 251 | * @chan : Freescale DMA channel |
173acc7c ZW |
252 | * @size : Address loop size, 0 for disable loop |
253 | * | |
254 | * The set destination address hold transfer size. The destination | |
255 | * address hold or loop transfer size is when the DMA transfer | |
256 | * data to destination address (TA), if the loop size is 4, the DMA will | |
257 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
258 | * TA + 1 ... and so on. | |
259 | */ | |
a1c03319 | 260 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 261 | { |
272ca655 IS |
262 | u32 mode; |
263 | ||
a1c03319 | 264 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 265 | |
173acc7c ZW |
266 | switch (size) { |
267 | case 0: | |
272ca655 | 268 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
269 | break; |
270 | case 1: | |
271 | case 2: | |
272 | case 4: | |
273 | case 8: | |
272ca655 | 274 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
275 | break; |
276 | } | |
272ca655 | 277 | |
a1c03319 | 278 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
279 | } |
280 | ||
281 | /** | |
e6c7ecb6 | 282 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 283 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
284 | * @size : Number of bytes to transfer in a single request |
285 | * | |
286 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
287 | * The DMA request count is how many bytes are allowed to transfer before | |
288 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
289 | * operation. | |
173acc7c | 290 | * |
e6c7ecb6 | 291 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 292 | */ |
a1c03319 | 293 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 294 | { |
272ca655 IS |
295 | u32 mode; |
296 | ||
e6c7ecb6 | 297 | BUG_ON(size > 1024); |
272ca655 | 298 | |
a1c03319 | 299 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
300 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
301 | ||
a1c03319 | 302 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 303 | } |
173acc7c | 304 | |
e6c7ecb6 IS |
305 | /** |
306 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 307 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
308 | * @enable : 0 is disabled, 1 is enabled. |
309 | * | |
310 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
311 | * The DMA Request Count feature should be used in addition to this feature | |
312 | * to set the number of bytes to transfer before pausing the channel. | |
313 | */ | |
a1c03319 | 314 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
315 | { |
316 | if (enable) | |
a1c03319 | 317 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 318 | else |
a1c03319 | 319 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
320 | } |
321 | ||
322 | /** | |
323 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 324 | * @chan : Freescale DMA channel |
173acc7c ZW |
325 | * @enable : 0 is disabled, 1 is enabled. |
326 | * | |
327 | * If enable the external start, the channel can be started by an | |
328 | * external DMA start pin. So the dma_start() does not start the | |
329 | * transfer immediately. The DMA channel will wait for the | |
330 | * control pin asserted. | |
331 | */ | |
a1c03319 | 332 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
333 | { |
334 | if (enable) | |
a1c03319 | 335 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 336 | else |
a1c03319 | 337 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
338 | } |
339 | ||
31f4306c | 340 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
341 | { |
342 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
343 | ||
344 | if (list_empty(&chan->ld_pending)) | |
345 | goto out_splice; | |
346 | ||
347 | /* | |
348 | * Add the hardware descriptor to the chain of hardware descriptors | |
349 | * that already exists in memory. | |
350 | * | |
351 | * This will un-set the EOL bit of the existing transaction, and the | |
352 | * last link in this transaction will become the EOL descriptor. | |
353 | */ | |
354 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
355 | ||
356 | /* | |
357 | * Add the software descriptor and all children to the list | |
358 | * of pending transactions | |
359 | */ | |
360 | out_splice: | |
361 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
362 | } | |
363 | ||
173acc7c ZW |
364 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
365 | { | |
a1c03319 | 366 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
367 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
368 | struct fsl_desc_sw *child; | |
173acc7c ZW |
369 | unsigned long flags; |
370 | dma_cookie_t cookie; | |
371 | ||
a1c03319 | 372 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 373 | |
9c3a50b7 IS |
374 | /* |
375 | * assign cookies to all of the software descriptors | |
376 | * that make up this transaction | |
377 | */ | |
a1c03319 | 378 | cookie = chan->common.cookie; |
eda34234 | 379 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 | 380 | cookie++; |
31f4306c IS |
381 | if (cookie < DMA_MIN_COOKIE) |
382 | cookie = DMA_MIN_COOKIE; | |
bcfb7465 | 383 | |
6ca3a7a9 | 384 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
385 | } |
386 | ||
a1c03319 | 387 | chan->common.cookie = cookie; |
9c3a50b7 IS |
388 | |
389 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 390 | append_ld_queue(chan, desc); |
173acc7c | 391 | |
a1c03319 | 392 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
393 | |
394 | return cookie; | |
395 | } | |
396 | ||
397 | /** | |
398 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 399 | * @chan : Freescale DMA channel |
173acc7c ZW |
400 | * |
401 | * Return - The descriptor allocated. NULL for failed. | |
402 | */ | |
31f4306c | 403 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 404 | { |
9c3a50b7 | 405 | struct fsl_desc_sw *desc; |
173acc7c | 406 | dma_addr_t pdesc; |
9c3a50b7 IS |
407 | |
408 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
409 | if (!desc) { | |
b158471e | 410 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 411 | return NULL; |
173acc7c ZW |
412 | } |
413 | ||
9c3a50b7 IS |
414 | memset(desc, 0, sizeof(*desc)); |
415 | INIT_LIST_HEAD(&desc->tx_list); | |
416 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
417 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
418 | desc->async_tx.phys = pdesc; | |
419 | ||
0ab09c36 IS |
420 | #ifdef FSL_DMA_LD_DEBUG |
421 | chan_dbg(chan, "LD %p allocated\n", desc); | |
422 | #endif | |
423 | ||
9c3a50b7 | 424 | return desc; |
173acc7c ZW |
425 | } |
426 | ||
173acc7c ZW |
427 | /** |
428 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 429 | * @chan : Freescale DMA channel |
173acc7c ZW |
430 | * |
431 | * This function will create a dma pool for descriptor allocation. | |
432 | * | |
433 | * Return - The number of descriptors allocated. | |
434 | */ | |
a1c03319 | 435 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 436 | { |
a1c03319 | 437 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
438 | |
439 | /* Has this channel already been allocated? */ | |
a1c03319 | 440 | if (chan->desc_pool) |
77cd62e8 | 441 | return 1; |
173acc7c | 442 | |
9c3a50b7 IS |
443 | /* |
444 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
445 | * for meeting FSL DMA specification requirement. |
446 | */ | |
b158471e | 447 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
448 | sizeof(struct fsl_desc_sw), |
449 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 450 | if (!chan->desc_pool) { |
b158471e | 451 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 452 | return -ENOMEM; |
173acc7c ZW |
453 | } |
454 | ||
9c3a50b7 | 455 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
456 | return 1; |
457 | } | |
458 | ||
9c3a50b7 IS |
459 | /** |
460 | * fsldma_free_desc_list - Free all descriptors in a queue | |
461 | * @chan: Freescae DMA channel | |
462 | * @list: the list to free | |
463 | * | |
464 | * LOCKING: must hold chan->desc_lock | |
465 | */ | |
466 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
467 | struct list_head *list) | |
468 | { | |
469 | struct fsl_desc_sw *desc, *_desc; | |
470 | ||
471 | list_for_each_entry_safe(desc, _desc, list, node) { | |
472 | list_del(&desc->node); | |
0ab09c36 IS |
473 | #ifdef FSL_DMA_LD_DEBUG |
474 | chan_dbg(chan, "LD %p free\n", desc); | |
475 | #endif | |
9c3a50b7 IS |
476 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
477 | } | |
478 | } | |
479 | ||
480 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
481 | struct list_head *list) | |
482 | { | |
483 | struct fsl_desc_sw *desc, *_desc; | |
484 | ||
485 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
486 | list_del(&desc->node); | |
0ab09c36 IS |
487 | #ifdef FSL_DMA_LD_DEBUG |
488 | chan_dbg(chan, "LD %p free\n", desc); | |
489 | #endif | |
9c3a50b7 IS |
490 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
491 | } | |
492 | } | |
493 | ||
173acc7c ZW |
494 | /** |
495 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 496 | * @chan : Freescale DMA channel |
173acc7c | 497 | */ |
a1c03319 | 498 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 499 | { |
a1c03319 | 500 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
501 | unsigned long flags; |
502 | ||
b158471e | 503 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 504 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
505 | fsldma_free_desc_list(chan, &chan->ld_pending); |
506 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 507 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 508 | |
9c3a50b7 | 509 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 510 | chan->desc_pool = NULL; |
173acc7c ZW |
511 | } |
512 | ||
2187c269 | 513 | static struct dma_async_tx_descriptor * |
a1c03319 | 514 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 515 | { |
a1c03319 | 516 | struct fsldma_chan *chan; |
2187c269 ZW |
517 | struct fsl_desc_sw *new; |
518 | ||
a1c03319 | 519 | if (!dchan) |
2187c269 ZW |
520 | return NULL; |
521 | ||
a1c03319 | 522 | chan = to_fsl_chan(dchan); |
2187c269 | 523 | |
a1c03319 | 524 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 525 | if (!new) { |
b158471e | 526 | chan_err(chan, "%s\n", msg_ld_oom); |
2187c269 ZW |
527 | return NULL; |
528 | } | |
529 | ||
530 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 531 | new->async_tx.flags = flags; |
2187c269 | 532 | |
f79abb62 | 533 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 534 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 535 | |
31f4306c | 536 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 537 | set_ld_eol(chan, new); |
2187c269 ZW |
538 | |
539 | return &new->async_tx; | |
540 | } | |
541 | ||
31f4306c IS |
542 | static struct dma_async_tx_descriptor * |
543 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
544 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
545 | size_t len, unsigned long flags) |
546 | { | |
a1c03319 | 547 | struct fsldma_chan *chan; |
173acc7c ZW |
548 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
549 | size_t copy; | |
173acc7c | 550 | |
a1c03319 | 551 | if (!dchan) |
173acc7c ZW |
552 | return NULL; |
553 | ||
554 | if (!len) | |
555 | return NULL; | |
556 | ||
a1c03319 | 557 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
558 | |
559 | do { | |
560 | ||
561 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 562 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 563 | if (!new) { |
b158471e | 564 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 565 | goto fail; |
173acc7c | 566 | } |
173acc7c | 567 | |
56822843 | 568 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 569 | |
a1c03319 IS |
570 | set_desc_cnt(chan, &new->hw, copy); |
571 | set_desc_src(chan, &new->hw, dma_src); | |
572 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
573 | |
574 | if (!first) | |
575 | first = new; | |
576 | else | |
a1c03319 | 577 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
578 | |
579 | new->async_tx.cookie = 0; | |
636bdeaa | 580 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
581 | |
582 | prev = new; | |
583 | len -= copy; | |
584 | dma_src += copy; | |
738f5f7e | 585 | dma_dst += copy; |
173acc7c ZW |
586 | |
587 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 588 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
589 | } while (len); |
590 | ||
636bdeaa | 591 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
592 | new->async_tx.cookie = -EBUSY; |
593 | ||
31f4306c | 594 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 595 | set_ld_eol(chan, new); |
173acc7c | 596 | |
2e077f8e IS |
597 | return &first->async_tx; |
598 | ||
599 | fail: | |
600 | if (!first) | |
601 | return NULL; | |
602 | ||
9c3a50b7 | 603 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 604 | return NULL; |
173acc7c ZW |
605 | } |
606 | ||
c1433041 IS |
607 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
608 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
609 | struct scatterlist *src_sg, unsigned int src_nents, | |
610 | unsigned long flags) | |
611 | { | |
612 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
613 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
614 | size_t dst_avail, src_avail; | |
615 | dma_addr_t dst, src; | |
616 | size_t len; | |
617 | ||
618 | /* basic sanity checks */ | |
619 | if (dst_nents == 0 || src_nents == 0) | |
620 | return NULL; | |
621 | ||
622 | if (dst_sg == NULL || src_sg == NULL) | |
623 | return NULL; | |
624 | ||
625 | /* | |
626 | * TODO: should we check that both scatterlists have the same | |
627 | * TODO: number of bytes in total? Is that really an error? | |
628 | */ | |
629 | ||
630 | /* get prepared for the loop */ | |
631 | dst_avail = sg_dma_len(dst_sg); | |
632 | src_avail = sg_dma_len(src_sg); | |
633 | ||
634 | /* run until we are out of scatterlist entries */ | |
635 | while (true) { | |
636 | ||
637 | /* create the largest transaction possible */ | |
638 | len = min_t(size_t, src_avail, dst_avail); | |
639 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
640 | if (len == 0) | |
641 | goto fetch; | |
642 | ||
643 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
644 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
645 | ||
646 | /* allocate and populate the descriptor */ | |
647 | new = fsl_dma_alloc_descriptor(chan); | |
648 | if (!new) { | |
b158471e | 649 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
650 | goto fail; |
651 | } | |
c1433041 IS |
652 | |
653 | set_desc_cnt(chan, &new->hw, len); | |
654 | set_desc_src(chan, &new->hw, src); | |
655 | set_desc_dst(chan, &new->hw, dst); | |
656 | ||
657 | if (!first) | |
658 | first = new; | |
659 | else | |
660 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
661 | ||
662 | new->async_tx.cookie = 0; | |
663 | async_tx_ack(&new->async_tx); | |
664 | prev = new; | |
665 | ||
666 | /* Insert the link descriptor to the LD ring */ | |
667 | list_add_tail(&new->node, &first->tx_list); | |
668 | ||
669 | /* update metadata */ | |
670 | dst_avail -= len; | |
671 | src_avail -= len; | |
672 | ||
673 | fetch: | |
674 | /* fetch the next dst scatterlist entry */ | |
675 | if (dst_avail == 0) { | |
676 | ||
677 | /* no more entries: we're done */ | |
678 | if (dst_nents == 0) | |
679 | break; | |
680 | ||
681 | /* fetch the next entry: if there are no more: done */ | |
682 | dst_sg = sg_next(dst_sg); | |
683 | if (dst_sg == NULL) | |
684 | break; | |
685 | ||
686 | dst_nents--; | |
687 | dst_avail = sg_dma_len(dst_sg); | |
688 | } | |
689 | ||
690 | /* fetch the next src scatterlist entry */ | |
691 | if (src_avail == 0) { | |
692 | ||
693 | /* no more entries: we're done */ | |
694 | if (src_nents == 0) | |
695 | break; | |
696 | ||
697 | /* fetch the next entry: if there are no more: done */ | |
698 | src_sg = sg_next(src_sg); | |
699 | if (src_sg == NULL) | |
700 | break; | |
701 | ||
702 | src_nents--; | |
703 | src_avail = sg_dma_len(src_sg); | |
704 | } | |
705 | } | |
706 | ||
707 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
708 | new->async_tx.cookie = -EBUSY; | |
709 | ||
710 | /* Set End-of-link to the last link descriptor of new list */ | |
711 | set_ld_eol(chan, new); | |
712 | ||
713 | return &first->async_tx; | |
714 | ||
715 | fail: | |
716 | if (!first) | |
717 | return NULL; | |
718 | ||
719 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
720 | return NULL; | |
721 | } | |
722 | ||
bbea0b6e IS |
723 | /** |
724 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
725 | * @chan: DMA channel | |
726 | * @sgl: scatterlist to transfer to/from | |
727 | * @sg_len: number of entries in @scatterlist | |
728 | * @direction: DMA direction | |
729 | * @flags: DMAEngine flags | |
730 | * | |
731 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
732 | * DMA_SLAVE API, this gets the device-specific information from the | |
733 | * chan->private variable. | |
734 | */ | |
735 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 736 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
737 | enum dma_data_direction direction, unsigned long flags) |
738 | { | |
bbea0b6e | 739 | /* |
968f19ae | 740 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 741 | * |
968f19ae IS |
742 | * However, we need to provide the function pointer to allow the |
743 | * device_control() method to work. | |
bbea0b6e | 744 | */ |
bbea0b6e IS |
745 | return NULL; |
746 | } | |
747 | ||
c3635c78 | 748 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 749 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 750 | { |
968f19ae | 751 | struct dma_slave_config *config; |
a1c03319 | 752 | struct fsldma_chan *chan; |
bbea0b6e | 753 | unsigned long flags; |
968f19ae | 754 | int size; |
c3635c78 | 755 | |
a1c03319 | 756 | if (!dchan) |
c3635c78 | 757 | return -EINVAL; |
bbea0b6e | 758 | |
a1c03319 | 759 | chan = to_fsl_chan(dchan); |
bbea0b6e | 760 | |
968f19ae IS |
761 | switch (cmd) { |
762 | case DMA_TERMINATE_ALL: | |
f04cd407 IS |
763 | spin_lock_irqsave(&chan->desc_lock, flags); |
764 | ||
968f19ae IS |
765 | /* Halt the DMA engine */ |
766 | dma_halt(chan); | |
bbea0b6e | 767 | |
968f19ae IS |
768 | /* Remove and free all of the descriptors in the LD queue */ |
769 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
770 | fsldma_free_desc_list(chan, &chan->ld_running); | |
f04cd407 | 771 | chan->idle = true; |
bbea0b6e | 772 | |
968f19ae IS |
773 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
774 | return 0; | |
775 | ||
776 | case DMA_SLAVE_CONFIG: | |
777 | config = (struct dma_slave_config *)arg; | |
778 | ||
779 | /* make sure the channel supports setting burst size */ | |
780 | if (!chan->set_request_count) | |
781 | return -ENXIO; | |
782 | ||
783 | /* we set the controller burst size depending on direction */ | |
784 | if (config->direction == DMA_TO_DEVICE) | |
785 | size = config->dst_addr_width * config->dst_maxburst; | |
786 | else | |
787 | size = config->src_addr_width * config->src_maxburst; | |
788 | ||
789 | chan->set_request_count(chan, size); | |
790 | return 0; | |
791 | ||
792 | case FSLDMA_EXTERNAL_START: | |
793 | ||
794 | /* make sure the channel supports external start */ | |
795 | if (!chan->toggle_ext_start) | |
796 | return -ENXIO; | |
797 | ||
798 | chan->toggle_ext_start(chan, arg); | |
799 | return 0; | |
800 | ||
801 | default: | |
802 | return -ENXIO; | |
803 | } | |
c3635c78 LW |
804 | |
805 | return 0; | |
bbea0b6e IS |
806 | } |
807 | ||
173acc7c | 808 | /** |
f04cd407 | 809 | * fsl_chan_ld_cleanup - Clean up link descriptors |
a1c03319 | 810 | * @chan : Freescale DMA channel |
9c3a50b7 | 811 | * |
f04cd407 IS |
812 | * This function is run after the queue of running descriptors has been |
813 | * executed by the DMA engine. It will run any callbacks, and then free | |
814 | * the descriptors. | |
815 | * | |
816 | * HARDWARE STATE: idle | |
173acc7c | 817 | */ |
f04cd407 | 818 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c | 819 | { |
f04cd407 | 820 | struct fsl_desc_sw *desc, *_desc; |
9c3a50b7 | 821 | unsigned long flags; |
173acc7c | 822 | |
9c3a50b7 | 823 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 824 | |
f04cd407 | 825 | /* if the ld_running list is empty, there is nothing to do */ |
9c3a50b7 | 826 | if (list_empty(&chan->ld_running)) { |
f04cd407 | 827 | chan_dbg(chan, "no descriptors to cleanup\n"); |
9c3a50b7 | 828 | goto out_unlock; |
173acc7c | 829 | } |
9c3a50b7 | 830 | |
f04cd407 IS |
831 | /* |
832 | * Get the last descriptor, update the cookie to it | |
833 | * | |
834 | * This is done before callbacks run so that clients can check the | |
835 | * status of their DMA transfer inside the callback. | |
836 | */ | |
9c3a50b7 | 837 | desc = to_fsl_desc(chan->ld_running.prev); |
f04cd407 IS |
838 | chan->completed_cookie = desc->async_tx.cookie; |
839 | chan_dbg(chan, "completed_cookie = %d\n", chan->completed_cookie); | |
173acc7c | 840 | |
f04cd407 | 841 | /* Run the callback for each descriptor, in order */ |
9c3a50b7 | 842 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { |
173acc7c ZW |
843 | dma_async_tx_callback callback; |
844 | void *callback_param; | |
845 | ||
9c3a50b7 | 846 | /* Remove from the list of running transactions */ |
173acc7c ZW |
847 | list_del(&desc->node); |
848 | ||
173acc7c | 849 | /* Run the link descriptor callback function */ |
9c3a50b7 IS |
850 | callback = desc->async_tx.callback; |
851 | callback_param = desc->async_tx.callback_param; | |
173acc7c | 852 | if (callback) { |
a1c03319 | 853 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
0ab09c36 | 854 | #ifdef FSL_DMA_LD_DEBUG |
b158471e | 855 | chan_dbg(chan, "LD %p callback\n", desc); |
0ab09c36 | 856 | #endif |
173acc7c | 857 | callback(callback_param); |
a1c03319 | 858 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 859 | } |
9c3a50b7 IS |
860 | |
861 | /* Run any dependencies, then free the descriptor */ | |
862 | dma_run_dependencies(&desc->async_tx); | |
0ab09c36 IS |
863 | #ifdef FSL_DMA_LD_DEBUG |
864 | chan_dbg(chan, "LD %p free\n", desc); | |
865 | #endif | |
9c3a50b7 | 866 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
173acc7c | 867 | } |
9c3a50b7 | 868 | |
f04cd407 | 869 | out_unlock: |
a1c03319 | 870 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
871 | } |
872 | ||
873 | /** | |
9c3a50b7 | 874 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 875 | * @chan : Freescale DMA channel |
9c3a50b7 | 876 | * |
f04cd407 | 877 | * HARDWARE STATE: idle |
173acc7c | 878 | */ |
a1c03319 | 879 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 880 | { |
9c3a50b7 | 881 | struct fsl_desc_sw *desc; |
173acc7c ZW |
882 | unsigned long flags; |
883 | ||
a1c03319 | 884 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 885 | |
9c3a50b7 IS |
886 | /* |
887 | * If the list of pending descriptors is empty, then we | |
888 | * don't need to do any work at all | |
889 | */ | |
890 | if (list_empty(&chan->ld_pending)) { | |
b158471e | 891 | chan_dbg(chan, "no pending LDs\n"); |
138ef018 | 892 | goto out_unlock; |
9c3a50b7 | 893 | } |
173acc7c | 894 | |
9c3a50b7 | 895 | /* |
f04cd407 IS |
896 | * The DMA controller is not idle, which means that the interrupt |
897 | * handler will start any queued transactions when it runs after | |
898 | * this transaction finishes | |
9c3a50b7 | 899 | */ |
f04cd407 | 900 | if (!chan->idle) { |
b158471e | 901 | chan_dbg(chan, "DMA controller still busy\n"); |
9c3a50b7 IS |
902 | goto out_unlock; |
903 | } | |
904 | ||
9c3a50b7 IS |
905 | /* |
906 | * If there are some link descriptors which have not been | |
907 | * transferred, we need to start the controller | |
173acc7c | 908 | */ |
173acc7c | 909 | |
9c3a50b7 IS |
910 | /* |
911 | * Move all elements from the queue of pending transactions | |
912 | * onto the list of running transactions | |
913 | */ | |
f04cd407 | 914 | chan_dbg(chan, "idle, starting controller\n"); |
9c3a50b7 IS |
915 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); |
916 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
917 | ||
f04cd407 IS |
918 | /* |
919 | * The 85xx DMA controller doesn't clear the channel start bit | |
920 | * automatically at the end of a transfer. Therefore we must clear | |
921 | * it in software before starting the transfer. | |
922 | */ | |
923 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
924 | u32 mode; | |
925 | ||
926 | mode = DMA_IN(chan, &chan->regs->mr, 32); | |
927 | mode &= ~FSL_DMA_MR_CS; | |
928 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
929 | } | |
930 | ||
9c3a50b7 IS |
931 | /* |
932 | * Program the descriptor's address into the DMA controller, | |
933 | * then start the DMA transaction | |
934 | */ | |
935 | set_cdar(chan, desc->async_tx.phys); | |
f04cd407 IS |
936 | get_cdar(chan); |
937 | ||
9c3a50b7 | 938 | dma_start(chan); |
f04cd407 | 939 | chan->idle = false; |
138ef018 IS |
940 | |
941 | out_unlock: | |
a1c03319 | 942 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
943 | } |
944 | ||
945 | /** | |
946 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 947 | * @chan : Freescale DMA channel |
173acc7c | 948 | */ |
a1c03319 | 949 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 950 | { |
a1c03319 | 951 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
a1c03319 | 952 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
953 | } |
954 | ||
173acc7c | 955 | /** |
07934481 | 956 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 957 | * @chan : Freescale DMA channel |
173acc7c | 958 | */ |
07934481 | 959 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 960 | dma_cookie_t cookie, |
07934481 | 961 | struct dma_tx_state *txstate) |
173acc7c | 962 | { |
a1c03319 | 963 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c | 964 | dma_cookie_t last_complete; |
f04cd407 IS |
965 | dma_cookie_t last_used; |
966 | unsigned long flags; | |
173acc7c | 967 | |
f04cd407 | 968 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 969 | |
a1c03319 | 970 | last_complete = chan->completed_cookie; |
f04cd407 | 971 | last_used = dchan->cookie; |
173acc7c | 972 | |
f04cd407 | 973 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c | 974 | |
f04cd407 | 975 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
976 | return dma_async_is_complete(cookie, last_complete, last_used); |
977 | } | |
978 | ||
d3f620b2 IS |
979 | /*----------------------------------------------------------------------------*/ |
980 | /* Interrupt Handling */ | |
981 | /*----------------------------------------------------------------------------*/ | |
982 | ||
e7a29151 | 983 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 984 | { |
a1c03319 | 985 | struct fsldma_chan *chan = data; |
a1c03319 | 986 | u32 stat; |
173acc7c | 987 | |
9c3a50b7 | 988 | /* save and clear the status register */ |
a1c03319 | 989 | stat = get_sr(chan); |
9c3a50b7 | 990 | set_sr(chan, stat); |
b158471e | 991 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 992 | |
f04cd407 | 993 | /* check that this was really our device */ |
173acc7c ZW |
994 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
995 | if (!stat) | |
996 | return IRQ_NONE; | |
997 | ||
998 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 999 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 1000 | |
9c3a50b7 IS |
1001 | /* |
1002 | * Programming Error | |
f79abb62 ZW |
1003 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1004 | * triger a PE interrupt. | |
1005 | */ | |
1006 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 1007 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 1008 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
1009 | if (get_bcr(chan) != 0) |
1010 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
1011 | } |
1012 | ||
9c3a50b7 IS |
1013 | /* |
1014 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1015 | * and start the next transfer if it exist. |
1016 | */ | |
1017 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 1018 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 1019 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
1020 | } |
1021 | ||
9c3a50b7 IS |
1022 | /* |
1023 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1024 | * we should clear the Channel Start bit for |
1025 | * prepare next transfer. | |
1026 | */ | |
1c62979e | 1027 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 1028 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 1029 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
1030 | } |
1031 | ||
f04cd407 IS |
1032 | /* check that the DMA controller is really idle */ |
1033 | if (!dma_is_idle(chan)) | |
1034 | chan_err(chan, "irq: controller not idle!\n"); | |
1035 | ||
1036 | /* check that we handled all of the bits */ | |
173acc7c | 1037 | if (stat) |
f04cd407 | 1038 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1039 | |
f04cd407 IS |
1040 | /* |
1041 | * Schedule the tasklet to handle all cleanup of the current | |
1042 | * transaction. It will start a new transaction if there is | |
1043 | * one pending. | |
1044 | */ | |
a1c03319 | 1045 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 1046 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
1047 | return IRQ_HANDLED; |
1048 | } | |
1049 | ||
d3f620b2 IS |
1050 | static void dma_do_tasklet(unsigned long data) |
1051 | { | |
a1c03319 | 1052 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
f04cd407 IS |
1053 | unsigned long flags; |
1054 | ||
1055 | chan_dbg(chan, "tasklet entry\n"); | |
1056 | ||
1057 | /* run all callbacks, free all used descriptors */ | |
a1c03319 | 1058 | fsl_chan_ld_cleanup(chan); |
f04cd407 IS |
1059 | |
1060 | /* the channel is now idle */ | |
1061 | spin_lock_irqsave(&chan->desc_lock, flags); | |
1062 | chan->idle = true; | |
1063 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
1064 | ||
1065 | /* start any pending transactions automatically */ | |
1066 | fsl_chan_xfer_ld_queue(chan); | |
1067 | chan_dbg(chan, "tasklet exit\n"); | |
d3f620b2 IS |
1068 | } |
1069 | ||
1070 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1071 | { |
a4f56d4b | 1072 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1073 | struct fsldma_chan *chan; |
1074 | unsigned int handled = 0; | |
1075 | u32 gsr, mask; | |
1076 | int i; | |
173acc7c | 1077 | |
e7a29151 | 1078 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1079 | : in_le32(fdev->regs); |
1080 | mask = 0xff000000; | |
1081 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1082 | |
d3f620b2 IS |
1083 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1084 | chan = fdev->chan[i]; | |
1085 | if (!chan) | |
1086 | continue; | |
1087 | ||
1088 | if (gsr & mask) { | |
1089 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1090 | fsldma_chan_irq(irq, chan); | |
1091 | handled++; | |
1092 | } | |
1093 | ||
1094 | gsr &= ~mask; | |
1095 | mask >>= 8; | |
1096 | } | |
1097 | ||
1098 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1099 | } |
1100 | ||
d3f620b2 | 1101 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1102 | { |
d3f620b2 IS |
1103 | struct fsldma_chan *chan; |
1104 | int i; | |
1105 | ||
1106 | if (fdev->irq != NO_IRQ) { | |
1107 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1108 | free_irq(fdev->irq, fdev); | |
1109 | return; | |
1110 | } | |
1111 | ||
1112 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1113 | chan = fdev->chan[i]; | |
1114 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1115 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1116 | free_irq(chan->irq, chan); |
1117 | } | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1122 | { | |
1123 | struct fsldma_chan *chan; | |
1124 | int ret; | |
1125 | int i; | |
1126 | ||
1127 | /* if we have a per-controller IRQ, use that */ | |
1128 | if (fdev->irq != NO_IRQ) { | |
1129 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1130 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1131 | "fsldma-controller", fdev); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1136 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1137 | chan = fdev->chan[i]; | |
1138 | if (!chan) | |
1139 | continue; | |
1140 | ||
1141 | if (chan->irq == NO_IRQ) { | |
b158471e | 1142 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1143 | ret = -ENODEV; |
1144 | goto out_unwind; | |
1145 | } | |
1146 | ||
b158471e | 1147 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1148 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1149 | "fsldma-chan", chan); | |
1150 | if (ret) { | |
b158471e | 1151 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1152 | goto out_unwind; |
1153 | } | |
1154 | } | |
1155 | ||
1156 | return 0; | |
1157 | ||
1158 | out_unwind: | |
1159 | for (/* none */; i >= 0; i--) { | |
1160 | chan = fdev->chan[i]; | |
1161 | if (!chan) | |
1162 | continue; | |
1163 | ||
1164 | if (chan->irq == NO_IRQ) | |
1165 | continue; | |
1166 | ||
1167 | free_irq(chan->irq, chan); | |
1168 | } | |
1169 | ||
1170 | return ret; | |
173acc7c ZW |
1171 | } |
1172 | ||
a4f56d4b IS |
1173 | /*----------------------------------------------------------------------------*/ |
1174 | /* OpenFirmware Subsystem */ | |
1175 | /*----------------------------------------------------------------------------*/ | |
1176 | ||
1177 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1178 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1179 | { |
a1c03319 | 1180 | struct fsldma_chan *chan; |
4ce0e953 | 1181 | struct resource res; |
173acc7c ZW |
1182 | int err; |
1183 | ||
173acc7c | 1184 | /* alloc channel */ |
a1c03319 IS |
1185 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1186 | if (!chan) { | |
e7a29151 IS |
1187 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1188 | err = -ENOMEM; | |
1189 | goto out_return; | |
1190 | } | |
1191 | ||
1192 | /* ioremap registers for use */ | |
a1c03319 IS |
1193 | chan->regs = of_iomap(node, 0); |
1194 | if (!chan->regs) { | |
e7a29151 IS |
1195 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1196 | err = -ENOMEM; | |
a1c03319 | 1197 | goto out_free_chan; |
173acc7c ZW |
1198 | } |
1199 | ||
4ce0e953 | 1200 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1201 | if (err) { |
e7a29151 IS |
1202 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1203 | goto out_iounmap_regs; | |
173acc7c ZW |
1204 | } |
1205 | ||
a1c03319 | 1206 | chan->feature = feature; |
173acc7c | 1207 | if (!fdev->feature) |
a1c03319 | 1208 | fdev->feature = chan->feature; |
173acc7c | 1209 | |
e7a29151 IS |
1210 | /* |
1211 | * If the DMA device's feature is different than the feature | |
1212 | * of its channels, report the bug | |
173acc7c | 1213 | */ |
a1c03319 | 1214 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1215 | |
a1c03319 IS |
1216 | chan->dev = fdev->dev; |
1217 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1218 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1219 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1220 | err = -EINVAL; |
e7a29151 | 1221 | goto out_iounmap_regs; |
173acc7c | 1222 | } |
173acc7c | 1223 | |
a1c03319 IS |
1224 | fdev->chan[chan->id] = chan; |
1225 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1226 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1227 | |
1228 | /* Initialize the channel */ | |
a1c03319 | 1229 | dma_init(chan); |
173acc7c ZW |
1230 | |
1231 | /* Clear cdar registers */ | |
a1c03319 | 1232 | set_cdar(chan, 0); |
173acc7c | 1233 | |
a1c03319 | 1234 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1235 | case FSL_DMA_IP_85XX: |
a1c03319 | 1236 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1237 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1238 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1239 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1240 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1241 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1242 | } |
1243 | ||
a1c03319 | 1244 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1245 | INIT_LIST_HEAD(&chan->ld_pending); |
1246 | INIT_LIST_HEAD(&chan->ld_running); | |
f04cd407 | 1247 | chan->idle = true; |
173acc7c | 1248 | |
a1c03319 | 1249 | chan->common.device = &fdev->common; |
173acc7c | 1250 | |
d3f620b2 | 1251 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1252 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1253 | |
173acc7c | 1254 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1255 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1256 | fdev->common.chancnt++; |
1257 | ||
a1c03319 IS |
1258 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1259 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1260 | |
1261 | return 0; | |
51ee87f2 | 1262 | |
e7a29151 | 1263 | out_iounmap_regs: |
a1c03319 IS |
1264 | iounmap(chan->regs); |
1265 | out_free_chan: | |
1266 | kfree(chan); | |
e7a29151 | 1267 | out_return: |
173acc7c ZW |
1268 | return err; |
1269 | } | |
1270 | ||
a1c03319 | 1271 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1272 | { |
a1c03319 IS |
1273 | irq_dispose_mapping(chan->irq); |
1274 | list_del(&chan->common.device_node); | |
1275 | iounmap(chan->regs); | |
1276 | kfree(chan); | |
173acc7c ZW |
1277 | } |
1278 | ||
2dc11581 | 1279 | static int __devinit fsldma_of_probe(struct platform_device *op, |
173acc7c ZW |
1280 | const struct of_device_id *match) |
1281 | { | |
a4f56d4b | 1282 | struct fsldma_device *fdev; |
77cd62e8 | 1283 | struct device_node *child; |
e7a29151 | 1284 | int err; |
173acc7c | 1285 | |
a4f56d4b | 1286 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1287 | if (!fdev) { |
e7a29151 IS |
1288 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1289 | err = -ENOMEM; | |
1290 | goto out_return; | |
173acc7c | 1291 | } |
e7a29151 IS |
1292 | |
1293 | fdev->dev = &op->dev; | |
173acc7c ZW |
1294 | INIT_LIST_HEAD(&fdev->common.channels); |
1295 | ||
e7a29151 | 1296 | /* ioremap the registers for use */ |
61c7a080 | 1297 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1298 | if (!fdev->regs) { |
1299 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1300 | err = -ENOMEM; | |
1301 | goto out_free_fdev; | |
173acc7c ZW |
1302 | } |
1303 | ||
d3f620b2 | 1304 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1305 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1306 | |
173acc7c ZW |
1307 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1308 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1309 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1310 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1311 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1312 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1313 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1314 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1315 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1316 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1317 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1318 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1319 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1320 | fdev->common.dev = &op->dev; |
173acc7c | 1321 | |
e2c8e425 LY |
1322 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1323 | ||
e7a29151 | 1324 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1325 | |
e7a29151 IS |
1326 | /* |
1327 | * We cannot use of_platform_bus_probe() because there is no | |
1328 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1329 | * channel object. |
1330 | */ | |
61c7a080 | 1331 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1332 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1333 | fsl_dma_chan_probe(fdev, child, |
1334 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1335 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1336 | } |
1337 | ||
1338 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1339 | fsl_dma_chan_probe(fdev, child, |
1340 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1341 | "fsl,elo-dma-channel"); | |
e7a29151 | 1342 | } |
77cd62e8 | 1343 | } |
173acc7c | 1344 | |
d3f620b2 IS |
1345 | /* |
1346 | * Hookup the IRQ handler(s) | |
1347 | * | |
1348 | * If we have a per-controller interrupt, we prefer that to the | |
1349 | * per-channel interrupts to reduce the number of shared interrupt | |
1350 | * handlers on the same IRQ line | |
1351 | */ | |
1352 | err = fsldma_request_irqs(fdev); | |
1353 | if (err) { | |
1354 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1355 | goto out_free_fdev; | |
1356 | } | |
1357 | ||
173acc7c ZW |
1358 | dma_async_device_register(&fdev->common); |
1359 | return 0; | |
1360 | ||
e7a29151 | 1361 | out_free_fdev: |
d3f620b2 | 1362 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1363 | kfree(fdev); |
e7a29151 | 1364 | out_return: |
173acc7c ZW |
1365 | return err; |
1366 | } | |
1367 | ||
2dc11581 | 1368 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1369 | { |
a4f56d4b | 1370 | struct fsldma_device *fdev; |
77cd62e8 TT |
1371 | unsigned int i; |
1372 | ||
e7a29151 | 1373 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1374 | dma_async_device_unregister(&fdev->common); |
1375 | ||
d3f620b2 IS |
1376 | fsldma_free_irqs(fdev); |
1377 | ||
e7a29151 | 1378 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1379 | if (fdev->chan[i]) |
1380 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1381 | } |
77cd62e8 | 1382 | |
e7a29151 IS |
1383 | iounmap(fdev->regs); |
1384 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1385 | kfree(fdev); |
77cd62e8 TT |
1386 | |
1387 | return 0; | |
1388 | } | |
1389 | ||
4b1cf1fa | 1390 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1391 | { .compatible = "fsl,eloplus-dma", }, |
1392 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1393 | {} |
1394 | }; | |
1395 | ||
a4f56d4b | 1396 | static struct of_platform_driver fsldma_of_driver = { |
4018294b GL |
1397 | .driver = { |
1398 | .name = "fsl-elo-dma", | |
1399 | .owner = THIS_MODULE, | |
1400 | .of_match_table = fsldma_of_ids, | |
1401 | }, | |
1402 | .probe = fsldma_of_probe, | |
1403 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1404 | }; |
1405 | ||
a4f56d4b IS |
1406 | /*----------------------------------------------------------------------------*/ |
1407 | /* Module Init / Exit */ | |
1408 | /*----------------------------------------------------------------------------*/ | |
1409 | ||
1410 | static __init int fsldma_init(void) | |
173acc7c | 1411 | { |
77cd62e8 TT |
1412 | int ret; |
1413 | ||
1414 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1415 | ||
a4f56d4b | 1416 | ret = of_register_platform_driver(&fsldma_of_driver); |
77cd62e8 TT |
1417 | if (ret) |
1418 | pr_err("fsldma: failed to register platform driver\n"); | |
1419 | ||
1420 | return ret; | |
1421 | } | |
1422 | ||
a4f56d4b | 1423 | static void __exit fsldma_exit(void) |
77cd62e8 | 1424 | { |
a4f56d4b | 1425 | of_unregister_platform_driver(&fsldma_of_driver); |
173acc7c ZW |
1426 | } |
1427 | ||
a4f56d4b IS |
1428 | subsys_initcall(fsldma_init); |
1429 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1430 | |
1431 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1432 | MODULE_LICENSE("GPL"); |