[deliverable/linux.git] / drivers / dma / fsldma.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author:
 *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
 *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */
#ifndef __DMA_FSLDMA_H
#define __DMA_FSLDMA_H

#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/dmaengine.h>

/* Define data structures needed by Freescale
 * MPC8540 and MPC8349 DMA controller.
 */
#define FSL_DMA_MR_CS		0x00000001
#define FSL_DMA_MR_CC		0x00000002
#define FSL_DMA_MR_CA		0x00000008
#define FSL_DMA_MR_EIE		0x00000040
#define FSL_DMA_MR_XFE		0x00000020
#define FSL_DMA_MR_EOLNIE	0x00000100
#define FSL_DMA_MR_EOLSIE	0x00000080
#define FSL_DMA_MR_EOSIE	0x00000200
#define FSL_DMA_MR_CDSM		0x00000010
#define FSL_DMA_MR_CTM		0x00000004
#define FSL_DMA_MR_EMP_EN	0x00200000
#define FSL_DMA_MR_EMS_EN	0x00040000
#define FSL_DMA_MR_DAHE		0x00002000
#define FSL_DMA_MR_SAHE		0x00001000

/* Special MR definition for MPC8349 */
#define FSL_DMA_MR_EOTIE	0x00000080

#define FSL_DMA_SR_CH		0x00000020
#define FSL_DMA_SR_CB		0x00000004
#define FSL_DMA_SR_TE		0x00000080
#define FSL_DMA_SR_EOSI		0x00000002
#define FSL_DMA_SR_EOLSI	0x00000001
#define FSL_DMA_SR_EOCDI	0x00000001
#define FSL_DMA_SR_EOLNI	0x00000008

#define FSL_DMA_SATR_SBPATMU			0x20000000
#define FSL_DMA_SATR_STRANSINT_RIO		0x00c00000
#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ	0x00050000
#define FSL_DMA_SATR_SREADTYPE_BP_IORH		0x00020000
#define FSL_DMA_SATR_SREADTYPE_BP_NREAD		0x00040000
#define FSL_DMA_SATR_SREADTYPE_BP_MREAD		0x00070000

#define FSL_DMA_DATR_DBPATMU			0x20000000
#define FSL_DMA_DATR_DTRANSINT_RIO		0x00c00000
#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE	0x00050000
#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH	0x00010000

#define FSL_DMA_EOL		((u64)0x1)
#define FSL_DMA_SNEN		((u64)0x10)
#define FSL_DMA_EOSIE		0x8
#define FSL_DMA_NLDA_MASK	(~(u64)0x1f)

#define FSL_DMA_BCR_MAX_CNT	0x03ffffffu

#define FSL_DMA_DGSR_TE		0x80
#define FSL_DMA_DGSR_CH		0x20
#define FSL_DMA_DGSR_PE		0x10
#define FSL_DMA_DGSR_EOLNI	0x08
#define FSL_DMA_DGSR_CB		0x04
#define FSL_DMA_DGSR_EOSI	0x02
#define FSL_DMA_DGSR_EOLSI	0x01

struct fsl_dma_ld_hw {
	u64 __bitwise	src_addr;
	u64 __bitwise	dst_addr;
	u64 __bitwise	next_ln_addr;
	u32 __bitwise	count;
	u32 __bitwise	reserve;
} __attribute__((aligned(32)));

struct fsl_desc_sw {
	struct fsl_dma_ld_hw hw;
	struct list_head node;
	struct dma_async_tx_descriptor async_tx;
	struct list_head *ld;
	void *priv;
} __attribute__((aligned(32)));

struct fsl_dma_chan_regs {
	u32 __bitwise	mr;	/* 0x00 - Mode Register */
	u32 __bitwise	sr;	/* 0x04 - Status Register */
	u64 __bitwise	cdar;	/* 0x08 - Current descriptor address register */
	u64 __bitwise	sar;	/* 0x10 - Source Address Register */
	u64 __bitwise	dar;	/* 0x18 - Destination Address Register */
	u32 __bitwise	bcr;	/* 0x20 - Byte Count Register */
	u64 __bitwise	ndar;	/* 0x24 - Next Descriptor Address Register */
};

struct fsl_dma_chan;
#define FSL_DMA_MAX_CHANS_PER_DEVICE 4

struct fsl_dma_device {
	void __iomem *reg_base;	/* DGSR register base */
	struct resource reg;	/* Resource for register */
	struct device *dev;
	struct dma_device common;
	struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
	u32 feature;		/* The same as DMA channels */
};

/* Define macros for fsl_dma_chan->feature property */
#define FSL_DMA_LITTLE_ENDIAN	0x00000000
#define FSL_DMA_BIG_ENDIAN	0x00000001

#define FSL_DMA_IP_MASK		0x00000ff0
#define FSL_DMA_IP_85XX		0x00000010
#define FSL_DMA_IP_83XX		0x00000020

#define FSL_DMA_CHAN_PAUSE_EXT	0x00001000
#define FSL_DMA_CHAN_START_EXT	0x00002000

struct fsl_dma_chan {
	struct fsl_dma_chan_regs __iomem *reg_base;
	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
	spinlock_t desc_lock;		/* Descriptor operation lock */
	struct list_head ld_queue;	/* Link descriptors queue */
	struct dma_chan common;		/* DMA common channel */
	struct dma_pool *desc_pool;	/* Descriptors pool */
	struct device *dev;		/* Channel device */
	struct resource reg;		/* Resource for register */
	int irq;			/* Channel IRQ */
	int id;				/* Raw id of this channel */
	struct tasklet_struct tasklet;
	u32 feature;

	void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int size);
	void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable);
	void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size);
	void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size);
};

#define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common)
#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)

#ifndef __powerpc64__
static u64 in_be64(const u64 __iomem *addr)
{
	return ((u64)in_be32((u32 *)addr) << 32) | (in_be32((u32 *)addr + 1));
}

static void out_be64(u64 __iomem *addr, u64 val)
{
	out_be32((u32 *)addr, val >> 32);
	out_be32((u32 *)addr + 1, (u32)val);
}

/* There is no asm instructions for 64 bits reverse loads and stores */
static u64 in_le64(const u64 __iomem *addr)
{
	return ((u64)in_le32((u32 *)addr + 1) << 32) | (in_le32((u32 *)addr));
}

static void out_le64(u64 __iomem *addr, u64 val)
{
	out_le32((u32 *)addr + 1, val >> 32);
	out_le32((u32 *)addr, (u32)val);
}
#endif

#define DMA_IN(fsl_chan, addr, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			in_be##width(addr) : in_le##width(addr))
#define DMA_OUT(fsl_chan, addr, val, width)				\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			out_be##width(addr, val) : out_le##width(addr, val))

#define DMA_TO_CPU(fsl_chan, d, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			be##width##_to_cpu(d) :	le##width##_to_cpu(d))
#define CPU_TO_DMA(fsl_chan, c, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			cpu_to_be##width(c) : cpu_to_le##width(c))

#endif	/* __DMA_FSLDMA_H */
Commit	Line	Data
173acc7c ZW	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
	3	*
	4	* Author:
	5	* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
	6	* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
	7	*
	8	* This is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14	#ifndef __DMA_FSLDMA_H
	15	#define __DMA_FSLDMA_H
	16
	17	#include <linux/device.h>
	18	#include <linux/dmapool.h>
	19	#include <linux/dmaengine.h>
	20
	21	/* Define data structures needed by Freescale
	22	* MPC8540 and MPC8349 DMA controller.
	23	*/
	24	#define FSL_DMA_MR_CS 0x00000001
	25	#define FSL_DMA_MR_CC 0x00000002
	26	#define FSL_DMA_MR_CA 0x00000008
	27	#define FSL_DMA_MR_EIE 0x00000040
	28	#define FSL_DMA_MR_XFE 0x00000020
	29	#define FSL_DMA_MR_EOLNIE 0x00000100
	30	#define FSL_DMA_MR_EOLSIE 0x00000080
	31	#define FSL_DMA_MR_EOSIE 0x00000200
	32	#define FSL_DMA_MR_CDSM 0x00000010
	33	#define FSL_DMA_MR_CTM 0x00000004
	34	#define FSL_DMA_MR_EMP_EN 0x00200000
	35	#define FSL_DMA_MR_EMS_EN 0x00040000
	36	#define FSL_DMA_MR_DAHE 0x00002000
	37	#define FSL_DMA_MR_SAHE 0x00001000
	38
	39	/* Special MR definition for MPC8349 */
	40	#define FSL_DMA_MR_EOTIE 0x00000080
	41
	42	#define FSL_DMA_SR_CH 0x00000020
	43	#define FSL_DMA_SR_CB 0x00000004
	44	#define FSL_DMA_SR_TE 0x00000080
	45	#define FSL_DMA_SR_EOSI 0x00000002
	46	#define FSL_DMA_SR_EOLSI 0x00000001
	47	#define FSL_DMA_SR_EOCDI 0x00000001
	48	#define FSL_DMA_SR_EOLNI 0x00000008
	49
	50	#define FSL_DMA_SATR_SBPATMU 0x20000000
	51	#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
	52	#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
	53	#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
	54	#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
	55	#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
	56
	57	#define FSL_DMA_DATR_DBPATMU 0x20000000
	58	#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
	59	#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
	60	#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
	61
	62	#define FSL_DMA_EOL ((u64)0x1)
	63	#define FSL_DMA_SNEN ((u64)0x10)
	64	#define FSL_DMA_EOSIE 0x8
65	#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
66
67	#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
68
69	#define FSL_DMA_DGSR_TE 0x80
70	#define FSL_DMA_DGSR_CH 0x20
71	#define FSL_DMA_DGSR_PE 0x10
72	#define FSL_DMA_DGSR_EOLNI 0x08
73	#define FSL_DMA_DGSR_CB 0x04
74	#define FSL_DMA_DGSR_EOSI 0x02
75	#define FSL_DMA_DGSR_EOLSI 0x01
76
77	struct fsl_dma_ld_hw {
78	u64 __bitwise src_addr;
79	u64 __bitwise dst_addr;
80	u64 __bitwise next_ln_addr;
81	u32 __bitwise count;
82	u32 __bitwise reserve;
83	} __attribute__((aligned(32)));
84
85	struct fsl_desc_sw {
86	struct fsl_dma_ld_hw hw;
87	struct list_head node;
88	struct dma_async_tx_descriptor async_tx;
89	struct list_head *ld;
90	void *priv;
91	} __attribute__((aligned(32)));
92
93	struct fsl_dma_chan_regs {
94	u32 __bitwise mr; /* 0x00 - Mode Register */
95	u32 __bitwise sr; /* 0x04 - Status Register */
96	u64 __bitwise cdar; /* 0x08 - Current descriptor address register */
97	u64 __bitwise sar; /* 0x10 - Source Address Register */
98	u64 __bitwise dar; /* 0x18 - Destination Address Register */
99	u32 __bitwise bcr; /* 0x20 - Byte Count Register */
100	u64 __bitwise ndar; /* 0x24 - Next Descriptor Address Register */
101	};
102
103	struct fsl_dma_chan;
104	#define FSL_DMA_MAX_CHANS_PER_DEVICE 4
105
106	struct fsl_dma_device {
107	void __iomem reg_base; / DGSR register base */
108	struct resource reg; /* Resource for register */
109	struct device *dev;
110	struct dma_device common;
111	struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
112	u32 feature; /* The same as DMA channels */
113	};
114
115	/* Define macros for fsl_dma_chan->feature property */
116	#define FSL_DMA_LITTLE_ENDIAN 0x00000000
117	#define FSL_DMA_BIG_ENDIAN 0x00000001
118
119	#define FSL_DMA_IP_MASK 0x00000ff0
120	#define FSL_DMA_IP_85XX 0x00000010
121	#define FSL_DMA_IP_83XX 0x00000020
122
123	#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
124	#define FSL_DMA_CHAN_START_EXT 0x00002000
125
126	struct fsl_dma_chan {
127	struct fsl_dma_chan_regs __iomem *reg_base;
128	dma_cookie_t completed_cookie; /* The maximum cookie completed */
129	spinlock_t desc_lock; /* Descriptor operation lock */
130	struct list_head ld_queue; /* Link descriptors queue */
131	struct dma_chan common; /* DMA common channel */
132	struct dma_pool desc_pool; / Descriptors pool */
133	struct device dev; / Channel device */
134	struct resource reg; /* Resource for register */
135	int irq; /* Channel IRQ */
136	int id; /* Raw id of this channel */
137	struct tasklet_struct tasklet;
138	u32 feature;
139
140	void (toggle_ext_pause)(struct fsl_dma_chan fsl_chan, int size);
141	void (toggle_ext_start)(struct fsl_dma_chan fsl_chan, int enable);
142	void (set_src_loop_size)(struct fsl_dma_chan fsl_chan, int size);
143	void (set_dest_loop_size)(struct fsl_dma_chan fsl_chan, int size);
144	};
145
146	#define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common)
147	#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
148	#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
149
150	#ifndef __powerpc64__
151	static u64 in_be64(const u64 __iomem *addr)
152	{
153	return ((u64)in_be32((u32 )addr) << 32) \| (in_be32((u32 )addr + 1));
154	}
155
156	static void out_be64(u64 __iomem *addr, u64 val)
157	{
158	out_be32((u32 *)addr, val >> 32);
159	out_be32((u32 *)addr + 1, (u32)val);
160	}
161
162	/* There is no asm instructions for 64 bits reverse loads and stores */
163	static u64 in_le64(const u64 __iomem *addr)
164	{
165	return ((u64)in_le32((u32 )addr + 1) << 32) \| (in_le32((u32 )addr));
166	}
167
168	static void out_le64(u64 __iomem *addr, u64 val)
169	{
170	out_le32((u32 *)addr + 1, val >> 32);
171	out_le32((u32 *)addr, (u32)val);
172	}
173	#endif
174
175	#define DMA_IN(fsl_chan, addr, width) \
176	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
177	in_be##width(addr) : in_le##width(addr))
178	#define DMA_OUT(fsl_chan, addr, val, width) \
179	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
180	out_be##width(addr, val) : out_le##width(addr, val))
181
182	#define DMA_TO_CPU(fsl_chan, d, width) \
183	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
184	be##width##_to_cpu(d) : le##width##_to_cpu(d))
185	#define CPU_TO_DMA(fsl_chan, c, width) \
186	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
187	cpu_to_be##width(c) : cpu_to_le##width(c))
188
189	#endif /* __DMA_FSLDMA_H */