[deliverable/linux.git] / drivers / dma / imx-dma.c

/*
 * drivers/dma/imx-dma.c
 *
 * This file contains a driver for the Freescale i.MX DMA engine
 * found on i.MX1/21/27
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/module.h>

#include <asm/irq.h>
#include <mach/dma-v1.h>
#include <mach/hardware.h>

#include "dmaengine.h"

struct imxdma_channel {
	struct imxdma_engine		*imxdma;
	unsigned int			channel;
	unsigned int			imxdma_channel;

	enum dma_slave_buswidth		word_size;
	dma_addr_t			per_address;
	u32				watermark_level;
	struct dma_chan			chan;
	spinlock_t			lock;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	int				dma_request;
	struct scatterlist		*sg_list;
};

#define MAX_DMA_CHANNELS 8

struct imxdma_engine {
	struct device			*dev;
	struct device_dma_parameters	dma_parms;
	struct dma_device		dma_device;
	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
};

static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct imxdma_channel, chan);
}

static void imxdma_handle(struct imxdma_channel *imxdmac)
{
	if (imxdmac->desc.callback)
		imxdmac->desc.callback(imxdmac->desc.callback_param);
	dma_cookie_complete(&imxdmac->desc);
}

static void imxdma_irq_handler(int channel, void *data)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_SUCCESS;
	imxdma_handle(imxdmac);
}

static void imxdma_err_handler(int channel, void *data, int error)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_ERROR;
	imxdma_handle(imxdmac);
}

static void imxdma_progression(int channel, void *data,
		struct scatterlist *sg)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_SUCCESS;
	imxdma_handle(imxdmac);
}

static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct dma_slave_config *dmaengine_cfg = (void *)arg;
	int ret;
	unsigned int mode = 0;

	switch (cmd) {
	case DMA_TERMINATE_ALL:
		imxdmac->status = DMA_ERROR;
		imx_dma_disable(imxdmac->imxdma_channel);
		return 0;
	case DMA_SLAVE_CONFIG:
		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
			imxdmac->per_address = dmaengine_cfg->src_addr;
			imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
			imxdmac->word_size = dmaengine_cfg->src_addr_width;
		} else {
			imxdmac->per_address = dmaengine_cfg->dst_addr;
			imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
			imxdmac->word_size = dmaengine_cfg->dst_addr_width;
		}

		switch (imxdmac->word_size) {
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
			mode = IMX_DMA_MEMSIZE_8;
			break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
			mode = IMX_DMA_MEMSIZE_16;
			break;
		default:
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
			mode = IMX_DMA_MEMSIZE_32;
			break;
		}
		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
				mode | IMX_DMA_TYPE_FIFO,
				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
				imxdmac->dma_request, 1);

		if (ret)
			return ret;

		imx_dma_config_burstlen(imxdmac->imxdma_channel,
				imxdmac->watermark_level * imxdmac->word_size);

		return 0;
	default:
		return -ENOSYS;
	}

	return -EINVAL;
}

static enum dma_status imxdma_tx_status(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate)
{
	return dma_cookie_status(chan, cookie, txstate);
}

static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
	dma_cookie_t cookie;

	spin_lock_irq(&imxdmac->lock);

	cookie = dma_cookie_assign(tx);

	spin_unlock_irq(&imxdmac->lock);

	return cookie;
}

static int imxdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imx_dma_data *data = chan->private;

	imxdmac->dma_request = data->dma_request;

	dma_async_tx_descriptor_init(&imxdmac->desc, chan);
	imxdmac->desc.tx_submit = imxdma_tx_submit;
	/* txd.flags will be overwritten in prep funcs */
	imxdmac->desc.flags = DMA_CTRL_ACK;

	imxdmac->status = DMA_SUCCESS;

	return 0;
}

static void imxdma_free_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);

	imx_dma_disable(imxdmac->imxdma_channel);

	if (imxdmac->sg_list) {
		kfree(imxdmac->sg_list);
		imxdmac->sg_list = NULL;
	}
}

static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct scatterlist *sg;
	int i, ret, dma_length = 0;
	unsigned int dmamode;

	if (imxdmac->status == DMA_IN_PROGRESS)
		return NULL;

	imxdmac->status = DMA_IN_PROGRESS;

	for_each_sg(sgl, sg, sg_len, i) {
		dma_length += sg->length;
	}

	if (direction == DMA_DEV_TO_MEM)
		dmamode = DMA_MODE_READ;
	else
		dmamode = DMA_MODE_WRITE;

	switch (imxdmac->word_size) {
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		if (sgl->length & 3 || sgl->dma_address & 3)
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
		if (sgl->length & 1 || sgl->dma_address & 1)
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		break;
	default:
		return NULL;
	}

	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
		 dma_length, imxdmac->per_address, dmamode);
	if (ret)
		return NULL;

	return &imxdmac->desc;
}

static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	int i, ret;
	unsigned int periods = buf_len / period_len;
	unsigned int dmamode;

	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
			__func__, imxdmac->channel, buf_len, period_len);

	if (imxdmac->status == DMA_IN_PROGRESS)
		return NULL;
	imxdmac->status = DMA_IN_PROGRESS;

	ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
			imxdma_progression);
	if (ret) {
		dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
		return NULL;
	}

	if (imxdmac->sg_list)
		kfree(imxdmac->sg_list);

	imxdmac->sg_list = kcalloc(periods + 1,
			sizeof(struct scatterlist), GFP_KERNEL);
	if (!imxdmac->sg_list)
		return NULL;

	sg_init_table(imxdmac->sg_list, periods);

	for (i = 0; i < periods; i++) {
		imxdmac->sg_list[i].page_link = 0;
		imxdmac->sg_list[i].offset = 0;
		imxdmac->sg_list[i].dma_address = dma_addr;
		imxdmac->sg_list[i].length = period_len;
		dma_addr += period_len;
	}

	/* close the loop */
	imxdmac->sg_list[periods].offset = 0;
	imxdmac->sg_list[periods].length = 0;
	imxdmac->sg_list[periods].page_link =
		((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;

	if (direction == DMA_DEV_TO_MEM)
		dmamode = DMA_MODE_READ;
	else
		dmamode = DMA_MODE_WRITE;

	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
		 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
	if (ret)
		return NULL;

	return &imxdmac->desc;
}

static void imxdma_issue_pending(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);

	if (imxdmac->status == DMA_IN_PROGRESS)
		imx_dma_enable(imxdmac->imxdma_channel);
}

static int __init imxdma_probe(struct platform_device *pdev)
{
	struct imxdma_engine *imxdma;
	int ret, i;

	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
	if (!imxdma)
		return -ENOMEM;

	INIT_LIST_HEAD(&imxdma->dma_device.channels);

	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);

	/* Initialize channel parameters */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
				DMA_PRIO_MEDIUM);
		if ((int)imxdmac->channel < 0) {
			ret = -ENODEV;
			goto err_init;
		}

		imx_dma_setup_handlers(imxdmac->imxdma_channel,
		       imxdma_irq_handler, imxdma_err_handler, imxdmac);

		imxdmac->imxdma = imxdma;
		spin_lock_init(&imxdmac->lock);

		imxdmac->chan.device = &imxdma->dma_device;
		imxdmac->channel = i;

		/* Add the channel to the DMAC list */
		list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
	}

	imxdma->dev = &pdev->dev;
	imxdma->dma_device.dev = &pdev->dev;

	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
	imxdma->dma_device.device_control = imxdma_control;
	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;

	platform_set_drvdata(pdev, imxdma);

	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);

	ret = dma_async_device_register(&imxdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
		goto err_init;
	}

	return 0;

err_init:
	while (--i >= 0) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];
		imx_dma_free(imxdmac->imxdma_channel);
	}

	kfree(imxdma);
	return ret;
}

static int __exit imxdma_remove(struct platform_device *pdev)
{
	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
	int i;

        dma_async_device_unregister(&imxdma->dma_device);

	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		 imx_dma_free(imxdmac->imxdma_channel);
	}

        kfree(imxdma);

        return 0;
}

static struct platform_driver imxdma_driver = {
	.driver		= {
		.name	= "imx-dma",
	},
	.remove		= __exit_p(imxdma_remove),
};

static int __init imxdma_module_init(void)
{
	return platform_driver_probe(&imxdma_driver, imxdma_probe);
}
subsys_initcall(imxdma_module_init);

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX dma driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1f1846c6 SH	1	/*
	2	* drivers/dma/imx-dma.c
	3	*
	4	* This file contains a driver for the Freescale i.MX DMA engine
	5	* found on i.MX1/21/27
	6	*
	7	* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16	#include <linux/init.h>
f8de8f4c	17	#include <linux/module.h>
1f1846c6 SH	18	#include <linux/types.h>
	19	#include <linux/mm.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/device.h>
	23	#include <linux/dma-mapping.h>
	24	#include <linux/slab.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/dmaengine.h>
5c45ad77	27	#include <linux/module.h>
1f1846c6 SH	28
	29	#include <asm/irq.h>
	30	#include <mach/dma-v1.h>
	31	#include <mach/hardware.h>
	32
d2ebfb33 RKAL	33	#include "dmaengine.h"
d2ebfb33 RKAL	34
1f1846c6 SH	35	struct imxdma_channel {
	36	struct imxdma_engine *imxdma;
	37	unsigned int channel;
	38	unsigned int imxdma_channel;
	39
	40	enum dma_slave_buswidth word_size;
	41	dma_addr_t per_address;
	42	u32 watermark_level;
	43	struct dma_chan chan;
	44	spinlock_t lock;
	45	struct dma_async_tx_descriptor desc;
1f1846c6 SH	46	enum dma_status status;
	47	int dma_request;
	48	struct scatterlist *sg_list;
	49	};
	50
	51	#define MAX_DMA_CHANNELS 8
	52
	53	struct imxdma_engine {
	54	struct device *dev;
1e070a60	55	struct device_dma_parameters dma_parms;
1f1846c6 SH	56	struct dma_device dma_device;
	57	struct imxdma_channel channel[MAX_DMA_CHANNELS];
	58	};
	59
	60	static struct imxdma_channel to_imxdma_chan(struct dma_chan chan)
	61	{
	62	return container_of(chan, struct imxdma_channel, chan);
	63	}
	64
	65	static void imxdma_handle(struct imxdma_channel *imxdmac)
	66	{
	67	if (imxdmac->desc.callback)
	68	imxdmac->desc.callback(imxdmac->desc.callback_param);
f7fbce07	69	dma_cookie_complete(&imxdmac->desc);
1f1846c6 SH	70	}
	71
	72	static void imxdma_irq_handler(int channel, void *data)
	73	{
	74	struct imxdma_channel *imxdmac = data;
	75
	76	imxdmac->status = DMA_SUCCESS;
	77	imxdma_handle(imxdmac);
	78	}
	79
	80	static void imxdma_err_handler(int channel, void *data, int error)
	81	{
	82	struct imxdma_channel *imxdmac = data;
	83
	84	imxdmac->status = DMA_ERROR;
	85	imxdma_handle(imxdmac);
	86	}
	87
	88	static void imxdma_progression(int channel, void *data,
	89	struct scatterlist *sg)
	90	{
	91	struct imxdma_channel *imxdmac = data;
	92
	93	imxdmac->status = DMA_SUCCESS;
	94	imxdma_handle(imxdmac);
	95	}
	96
	97	static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
	98	unsigned long arg)
	99	{
	100	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	101	struct dma_slave_config dmaengine_cfg = (void )arg;
	102	int ret;
	103	unsigned int mode = 0;
	104
	105	switch (cmd) {
	106	case DMA_TERMINATE_ALL:
	107	imxdmac->status = DMA_ERROR;
	108	imx_dma_disable(imxdmac->imxdma_channel);
	109	return 0;
	110	case DMA_SLAVE_CONFIG:
db8196df	111	if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1f1846c6 SH	112	imxdmac->per_address = dmaengine_cfg->src_addr;
	113	imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
	114	imxdmac->word_size = dmaengine_cfg->src_addr_width;
	115	} else {
	116	imxdmac->per_address = dmaengine_cfg->dst_addr;
	117	imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
	118	imxdmac->word_size = dmaengine_cfg->dst_addr_width;
	119	}
	120
	121	switch (imxdmac->word_size) {
	122	case DMA_SLAVE_BUSWIDTH_1_BYTE:
	123	mode = IMX_DMA_MEMSIZE_8;
	124	break;
	125	case DMA_SLAVE_BUSWIDTH_2_BYTES:
	126	mode = IMX_DMA_MEMSIZE_16;
	127	break;
	128	default:
	129	case DMA_SLAVE_BUSWIDTH_4_BYTES:
	130	mode = IMX_DMA_MEMSIZE_32;
	131	break;
	132	}
	133	ret = imx_dma_config_channel(imxdmac->imxdma_channel,
	134	mode \| IMX_DMA_TYPE_FIFO,
	135	IMX_DMA_MEMSIZE_32 \| IMX_DMA_TYPE_LINEAR,
	136	imxdmac->dma_request, 1);
	137
	138	if (ret)
	139	return ret;
	140
6584cb88 SH	141	imx_dma_config_burstlen(imxdmac->imxdma_channel,
6584cb88 SH	142	imxdmac->watermark_level * imxdmac->word_size);
1f1846c6 SH	143
	144	return 0;
	145	default:
	146	return -ENOSYS;
	147	}
	148
	149	return -EINVAL;
	150	}
	151
	152	static enum dma_status imxdma_tx_status(struct dma_chan *chan,
	153	dma_cookie_t cookie,
	154	struct dma_tx_state *txstate)
	155	{
96a2af41	156	return dma_cookie_status(chan, cookie, txstate);
1f1846c6 SH	157	}
1f1846c6 SH	158
1f1846c6 SH	159	static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
	160	{
	161	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
	162	dma_cookie_t cookie;
	163
	164	spin_lock_irq(&imxdmac->lock);
	165
884485e1	166	cookie = dma_cookie_assign(tx);
1f1846c6	167
1f1846c6 SH	168	spin_unlock_irq(&imxdmac->lock);
	169
	170	return cookie;
	171	}
	172
	173	static int imxdma_alloc_chan_resources(struct dma_chan *chan)
	174	{
	175	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	176	struct imx_dma_data *data = chan->private;
	177
	178	imxdmac->dma_request = data->dma_request;
	179
	180	dma_async_tx_descriptor_init(&imxdmac->desc, chan);
	181	imxdmac->desc.tx_submit = imxdma_tx_submit;
	182	/* txd.flags will be overwritten in prep funcs */
	183	imxdmac->desc.flags = DMA_CTRL_ACK;
	184
	185	imxdmac->status = DMA_SUCCESS;
	186
	187	return 0;
	188	}
	189
	190	static void imxdma_free_chan_resources(struct dma_chan *chan)
	191	{
	192	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	193
	194	imx_dma_disable(imxdmac->imxdma_channel);
	195
	196	if (imxdmac->sg_list) {
	197	kfree(imxdmac->sg_list);
	198	imxdmac->sg_list = NULL;
	199	}
	200	}
	201
	202	static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
	203	struct dma_chan chan, struct scatterlist sgl,
db8196df	204	unsigned int sg_len, enum dma_transfer_direction direction,
1f1846c6 SH	205	unsigned long flags)
	206	{
	207	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	208	struct scatterlist *sg;
	209	int i, ret, dma_length = 0;
	210	unsigned int dmamode;
	211
	212	if (imxdmac->status == DMA_IN_PROGRESS)
	213	return NULL;
	214
	215	imxdmac->status = DMA_IN_PROGRESS;
	216
	217	for_each_sg(sgl, sg, sg_len, i) {
	218	dma_length += sg->length;
	219	}
	220
db8196df	221	if (direction == DMA_DEV_TO_MEM)
1f1846c6 SH	222	dmamode = DMA_MODE_READ;
	223	else
	224	dmamode = DMA_MODE_WRITE;
	225
d07102a1 SH	226	switch (imxdmac->word_size) {
	227	case DMA_SLAVE_BUSWIDTH_4_BYTES:
	228	if (sgl->length & 3 \|\| sgl->dma_address & 3)
	229	return NULL;
	230	break;
	231	case DMA_SLAVE_BUSWIDTH_2_BYTES:
	232	if (sgl->length & 1 \|\| sgl->dma_address & 1)
	233	return NULL;
	234	break;
	235	case DMA_SLAVE_BUSWIDTH_1_BYTE:
	236	break;
	237	default:
	238	return NULL;
	239	}
	240
1f1846c6 SH	241	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
	242	dma_length, imxdmac->per_address, dmamode);
	243	if (ret)
	244	return NULL;
	245
	246	return &imxdmac->desc;
	247	}
	248
	249	static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
	250	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
db8196df	251	size_t period_len, enum dma_transfer_direction direction)
1f1846c6 SH	252	{
	253	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	254	struct imxdma_engine *imxdma = imxdmac->imxdma;
	255	int i, ret;
	256	unsigned int periods = buf_len / period_len;
	257	unsigned int dmamode;
	258
	259	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
	260	__func__, imxdmac->channel, buf_len, period_len);
	261
	262	if (imxdmac->status == DMA_IN_PROGRESS)
	263	return NULL;
	264	imxdmac->status = DMA_IN_PROGRESS;
	265
	266	ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
	267	imxdma_progression);
	268	if (ret) {
	269	dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
	270	return NULL;
	271	}
	272
	273	if (imxdmac->sg_list)
	274	kfree(imxdmac->sg_list);
	275
	276	imxdmac->sg_list = kcalloc(periods + 1,
	277	sizeof(struct scatterlist), GFP_KERNEL);
	278	if (!imxdmac->sg_list)
	279	return NULL;
	280
	281	sg_init_table(imxdmac->sg_list, periods);
	282
	283	for (i = 0; i < periods; i++) {
	284	imxdmac->sg_list[i].page_link = 0;
	285	imxdmac->sg_list[i].offset = 0;
	286	imxdmac->sg_list[i].dma_address = dma_addr;
	287	imxdmac->sg_list[i].length = period_len;
	288	dma_addr += period_len;
	289	}
	290
	291	/* close the loop */
	292	imxdmac->sg_list[periods].offset = 0;
	293	imxdmac->sg_list[periods].length = 0;
	294	imxdmac->sg_list[periods].page_link =
	295	((unsigned long)imxdmac->sg_list \| 0x01) & ~0x02;
	296
db8196df	297	if (direction == DMA_DEV_TO_MEM)
1f1846c6 SH	298	dmamode = DMA_MODE_READ;
	299	else
	300	dmamode = DMA_MODE_WRITE;
	301
	302	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
	303	IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
	304	if (ret)
	305	return NULL;
	306
	307	return &imxdmac->desc;
	308	}
	309
	310	static void imxdma_issue_pending(struct dma_chan *chan)
	311	{
5b316876 SH	312	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	313
	314	if (imxdmac->status == DMA_IN_PROGRESS)
	315	imx_dma_enable(imxdmac->imxdma_channel);
1f1846c6 SH	316	}
	317
	318	static int __init imxdma_probe(struct platform_device *pdev)
	319	{
	320	struct imxdma_engine *imxdma;
	321	int ret, i;
	322
	323	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
	324	if (!imxdma)
	325	return -ENOMEM;
	326
	327	INIT_LIST_HEAD(&imxdma->dma_device.channels);
	328
f8a356ff SH	329	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	330	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
	331
1f1846c6 SH	332	/* Initialize channel parameters */
	333	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
	334	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	335
	336	imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
	337	DMA_PRIO_MEDIUM);
8267f16e SH	338	if ((int)imxdmac->channel < 0) {
8267f16e SH	339	ret = -ENODEV;
1f1846c6	340	goto err_init;
8267f16e	341	}
1f1846c6 SH	342
	343	imx_dma_setup_handlers(imxdmac->imxdma_channel,
	344	imxdma_irq_handler, imxdma_err_handler, imxdmac);
	345
	346	imxdmac->imxdma = imxdma;
	347	spin_lock_init(&imxdmac->lock);
	348
1f1846c6	349	imxdmac->chan.device = &imxdma->dma_device;
1f1846c6 SH	350	imxdmac->channel = i;
	351
	352	/* Add the channel to the DMAC list */
	353	list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
	354	}
	355
	356	imxdma->dev = &pdev->dev;
	357	imxdma->dma_device.dev = &pdev->dev;
	358
	359	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	360	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	361	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	362	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	363	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
	364	imxdma->dma_device.device_control = imxdma_control;
	365	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
	366
	367	platform_set_drvdata(pdev, imxdma);
	368
1e070a60 SH	369	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	370	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
	371
1f1846c6 SH	372	ret = dma_async_device_register(&imxdma->dma_device);
	373	if (ret) {
	374	dev_err(&pdev->dev, "unable to register\n");
	375	goto err_init;
	376	}
	377
	378	return 0;
	379
	380	err_init:
cbeae418	381	while (--i >= 0) {
1f1846c6 SH	382	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	383	imx_dma_free(imxdmac->imxdma_channel);
	384	}
	385
	386	kfree(imxdma);
	387	return ret;
	388	}
	389
	390	static int __exit imxdma_remove(struct platform_device *pdev)
	391	{
	392	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
	393	int i;
	394
	395	dma_async_device_unregister(&imxdma->dma_device);
	396
	397	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
	398	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	399
	400	imx_dma_free(imxdmac->imxdma_channel);
	401	}
	402
	403	kfree(imxdma);
	404
	405	return 0;
	406	}
	407
	408	static struct platform_driver imxdma_driver = {
	409	.driver = {
	410	.name = "imx-dma",
	411	},
	412	.remove = __exit_p(imxdma_remove),
	413	};
	414
	415	static int __init imxdma_module_init(void)
	416	{
	417	return platform_driver_probe(&imxdma_driver, imxdma_probe);
	418	}
	419	subsys_initcall(imxdma_module_init);
	420
	421	MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
	422	MODULE_DESCRIPTION("i.MX dma driver");
	423	MODULE_LICENSE("GPL");