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dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[deliverable/linux.git] / drivers / dma / imx-dma.c
CommitLineData
1f1846c6
SH		 1/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9e15db7c 8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
1f1846c6
SH		 9 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17#include <linux/init.h>
f8de8f4c 18#include <linux/module.h>
1f1846c6
SH		 19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
6bd08127 27#include <linux/clk.h>
1f1846c6 28#include <linux/dmaengine.h>
5170c051 29#include <linux/module.h>
1f1846c6
SH		 30
31#include <asm/irq.h>
6bd08127 32#include <mach/dma.h>
1f1846c6
SH		 33#include <mach/hardware.h>
34
d2ebfb33 35#include "dmaengine.h"
9e15db7c 36#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
6bd08127
JM		 37#define IMX_DMA_CHANNELS 16
38
6bd08127
JM		 39#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
40#define IMX_DMA_MEMSIZE_32 (0 << 4)
41#define IMX_DMA_MEMSIZE_8 (1 << 4)
42#define IMX_DMA_MEMSIZE_16 (2 << 4)
43#define IMX_DMA_TYPE_LINEAR (0 << 10)
44#define IMX_DMA_TYPE_2D (1 << 10)
45#define IMX_DMA_TYPE_FIFO (2 << 10)
46
47#define IMX_DMA_ERR_BURST (1 << 0)
48#define IMX_DMA_ERR_REQUEST (1 << 1)
49#define IMX_DMA_ERR_TRANSFER (1 << 2)
50#define IMX_DMA_ERR_BUFFER (1 << 3)
51#define IMX_DMA_ERR_TIMEOUT (1 << 4)
52
53#define DMA_DCR 0x00 /* Control Register */
54#define DMA_DISR 0x04 /* Interrupt status Register */
55#define DMA_DIMR 0x08 /* Interrupt mask Register */
56#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
57#define DMA_DRTOSR 0x10 /* Request timeout Register */
58#define DMA_DSESR 0x14 /* Transfer Error Status Register */
59#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
60#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
61#define DMA_WSRA 0x40 /* W-Size Register A */
62#define DMA_XSRA 0x44 /* X-Size Register A */
63#define DMA_YSRA 0x48 /* Y-Size Register A */
64#define DMA_WSRB 0x4c /* W-Size Register B */
65#define DMA_XSRB 0x50 /* X-Size Register B */
66#define DMA_YSRB 0x54 /* Y-Size Register B */
67#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
68#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
69#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
70#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
71#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
72#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
73#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
74#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
75#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
76
77#define DCR_DRST (1<<1)
78#define DCR_DEN (1<<0)
79#define DBTOCR_EN (1<<15)
80#define DBTOCR_CNT(x) ((x) & 0x7fff)
81#define CNTR_CNT(x) ((x) & 0xffffff)
82#define CCR_ACRPT (1<<14)
83#define CCR_DMOD_LINEAR (0x0 << 12)
84#define CCR_DMOD_2D (0x1 << 12)
85#define CCR_DMOD_FIFO (0x2 << 12)
86#define CCR_DMOD_EOBFIFO (0x3 << 12)
87#define CCR_SMOD_LINEAR (0x0 << 10)
88#define CCR_SMOD_2D (0x1 << 10)
89#define CCR_SMOD_FIFO (0x2 << 10)
90#define CCR_SMOD_EOBFIFO (0x3 << 10)
91#define CCR_MDIR_DEC (1<<9)
92#define CCR_MSEL_B (1<<8)
93#define CCR_DSIZ_32 (0x0 << 6)
94#define CCR_DSIZ_8 (0x1 << 6)
95#define CCR_DSIZ_16 (0x2 << 6)
96#define CCR_SSIZ_32 (0x0 << 4)
97#define CCR_SSIZ_8 (0x1 << 4)
98#define CCR_SSIZ_16 (0x2 << 4)
99#define CCR_REN (1<<3)
100#define CCR_RPT (1<<2)
101#define CCR_FRC (1<<1)
102#define CCR_CEN (1<<0)
103#define RTOR_EN (1<<15)
104#define RTOR_CLK (1<<14)
105#define RTOR_PSC (1<<13)
9e15db7c
JM		 106
107enum imxdma_prep_type {
108 IMXDMA_DESC_MEMCPY,
109 IMXDMA_DESC_INTERLEAVED,
110 IMXDMA_DESC_SLAVE_SG,
111 IMXDMA_DESC_CYCLIC,
112};
113
6bd08127
JM		 114/*
115 * struct imxdma_channel_internal - i.MX specific DMA extension
116 * @name: name specified by DMA client
117 * @irq_handler: client callback for end of transfer
118 * @err_handler: client callback for error condition
119 * @data: clients context data for callbacks
120 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
121 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
122 * @resbytes: total residual number of bytes to transfer
123 * (it can be lower or same as sum of SG mapped chunk sizes)
124 * @sgcount: number of chunks to be read/written
125 *
126 * Structure is used for IMX DMA processing. It would be probably good
127 * @struct dma_struct in the future for external interfacing and use
128 * @struct imxdma_channel_internal only as extension to it.
129 */
130
131struct imxdma_channel_internal {
6bd08127
JM		 132 struct scatterlist *sg;
133 unsigned int resbytes;
134
135 int in_use;
136
137 u32 ccr_from_device;
138 u32 ccr_to_device;
139
140 struct timer_list watchdog;
141
142 int hw_chaining;
143};
144
9e15db7c
JM		 145struct imxdma_desc {
146 struct list_head node;
147 struct dma_async_tx_descriptor desc;
148 enum dma_status status;
149 dma_addr_t src;
150 dma_addr_t dest;
151 size_t len;
2efc3449 152 enum dma_transfer_direction direction;
9e15db7c
JM		 153 enum imxdma_prep_type type;
154 /* For memcpy and interleaved */
155 unsigned int config_port;
156 unsigned int config_mem;
157 /* For interleaved transfers */
158 unsigned int x;
159 unsigned int y;
160 unsigned int w;
161 /* For slave sg and cyclic */
162 struct scatterlist *sg;
163 unsigned int sgcount;
164};
165
1f1846c6 166struct imxdma_channel {
6bd08127 167 struct imxdma_channel_internal internal;
1f1846c6
SH		 168 struct imxdma_engine *imxdma;
169 unsigned int channel;
1f1846c6 170
9e15db7c
JM		 171 struct tasklet_struct dma_tasklet;
172 struct list_head ld_free;
173 struct list_head ld_queue;
174 struct list_head ld_active;
175 int descs_allocated;
1f1846c6
SH		 176 enum dma_slave_buswidth word_size;
177 dma_addr_t per_address;
178 u32 watermark_level;
179 struct dma_chan chan;
180 spinlock_t lock;
181 struct dma_async_tx_descriptor desc;
1f1846c6
SH		 182 enum dma_status status;
183 int dma_request;
184 struct scatterlist *sg_list;
185};
186
1f1846c6
SH		 187struct imxdma_engine {
188 struct device *dev;
1e070a60 189 struct device_dma_parameters dma_parms;
1f1846c6 190 struct dma_device dma_device;
6bd08127 191 struct imxdma_channel channel[IMX_DMA_CHANNELS];
1f1846c6
SH		 192};
193
194static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
195{
196 return container_of(chan, struct imxdma_channel, chan);
197}
198
9e15db7c 199static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
1f1846c6 200{
9e15db7c
JM		 201 struct imxdma_desc *desc;
202
203 if (!list_empty(&imxdmac->ld_active)) {
204 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
205 node);
206 if (desc->type == IMXDMA_DESC_CYCLIC)
207 return true;
208 }
209 return false;
1f1846c6
SH		 210}
211
6bd08127
JM		 212/* TODO: put this inside any struct */
213static void __iomem *imx_dmav1_baseaddr;
214static struct clk *dma_clk;
215
216static void imx_dmav1_writel(unsigned val, unsigned offset)
217{
218 __raw_writel(val, imx_dmav1_baseaddr + offset);
219}
220
221static unsigned imx_dmav1_readl(unsigned offset)
1f1846c6 222{
6bd08127
JM		 223 return __raw_readl(imx_dmav1_baseaddr + offset);
224}
1f1846c6 225
6bd08127
JM		 226static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
227{
228 if (cpu_is_mx27())
229 return imxdma->hw_chaining;
230 else
231 return 0;
232}
233
234/*
235 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
236 */
2efc3449 237static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
6bd08127 238{
2efc3449 239 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 240 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
241 unsigned long now;
242
243 now = min(imxdma->resbytes, sg->length);
244 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
245 imxdma->resbytes -= now;
246
2efc3449 247 if (d->direction == DMA_DEV_TO_MEM)
6bd08127
JM		 248 imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
249 else
250 imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
251
252 imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
253
254 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
255 "size 0x%08x\n", imxdmac->channel,
256 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
257 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
258 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
259
260 return now;
261}
262
2efc3449 263static void imxdma_enable_hw(struct imxdma_desc *d)
6bd08127 264{
2efc3449 265 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 266 int channel = imxdmac->channel;
267 unsigned long flags;
268
269 pr_debug("imxdma%d: imx_dma_enable\n", channel);
270
271 if (imxdmac->internal.in_use)
272 return;
273
274 local_irq_save(flags);
275
276 imx_dmav1_writel(1 << channel, DMA_DISR);
277 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
278 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
279 CCR_ACRPT, DMA_CCR(channel));
280
281 if ((cpu_is_mx21() || cpu_is_mx27()) &&
282 imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
283 imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
284 if (imxdmac->internal.sg) {
285 u32 tmp;
2efc3449 286 imxdma_sg_next(d, imxdmac->internal.sg);
6bd08127
JM		 287 tmp = imx_dmav1_readl(DMA_CCR(channel));
288 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
289 DMA_CCR(channel));
290 }
291 }
292 imxdmac->internal.in_use = 1;
293
294 local_irq_restore(flags);
295}
296
297static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
298{
299 int channel = imxdmac->channel;
300 unsigned long flags;
301
302 pr_debug("imxdma%d: imx_dma_disable\n", channel);
303
304 if (imxdma_hw_chain(&imxdmac->internal))
305 del_timer(&imxdmac->internal.watchdog);
306
307 local_irq_save(flags);
308 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
309 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
310 DMA_CCR(channel));
311 imx_dmav1_writel(1 << channel, DMA_DISR);
312 imxdmac->internal.in_use = 0;
313 local_irq_restore(flags);
314}
315
316static int
317imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
318 unsigned int config_mem, unsigned int dmareq, int hw_chaining)
319{
320 int channel = imxdmac->channel;
321 u32 dreq = 0;
322
323 imxdmac->internal.hw_chaining = 0;
324
325 if (hw_chaining) {
326 imxdmac->internal.hw_chaining = 1;
327 if (!imxdma_hw_chain(&imxdmac->internal))
328 return -EINVAL;
329 }
330
331 if (dmareq)
332 dreq = CCR_REN;
333
334 imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
335 imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
336
337 imx_dmav1_writel(dmareq, DMA_RSSR(channel));
338
339 return 0;
340}
341
342static int
2efc3449 343imxdma_setup_sg_hw(struct imxdma_desc *d,
6bd08127
JM		 344 struct scatterlist *sg, unsigned int sgcount,
345 unsigned int dma_length, unsigned int dev_addr,
2efc3449 346 enum dma_transfer_direction direction)
6bd08127 347{
2efc3449 348 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 349 int channel = imxdmac->channel;
350
351 if (imxdmac->internal.in_use)
352 return -EBUSY;
353
354 imxdmac->internal.sg = sg;
6bd08127
JM		 355 imxdmac->internal.resbytes = dma_length;
356
357 if (!sg || !sgcount) {
358 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
359 channel);
360 return -EINVAL;
361 }
362
363 if (!sg->length) {
364 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
365 channel);
366 return -EINVAL;
367 }
368
2efc3449 369 if (direction == DMA_DEV_TO_MEM) {
6bd08127
JM		 370 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
371 "dev_addr=0x%08x for read\n",
372 channel, __func__, sg, sgcount, dma_length, dev_addr);
373
374 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
375 imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
2efc3449 376 } else if (direction == DMA_MEM_TO_DEV) {
6bd08127
JM		 377 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
378 "dev_addr=0x%08x for write\n",
379 channel, __func__, sg, sgcount, dma_length, dev_addr);
380
381 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
382 imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
383 } else {
384 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
385 channel);
386 return -EINVAL;
387 }
388
2efc3449 389 imxdma_sg_next(d, sg);
6bd08127
JM		 390
391 return 0;
1f1846c6
SH		 392}
393
6bd08127 394static void imxdma_watchdog(unsigned long data)
1f1846c6 395{
6bd08127
JM		 396 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
397 int channel = imxdmac->channel;
1f1846c6 398
6bd08127
JM		 399 imx_dmav1_writel(0, DMA_CCR(channel));
400 imxdmac->internal.in_use = 0;
401 imxdmac->internal.sg = NULL;
402
403 /* Tasklet watchdog error handler */
9e15db7c 404 tasklet_schedule(&imxdmac->dma_tasklet);
6bd08127
JM		 405 pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
406}
407
408static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
409{
410 struct imxdma_engine *imxdma = dev_id;
411 struct imxdma_channel_internal *internal;
412 unsigned int err_mask;
413 int i, disr;
414 int errcode;
415
416 disr = imx_dmav1_readl(DMA_DISR);
417
418 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
419 imx_dmav1_readl(DMA_DRTOSR) |
420 imx_dmav1_readl(DMA_DSESR) |
421 imx_dmav1_readl(DMA_DBOSR);
422
423 if (!err_mask)
424 return IRQ_HANDLED;
425
426 imx_dmav1_writel(disr & err_mask, DMA_DISR);
427
428 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
429 if (!(err_mask & (1 << i)))
430 continue;
431 internal = &imxdma->channel[i].internal;
432 errcode = 0;
433
434 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
435 imx_dmav1_writel(1 << i, DMA_DBTOSR);
436 errcode |= IMX_DMA_ERR_BURST;
437 }
438 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
439 imx_dmav1_writel(1 << i, DMA_DRTOSR);
440 errcode |= IMX_DMA_ERR_REQUEST;
441 }
442 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
443 imx_dmav1_writel(1 << i, DMA_DSESR);
444 errcode |= IMX_DMA_ERR_TRANSFER;
445 }
446 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
447 imx_dmav1_writel(1 << i, DMA_DBOSR);
448 errcode |= IMX_DMA_ERR_BUFFER;
449 }
450 /* Tasklet error handler */
451 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
452
453 printk(KERN_WARNING
454 "DMA timeout on channel %d -%s%s%s%s\n", i,
455 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
456 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
457 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
458 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
459 }
460 return IRQ_HANDLED;
1f1846c6
SH		 461}
462
6bd08127 463static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
1f1846c6 464{
6bd08127
JM		 465 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
466 int chno = imxdmac->channel;
2efc3449 467 struct imxdma_desc *desc;
6bd08127
JM		 468
469 if (imxdma->sg) {
470 u32 tmp;
471 imxdma->sg = sg_next(imxdma->sg);
472
473 if (imxdma->sg) {
2efc3449
JM		 474
475 spin_lock(&imxdmac->lock);
476 if (list_empty(&imxdmac->ld_active)) {
477 spin_unlock(&imxdmac->lock);
478 goto out;
479 }
480
481 desc = list_first_entry(&imxdmac->ld_active,
482 struct imxdma_desc,
483 node);
484 spin_unlock(&imxdmac->lock);
485
486 imxdma_sg_next(desc, imxdma->sg);
6bd08127
JM		 487
488 tmp = imx_dmav1_readl(DMA_CCR(chno));
489
490 if (imxdma_hw_chain(imxdma)) {
491 /* FIXME: The timeout should probably be
492 * configurable
493 */
494 mod_timer(&imxdma->watchdog,
495 jiffies + msecs_to_jiffies(500));
496
497 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
498 imx_dmav1_writel(tmp, DMA_CCR(chno));
499 } else {
500 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
501 tmp |= CCR_CEN;
502 }
503
504 imx_dmav1_writel(tmp, DMA_CCR(chno));
505
506 if (imxdma_chan_is_doing_cyclic(imxdmac))
507 /* Tasklet progression */
508 tasklet_schedule(&imxdmac->dma_tasklet);
1f1846c6 509
6bd08127
JM		 510 return;
511 }
512
513 if (imxdma_hw_chain(imxdma)) {
514 del_timer(&imxdma->watchdog);
515 return;
516 }
517 }
518
2efc3449 519out:
6bd08127
JM		 520 imx_dmav1_writel(0, DMA_CCR(chno));
521 imxdma->in_use = 0;
522 /* Tasklet irq */
9e15db7c
JM		 523 tasklet_schedule(&imxdmac->dma_tasklet);
524}
525
6bd08127
JM		 526static irqreturn_t dma_irq_handler(int irq, void *dev_id)
527{
528 struct imxdma_engine *imxdma = dev_id;
529 struct imxdma_channel_internal *internal;
530 int i, disr;
531
532 if (cpu_is_mx21() || cpu_is_mx27())
533 imxdma_err_handler(irq, dev_id);
534
535 disr = imx_dmav1_readl(DMA_DISR);
536
537 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
538 disr);
539
540 imx_dmav1_writel(disr, DMA_DISR);
541 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
542 if (disr & (1 << i)) {
543 internal = &imxdma->channel[i].internal;
544 dma_irq_handle_channel(&imxdma->channel[i]);
545 }
546 }
547
548 return IRQ_HANDLED;
549}
550
9e15db7c
JM		 551static int imxdma_xfer_desc(struct imxdma_desc *d)
552{
553 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
3b4b6dfc 554 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c
JM		 555 int ret;
556
557 /* Configure and enable */
558 switch (d->type) {
559 case IMXDMA_DESC_MEMCPY:
3b4b6dfc
JM		 560 imxdmac->internal.sg = NULL;
561
562 imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
563 imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
564 imx_dmav1_writel(d->config_mem | (d->config_port << 2),
565 DMA_CCR(imxdmac->channel));
6bd08127 566
3b4b6dfc
JM		 567 imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
568
569 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
570 "dma_length=%d\n", __func__, imxdmac->channel,
571 d->dest, d->src, d->len);
572
573 break;
6bd08127 574 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
9e15db7c 575 case IMXDMA_DESC_CYCLIC:
9e15db7c 576 case IMXDMA_DESC_SLAVE_SG:
2efc3449
JM		 577 ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
578 imxdmac->per_address, d->direction);
9e15db7c
JM		 579 if (ret < 0)
580 return ret;
581 break;
582 default:
583 return -EINVAL;
584 }
2efc3449 585 imxdma_enable_hw(d);
9e15db7c
JM		 586 return 0;
587}
588
589static void imxdma_tasklet(unsigned long data)
590{
591 struct imxdma_channel *imxdmac = (void *)data;
592 struct imxdma_engine *imxdma = imxdmac->imxdma;
593 struct imxdma_desc *desc;
594
595 spin_lock(&imxdmac->lock);
596
597 if (list_empty(&imxdmac->ld_active)) {
598 /* Someone might have called terminate all */
599 goto out;
600 }
601 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
602
603 if (desc->desc.callback)
604 desc->desc.callback(desc->desc.callback_param);
605
1f3d6dc0 606 dma_cookie_complete(&desc->desc);
9e15db7c
JM		 607
608 /* If we are dealing with a cyclic descriptor keep it on ld_active */
609 if (imxdma_chan_is_doing_cyclic(imxdmac))
610 goto out;
611
612 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
613
614 if (!list_empty(&imxdmac->ld_queue)) {
615 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
616 node);
617 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
618 if (imxdma_xfer_desc(desc) < 0)
619 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
620 __func__, imxdmac->channel);
621 }
622out:
623 spin_unlock(&imxdmac->lock);
1f1846c6
SH		 624}
625
626static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
627 unsigned long arg)
628{
629 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
630 struct dma_slave_config *dmaengine_cfg = (void *)arg;
631 int ret;
9e15db7c 632 unsigned long flags;
1f1846c6
SH		 633 unsigned int mode = 0;
634
635 switch (cmd) {
636 case DMA_TERMINATE_ALL:
6bd08127 637 imxdma_disable_hw(imxdmac);
9e15db7c
JM		 638
639 spin_lock_irqsave(&imxdmac->lock, flags);
640 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
641 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
642 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 643 return 0;
644 case DMA_SLAVE_CONFIG:
db8196df 645 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1f1846c6
SH		 646 imxdmac->per_address = dmaengine_cfg->src_addr;
647 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
648 imxdmac->word_size = dmaengine_cfg->src_addr_width;
649 } else {
650 imxdmac->per_address = dmaengine_cfg->dst_addr;
651 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
652 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
653 }
654
655 switch (imxdmac->word_size) {
656 case DMA_SLAVE_BUSWIDTH_1_BYTE:
657 mode = IMX_DMA_MEMSIZE_8;
658 break;
659 case DMA_SLAVE_BUSWIDTH_2_BYTES:
660 mode = IMX_DMA_MEMSIZE_16;
661 break;
662 default:
663 case DMA_SLAVE_BUSWIDTH_4_BYTES:
664 mode = IMX_DMA_MEMSIZE_32;
665 break;
666 }
6bd08127 667 ret = imxdma_config_channel_hw(imxdmac,
1f1846c6
SH		 668 mode | IMX_DMA_TYPE_FIFO,
669 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
670 imxdmac->dma_request, 1);
671
672 if (ret)
673 return ret;
6bd08127
JM		 674 /* Set burst length */
675 imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
676 DMA_BLR(imxdmac->channel));
1f1846c6
SH		 677
678 return 0;
679 default:
680 return -ENOSYS;
681 }
682
683 return -EINVAL;
684}
685
686static enum dma_status imxdma_tx_status(struct dma_chan *chan,
687 dma_cookie_t cookie,
688 struct dma_tx_state *txstate)
689{
96a2af41 690 return dma_cookie_status(chan, cookie, txstate);
1f1846c6
SH		 691}
692
693static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
694{
695 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
696 dma_cookie_t cookie;
9e15db7c 697 unsigned long flags;
1f1846c6 698
9e15db7c 699 spin_lock_irqsave(&imxdmac->lock, flags);
884485e1 700 cookie = dma_cookie_assign(tx);
9e15db7c 701 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 702
703 return cookie;
704}
705
706static int imxdma_alloc_chan_resources(struct dma_chan *chan)
707{
708 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
709 struct imx_dma_data *data = chan->private;
710
6c05f091
JM		 711 if (data != NULL)
712 imxdmac->dma_request = data->dma_request;
1f1846c6 713
9e15db7c
JM		 714 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
715 struct imxdma_desc *desc;
1f1846c6 716
9e15db7c
JM		 717 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
718 if (!desc)
719 break;
720 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
721 dma_async_tx_descriptor_init(&desc->desc, chan);
722 desc->desc.tx_submit = imxdma_tx_submit;
723 /* txd.flags will be overwritten in prep funcs */
724 desc->desc.flags = DMA_CTRL_ACK;
725 desc->status = DMA_SUCCESS;
726
727 list_add_tail(&desc->node, &imxdmac->ld_free);
728 imxdmac->descs_allocated++;
729 }
1f1846c6 730
9e15db7c
JM		 731 if (!imxdmac->descs_allocated)
732 return -ENOMEM;
733
734 return imxdmac->descs_allocated;
1f1846c6
SH		 735}
736
737static void imxdma_free_chan_resources(struct dma_chan *chan)
738{
739 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
9e15db7c
JM		 740 struct imxdma_desc *desc, *_desc;
741 unsigned long flags;
742
743 spin_lock_irqsave(&imxdmac->lock, flags);
1f1846c6 744
6bd08127 745 imxdma_disable_hw(imxdmac);
9e15db7c
JM		 746 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
747 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
748
749 spin_unlock_irqrestore(&imxdmac->lock, flags);
750
751 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
752 kfree(desc);
753 imxdmac->descs_allocated--;
754 }
755 INIT_LIST_HEAD(&imxdmac->ld_free);
1f1846c6
SH		 756
757 if (imxdmac->sg_list) {
758 kfree(imxdmac->sg_list);
759 imxdmac->sg_list = NULL;
760 }
761}
762
763static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
764 struct dma_chan *chan, struct scatterlist *sgl,
db8196df 765 unsigned int sg_len, enum dma_transfer_direction direction,
185ecb5f 766 unsigned long flags, void *context)
1f1846c6
SH		 767{
768 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
769 struct scatterlist *sg;
9e15db7c
JM		 770 int i, dma_length = 0;
771 struct imxdma_desc *desc;
1f1846c6 772
9e15db7c
JM		 773 if (list_empty(&imxdmac->ld_free) ||
774 imxdma_chan_is_doing_cyclic(imxdmac))
1f1846c6
SH		 775 return NULL;
776
9e15db7c 777 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
1f1846c6
SH		 778
779 for_each_sg(sgl, sg, sg_len, i) {
780 dma_length += sg->length;
781 }
782
d07102a1
SH		 783 switch (imxdmac->word_size) {
784 case DMA_SLAVE_BUSWIDTH_4_BYTES:
785 if (sgl->length & 3 || sgl->dma_address & 3)
786 return NULL;
787 break;
788 case DMA_SLAVE_BUSWIDTH_2_BYTES:
789 if (sgl->length & 1 || sgl->dma_address & 1)
790 return NULL;
791 break;
792 case DMA_SLAVE_BUSWIDTH_1_BYTE:
793 break;
794 default:
795 return NULL;
796 }
797
9e15db7c
JM		 798 desc->type = IMXDMA_DESC_SLAVE_SG;
799 desc->sg = sgl;
800 desc->sgcount = sg_len;
801 desc->len = dma_length;
2efc3449 802 desc->direction = direction;
9e15db7c 803 if (direction == DMA_DEV_TO_MEM) {
9e15db7c
JM		 804 desc->src = imxdmac->per_address;
805 } else {
9e15db7c
JM		 806 desc->dest = imxdmac->per_address;
807 }
808 desc->desc.callback = NULL;
809 desc->desc.callback_param = NULL;
1f1846c6 810
9e15db7c 811 return &desc->desc;
1f1846c6
SH		 812}
813
814static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
815 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
185ecb5f
AB		 816 size_t period_len, enum dma_transfer_direction direction,
817 void *context)
1f1846c6
SH		 818{
819 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
820 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c
JM		 821 struct imxdma_desc *desc;
822 int i;
1f1846c6 823 unsigned int periods = buf_len / period_len;
1f1846c6
SH		 824
825 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
826 __func__, imxdmac->channel, buf_len, period_len);
827
9e15db7c
JM		 828 if (list_empty(&imxdmac->ld_free) ||
829 imxdma_chan_is_doing_cyclic(imxdmac))
1f1846c6 830 return NULL;
1f1846c6 831
9e15db7c 832 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
1f1846c6
SH		 833
834 if (imxdmac->sg_list)
835 kfree(imxdmac->sg_list);
836
837 imxdmac->sg_list = kcalloc(periods + 1,
838 sizeof(struct scatterlist), GFP_KERNEL);
839 if (!imxdmac->sg_list)
840 return NULL;
841
842 sg_init_table(imxdmac->sg_list, periods);
843
844 for (i = 0; i < periods; i++) {
845 imxdmac->sg_list[i].page_link = 0;
846 imxdmac->sg_list[i].offset = 0;
847 imxdmac->sg_list[i].dma_address = dma_addr;
848 imxdmac->sg_list[i].length = period_len;
849 dma_addr += period_len;
850 }
851
852 /* close the loop */
853 imxdmac->sg_list[periods].offset = 0;
854 imxdmac->sg_list[periods].length = 0;
855 imxdmac->sg_list[periods].page_link =
856 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
857
9e15db7c
JM		 858 desc->type = IMXDMA_DESC_CYCLIC;
859 desc->sg = imxdmac->sg_list;
860 desc->sgcount = periods;
861 desc->len = IMX_DMA_LENGTH_LOOP;
2efc3449 862 desc->direction = direction;
9e15db7c 863 if (direction == DMA_DEV_TO_MEM) {
9e15db7c
JM		 864 desc->src = imxdmac->per_address;
865 } else {
9e15db7c
JM		 866 desc->dest = imxdmac->per_address;
867 }
868 desc->desc.callback = NULL;
869 desc->desc.callback_param = NULL;
1f1846c6 870
9e15db7c 871 return &desc->desc;
1f1846c6
SH		 872}
873
6c05f091
JM		 874static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
875 struct dma_chan *chan, dma_addr_t dest,
876 dma_addr_t src, size_t len, unsigned long flags)
877{
878 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
879 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c 880 struct imxdma_desc *desc;
6c05f091
JM		 881
882 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
883 __func__, imxdmac->channel, src, dest, len);
884
9e15db7c
JM		 885 if (list_empty(&imxdmac->ld_free) ||
886 imxdma_chan_is_doing_cyclic(imxdmac))
6c05f091 887 return NULL;
6c05f091 888
9e15db7c 889 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
6c05f091 890
9e15db7c
JM		 891 desc->type = IMXDMA_DESC_MEMCPY;
892 desc->src = src;
893 desc->dest = dest;
894 desc->len = len;
2efc3449 895 desc->direction = DMA_MEM_TO_MEM;
9e15db7c
JM		 896 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
897 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
898 desc->desc.callback = NULL;
899 desc->desc.callback_param = NULL;
6c05f091 900
9e15db7c 901 return &desc->desc;
6c05f091
JM		 902}
903
1f1846c6
SH		 904static void imxdma_issue_pending(struct dma_chan *chan)
905{
5b316876 906 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
9e15db7c
JM		 907 struct imxdma_engine *imxdma = imxdmac->imxdma;
908 struct imxdma_desc *desc;
909 unsigned long flags;
910
911 spin_lock_irqsave(&imxdmac->lock, flags);
912 if (list_empty(&imxdmac->ld_active) &&
913 !list_empty(&imxdmac->ld_queue)) {
914 desc = list_first_entry(&imxdmac->ld_queue,
915 struct imxdma_desc, node);
916
917 if (imxdma_xfer_desc(desc) < 0) {
918 dev_warn(imxdma->dev,
919 "%s: channel: %d couldn't issue DMA xfer\n",
920 __func__, imxdmac->channel);
921 } else {
922 list_move_tail(imxdmac->ld_queue.next,
923 &imxdmac->ld_active);
924 }
925 }
926 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 927}
928
929static int __init imxdma_probe(struct platform_device *pdev)
6bd08127 930 {
1f1846c6
SH		 931 struct imxdma_engine *imxdma;
932 int ret, i;
933
6bd08127
JM		 934 if (cpu_is_mx1())
935 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
936 else if (cpu_is_mx21())
937 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
938 else if (cpu_is_mx27())
939 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
940 else
941 return 0;
942
943 dma_clk = clk_get(NULL, "dma");
944 if (IS_ERR(dma_clk))
945 return PTR_ERR(dma_clk);
946 clk_enable(dma_clk);
947
948 /* reset DMA module */
949 imx_dmav1_writel(DCR_DRST, DMA_DCR);
950
951 if (cpu_is_mx1()) {
952 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
953 if (ret) {
954 pr_crit("Can't register IRQ for DMA\n");
955 return ret;
956 }
957
958 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
959 if (ret) {
960 pr_crit("Can't register ERRIRQ for DMA\n");
961 free_irq(MX1_DMA_INT, NULL);
962 return ret;
963 }
964 }
965
966 /* enable DMA module */
967 imx_dmav1_writel(DCR_DEN, DMA_DCR);
968
969 /* clear all interrupts */
970 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
971
972 /* disable interrupts */
973 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
974
1f1846c6
SH		 975 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
976 if (!imxdma)
977 return -ENOMEM;
978
979 INIT_LIST_HEAD(&imxdma->dma_device.channels);
980
f8a356ff
SH		 981 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
982 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
6c05f091 983 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
f8a356ff 984
1f1846c6 985 /* Initialize channel parameters */
6bd08127 986 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1f1846c6 987 struct imxdma_channel *imxdmac = &imxdma->channel[i];
6bd08127
JM		 988 memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
989 if (cpu_is_mx21() || cpu_is_mx27()) {
990 ret = request_irq(MX2x_INT_DMACH0 + i,
991 dma_irq_handler, 0, "DMA", imxdma);
992 if (ret) {
993 pr_crit("Can't register IRQ %d for DMA channel %d\n",
994 MX2x_INT_DMACH0 + i, i);
995 goto err_init;
996 }
997 init_timer(&imxdmac->internal.watchdog);
998 imxdmac->internal.watchdog.function = &imxdma_watchdog;
999 imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
8267f16e 1000 }
1f1846c6 1001
1f1846c6
SH		 1002 imxdmac->imxdma = imxdma;
1003 spin_lock_init(&imxdmac->lock);
1004
9e15db7c
JM		 1005 INIT_LIST_HEAD(&imxdmac->ld_queue);
1006 INIT_LIST_HEAD(&imxdmac->ld_free);
1007 INIT_LIST_HEAD(&imxdmac->ld_active);
1008
1009 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1010 (unsigned long)imxdmac);
1f1846c6 1011 imxdmac->chan.device = &imxdma->dma_device;
8ac69546 1012 dma_cookie_init(&imxdmac->chan);
1f1846c6
SH		 1013 imxdmac->channel = i;
1014
1015 /* Add the channel to the DMAC list */
9e15db7c
JM		 1016 list_add_tail(&imxdmac->chan.device_node,
1017 &imxdma->dma_device.channels);
1f1846c6
SH		 1018 }
1019
1020 imxdma->dev = &pdev->dev;
1021 imxdma->dma_device.dev = &pdev->dev;
1022
1023 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1024 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1025 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1026 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1027 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
6c05f091 1028 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1f1846c6
SH		 1029 imxdma->dma_device.device_control = imxdma_control;
1030 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1031
1032 platform_set_drvdata(pdev, imxdma);
1033
6c05f091 1034 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1e070a60
SH		 1035 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1036 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1037
1f1846c6
SH		 1038 ret = dma_async_device_register(&imxdma->dma_device);
1039 if (ret) {
1040 dev_err(&pdev->dev, "unable to register\n");
1041 goto err_init;
1042 }
1043
1044 return 0;
1045
1046err_init:
6bd08127
JM		 1047
1048 if (cpu_is_mx21() || cpu_is_mx27()) {
1049 while (--i >= 0)
1050 free_irq(MX2x_INT_DMACH0 + i, NULL);
1051 } else if cpu_is_mx1() {
1052 free_irq(MX1_DMA_INT, NULL);
1053 free_irq(MX1_DMA_ERR, NULL);
1f1846c6
SH		 1054 }
1055
1056 kfree(imxdma);
1057 return ret;
1058}
1059
1060static int __exit imxdma_remove(struct platform_device *pdev)
1061{
1062 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1063 int i;
1064
1065 dma_async_device_unregister(&imxdma->dma_device);
1066
6bd08127
JM		 1067 if (cpu_is_mx21() || cpu_is_mx27()) {
1068 for (i = 0; i < IMX_DMA_CHANNELS; i++)
1069 free_irq(MX2x_INT_DMACH0 + i, NULL);
1070 } else if cpu_is_mx1() {
1071 free_irq(MX1_DMA_INT, NULL);
1072 free_irq(MX1_DMA_ERR, NULL);
1f1846c6
SH		 1073 }
1074
1075 kfree(imxdma);
1076
1077 return 0;
1078}
1079
1080static struct platform_driver imxdma_driver = {
1081 .driver = {
1082 .name = "imx-dma",
1083 },
1084 .remove = __exit_p(imxdma_remove),
1085};
1086
1087static int __init imxdma_module_init(void)
1088{
1089 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1090}
1091subsys_initcall(imxdma_module_init);
1092
1093MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1094MODULE_DESCRIPTION("i.MX dma driver");
1095MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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