Commit | Line | Data |
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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
7331205a | 17 | #include <linux/err.h> |
1f1846c6 SH |
18 | #include <linux/init.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5c45ad77 | 29 | #include <linux/module.h> |
290ad0f9 MP |
30 | #include <linux/of_device.h> |
31 | #include <linux/of_dma.h> | |
1f1846c6 SH |
32 | |
33 | #include <asm/irq.h> | |
82906b13 | 34 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 35 | |
d2ebfb33 | 36 | #include "dmaengine.h" |
9e15db7c | 37 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
38 | #define IMX_DMA_CHANNELS 16 |
39 | ||
f606ab89 JM |
40 | #define IMX_DMA_2D_SLOTS 2 |
41 | #define IMX_DMA_2D_SLOT_A 0 | |
42 | #define IMX_DMA_2D_SLOT_B 1 | |
43 | ||
6bd08127 JM |
44 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
45 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
46 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
47 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
48 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
49 | #define IMX_DMA_TYPE_2D (1 << 10) | |
50 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
51 | ||
52 | #define IMX_DMA_ERR_BURST (1 << 0) | |
53 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
54 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
55 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
56 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
57 | ||
58 | #define DMA_DCR 0x00 /* Control Register */ | |
59 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
60 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
61 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
62 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
63 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
64 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
65 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
66 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
67 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
68 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
69 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
70 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
71 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
72 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
73 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
74 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
75 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
76 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
77 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
78 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
79 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
80 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
81 | ||
82 | #define DCR_DRST (1<<1) | |
83 | #define DCR_DEN (1<<0) | |
84 | #define DBTOCR_EN (1<<15) | |
85 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
86 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
87 | #define CCR_ACRPT (1<<14) | |
88 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
89 | #define CCR_DMOD_2D (0x1 << 12) | |
90 | #define CCR_DMOD_FIFO (0x2 << 12) | |
91 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
92 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
93 | #define CCR_SMOD_2D (0x1 << 10) | |
94 | #define CCR_SMOD_FIFO (0x2 << 10) | |
95 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
96 | #define CCR_MDIR_DEC (1<<9) | |
97 | #define CCR_MSEL_B (1<<8) | |
98 | #define CCR_DSIZ_32 (0x0 << 6) | |
99 | #define CCR_DSIZ_8 (0x1 << 6) | |
100 | #define CCR_DSIZ_16 (0x2 << 6) | |
101 | #define CCR_SSIZ_32 (0x0 << 4) | |
102 | #define CCR_SSIZ_8 (0x1 << 4) | |
103 | #define CCR_SSIZ_16 (0x2 << 4) | |
104 | #define CCR_REN (1<<3) | |
105 | #define CCR_RPT (1<<2) | |
106 | #define CCR_FRC (1<<1) | |
107 | #define CCR_CEN (1<<0) | |
108 | #define RTOR_EN (1<<15) | |
109 | #define RTOR_CLK (1<<14) | |
110 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
111 | |
112 | enum imxdma_prep_type { | |
113 | IMXDMA_DESC_MEMCPY, | |
114 | IMXDMA_DESC_INTERLEAVED, | |
115 | IMXDMA_DESC_SLAVE_SG, | |
116 | IMXDMA_DESC_CYCLIC, | |
117 | }; | |
118 | ||
f606ab89 JM |
119 | struct imx_dma_2d_config { |
120 | u16 xsr; | |
121 | u16 ysr; | |
122 | u16 wsr; | |
123 | int count; | |
124 | }; | |
125 | ||
9e15db7c JM |
126 | struct imxdma_desc { |
127 | struct list_head node; | |
128 | struct dma_async_tx_descriptor desc; | |
129 | enum dma_status status; | |
130 | dma_addr_t src; | |
131 | dma_addr_t dest; | |
132 | size_t len; | |
2efc3449 | 133 | enum dma_transfer_direction direction; |
9e15db7c JM |
134 | enum imxdma_prep_type type; |
135 | /* For memcpy and interleaved */ | |
136 | unsigned int config_port; | |
137 | unsigned int config_mem; | |
138 | /* For interleaved transfers */ | |
139 | unsigned int x; | |
140 | unsigned int y; | |
141 | unsigned int w; | |
142 | /* For slave sg and cyclic */ | |
143 | struct scatterlist *sg; | |
144 | unsigned int sgcount; | |
145 | }; | |
146 | ||
1f1846c6 | 147 | struct imxdma_channel { |
2d9c2fc5 JM |
148 | int hw_chaining; |
149 | struct timer_list watchdog; | |
1f1846c6 SH |
150 | struct imxdma_engine *imxdma; |
151 | unsigned int channel; | |
1f1846c6 | 152 | |
9e15db7c JM |
153 | struct tasklet_struct dma_tasklet; |
154 | struct list_head ld_free; | |
155 | struct list_head ld_queue; | |
156 | struct list_head ld_active; | |
157 | int descs_allocated; | |
1f1846c6 SH |
158 | enum dma_slave_buswidth word_size; |
159 | dma_addr_t per_address; | |
160 | u32 watermark_level; | |
161 | struct dma_chan chan; | |
1f1846c6 | 162 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
163 | enum dma_status status; |
164 | int dma_request; | |
165 | struct scatterlist *sg_list; | |
359291a1 JM |
166 | u32 ccr_from_device; |
167 | u32 ccr_to_device; | |
f606ab89 JM |
168 | bool enabled_2d; |
169 | int slot_2d; | |
1f1846c6 SH |
170 | }; |
171 | ||
e51d0f0a SG |
172 | enum imx_dma_type { |
173 | IMX1_DMA, | |
174 | IMX21_DMA, | |
175 | IMX27_DMA, | |
176 | }; | |
177 | ||
1f1846c6 SH |
178 | struct imxdma_engine { |
179 | struct device *dev; | |
1e070a60 | 180 | struct device_dma_parameters dma_parms; |
1f1846c6 | 181 | struct dma_device dma_device; |
cd5cf9da | 182 | void __iomem *base; |
a2367db2 FE |
183 | struct clk *dma_ahb; |
184 | struct clk *dma_ipg; | |
f606ab89 JM |
185 | spinlock_t lock; |
186 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 187 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 188 | enum imx_dma_type devtype; |
1f1846c6 SH |
189 | }; |
190 | ||
290ad0f9 MP |
191 | struct imxdma_filter_data { |
192 | struct imxdma_engine *imxdma; | |
193 | int request; | |
194 | }; | |
195 | ||
e51d0f0a SG |
196 | static struct platform_device_id imx_dma_devtype[] = { |
197 | { | |
198 | .name = "imx1-dma", | |
199 | .driver_data = IMX1_DMA, | |
200 | }, { | |
201 | .name = "imx21-dma", | |
202 | .driver_data = IMX21_DMA, | |
203 | }, { | |
204 | .name = "imx27-dma", | |
205 | .driver_data = IMX27_DMA, | |
206 | }, { | |
207 | /* sentinel */ | |
208 | } | |
209 | }; | |
210 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
211 | ||
290ad0f9 MP |
212 | static const struct of_device_id imx_dma_of_dev_id[] = { |
213 | { | |
214 | .compatible = "fsl,imx1-dma", | |
215 | .data = &imx_dma_devtype[IMX1_DMA], | |
216 | }, { | |
217 | .compatible = "fsl,imx21-dma", | |
218 | .data = &imx_dma_devtype[IMX21_DMA], | |
219 | }, { | |
220 | .compatible = "fsl,imx27-dma", | |
221 | .data = &imx_dma_devtype[IMX27_DMA], | |
222 | }, { | |
223 | /* sentinel */ | |
224 | } | |
225 | }; | |
226 | MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); | |
227 | ||
e51d0f0a SG |
228 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) |
229 | { | |
230 | return imxdma->devtype == IMX1_DMA; | |
231 | } | |
232 | ||
233 | static inline int is_imx21_dma(struct imxdma_engine *imxdma) | |
234 | { | |
235 | return imxdma->devtype == IMX21_DMA; | |
236 | } | |
237 | ||
238 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) | |
239 | { | |
240 | return imxdma->devtype == IMX27_DMA; | |
241 | } | |
242 | ||
1f1846c6 SH |
243 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
244 | { | |
245 | return container_of(chan, struct imxdma_channel, chan); | |
246 | } | |
247 | ||
9e15db7c | 248 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 249 | { |
9e15db7c JM |
250 | struct imxdma_desc *desc; |
251 | ||
252 | if (!list_empty(&imxdmac->ld_active)) { | |
253 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
254 | node); | |
255 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
256 | return true; | |
257 | } | |
258 | return false; | |
1f1846c6 SH |
259 | } |
260 | ||
6bd08127 | 261 | |
cd5cf9da JM |
262 | |
263 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
264 | unsigned offset) | |
6bd08127 | 265 | { |
cd5cf9da | 266 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
267 | } |
268 | ||
cd5cf9da | 269 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 270 | { |
cd5cf9da | 271 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 272 | } |
1f1846c6 | 273 | |
2d9c2fc5 | 274 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 275 | { |
e51d0f0a SG |
276 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
277 | ||
278 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 279 | return imxdmac->hw_chaining; |
6bd08127 JM |
280 | else |
281 | return 0; | |
282 | } | |
283 | ||
284 | /* | |
285 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
286 | */ | |
a6cbb2d8 | 287 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 288 | { |
2efc3449 | 289 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 290 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 291 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
292 | unsigned long now; |
293 | ||
fdaf9c4b | 294 | now = min(d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
295 | if (d->len != IMX_DMA_LENGTH_LOOP) |
296 | d->len -= now; | |
6bd08127 | 297 | |
2efc3449 | 298 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
299 | imx_dmav1_writel(imxdma, sg->dma_address, |
300 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 301 | else |
cd5cf9da JM |
302 | imx_dmav1_writel(imxdma, sg->dma_address, |
303 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 304 | |
cd5cf9da | 305 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 306 | |
f9b283a6 JM |
307 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
308 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
309 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
310 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
311 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
312 | |
313 | return now; | |
1f1846c6 SH |
314 | } |
315 | ||
2efc3449 | 316 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 317 | { |
2efc3449 | 318 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 319 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
320 | int channel = imxdmac->channel; |
321 | unsigned long flags; | |
322 | ||
f9b283a6 | 323 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 324 | |
6bd08127 JM |
325 | local_irq_save(flags); |
326 | ||
cd5cf9da JM |
327 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
328 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
329 | ~(1 << channel), DMA_DIMR); | |
330 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
331 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 332 | |
e51d0f0a | 333 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 334 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
335 | d->sg = sg_next(d->sg); |
336 | if (d->sg) { | |
6bd08127 | 337 | u32 tmp; |
a6cbb2d8 | 338 | imxdma_sg_next(d); |
cd5cf9da JM |
339 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
340 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
341 | DMA_CCR(channel)); | |
6bd08127 JM |
342 | } |
343 | } | |
6bd08127 JM |
344 | |
345 | local_irq_restore(flags); | |
346 | } | |
347 | ||
348 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
349 | { | |
cd5cf9da | 350 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
351 | int channel = imxdmac->channel; |
352 | unsigned long flags; | |
353 | ||
f9b283a6 | 354 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 355 | |
2d9c2fc5 JM |
356 | if (imxdma_hw_chain(imxdmac)) |
357 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
358 | |
359 | local_irq_save(flags); | |
cd5cf9da JM |
360 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
361 | (1 << channel), DMA_DIMR); | |
362 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
363 | ~CCR_CEN, DMA_CCR(channel)); | |
364 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
365 | local_irq_restore(flags); |
366 | } | |
367 | ||
6bd08127 | 368 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 369 | { |
6bd08127 | 370 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
cd5cf9da | 371 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 372 | int channel = imxdmac->channel; |
1f1846c6 | 373 | |
cd5cf9da | 374 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 375 | |
6bd08127 | 376 | /* Tasklet watchdog error handler */ |
9e15db7c | 377 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
378 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
379 | imxdmac->channel); | |
1f1846c6 SH |
380 | } |
381 | ||
6bd08127 | 382 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 383 | { |
6bd08127 | 384 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
385 | unsigned int err_mask; |
386 | int i, disr; | |
387 | int errcode; | |
388 | ||
cd5cf9da | 389 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 390 | |
cd5cf9da JM |
391 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
392 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
393 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
394 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
395 | |
396 | if (!err_mask) | |
397 | return IRQ_HANDLED; | |
398 | ||
cd5cf9da | 399 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
400 | |
401 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
402 | if (!(err_mask & (1 << i))) | |
403 | continue; | |
6bd08127 JM |
404 | errcode = 0; |
405 | ||
cd5cf9da JM |
406 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
407 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
408 | errcode |= IMX_DMA_ERR_BURST; |
409 | } | |
cd5cf9da JM |
410 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
411 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
412 | errcode |= IMX_DMA_ERR_REQUEST; |
413 | } | |
cd5cf9da JM |
414 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
415 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
416 | errcode |= IMX_DMA_ERR_TRANSFER; |
417 | } | |
cd5cf9da JM |
418 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
419 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
420 | errcode |= IMX_DMA_ERR_BUFFER; |
421 | } | |
422 | /* Tasklet error handler */ | |
423 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
424 | ||
425 | printk(KERN_WARNING | |
426 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
427 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
428 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
429 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
430 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
431 | } | |
432 | return IRQ_HANDLED; | |
1f1846c6 SH |
433 | } |
434 | ||
6bd08127 | 435 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 436 | { |
cd5cf9da | 437 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 438 | int chno = imxdmac->channel; |
2efc3449 | 439 | struct imxdma_desc *desc; |
5a276fa6 | 440 | unsigned long flags; |
6bd08127 | 441 | |
5a276fa6 | 442 | spin_lock_irqsave(&imxdma->lock, flags); |
833bc03b | 443 | if (list_empty(&imxdmac->ld_active)) { |
5a276fa6 | 444 | spin_unlock_irqrestore(&imxdma->lock, flags); |
833bc03b JM |
445 | goto out; |
446 | } | |
2efc3449 | 447 | |
833bc03b JM |
448 | desc = list_first_entry(&imxdmac->ld_active, |
449 | struct imxdma_desc, | |
450 | node); | |
5a276fa6 | 451 | spin_unlock_irqrestore(&imxdma->lock, flags); |
2efc3449 | 452 | |
833bc03b JM |
453 | if (desc->sg) { |
454 | u32 tmp; | |
455 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 456 | |
833bc03b | 457 | if (desc->sg) { |
a6cbb2d8 | 458 | imxdma_sg_next(desc); |
6bd08127 | 459 | |
cd5cf9da | 460 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 461 | |
2d9c2fc5 | 462 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
463 | /* FIXME: The timeout should probably be |
464 | * configurable | |
465 | */ | |
2d9c2fc5 | 466 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
467 | jiffies + msecs_to_jiffies(500)); |
468 | ||
469 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 470 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 471 | } else { |
cd5cf9da JM |
472 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
473 | DMA_CCR(chno)); | |
6bd08127 JM |
474 | tmp |= CCR_CEN; |
475 | } | |
476 | ||
cd5cf9da | 477 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
478 | |
479 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
480 | /* Tasklet progression */ | |
481 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 482 | |
6bd08127 JM |
483 | return; |
484 | } | |
485 | ||
2d9c2fc5 JM |
486 | if (imxdma_hw_chain(imxdmac)) { |
487 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
488 | return; |
489 | } | |
490 | } | |
491 | ||
2efc3449 | 492 | out: |
cd5cf9da | 493 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 494 | /* Tasklet irq */ |
9e15db7c JM |
495 | tasklet_schedule(&imxdmac->dma_tasklet); |
496 | } | |
497 | ||
6bd08127 JM |
498 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
499 | { | |
500 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
501 | int i, disr; |
502 | ||
e51d0f0a | 503 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
504 | imxdma_err_handler(irq, dev_id); |
505 | ||
cd5cf9da | 506 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 507 | |
f9b283a6 | 508 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 509 | |
cd5cf9da | 510 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 511 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 512 | if (disr & (1 << i)) |
6bd08127 | 513 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
514 | } |
515 | ||
516 | return IRQ_HANDLED; | |
517 | } | |
518 | ||
9e15db7c JM |
519 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
520 | { | |
521 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 522 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
523 | int slot = -1; |
524 | int i; | |
9e15db7c JM |
525 | |
526 | /* Configure and enable */ | |
527 | switch (d->type) { | |
f606ab89 JM |
528 | case IMXDMA_DESC_INTERLEAVED: |
529 | /* Try to get a free 2D slot */ | |
f606ab89 JM |
530 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { |
531 | if ((imxdma->slots_2d[i].count > 0) && | |
532 | ((imxdma->slots_2d[i].xsr != d->x) || | |
533 | (imxdma->slots_2d[i].ysr != d->y) || | |
534 | (imxdma->slots_2d[i].wsr != d->w))) | |
535 | continue; | |
536 | slot = i; | |
537 | break; | |
538 | } | |
5a276fa6 | 539 | if (slot < 0) |
f606ab89 JM |
540 | return -EBUSY; |
541 | ||
542 | imxdma->slots_2d[slot].xsr = d->x; | |
543 | imxdma->slots_2d[slot].ysr = d->y; | |
544 | imxdma->slots_2d[slot].wsr = d->w; | |
545 | imxdma->slots_2d[slot].count++; | |
546 | ||
547 | imxdmac->slot_2d = slot; | |
548 | imxdmac->enabled_2d = true; | |
f606ab89 JM |
549 | |
550 | if (slot == IMX_DMA_2D_SLOT_A) { | |
551 | d->config_mem &= ~CCR_MSEL_B; | |
552 | d->config_port &= ~CCR_MSEL_B; | |
553 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
554 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
555 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
556 | } else { | |
557 | d->config_mem |= CCR_MSEL_B; | |
558 | d->config_port |= CCR_MSEL_B; | |
559 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
560 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
561 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
562 | } | |
563 | /* | |
564 | * We fall-through here intentionally, since a 2D transfer is | |
565 | * similar to MEMCPY just adding the 2D slot configuration. | |
566 | */ | |
9e15db7c | 567 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
568 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
569 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
570 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 571 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 572 | |
cd5cf9da | 573 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc JM |
574 | |
575 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
576 | "dma_length=%d\n", __func__, imxdmac->channel, | |
577 | d->dest, d->src, d->len); | |
578 | ||
579 | break; | |
6bd08127 | 580 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 581 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 582 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 583 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 584 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 585 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 586 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
587 | DMA_CCR(imxdmac->channel)); |
588 | ||
589 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
590 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
591 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
592 | d->len, imxdmac->per_address); | |
593 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
cd5cf9da | 594 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 595 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 596 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
597 | DMA_CCR(imxdmac->channel)); |
598 | ||
599 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
600 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
601 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
602 | d->len, imxdmac->per_address); | |
603 | } else { | |
604 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
605 | __func__, imxdmac->channel); | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
a6cbb2d8 | 609 | imxdma_sg_next(d); |
1f1846c6 | 610 | |
9e15db7c JM |
611 | break; |
612 | default: | |
613 | return -EINVAL; | |
614 | } | |
2efc3449 | 615 | imxdma_enable_hw(d); |
9e15db7c | 616 | return 0; |
1f1846c6 SH |
617 | } |
618 | ||
9e15db7c | 619 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 620 | { |
9e15db7c JM |
621 | struct imxdma_channel *imxdmac = (void *)data; |
622 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
623 | struct imxdma_desc *desc; | |
5a276fa6 | 624 | unsigned long flags; |
1f1846c6 | 625 | |
5a276fa6 | 626 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
627 | |
628 | if (list_empty(&imxdmac->ld_active)) { | |
629 | /* Someone might have called terminate all */ | |
630 | goto out; | |
631 | } | |
632 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
633 | ||
634 | if (desc->desc.callback) | |
635 | desc->desc.callback(desc->desc.callback_param); | |
636 | ||
d73111c6 MI |
637 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
638 | * and dont mark the descriptor as complete. | |
60f2951e VK |
639 | * Only in non-cyclic cases it would be marked as complete |
640 | */ | |
9e15db7c JM |
641 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
642 | goto out; | |
60f2951e VK |
643 | else |
644 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 645 | |
f606ab89 JM |
646 | /* Free 2D slot if it was an interleaved transfer */ |
647 | if (imxdmac->enabled_2d) { | |
648 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
649 | imxdmac->enabled_2d = false; | |
650 | } | |
651 | ||
9e15db7c JM |
652 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
653 | ||
654 | if (!list_empty(&imxdmac->ld_queue)) { | |
655 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
656 | node); | |
657 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
658 | if (imxdma_xfer_desc(desc) < 0) | |
659 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
660 | __func__, imxdmac->channel); | |
661 | } | |
662 | out: | |
5a276fa6 | 663 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
664 | } |
665 | ||
666 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
667 | unsigned long arg) | |
668 | { | |
669 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
670 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
cd5cf9da | 671 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 672 | unsigned long flags; |
1f1846c6 SH |
673 | unsigned int mode = 0; |
674 | ||
675 | switch (cmd) { | |
676 | case DMA_TERMINATE_ALL: | |
6bd08127 | 677 | imxdma_disable_hw(imxdmac); |
9e15db7c | 678 | |
f606ab89 | 679 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
680 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
681 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
f606ab89 | 682 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
683 | return 0; |
684 | case DMA_SLAVE_CONFIG: | |
db8196df | 685 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
686 | imxdmac->per_address = dmaengine_cfg->src_addr; |
687 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
688 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
689 | } else { | |
690 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
691 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
692 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
693 | } | |
694 | ||
695 | switch (imxdmac->word_size) { | |
696 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
697 | mode = IMX_DMA_MEMSIZE_8; | |
698 | break; | |
699 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
700 | mode = IMX_DMA_MEMSIZE_16; | |
701 | break; | |
702 | default: | |
703 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
704 | mode = IMX_DMA_MEMSIZE_32; | |
705 | break; | |
706 | } | |
1f1846c6 | 707 | |
bef2a8d3 JM |
708 | imxdmac->hw_chaining = 0; |
709 | ||
359291a1 | 710 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
711 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
712 | CCR_REN; | |
359291a1 | 713 | imxdmac->ccr_to_device = |
bdc0c753 JM |
714 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
715 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
cd5cf9da | 716 | imx_dmav1_writel(imxdma, imxdmac->dma_request, |
bdc0c753 JM |
717 | DMA_RSSR(imxdmac->channel)); |
718 | ||
6bd08127 | 719 | /* Set burst length */ |
cd5cf9da JM |
720 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * |
721 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
722 | |
723 | return 0; | |
724 | default: | |
725 | return -ENOSYS; | |
726 | } | |
727 | ||
728 | return -EINVAL; | |
729 | } | |
730 | ||
731 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
732 | dma_cookie_t cookie, | |
733 | struct dma_tx_state *txstate) | |
734 | { | |
96a2af41 | 735 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
736 | } |
737 | ||
738 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
739 | { | |
740 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 741 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 742 | dma_cookie_t cookie; |
9e15db7c | 743 | unsigned long flags; |
1f1846c6 | 744 | |
f606ab89 | 745 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 746 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 747 | cookie = dma_cookie_assign(tx); |
f606ab89 | 748 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
749 | |
750 | return cookie; | |
751 | } | |
752 | ||
753 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
754 | { | |
755 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
756 | struct imx_dma_data *data = chan->private; | |
757 | ||
6c05f091 JM |
758 | if (data != NULL) |
759 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 760 | |
9e15db7c JM |
761 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
762 | struct imxdma_desc *desc; | |
1f1846c6 | 763 | |
9e15db7c JM |
764 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
765 | if (!desc) | |
766 | break; | |
767 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
768 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
769 | desc->desc.tx_submit = imxdma_tx_submit; | |
770 | /* txd.flags will be overwritten in prep funcs */ | |
771 | desc->desc.flags = DMA_CTRL_ACK; | |
772 | desc->status = DMA_SUCCESS; | |
773 | ||
774 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
775 | imxdmac->descs_allocated++; | |
776 | } | |
1f1846c6 | 777 | |
9e15db7c JM |
778 | if (!imxdmac->descs_allocated) |
779 | return -ENOMEM; | |
780 | ||
781 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
782 | } |
783 | ||
784 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
785 | { | |
786 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 787 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
788 | struct imxdma_desc *desc, *_desc; |
789 | unsigned long flags; | |
790 | ||
f606ab89 | 791 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 792 | |
6bd08127 | 793 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
794 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
795 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 796 | |
f606ab89 | 797 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
798 | |
799 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
800 | kfree(desc); | |
801 | imxdmac->descs_allocated--; | |
802 | } | |
803 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 | 804 | |
06f8db4b SK |
805 | kfree(imxdmac->sg_list); |
806 | imxdmac->sg_list = NULL; | |
1f1846c6 SH |
807 | } |
808 | ||
809 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
810 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 811 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 812 | unsigned long flags, void *context) |
1f1846c6 SH |
813 | { |
814 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
815 | struct scatterlist *sg; | |
9e15db7c JM |
816 | int i, dma_length = 0; |
817 | struct imxdma_desc *desc; | |
1f1846c6 | 818 | |
9e15db7c JM |
819 | if (list_empty(&imxdmac->ld_free) || |
820 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
821 | return NULL; |
822 | ||
9e15db7c | 823 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
824 | |
825 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 826 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
827 | } |
828 | ||
d07102a1 SH |
829 | switch (imxdmac->word_size) { |
830 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 831 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
832 | return NULL; |
833 | break; | |
834 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 835 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
836 | return NULL; |
837 | break; | |
838 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
839 | break; | |
840 | default: | |
841 | return NULL; | |
842 | } | |
843 | ||
9e15db7c JM |
844 | desc->type = IMXDMA_DESC_SLAVE_SG; |
845 | desc->sg = sgl; | |
846 | desc->sgcount = sg_len; | |
847 | desc->len = dma_length; | |
2efc3449 | 848 | desc->direction = direction; |
9e15db7c | 849 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
850 | desc->src = imxdmac->per_address; |
851 | } else { | |
9e15db7c JM |
852 | desc->dest = imxdmac->per_address; |
853 | } | |
854 | desc->desc.callback = NULL; | |
855 | desc->desc.callback_param = NULL; | |
1f1846c6 | 856 | |
9e15db7c | 857 | return &desc->desc; |
1f1846c6 SH |
858 | } |
859 | ||
860 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
861 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 862 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 863 | unsigned long flags, void *context) |
1f1846c6 SH |
864 | { |
865 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
866 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
867 | struct imxdma_desc *desc; |
868 | int i; | |
1f1846c6 | 869 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
870 | |
871 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
872 | __func__, imxdmac->channel, buf_len, period_len); | |
873 | ||
9e15db7c JM |
874 | if (list_empty(&imxdmac->ld_free) || |
875 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 876 | return NULL; |
1f1846c6 | 877 | |
9e15db7c | 878 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 | 879 | |
96a3713e | 880 | kfree(imxdmac->sg_list); |
1f1846c6 SH |
881 | |
882 | imxdmac->sg_list = kcalloc(periods + 1, | |
edc530fe | 883 | sizeof(struct scatterlist), GFP_ATOMIC); |
1f1846c6 SH |
884 | if (!imxdmac->sg_list) |
885 | return NULL; | |
886 | ||
887 | sg_init_table(imxdmac->sg_list, periods); | |
888 | ||
889 | for (i = 0; i < periods; i++) { | |
890 | imxdmac->sg_list[i].page_link = 0; | |
891 | imxdmac->sg_list[i].offset = 0; | |
892 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 893 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
894 | dma_addr += period_len; |
895 | } | |
896 | ||
897 | /* close the loop */ | |
898 | imxdmac->sg_list[periods].offset = 0; | |
fdaf9c4b | 899 | sg_dma_len(&imxdmac->sg_list[periods]) = 0; |
1f1846c6 SH |
900 | imxdmac->sg_list[periods].page_link = |
901 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
902 | ||
9e15db7c JM |
903 | desc->type = IMXDMA_DESC_CYCLIC; |
904 | desc->sg = imxdmac->sg_list; | |
905 | desc->sgcount = periods; | |
906 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 907 | desc->direction = direction; |
9e15db7c | 908 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
909 | desc->src = imxdmac->per_address; |
910 | } else { | |
9e15db7c JM |
911 | desc->dest = imxdmac->per_address; |
912 | } | |
913 | desc->desc.callback = NULL; | |
914 | desc->desc.callback_param = NULL; | |
1f1846c6 | 915 | |
9e15db7c | 916 | return &desc->desc; |
1f1846c6 SH |
917 | } |
918 | ||
6c05f091 JM |
919 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
920 | struct dma_chan *chan, dma_addr_t dest, | |
921 | dma_addr_t src, size_t len, unsigned long flags) | |
922 | { | |
923 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
924 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 925 | struct imxdma_desc *desc; |
1f1846c6 | 926 | |
6c05f091 JM |
927 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", |
928 | __func__, imxdmac->channel, src, dest, len); | |
929 | ||
9e15db7c JM |
930 | if (list_empty(&imxdmac->ld_free) || |
931 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
932 | return NULL; |
933 | ||
9e15db7c | 934 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 935 | |
9e15db7c JM |
936 | desc->type = IMXDMA_DESC_MEMCPY; |
937 | desc->src = src; | |
938 | desc->dest = dest; | |
939 | desc->len = len; | |
2efc3449 | 940 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
941 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
942 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
943 | desc->desc.callback = NULL; | |
944 | desc->desc.callback_param = NULL; | |
6c05f091 | 945 | |
9e15db7c | 946 | return &desc->desc; |
6c05f091 JM |
947 | } |
948 | ||
f606ab89 JM |
949 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
950 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
951 | unsigned long flags) | |
952 | { | |
953 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
954 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
955 | struct imxdma_desc *desc; | |
956 | ||
957 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n" | |
958 | " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__, | |
959 | imxdmac->channel, xt->src_start, xt->dst_start, | |
960 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", | |
961 | xt->numf, xt->frame_size); | |
962 | ||
963 | if (list_empty(&imxdmac->ld_free) || | |
964 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
965 | return NULL; | |
966 | ||
967 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
968 | return NULL; | |
969 | ||
970 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
971 | ||
972 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
973 | desc->src = xt->src_start; | |
974 | desc->dest = xt->dst_start; | |
975 | desc->x = xt->sgl[0].size; | |
976 | desc->y = xt->numf; | |
977 | desc->w = xt->sgl[0].icg + desc->x; | |
978 | desc->len = desc->x * desc->y; | |
979 | desc->direction = DMA_MEM_TO_MEM; | |
980 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
981 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
982 | if (xt->src_sgl) | |
983 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
984 | if (xt->dst_sgl) | |
985 | desc->config_port |= IMX_DMA_TYPE_2D; | |
986 | desc->desc.callback = NULL; | |
987 | desc->desc.callback_param = NULL; | |
988 | ||
989 | return &desc->desc; | |
1f1846c6 SH |
990 | } |
991 | ||
992 | static void imxdma_issue_pending(struct dma_chan *chan) | |
993 | { | |
5b316876 | 994 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
995 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
996 | struct imxdma_desc *desc; | |
997 | unsigned long flags; | |
998 | ||
f606ab89 | 999 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
1000 | if (list_empty(&imxdmac->ld_active) && |
1001 | !list_empty(&imxdmac->ld_queue)) { | |
1002 | desc = list_first_entry(&imxdmac->ld_queue, | |
1003 | struct imxdma_desc, node); | |
1004 | ||
1005 | if (imxdma_xfer_desc(desc) < 0) { | |
1006 | dev_warn(imxdma->dev, | |
1007 | "%s: channel: %d couldn't issue DMA xfer\n", | |
1008 | __func__, imxdmac->channel); | |
1009 | } else { | |
1010 | list_move_tail(imxdmac->ld_queue.next, | |
1011 | &imxdmac->ld_active); | |
1012 | } | |
1013 | } | |
f606ab89 | 1014 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
1015 | } |
1016 | ||
290ad0f9 MP |
1017 | static bool imxdma_filter_fn(struct dma_chan *chan, void *param) |
1018 | { | |
1019 | struct imxdma_filter_data *fdata = param; | |
1020 | struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); | |
1021 | ||
1022 | if (chan->device->dev != fdata->imxdma->dev) | |
1023 | return false; | |
1024 | ||
1025 | imxdma_chan->dma_request = fdata->request; | |
1026 | chan->private = NULL; | |
1027 | ||
1028 | return true; | |
1029 | } | |
1030 | ||
1031 | static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, | |
1032 | struct of_dma *ofdma) | |
1033 | { | |
1034 | int count = dma_spec->args_count; | |
1035 | struct imxdma_engine *imxdma = ofdma->of_dma_data; | |
1036 | struct imxdma_filter_data fdata = { | |
1037 | .imxdma = imxdma, | |
1038 | }; | |
1039 | ||
1040 | if (count != 1) | |
1041 | return NULL; | |
1042 | ||
1043 | fdata.request = dma_spec->args[0]; | |
1044 | ||
1045 | return dma_request_channel(imxdma->dma_device.cap_mask, | |
1046 | imxdma_filter_fn, &fdata); | |
1047 | } | |
1048 | ||
1f1846c6 | 1049 | static int __init imxdma_probe(struct platform_device *pdev) |
6bd08127 | 1050 | { |
1f1846c6 | 1051 | struct imxdma_engine *imxdma; |
73930eb3 | 1052 | struct resource *res; |
290ad0f9 | 1053 | const struct of_device_id *of_id; |
1f1846c6 | 1054 | int ret, i; |
73930eb3 | 1055 | int irq, irq_err; |
cd5cf9da | 1056 | |
290ad0f9 MP |
1057 | of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); |
1058 | if (of_id) | |
1059 | pdev->id_entry = of_id->data; | |
1060 | ||
04bbd8ef | 1061 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1062 | if (!imxdma) |
1063 | return -ENOMEM; | |
1064 | ||
5c6b3e77 | 1065 | imxdma->dev = &pdev->dev; |
e51d0f0a SG |
1066 | imxdma->devtype = pdev->id_entry->driver_data; |
1067 | ||
73930eb3 | 1068 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1069 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1070 | if (IS_ERR(imxdma->base)) | |
1071 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1072 | |
1073 | irq = platform_get_irq(pdev, 0); | |
1074 | if (irq < 0) | |
1075 | return irq; | |
6bd08127 | 1076 | |
a2367db2 | 1077 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1078 | if (IS_ERR(imxdma->dma_ipg)) |
1079 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1080 | |
1081 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1082 | if (IS_ERR(imxdma->dma_ahb)) |
1083 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 FE |
1084 | |
1085 | clk_prepare_enable(imxdma->dma_ipg); | |
1086 | clk_prepare_enable(imxdma->dma_ahb); | |
6bd08127 JM |
1087 | |
1088 | /* reset DMA module */ | |
cd5cf9da | 1089 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1090 | |
e51d0f0a | 1091 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1092 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1093 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1094 | if (ret) { |
f9b283a6 | 1095 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
04bbd8ef | 1096 | goto err; |
6bd08127 JM |
1097 | } |
1098 | ||
73930eb3 SG |
1099 | irq_err = platform_get_irq(pdev, 1); |
1100 | if (irq_err < 0) { | |
1101 | ret = irq_err; | |
1102 | goto err; | |
1103 | } | |
1104 | ||
1105 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1106 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1107 | if (ret) { |
f9b283a6 | 1108 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
04bbd8ef | 1109 | goto err; |
6bd08127 JM |
1110 | } |
1111 | } | |
1112 | ||
1113 | /* enable DMA module */ | |
cd5cf9da | 1114 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1115 | |
1116 | /* clear all interrupts */ | |
cd5cf9da | 1117 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1118 | |
1119 | /* disable interrupts */ | |
cd5cf9da | 1120 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1121 | |
1122 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1123 | ||
f8a356ff SH |
1124 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1125 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1126 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1127 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1128 | ||
1129 | /* Initialize 2D global parameters */ | |
1130 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1131 | imxdma->slots_2d[i].count = 0; | |
1132 | ||
1133 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1134 | |
1f1846c6 | 1135 | /* Initialize channel parameters */ |
6bd08127 | 1136 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1137 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1138 | ||
e51d0f0a | 1139 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1140 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1141 | dma_irq_handler, 0, "DMA", imxdma); |
1142 | if (ret) { | |
f9b283a6 JM |
1143 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1144 | "for DMA channel %d\n", | |
73930eb3 | 1145 | irq + i, i); |
04bbd8ef | 1146 | goto err; |
6bd08127 | 1147 | } |
2d9c2fc5 JM |
1148 | init_timer(&imxdmac->watchdog); |
1149 | imxdmac->watchdog.function = &imxdma_watchdog; | |
1150 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 1151 | } |
1f1846c6 | 1152 | |
1f1846c6 | 1153 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1154 | |
9e15db7c JM |
1155 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1156 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1157 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1158 | ||
1159 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1160 | (unsigned long)imxdmac); | |
1f1846c6 | 1161 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1162 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1163 | imxdmac->channel = i; |
1164 | ||
1165 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1166 | list_add_tail(&imxdmac->chan.device_node, |
1167 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1168 | } |
1169 | ||
1f1846c6 SH |
1170 | imxdma->dma_device.dev = &pdev->dev; |
1171 | ||
1172 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1173 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1174 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1175 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1176 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1177 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1178 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
1f1846c6 SH |
1179 | imxdma->dma_device.device_control = imxdma_control; |
1180 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
1181 | ||
1182 | platform_set_drvdata(pdev, imxdma); | |
1183 | ||
6c05f091 | 1184 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
1185 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1186 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1187 | ||
1f1846c6 SH |
1188 | ret = dma_async_device_register(&imxdma->dma_device); |
1189 | if (ret) { | |
1190 | dev_err(&pdev->dev, "unable to register\n"); | |
04bbd8ef | 1191 | goto err; |
1f1846c6 SH |
1192 | } |
1193 | ||
290ad0f9 MP |
1194 | if (pdev->dev.of_node) { |
1195 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1196 | imxdma_xlate, imxdma); | |
1197 | if (ret) { | |
1198 | dev_err(&pdev->dev, "unable to register of_dma_controller\n"); | |
1199 | goto err_of_dma_controller; | |
1200 | } | |
1201 | } | |
1202 | ||
1f1846c6 SH |
1203 | return 0; |
1204 | ||
290ad0f9 MP |
1205 | err_of_dma_controller: |
1206 | dma_async_device_unregister(&imxdma->dma_device); | |
04bbd8ef | 1207 | err: |
a2367db2 FE |
1208 | clk_disable_unprepare(imxdma->dma_ipg); |
1209 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1210 | return ret; |
1211 | } | |
1212 | ||
1d1bbd30 | 1213 | static int imxdma_remove(struct platform_device *pdev) |
1f1846c6 SH |
1214 | { |
1215 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 SH |
1216 | |
1217 | dma_async_device_unregister(&imxdma->dma_device); | |
1218 | ||
290ad0f9 MP |
1219 | if (pdev->dev.of_node) |
1220 | of_dma_controller_free(pdev->dev.of_node); | |
1221 | ||
a2367db2 FE |
1222 | clk_disable_unprepare(imxdma->dma_ipg); |
1223 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1224 | |
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | static struct platform_driver imxdma_driver = { | |
1229 | .driver = { | |
1230 | .name = "imx-dma", | |
290ad0f9 | 1231 | .of_match_table = imx_dma_of_dev_id, |
1f1846c6 | 1232 | }, |
e51d0f0a | 1233 | .id_table = imx_dma_devtype, |
1d1bbd30 | 1234 | .remove = imxdma_remove, |
1f1846c6 SH |
1235 | }; |
1236 | ||
1237 | static int __init imxdma_module_init(void) | |
1238 | { | |
1239 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1240 | } | |
1241 | subsys_initcall(imxdma_module_init); | |
1242 | ||
1243 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1244 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1245 | MODULE_LICENSE("GPL"); |