Commit | Line | Data |
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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
17 | #include <linux/init.h> | |
f8de8f4c | 18 | #include <linux/module.h> |
1f1846c6 SH |
19 | #include <linux/types.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5170c051 | 29 | #include <linux/module.h> |
1f1846c6 SH |
30 | |
31 | #include <asm/irq.h> | |
6bd08127 | 32 | #include <mach/dma.h> |
1f1846c6 SH |
33 | #include <mach/hardware.h> |
34 | ||
d2ebfb33 | 35 | #include "dmaengine.h" |
9e15db7c | 36 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
37 | #define IMX_DMA_CHANNELS 16 |
38 | ||
6bd08127 JM |
39 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
40 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
41 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
42 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
43 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
44 | #define IMX_DMA_TYPE_2D (1 << 10) | |
45 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
46 | ||
47 | #define IMX_DMA_ERR_BURST (1 << 0) | |
48 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
49 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
50 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
51 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
52 | ||
53 | #define DMA_DCR 0x00 /* Control Register */ | |
54 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
55 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
56 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
57 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
58 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
59 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
60 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
61 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
62 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
63 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
64 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
65 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
66 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
67 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
68 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
69 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
70 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
71 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
72 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
73 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
74 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
75 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
76 | ||
77 | #define DCR_DRST (1<<1) | |
78 | #define DCR_DEN (1<<0) | |
79 | #define DBTOCR_EN (1<<15) | |
80 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
81 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
82 | #define CCR_ACRPT (1<<14) | |
83 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
84 | #define CCR_DMOD_2D (0x1 << 12) | |
85 | #define CCR_DMOD_FIFO (0x2 << 12) | |
86 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
87 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
88 | #define CCR_SMOD_2D (0x1 << 10) | |
89 | #define CCR_SMOD_FIFO (0x2 << 10) | |
90 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
91 | #define CCR_MDIR_DEC (1<<9) | |
92 | #define CCR_MSEL_B (1<<8) | |
93 | #define CCR_DSIZ_32 (0x0 << 6) | |
94 | #define CCR_DSIZ_8 (0x1 << 6) | |
95 | #define CCR_DSIZ_16 (0x2 << 6) | |
96 | #define CCR_SSIZ_32 (0x0 << 4) | |
97 | #define CCR_SSIZ_8 (0x1 << 4) | |
98 | #define CCR_SSIZ_16 (0x2 << 4) | |
99 | #define CCR_REN (1<<3) | |
100 | #define CCR_RPT (1<<2) | |
101 | #define CCR_FRC (1<<1) | |
102 | #define CCR_CEN (1<<0) | |
103 | #define RTOR_EN (1<<15) | |
104 | #define RTOR_CLK (1<<14) | |
105 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
106 | |
107 | enum imxdma_prep_type { | |
108 | IMXDMA_DESC_MEMCPY, | |
109 | IMXDMA_DESC_INTERLEAVED, | |
110 | IMXDMA_DESC_SLAVE_SG, | |
111 | IMXDMA_DESC_CYCLIC, | |
112 | }; | |
113 | ||
114 | struct imxdma_desc { | |
115 | struct list_head node; | |
116 | struct dma_async_tx_descriptor desc; | |
117 | enum dma_status status; | |
118 | dma_addr_t src; | |
119 | dma_addr_t dest; | |
120 | size_t len; | |
2efc3449 | 121 | enum dma_transfer_direction direction; |
9e15db7c JM |
122 | enum imxdma_prep_type type; |
123 | /* For memcpy and interleaved */ | |
124 | unsigned int config_port; | |
125 | unsigned int config_mem; | |
126 | /* For interleaved transfers */ | |
127 | unsigned int x; | |
128 | unsigned int y; | |
129 | unsigned int w; | |
130 | /* For slave sg and cyclic */ | |
131 | struct scatterlist *sg; | |
132 | unsigned int sgcount; | |
133 | }; | |
134 | ||
1f1846c6 | 135 | struct imxdma_channel { |
2d9c2fc5 JM |
136 | int hw_chaining; |
137 | struct timer_list watchdog; | |
1f1846c6 SH |
138 | struct imxdma_engine *imxdma; |
139 | unsigned int channel; | |
1f1846c6 | 140 | |
9e15db7c JM |
141 | struct tasklet_struct dma_tasklet; |
142 | struct list_head ld_free; | |
143 | struct list_head ld_queue; | |
144 | struct list_head ld_active; | |
145 | int descs_allocated; | |
1f1846c6 SH |
146 | enum dma_slave_buswidth word_size; |
147 | dma_addr_t per_address; | |
148 | u32 watermark_level; | |
149 | struct dma_chan chan; | |
150 | spinlock_t lock; | |
151 | struct dma_async_tx_descriptor desc; | |
1f1846c6 SH |
152 | enum dma_status status; |
153 | int dma_request; | |
154 | struct scatterlist *sg_list; | |
359291a1 JM |
155 | u32 ccr_from_device; |
156 | u32 ccr_to_device; | |
1f1846c6 SH |
157 | }; |
158 | ||
1f1846c6 SH |
159 | struct imxdma_engine { |
160 | struct device *dev; | |
1e070a60 | 161 | struct device_dma_parameters dma_parms; |
1f1846c6 | 162 | struct dma_device dma_device; |
6bd08127 | 163 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
1f1846c6 SH |
164 | }; |
165 | ||
166 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) | |
167 | { | |
168 | return container_of(chan, struct imxdma_channel, chan); | |
169 | } | |
170 | ||
9e15db7c | 171 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 172 | { |
9e15db7c JM |
173 | struct imxdma_desc *desc; |
174 | ||
175 | if (!list_empty(&imxdmac->ld_active)) { | |
176 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
177 | node); | |
178 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
179 | return true; | |
180 | } | |
181 | return false; | |
1f1846c6 SH |
182 | } |
183 | ||
6bd08127 JM |
184 | /* TODO: put this inside any struct */ |
185 | static void __iomem *imx_dmav1_baseaddr; | |
186 | static struct clk *dma_clk; | |
187 | ||
188 | static void imx_dmav1_writel(unsigned val, unsigned offset) | |
189 | { | |
190 | __raw_writel(val, imx_dmav1_baseaddr + offset); | |
191 | } | |
192 | ||
193 | static unsigned imx_dmav1_readl(unsigned offset) | |
1f1846c6 | 194 | { |
6bd08127 JM |
195 | return __raw_readl(imx_dmav1_baseaddr + offset); |
196 | } | |
1f1846c6 | 197 | |
2d9c2fc5 | 198 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 JM |
199 | { |
200 | if (cpu_is_mx27()) | |
2d9c2fc5 | 201 | return imxdmac->hw_chaining; |
6bd08127 JM |
202 | else |
203 | return 0; | |
204 | } | |
205 | ||
206 | /* | |
207 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
208 | */ | |
a6cbb2d8 | 209 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
6bd08127 | 210 | { |
2efc3449 | 211 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
a6cbb2d8 | 212 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
213 | unsigned long now; |
214 | ||
6b0e2f55 JM |
215 | now = min(d->len, sg->length); |
216 | if (d->len != IMX_DMA_LENGTH_LOOP) | |
217 | d->len -= now; | |
6bd08127 | 218 | |
2efc3449 | 219 | if (d->direction == DMA_DEV_TO_MEM) |
6bd08127 JM |
220 | imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel)); |
221 | else | |
222 | imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel)); | |
223 | ||
224 | imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel)); | |
225 | ||
226 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " | |
227 | "size 0x%08x\n", imxdmac->channel, | |
228 | imx_dmav1_readl(DMA_DAR(imxdmac->channel)), | |
229 | imx_dmav1_readl(DMA_SAR(imxdmac->channel)), | |
230 | imx_dmav1_readl(DMA_CNTR(imxdmac->channel))); | |
231 | ||
232 | return now; | |
233 | } | |
234 | ||
2efc3449 | 235 | static void imxdma_enable_hw(struct imxdma_desc *d) |
6bd08127 | 236 | { |
2efc3449 | 237 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
6bd08127 JM |
238 | int channel = imxdmac->channel; |
239 | unsigned long flags; | |
240 | ||
241 | pr_debug("imxdma%d: imx_dma_enable\n", channel); | |
242 | ||
6bd08127 JM |
243 | local_irq_save(flags); |
244 | ||
245 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
246 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); | |
247 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | | |
248 | CCR_ACRPT, DMA_CCR(channel)); | |
249 | ||
250 | if ((cpu_is_mx21() || cpu_is_mx27()) && | |
2d9c2fc5 | 251 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
252 | d->sg = sg_next(d->sg); |
253 | if (d->sg) { | |
6bd08127 | 254 | u32 tmp; |
a6cbb2d8 | 255 | imxdma_sg_next(d); |
6bd08127 JM |
256 | tmp = imx_dmav1_readl(DMA_CCR(channel)); |
257 | imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, | |
258 | DMA_CCR(channel)); | |
259 | } | |
260 | } | |
6bd08127 JM |
261 | |
262 | local_irq_restore(flags); | |
263 | } | |
264 | ||
265 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
266 | { | |
267 | int channel = imxdmac->channel; | |
268 | unsigned long flags; | |
269 | ||
270 | pr_debug("imxdma%d: imx_dma_disable\n", channel); | |
271 | ||
2d9c2fc5 JM |
272 | if (imxdma_hw_chain(imxdmac)) |
273 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
274 | |
275 | local_irq_save(flags); | |
276 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); | |
277 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, | |
278 | DMA_CCR(channel)); | |
279 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
6bd08127 JM |
280 | local_irq_restore(flags); |
281 | } | |
282 | ||
6bd08127 | 283 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 284 | { |
6bd08127 JM |
285 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
286 | int channel = imxdmac->channel; | |
1f1846c6 | 287 | |
6bd08127 | 288 | imx_dmav1_writel(0, DMA_CCR(channel)); |
6bd08127 JM |
289 | |
290 | /* Tasklet watchdog error handler */ | |
9e15db7c | 291 | tasklet_schedule(&imxdmac->dma_tasklet); |
6bd08127 JM |
292 | pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel); |
293 | } | |
294 | ||
295 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) | |
296 | { | |
297 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
298 | unsigned int err_mask; |
299 | int i, disr; | |
300 | int errcode; | |
301 | ||
302 | disr = imx_dmav1_readl(DMA_DISR); | |
303 | ||
304 | err_mask = imx_dmav1_readl(DMA_DBTOSR) | | |
305 | imx_dmav1_readl(DMA_DRTOSR) | | |
306 | imx_dmav1_readl(DMA_DSESR) | | |
307 | imx_dmav1_readl(DMA_DBOSR); | |
308 | ||
309 | if (!err_mask) | |
310 | return IRQ_HANDLED; | |
311 | ||
312 | imx_dmav1_writel(disr & err_mask, DMA_DISR); | |
313 | ||
314 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
315 | if (!(err_mask & (1 << i))) | |
316 | continue; | |
6bd08127 JM |
317 | errcode = 0; |
318 | ||
319 | if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { | |
320 | imx_dmav1_writel(1 << i, DMA_DBTOSR); | |
321 | errcode |= IMX_DMA_ERR_BURST; | |
322 | } | |
323 | if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { | |
324 | imx_dmav1_writel(1 << i, DMA_DRTOSR); | |
325 | errcode |= IMX_DMA_ERR_REQUEST; | |
326 | } | |
327 | if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { | |
328 | imx_dmav1_writel(1 << i, DMA_DSESR); | |
329 | errcode |= IMX_DMA_ERR_TRANSFER; | |
330 | } | |
331 | if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { | |
332 | imx_dmav1_writel(1 << i, DMA_DBOSR); | |
333 | errcode |= IMX_DMA_ERR_BUFFER; | |
334 | } | |
335 | /* Tasklet error handler */ | |
336 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
337 | ||
338 | printk(KERN_WARNING | |
339 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
340 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
341 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
342 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
343 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
344 | } | |
345 | return IRQ_HANDLED; | |
1f1846c6 SH |
346 | } |
347 | ||
6bd08127 | 348 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 349 | { |
6bd08127 | 350 | int chno = imxdmac->channel; |
2efc3449 | 351 | struct imxdma_desc *desc; |
6bd08127 | 352 | |
833bc03b JM |
353 | spin_lock(&imxdmac->lock); |
354 | if (list_empty(&imxdmac->ld_active)) { | |
355 | spin_unlock(&imxdmac->lock); | |
356 | goto out; | |
357 | } | |
2efc3449 | 358 | |
833bc03b JM |
359 | desc = list_first_entry(&imxdmac->ld_active, |
360 | struct imxdma_desc, | |
361 | node); | |
362 | spin_unlock(&imxdmac->lock); | |
2efc3449 | 363 | |
833bc03b JM |
364 | if (desc->sg) { |
365 | u32 tmp; | |
366 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 367 | |
833bc03b | 368 | if (desc->sg) { |
a6cbb2d8 | 369 | imxdma_sg_next(desc); |
6bd08127 JM |
370 | |
371 | tmp = imx_dmav1_readl(DMA_CCR(chno)); | |
372 | ||
2d9c2fc5 | 373 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
374 | /* FIXME: The timeout should probably be |
375 | * configurable | |
376 | */ | |
2d9c2fc5 | 377 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
378 | jiffies + msecs_to_jiffies(500)); |
379 | ||
380 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
381 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
382 | } else { | |
383 | imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); | |
384 | tmp |= CCR_CEN; | |
385 | } | |
386 | ||
387 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
388 | ||
389 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
390 | /* Tasklet progression */ | |
391 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 392 | |
6bd08127 JM |
393 | return; |
394 | } | |
395 | ||
2d9c2fc5 JM |
396 | if (imxdma_hw_chain(imxdmac)) { |
397 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
398 | return; |
399 | } | |
400 | } | |
401 | ||
2efc3449 | 402 | out: |
6bd08127 | 403 | imx_dmav1_writel(0, DMA_CCR(chno)); |
6bd08127 | 404 | /* Tasklet irq */ |
9e15db7c JM |
405 | tasklet_schedule(&imxdmac->dma_tasklet); |
406 | } | |
407 | ||
6bd08127 JM |
408 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
409 | { | |
410 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
411 | int i, disr; |
412 | ||
413 | if (cpu_is_mx21() || cpu_is_mx27()) | |
414 | imxdma_err_handler(irq, dev_id); | |
415 | ||
416 | disr = imx_dmav1_readl(DMA_DISR); | |
417 | ||
418 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", | |
419 | disr); | |
420 | ||
421 | imx_dmav1_writel(disr, DMA_DISR); | |
422 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
2d9c2fc5 | 423 | if (disr & (1 << i)) |
6bd08127 | 424 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
425 | } |
426 | ||
427 | return IRQ_HANDLED; | |
428 | } | |
429 | ||
9e15db7c JM |
430 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
431 | { | |
432 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 433 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
434 | |
435 | /* Configure and enable */ | |
436 | switch (d->type) { | |
437 | case IMXDMA_DESC_MEMCPY: | |
3b4b6dfc JM |
438 | imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel)); |
439 | imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel)); | |
440 | imx_dmav1_writel(d->config_mem | (d->config_port << 2), | |
441 | DMA_CCR(imxdmac->channel)); | |
6bd08127 | 442 | |
3b4b6dfc JM |
443 | imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel)); |
444 | ||
445 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
446 | "dma_length=%d\n", __func__, imxdmac->channel, | |
447 | d->dest, d->src, d->len); | |
448 | ||
449 | break; | |
6bd08127 | 450 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 451 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 452 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 JM |
453 | if (d->direction == DMA_DEV_TO_MEM) { |
454 | imx_dmav1_writel(imxdmac->per_address, | |
455 | DMA_SAR(imxdmac->channel)); | |
456 | imx_dmav1_writel(imxdmac->ccr_from_device, | |
457 | DMA_CCR(imxdmac->channel)); | |
458 | ||
459 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
460 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
461 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
462 | d->len, imxdmac->per_address); | |
463 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
464 | imx_dmav1_writel(imxdmac->per_address, | |
465 | DMA_DAR(imxdmac->channel)); | |
466 | imx_dmav1_writel(imxdmac->ccr_to_device, | |
467 | DMA_CCR(imxdmac->channel)); | |
468 | ||
469 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
470 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
471 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
472 | d->len, imxdmac->per_address); | |
473 | } else { | |
474 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
475 | __func__, imxdmac->channel); | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
a6cbb2d8 | 479 | imxdma_sg_next(d); |
359291a1 | 480 | |
9e15db7c JM |
481 | break; |
482 | default: | |
483 | return -EINVAL; | |
484 | } | |
2efc3449 | 485 | imxdma_enable_hw(d); |
9e15db7c JM |
486 | return 0; |
487 | } | |
488 | ||
489 | static void imxdma_tasklet(unsigned long data) | |
490 | { | |
491 | struct imxdma_channel *imxdmac = (void *)data; | |
492 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
493 | struct imxdma_desc *desc; | |
494 | ||
495 | spin_lock(&imxdmac->lock); | |
496 | ||
497 | if (list_empty(&imxdmac->ld_active)) { | |
498 | /* Someone might have called terminate all */ | |
499 | goto out; | |
500 | } | |
501 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
502 | ||
503 | if (desc->desc.callback) | |
504 | desc->desc.callback(desc->desc.callback_param); | |
505 | ||
1f3d6dc0 | 506 | dma_cookie_complete(&desc->desc); |
9e15db7c JM |
507 | |
508 | /* If we are dealing with a cyclic descriptor keep it on ld_active */ | |
509 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
510 | goto out; | |
511 | ||
512 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); | |
513 | ||
514 | if (!list_empty(&imxdmac->ld_queue)) { | |
515 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
516 | node); | |
517 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
518 | if (imxdma_xfer_desc(desc) < 0) | |
519 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
520 | __func__, imxdmac->channel); | |
521 | } | |
522 | out: | |
523 | spin_unlock(&imxdmac->lock); | |
1f1846c6 SH |
524 | } |
525 | ||
526 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
527 | unsigned long arg) | |
528 | { | |
529 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
530 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
9e15db7c | 531 | unsigned long flags; |
1f1846c6 SH |
532 | unsigned int mode = 0; |
533 | ||
534 | switch (cmd) { | |
535 | case DMA_TERMINATE_ALL: | |
6bd08127 | 536 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
537 | |
538 | spin_lock_irqsave(&imxdmac->lock, flags); | |
539 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
540 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
541 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
542 | return 0; |
543 | case DMA_SLAVE_CONFIG: | |
db8196df | 544 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
545 | imxdmac->per_address = dmaengine_cfg->src_addr; |
546 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
547 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
548 | } else { | |
549 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
550 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
551 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
552 | } | |
553 | ||
554 | switch (imxdmac->word_size) { | |
555 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
556 | mode = IMX_DMA_MEMSIZE_8; | |
557 | break; | |
558 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
559 | mode = IMX_DMA_MEMSIZE_16; | |
560 | break; | |
561 | default: | |
562 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
563 | mode = IMX_DMA_MEMSIZE_32; | |
564 | break; | |
565 | } | |
1f1846c6 | 566 | |
2d9c2fc5 JM |
567 | imxdmac->hw_chaining = 1; |
568 | if (!imxdma_hw_chain(imxdmac)) | |
bdc0c753 | 569 | return -EINVAL; |
359291a1 | 570 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
571 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
572 | CCR_REN; | |
359291a1 | 573 | imxdmac->ccr_to_device = |
bdc0c753 JM |
574 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
575 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
576 | imx_dmav1_writel(imxdmac->dma_request, | |
577 | DMA_RSSR(imxdmac->channel)); | |
578 | ||
6bd08127 JM |
579 | /* Set burst length */ |
580 | imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size, | |
581 | DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
582 | |
583 | return 0; | |
584 | default: | |
585 | return -ENOSYS; | |
586 | } | |
587 | ||
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
592 | dma_cookie_t cookie, | |
593 | struct dma_tx_state *txstate) | |
594 | { | |
96a2af41 | 595 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
596 | } |
597 | ||
598 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
599 | { | |
600 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
601 | dma_cookie_t cookie; | |
9e15db7c | 602 | unsigned long flags; |
1f1846c6 | 603 | |
9e15db7c | 604 | spin_lock_irqsave(&imxdmac->lock, flags); |
884485e1 | 605 | cookie = dma_cookie_assign(tx); |
9e15db7c | 606 | spin_unlock_irqrestore(&imxdmac->lock, flags); |
1f1846c6 SH |
607 | |
608 | return cookie; | |
609 | } | |
610 | ||
611 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
612 | { | |
613 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
614 | struct imx_dma_data *data = chan->private; | |
615 | ||
6c05f091 JM |
616 | if (data != NULL) |
617 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 618 | |
9e15db7c JM |
619 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
620 | struct imxdma_desc *desc; | |
1f1846c6 | 621 | |
9e15db7c JM |
622 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
623 | if (!desc) | |
624 | break; | |
625 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
626 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
627 | desc->desc.tx_submit = imxdma_tx_submit; | |
628 | /* txd.flags will be overwritten in prep funcs */ | |
629 | desc->desc.flags = DMA_CTRL_ACK; | |
630 | desc->status = DMA_SUCCESS; | |
631 | ||
632 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
633 | imxdmac->descs_allocated++; | |
634 | } | |
1f1846c6 | 635 | |
9e15db7c JM |
636 | if (!imxdmac->descs_allocated) |
637 | return -ENOMEM; | |
638 | ||
639 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
640 | } |
641 | ||
642 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
643 | { | |
644 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
9e15db7c JM |
645 | struct imxdma_desc *desc, *_desc; |
646 | unsigned long flags; | |
647 | ||
648 | spin_lock_irqsave(&imxdmac->lock, flags); | |
1f1846c6 | 649 | |
6bd08127 | 650 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
651 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
652 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
653 | ||
654 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
655 | ||
656 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
657 | kfree(desc); | |
658 | imxdmac->descs_allocated--; | |
659 | } | |
660 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
661 | |
662 | if (imxdmac->sg_list) { | |
663 | kfree(imxdmac->sg_list); | |
664 | imxdmac->sg_list = NULL; | |
665 | } | |
666 | } | |
667 | ||
668 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
669 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 670 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 671 | unsigned long flags, void *context) |
1f1846c6 SH |
672 | { |
673 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
674 | struct scatterlist *sg; | |
9e15db7c JM |
675 | int i, dma_length = 0; |
676 | struct imxdma_desc *desc; | |
1f1846c6 | 677 | |
9e15db7c JM |
678 | if (list_empty(&imxdmac->ld_free) || |
679 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
680 | return NULL; |
681 | ||
9e15db7c | 682 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
683 | |
684 | for_each_sg(sgl, sg, sg_len, i) { | |
685 | dma_length += sg->length; | |
686 | } | |
687 | ||
d07102a1 SH |
688 | switch (imxdmac->word_size) { |
689 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
690 | if (sgl->length & 3 || sgl->dma_address & 3) | |
691 | return NULL; | |
692 | break; | |
693 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
694 | if (sgl->length & 1 || sgl->dma_address & 1) | |
695 | return NULL; | |
696 | break; | |
697 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
698 | break; | |
699 | default: | |
700 | return NULL; | |
701 | } | |
702 | ||
9e15db7c JM |
703 | desc->type = IMXDMA_DESC_SLAVE_SG; |
704 | desc->sg = sgl; | |
705 | desc->sgcount = sg_len; | |
706 | desc->len = dma_length; | |
2efc3449 | 707 | desc->direction = direction; |
9e15db7c | 708 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
709 | desc->src = imxdmac->per_address; |
710 | } else { | |
9e15db7c JM |
711 | desc->dest = imxdmac->per_address; |
712 | } | |
713 | desc->desc.callback = NULL; | |
714 | desc->desc.callback_param = NULL; | |
1f1846c6 | 715 | |
9e15db7c | 716 | return &desc->desc; |
1f1846c6 SH |
717 | } |
718 | ||
719 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
720 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f AB |
721 | size_t period_len, enum dma_transfer_direction direction, |
722 | void *context) | |
1f1846c6 SH |
723 | { |
724 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
725 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
726 | struct imxdma_desc *desc; |
727 | int i; | |
1f1846c6 | 728 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
729 | |
730 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
731 | __func__, imxdmac->channel, buf_len, period_len); | |
732 | ||
9e15db7c JM |
733 | if (list_empty(&imxdmac->ld_free) || |
734 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 735 | return NULL; |
1f1846c6 | 736 | |
9e15db7c | 737 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
738 | |
739 | if (imxdmac->sg_list) | |
740 | kfree(imxdmac->sg_list); | |
741 | ||
742 | imxdmac->sg_list = kcalloc(periods + 1, | |
743 | sizeof(struct scatterlist), GFP_KERNEL); | |
744 | if (!imxdmac->sg_list) | |
745 | return NULL; | |
746 | ||
747 | sg_init_table(imxdmac->sg_list, periods); | |
748 | ||
749 | for (i = 0; i < periods; i++) { | |
750 | imxdmac->sg_list[i].page_link = 0; | |
751 | imxdmac->sg_list[i].offset = 0; | |
752 | imxdmac->sg_list[i].dma_address = dma_addr; | |
753 | imxdmac->sg_list[i].length = period_len; | |
754 | dma_addr += period_len; | |
755 | } | |
756 | ||
757 | /* close the loop */ | |
758 | imxdmac->sg_list[periods].offset = 0; | |
759 | imxdmac->sg_list[periods].length = 0; | |
760 | imxdmac->sg_list[periods].page_link = | |
761 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
762 | ||
9e15db7c JM |
763 | desc->type = IMXDMA_DESC_CYCLIC; |
764 | desc->sg = imxdmac->sg_list; | |
765 | desc->sgcount = periods; | |
766 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 767 | desc->direction = direction; |
9e15db7c | 768 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
769 | desc->src = imxdmac->per_address; |
770 | } else { | |
9e15db7c JM |
771 | desc->dest = imxdmac->per_address; |
772 | } | |
773 | desc->desc.callback = NULL; | |
774 | desc->desc.callback_param = NULL; | |
1f1846c6 | 775 | |
9e15db7c | 776 | return &desc->desc; |
1f1846c6 SH |
777 | } |
778 | ||
6c05f091 JM |
779 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
780 | struct dma_chan *chan, dma_addr_t dest, | |
781 | dma_addr_t src, size_t len, unsigned long flags) | |
782 | { | |
783 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
784 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 785 | struct imxdma_desc *desc; |
6c05f091 JM |
786 | |
787 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", | |
788 | __func__, imxdmac->channel, src, dest, len); | |
789 | ||
9e15db7c JM |
790 | if (list_empty(&imxdmac->ld_free) || |
791 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
6c05f091 | 792 | return NULL; |
6c05f091 | 793 | |
9e15db7c | 794 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 795 | |
9e15db7c JM |
796 | desc->type = IMXDMA_DESC_MEMCPY; |
797 | desc->src = src; | |
798 | desc->dest = dest; | |
799 | desc->len = len; | |
2efc3449 | 800 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
801 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
802 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
803 | desc->desc.callback = NULL; | |
804 | desc->desc.callback_param = NULL; | |
6c05f091 | 805 | |
9e15db7c | 806 | return &desc->desc; |
6c05f091 JM |
807 | } |
808 | ||
1f1846c6 SH |
809 | static void imxdma_issue_pending(struct dma_chan *chan) |
810 | { | |
5b316876 | 811 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
812 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
813 | struct imxdma_desc *desc; | |
814 | unsigned long flags; | |
815 | ||
816 | spin_lock_irqsave(&imxdmac->lock, flags); | |
817 | if (list_empty(&imxdmac->ld_active) && | |
818 | !list_empty(&imxdmac->ld_queue)) { | |
819 | desc = list_first_entry(&imxdmac->ld_queue, | |
820 | struct imxdma_desc, node); | |
821 | ||
822 | if (imxdma_xfer_desc(desc) < 0) { | |
823 | dev_warn(imxdma->dev, | |
824 | "%s: channel: %d couldn't issue DMA xfer\n", | |
825 | __func__, imxdmac->channel); | |
826 | } else { | |
827 | list_move_tail(imxdmac->ld_queue.next, | |
828 | &imxdmac->ld_active); | |
829 | } | |
830 | } | |
831 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
832 | } |
833 | ||
834 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 835 | { |
1f1846c6 SH |
836 | struct imxdma_engine *imxdma; |
837 | int ret, i; | |
838 | ||
6bd08127 JM |
839 | if (cpu_is_mx1()) |
840 | imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); | |
841 | else if (cpu_is_mx21()) | |
842 | imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); | |
843 | else if (cpu_is_mx27()) | |
844 | imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); | |
845 | else | |
846 | return 0; | |
847 | ||
848 | dma_clk = clk_get(NULL, "dma"); | |
849 | if (IS_ERR(dma_clk)) | |
850 | return PTR_ERR(dma_clk); | |
851 | clk_enable(dma_clk); | |
852 | ||
853 | /* reset DMA module */ | |
854 | imx_dmav1_writel(DCR_DRST, DMA_DCR); | |
855 | ||
856 | if (cpu_is_mx1()) { | |
857 | ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma); | |
858 | if (ret) { | |
859 | pr_crit("Can't register IRQ for DMA\n"); | |
860 | return ret; | |
861 | } | |
862 | ||
863 | ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma); | |
864 | if (ret) { | |
865 | pr_crit("Can't register ERRIRQ for DMA\n"); | |
866 | free_irq(MX1_DMA_INT, NULL); | |
867 | return ret; | |
868 | } | |
869 | } | |
870 | ||
871 | /* enable DMA module */ | |
872 | imx_dmav1_writel(DCR_DEN, DMA_DCR); | |
873 | ||
874 | /* clear all interrupts */ | |
875 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); | |
876 | ||
877 | /* disable interrupts */ | |
878 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); | |
879 | ||
1f1846c6 SH |
880 | imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); |
881 | if (!imxdma) | |
882 | return -ENOMEM; | |
883 | ||
884 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
885 | ||
f8a356ff SH |
886 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
887 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 888 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f8a356ff | 889 | |
1f1846c6 | 890 | /* Initialize channel parameters */ |
6bd08127 | 891 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 | 892 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
2d9c2fc5 | 893 | |
6bd08127 JM |
894 | if (cpu_is_mx21() || cpu_is_mx27()) { |
895 | ret = request_irq(MX2x_INT_DMACH0 + i, | |
896 | dma_irq_handler, 0, "DMA", imxdma); | |
897 | if (ret) { | |
898 | pr_crit("Can't register IRQ %d for DMA channel %d\n", | |
899 | MX2x_INT_DMACH0 + i, i); | |
900 | goto err_init; | |
901 | } | |
2d9c2fc5 JM |
902 | init_timer(&imxdmac->watchdog); |
903 | imxdmac->watchdog.function = &imxdma_watchdog; | |
904 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 905 | } |
1f1846c6 | 906 | |
1f1846c6 SH |
907 | imxdmac->imxdma = imxdma; |
908 | spin_lock_init(&imxdmac->lock); | |
909 | ||
9e15db7c JM |
910 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
911 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
912 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
913 | ||
914 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
915 | (unsigned long)imxdmac); | |
1f1846c6 | 916 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 917 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
918 | imxdmac->channel = i; |
919 | ||
920 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
921 | list_add_tail(&imxdmac->chan.device_node, |
922 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
923 | } |
924 | ||
925 | imxdma->dev = &pdev->dev; | |
926 | imxdma->dma_device.dev = &pdev->dev; | |
927 | ||
928 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
929 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
930 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
931 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
932 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 933 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
1f1846c6 SH |
934 | imxdma->dma_device.device_control = imxdma_control; |
935 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
936 | ||
937 | platform_set_drvdata(pdev, imxdma); | |
938 | ||
6c05f091 | 939 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
940 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
941 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
942 | ||
1f1846c6 SH |
943 | ret = dma_async_device_register(&imxdma->dma_device); |
944 | if (ret) { | |
945 | dev_err(&pdev->dev, "unable to register\n"); | |
946 | goto err_init; | |
947 | } | |
948 | ||
949 | return 0; | |
950 | ||
951 | err_init: | |
6bd08127 JM |
952 | |
953 | if (cpu_is_mx21() || cpu_is_mx27()) { | |
954 | while (--i >= 0) | |
955 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
956 | } else if cpu_is_mx1() { | |
957 | free_irq(MX1_DMA_INT, NULL); | |
958 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
959 | } |
960 | ||
961 | kfree(imxdma); | |
962 | return ret; | |
963 | } | |
964 | ||
965 | static int __exit imxdma_remove(struct platform_device *pdev) | |
966 | { | |
967 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
968 | int i; | |
969 | ||
970 | dma_async_device_unregister(&imxdma->dma_device); | |
971 | ||
6bd08127 JM |
972 | if (cpu_is_mx21() || cpu_is_mx27()) { |
973 | for (i = 0; i < IMX_DMA_CHANNELS; i++) | |
974 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
975 | } else if cpu_is_mx1() { | |
976 | free_irq(MX1_DMA_INT, NULL); | |
977 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
978 | } |
979 | ||
980 | kfree(imxdma); | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | static struct platform_driver imxdma_driver = { | |
986 | .driver = { | |
987 | .name = "imx-dma", | |
988 | }, | |
989 | .remove = __exit_p(imxdma_remove), | |
990 | }; | |
991 | ||
992 | static int __init imxdma_module_init(void) | |
993 | { | |
994 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
995 | } | |
996 | subsys_initcall(imxdma_module_init); | |
997 | ||
998 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
999 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1000 | MODULE_LICENSE("GPL"); |