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dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[deliverable/linux.git] / drivers / dma / imx-dma.c
CommitLineData
1f1846c6
SH		 1/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9e15db7c 8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
1f1846c6
SH		 9 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17#include <linux/init.h>
f8de8f4c 18#include <linux/module.h>
1f1846c6
SH		 19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
6bd08127 27#include <linux/clk.h>
1f1846c6 28#include <linux/dmaengine.h>
5170c051 29#include <linux/module.h>
1f1846c6
SH		 30
31#include <asm/irq.h>
6bd08127 32#include <mach/dma.h>
1f1846c6
SH		 33#include <mach/hardware.h>
34
d2ebfb33 35#include "dmaengine.h"
9e15db7c 36#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
6bd08127
JM		 37#define IMX_DMA_CHANNELS 16
38
6bd08127
JM		 39#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
40#define IMX_DMA_MEMSIZE_32 (0 << 4)
41#define IMX_DMA_MEMSIZE_8 (1 << 4)
42#define IMX_DMA_MEMSIZE_16 (2 << 4)
43#define IMX_DMA_TYPE_LINEAR (0 << 10)
44#define IMX_DMA_TYPE_2D (1 << 10)
45#define IMX_DMA_TYPE_FIFO (2 << 10)
46
47#define IMX_DMA_ERR_BURST (1 << 0)
48#define IMX_DMA_ERR_REQUEST (1 << 1)
49#define IMX_DMA_ERR_TRANSFER (1 << 2)
50#define IMX_DMA_ERR_BUFFER (1 << 3)
51#define IMX_DMA_ERR_TIMEOUT (1 << 4)
52
53#define DMA_DCR 0x00 /* Control Register */
54#define DMA_DISR 0x04 /* Interrupt status Register */
55#define DMA_DIMR 0x08 /* Interrupt mask Register */
56#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
57#define DMA_DRTOSR 0x10 /* Request timeout Register */
58#define DMA_DSESR 0x14 /* Transfer Error Status Register */
59#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
60#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
61#define DMA_WSRA 0x40 /* W-Size Register A */
62#define DMA_XSRA 0x44 /* X-Size Register A */
63#define DMA_YSRA 0x48 /* Y-Size Register A */
64#define DMA_WSRB 0x4c /* W-Size Register B */
65#define DMA_XSRB 0x50 /* X-Size Register B */
66#define DMA_YSRB 0x54 /* Y-Size Register B */
67#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
68#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
69#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
70#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
71#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
72#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
73#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
74#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
75#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
76
77#define DCR_DRST (1<<1)
78#define DCR_DEN (1<<0)
79#define DBTOCR_EN (1<<15)
80#define DBTOCR_CNT(x) ((x) & 0x7fff)
81#define CNTR_CNT(x) ((x) & 0xffffff)
82#define CCR_ACRPT (1<<14)
83#define CCR_DMOD_LINEAR (0x0 << 12)
84#define CCR_DMOD_2D (0x1 << 12)
85#define CCR_DMOD_FIFO (0x2 << 12)
86#define CCR_DMOD_EOBFIFO (0x3 << 12)
87#define CCR_SMOD_LINEAR (0x0 << 10)
88#define CCR_SMOD_2D (0x1 << 10)
89#define CCR_SMOD_FIFO (0x2 << 10)
90#define CCR_SMOD_EOBFIFO (0x3 << 10)
91#define CCR_MDIR_DEC (1<<9)
92#define CCR_MSEL_B (1<<8)
93#define CCR_DSIZ_32 (0x0 << 6)
94#define CCR_DSIZ_8 (0x1 << 6)
95#define CCR_DSIZ_16 (0x2 << 6)
96#define CCR_SSIZ_32 (0x0 << 4)
97#define CCR_SSIZ_8 (0x1 << 4)
98#define CCR_SSIZ_16 (0x2 << 4)
99#define CCR_REN (1<<3)
100#define CCR_RPT (1<<2)
101#define CCR_FRC (1<<1)
102#define CCR_CEN (1<<0)
103#define RTOR_EN (1<<15)
104#define RTOR_CLK (1<<14)
105#define RTOR_PSC (1<<13)
9e15db7c
JM		 106
107enum imxdma_prep_type {
108 IMXDMA_DESC_MEMCPY,
109 IMXDMA_DESC_INTERLEAVED,
110 IMXDMA_DESC_SLAVE_SG,
111 IMXDMA_DESC_CYCLIC,
112};
113
6bd08127
JM		 114/*
115 * struct imxdma_channel_internal - i.MX specific DMA extension
116 * @name: name specified by DMA client
117 * @irq_handler: client callback for end of transfer
118 * @err_handler: client callback for error condition
119 * @data: clients context data for callbacks
120 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
121 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
122 * @resbytes: total residual number of bytes to transfer
123 * (it can be lower or same as sum of SG mapped chunk sizes)
124 * @sgcount: number of chunks to be read/written
125 *
126 * Structure is used for IMX DMA processing. It would be probably good
127 * @struct dma_struct in the future for external interfacing and use
128 * @struct imxdma_channel_internal only as extension to it.
129 */
130
131struct imxdma_channel_internal {
6bd08127
JM		 132 struct scatterlist *sg;
133 unsigned int resbytes;
134
135 int in_use;
136
137 u32 ccr_from_device;
138 u32 ccr_to_device;
139
140 struct timer_list watchdog;
141
142 int hw_chaining;
143};
144
9e15db7c
JM		 145struct imxdma_desc {
146 struct list_head node;
147 struct dma_async_tx_descriptor desc;
148 enum dma_status status;
149 dma_addr_t src;
150 dma_addr_t dest;
151 size_t len;
2efc3449 152 enum dma_transfer_direction direction;
9e15db7c
JM		 153 enum imxdma_prep_type type;
154 /* For memcpy and interleaved */
155 unsigned int config_port;
156 unsigned int config_mem;
157 /* For interleaved transfers */
158 unsigned int x;
159 unsigned int y;
160 unsigned int w;
161 /* For slave sg and cyclic */
162 struct scatterlist *sg;
163 unsigned int sgcount;
164};
165
1f1846c6 166struct imxdma_channel {
6bd08127 167 struct imxdma_channel_internal internal;
1f1846c6
SH		 168 struct imxdma_engine *imxdma;
169 unsigned int channel;
1f1846c6 170
9e15db7c
JM		 171 struct tasklet_struct dma_tasklet;
172 struct list_head ld_free;
173 struct list_head ld_queue;
174 struct list_head ld_active;
175 int descs_allocated;
1f1846c6
SH		 176 enum dma_slave_buswidth word_size;
177 dma_addr_t per_address;
178 u32 watermark_level;
179 struct dma_chan chan;
180 spinlock_t lock;
181 struct dma_async_tx_descriptor desc;
1f1846c6
SH		 182 enum dma_status status;
183 int dma_request;
184 struct scatterlist *sg_list;
185};
186
1f1846c6
SH		 187struct imxdma_engine {
188 struct device *dev;
1e070a60 189 struct device_dma_parameters dma_parms;
1f1846c6 190 struct dma_device dma_device;
6bd08127 191 struct imxdma_channel channel[IMX_DMA_CHANNELS];
1f1846c6
SH		 192};
193
194static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
195{
196 return container_of(chan, struct imxdma_channel, chan);
197}
198
9e15db7c 199static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
1f1846c6 200{
9e15db7c
JM		 201 struct imxdma_desc *desc;
202
203 if (!list_empty(&imxdmac->ld_active)) {
204 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
205 node);
206 if (desc->type == IMXDMA_DESC_CYCLIC)
207 return true;
208 }
209 return false;
1f1846c6
SH		 210}
211
6bd08127
JM		 212/* TODO: put this inside any struct */
213static void __iomem *imx_dmav1_baseaddr;
214static struct clk *dma_clk;
215
216static void imx_dmav1_writel(unsigned val, unsigned offset)
217{
218 __raw_writel(val, imx_dmav1_baseaddr + offset);
219}
220
221static unsigned imx_dmav1_readl(unsigned offset)
1f1846c6 222{
6bd08127
JM		 223 return __raw_readl(imx_dmav1_baseaddr + offset);
224}
1f1846c6 225
6bd08127
JM		 226static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
227{
228 if (cpu_is_mx27())
229 return imxdma->hw_chaining;
230 else
231 return 0;
232}
233
234/*
235 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
236 */
2efc3449 237static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
6bd08127 238{
2efc3449 239 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 240 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
241 unsigned long now;
242
243 now = min(imxdma->resbytes, sg->length);
244 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
245 imxdma->resbytes -= now;
246
2efc3449 247 if (d->direction == DMA_DEV_TO_MEM)
6bd08127
JM		 248 imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
249 else
250 imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
251
252 imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
253
254 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
255 "size 0x%08x\n", imxdmac->channel,
256 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
257 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
258 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
259
260 return now;
261}
262
2efc3449 263static void imxdma_enable_hw(struct imxdma_desc *d)
6bd08127 264{
2efc3449 265 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 266 int channel = imxdmac->channel;
267 unsigned long flags;
268
269 pr_debug("imxdma%d: imx_dma_enable\n", channel);
270
271 if (imxdmac->internal.in_use)
272 return;
273
274 local_irq_save(flags);
275
276 imx_dmav1_writel(1 << channel, DMA_DISR);
277 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
278 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
279 CCR_ACRPT, DMA_CCR(channel));
280
281 if ((cpu_is_mx21() || cpu_is_mx27()) &&
282 imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
283 imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
284 if (imxdmac->internal.sg) {
285 u32 tmp;
2efc3449 286 imxdma_sg_next(d, imxdmac->internal.sg);
6bd08127
JM		 287 tmp = imx_dmav1_readl(DMA_CCR(channel));
288 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
289 DMA_CCR(channel));
290 }
291 }
292 imxdmac->internal.in_use = 1;
293
294 local_irq_restore(flags);
295}
296
297static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
298{
299 int channel = imxdmac->channel;
300 unsigned long flags;
301
302 pr_debug("imxdma%d: imx_dma_disable\n", channel);
303
304 if (imxdma_hw_chain(&imxdmac->internal))
305 del_timer(&imxdmac->internal.watchdog);
306
307 local_irq_save(flags);
308 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
309 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
310 DMA_CCR(channel));
311 imx_dmav1_writel(1 << channel, DMA_DISR);
312 imxdmac->internal.in_use = 0;
313 local_irq_restore(flags);
314}
315
6bd08127 316static int
2efc3449 317imxdma_setup_sg_hw(struct imxdma_desc *d,
6bd08127
JM		 318 struct scatterlist *sg, unsigned int sgcount,
319 unsigned int dma_length, unsigned int dev_addr,
2efc3449 320 enum dma_transfer_direction direction)
6bd08127 321{
2efc3449 322 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
6bd08127
JM		 323 int channel = imxdmac->channel;
324
325 if (imxdmac->internal.in_use)
326 return -EBUSY;
327
328 imxdmac->internal.sg = sg;
6bd08127
JM		 329 imxdmac->internal.resbytes = dma_length;
330
331 if (!sg || !sgcount) {
332 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
333 channel);
334 return -EINVAL;
335 }
336
337 if (!sg->length) {
338 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
339 channel);
340 return -EINVAL;
341 }
342
2efc3449 343 if (direction == DMA_DEV_TO_MEM) {
6bd08127
JM		 344 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
345 "dev_addr=0x%08x for read\n",
346 channel, __func__, sg, sgcount, dma_length, dev_addr);
347
348 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
349 imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
2efc3449 350 } else if (direction == DMA_MEM_TO_DEV) {
6bd08127
JM		 351 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
352 "dev_addr=0x%08x for write\n",
353 channel, __func__, sg, sgcount, dma_length, dev_addr);
354
355 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
356 imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
357 } else {
358 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
359 channel);
360 return -EINVAL;
361 }
362
2efc3449 363 imxdma_sg_next(d, sg);
6bd08127
JM		 364
365 return 0;
1f1846c6
SH		 366}
367
6bd08127 368static void imxdma_watchdog(unsigned long data)
1f1846c6 369{
6bd08127
JM		 370 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
371 int channel = imxdmac->channel;
1f1846c6 372
6bd08127
JM		 373 imx_dmav1_writel(0, DMA_CCR(channel));
374 imxdmac->internal.in_use = 0;
375 imxdmac->internal.sg = NULL;
376
377 /* Tasklet watchdog error handler */
9e15db7c 378 tasklet_schedule(&imxdmac->dma_tasklet);
6bd08127
JM		 379 pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
380}
381
382static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
383{
384 struct imxdma_engine *imxdma = dev_id;
385 struct imxdma_channel_internal *internal;
386 unsigned int err_mask;
387 int i, disr;
388 int errcode;
389
390 disr = imx_dmav1_readl(DMA_DISR);
391
392 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
393 imx_dmav1_readl(DMA_DRTOSR) |
394 imx_dmav1_readl(DMA_DSESR) |
395 imx_dmav1_readl(DMA_DBOSR);
396
397 if (!err_mask)
398 return IRQ_HANDLED;
399
400 imx_dmav1_writel(disr & err_mask, DMA_DISR);
401
402 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
403 if (!(err_mask & (1 << i)))
404 continue;
405 internal = &imxdma->channel[i].internal;
406 errcode = 0;
407
408 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
409 imx_dmav1_writel(1 << i, DMA_DBTOSR);
410 errcode |= IMX_DMA_ERR_BURST;
411 }
412 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
413 imx_dmav1_writel(1 << i, DMA_DRTOSR);
414 errcode |= IMX_DMA_ERR_REQUEST;
415 }
416 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
417 imx_dmav1_writel(1 << i, DMA_DSESR);
418 errcode |= IMX_DMA_ERR_TRANSFER;
419 }
420 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
421 imx_dmav1_writel(1 << i, DMA_DBOSR);
422 errcode |= IMX_DMA_ERR_BUFFER;
423 }
424 /* Tasklet error handler */
425 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
426
427 printk(KERN_WARNING
428 "DMA timeout on channel %d -%s%s%s%s\n", i,
429 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
430 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
431 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
432 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
433 }
434 return IRQ_HANDLED;
1f1846c6
SH		 435}
436
6bd08127 437static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
1f1846c6 438{
6bd08127
JM		 439 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
440 int chno = imxdmac->channel;
2efc3449 441 struct imxdma_desc *desc;
6bd08127
JM		 442
443 if (imxdma->sg) {
444 u32 tmp;
445 imxdma->sg = sg_next(imxdma->sg);
446
447 if (imxdma->sg) {
2efc3449
JM		 448
449 spin_lock(&imxdmac->lock);
450 if (list_empty(&imxdmac->ld_active)) {
451 spin_unlock(&imxdmac->lock);
452 goto out;
453 }
454
455 desc = list_first_entry(&imxdmac->ld_active,
456 struct imxdma_desc,
457 node);
458 spin_unlock(&imxdmac->lock);
459
460 imxdma_sg_next(desc, imxdma->sg);
6bd08127
JM		 461
462 tmp = imx_dmav1_readl(DMA_CCR(chno));
463
464 if (imxdma_hw_chain(imxdma)) {
465 /* FIXME: The timeout should probably be
466 * configurable
467 */
468 mod_timer(&imxdma->watchdog,
469 jiffies + msecs_to_jiffies(500));
470
471 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
472 imx_dmav1_writel(tmp, DMA_CCR(chno));
473 } else {
474 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
475 tmp |= CCR_CEN;
476 }
477
478 imx_dmav1_writel(tmp, DMA_CCR(chno));
479
480 if (imxdma_chan_is_doing_cyclic(imxdmac))
481 /* Tasklet progression */
482 tasklet_schedule(&imxdmac->dma_tasklet);
1f1846c6 483
6bd08127
JM		 484 return;
485 }
486
487 if (imxdma_hw_chain(imxdma)) {
488 del_timer(&imxdma->watchdog);
489 return;
490 }
491 }
492
2efc3449 493out:
6bd08127
JM		 494 imx_dmav1_writel(0, DMA_CCR(chno));
495 imxdma->in_use = 0;
496 /* Tasklet irq */
9e15db7c
JM		 497 tasklet_schedule(&imxdmac->dma_tasklet);
498}
499
6bd08127
JM		 500static irqreturn_t dma_irq_handler(int irq, void *dev_id)
501{
502 struct imxdma_engine *imxdma = dev_id;
503 struct imxdma_channel_internal *internal;
504 int i, disr;
505
506 if (cpu_is_mx21() || cpu_is_mx27())
507 imxdma_err_handler(irq, dev_id);
508
509 disr = imx_dmav1_readl(DMA_DISR);
510
511 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
512 disr);
513
514 imx_dmav1_writel(disr, DMA_DISR);
515 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
516 if (disr & (1 << i)) {
517 internal = &imxdma->channel[i].internal;
518 dma_irq_handle_channel(&imxdma->channel[i]);
519 }
520 }
521
522 return IRQ_HANDLED;
523}
524
9e15db7c
JM		 525static int imxdma_xfer_desc(struct imxdma_desc *d)
526{
527 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
3b4b6dfc 528 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c
JM		 529 int ret;
530
531 /* Configure and enable */
532 switch (d->type) {
533 case IMXDMA_DESC_MEMCPY:
3b4b6dfc
JM		 534 imxdmac->internal.sg = NULL;
535
536 imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
537 imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
538 imx_dmav1_writel(d->config_mem | (d->config_port << 2),
539 DMA_CCR(imxdmac->channel));
6bd08127 540
3b4b6dfc
JM		 541 imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
542
543 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
544 "dma_length=%d\n", __func__, imxdmac->channel,
545 d->dest, d->src, d->len);
546
547 break;
6bd08127 548 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
9e15db7c 549 case IMXDMA_DESC_CYCLIC:
9e15db7c 550 case IMXDMA_DESC_SLAVE_SG:
2efc3449
JM		 551 ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
552 imxdmac->per_address, d->direction);
9e15db7c
JM		 553 if (ret < 0)
554 return ret;
555 break;
556 default:
557 return -EINVAL;
558 }
2efc3449 559 imxdma_enable_hw(d);
9e15db7c
JM		 560 return 0;
561}
562
563static void imxdma_tasklet(unsigned long data)
564{
565 struct imxdma_channel *imxdmac = (void *)data;
566 struct imxdma_engine *imxdma = imxdmac->imxdma;
567 struct imxdma_desc *desc;
568
569 spin_lock(&imxdmac->lock);
570
571 if (list_empty(&imxdmac->ld_active)) {
572 /* Someone might have called terminate all */
573 goto out;
574 }
575 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
576
577 if (desc->desc.callback)
578 desc->desc.callback(desc->desc.callback_param);
579
1f3d6dc0 580 dma_cookie_complete(&desc->desc);
9e15db7c
JM		 581
582 /* If we are dealing with a cyclic descriptor keep it on ld_active */
583 if (imxdma_chan_is_doing_cyclic(imxdmac))
584 goto out;
585
586 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
587
588 if (!list_empty(&imxdmac->ld_queue)) {
589 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
590 node);
591 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
592 if (imxdma_xfer_desc(desc) < 0)
593 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
594 __func__, imxdmac->channel);
595 }
596out:
597 spin_unlock(&imxdmac->lock);
1f1846c6
SH		 598}
599
600static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
601 unsigned long arg)
602{
603 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
604 struct dma_slave_config *dmaengine_cfg = (void *)arg;
9e15db7c 605 unsigned long flags;
1f1846c6
SH		 606 unsigned int mode = 0;
607
608 switch (cmd) {
609 case DMA_TERMINATE_ALL:
6bd08127 610 imxdma_disable_hw(imxdmac);
9e15db7c
JM		 611
612 spin_lock_irqsave(&imxdmac->lock, flags);
613 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
614 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
615 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 616 return 0;
617 case DMA_SLAVE_CONFIG:
db8196df 618 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1f1846c6
SH		 619 imxdmac->per_address = dmaengine_cfg->src_addr;
620 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
621 imxdmac->word_size = dmaengine_cfg->src_addr_width;
622 } else {
623 imxdmac->per_address = dmaengine_cfg->dst_addr;
624 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
625 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
626 }
627
628 switch (imxdmac->word_size) {
629 case DMA_SLAVE_BUSWIDTH_1_BYTE:
630 mode = IMX_DMA_MEMSIZE_8;
631 break;
632 case DMA_SLAVE_BUSWIDTH_2_BYTES:
633 mode = IMX_DMA_MEMSIZE_16;
634 break;
635 default:
636 case DMA_SLAVE_BUSWIDTH_4_BYTES:
637 mode = IMX_DMA_MEMSIZE_32;
638 break;
639 }
1f1846c6 640
bdc0c753
JM		 641 imxdmac->internal.hw_chaining = 1;
642 if (!imxdma_hw_chain(&imxdmac->internal))
643 return -EINVAL;
644 imxdmac->internal.ccr_from_device =
645 (mode | IMX_DMA_TYPE_FIFO) |
646 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
647 CCR_REN;
648 imxdmac->internal.ccr_to_device =
649 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
650 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
651 imx_dmav1_writel(imxdmac->dma_request,
652 DMA_RSSR(imxdmac->channel));
653
6bd08127
JM		 654 /* Set burst length */
655 imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
656 DMA_BLR(imxdmac->channel));
1f1846c6
SH		 657
658 return 0;
659 default:
660 return -ENOSYS;
661 }
662
663 return -EINVAL;
664}
665
666static enum dma_status imxdma_tx_status(struct dma_chan *chan,
667 dma_cookie_t cookie,
668 struct dma_tx_state *txstate)
669{
96a2af41 670 return dma_cookie_status(chan, cookie, txstate);
1f1846c6
SH		 671}
672
673static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
674{
675 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
676 dma_cookie_t cookie;
9e15db7c 677 unsigned long flags;
1f1846c6 678
9e15db7c 679 spin_lock_irqsave(&imxdmac->lock, flags);
884485e1 680 cookie = dma_cookie_assign(tx);
9e15db7c 681 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 682
683 return cookie;
684}
685
686static int imxdma_alloc_chan_resources(struct dma_chan *chan)
687{
688 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
689 struct imx_dma_data *data = chan->private;
690
6c05f091
JM		 691 if (data != NULL)
692 imxdmac->dma_request = data->dma_request;
1f1846c6 693
9e15db7c
JM		 694 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
695 struct imxdma_desc *desc;
1f1846c6 696
9e15db7c
JM		 697 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
698 if (!desc)
699 break;
700 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
701 dma_async_tx_descriptor_init(&desc->desc, chan);
702 desc->desc.tx_submit = imxdma_tx_submit;
703 /* txd.flags will be overwritten in prep funcs */
704 desc->desc.flags = DMA_CTRL_ACK;
705 desc->status = DMA_SUCCESS;
706
707 list_add_tail(&desc->node, &imxdmac->ld_free);
708 imxdmac->descs_allocated++;
709 }
1f1846c6 710
9e15db7c
JM		 711 if (!imxdmac->descs_allocated)
712 return -ENOMEM;
713
714 return imxdmac->descs_allocated;
1f1846c6
SH		 715}
716
717static void imxdma_free_chan_resources(struct dma_chan *chan)
718{
719 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
9e15db7c
JM		 720 struct imxdma_desc *desc, *_desc;
721 unsigned long flags;
722
723 spin_lock_irqsave(&imxdmac->lock, flags);
1f1846c6 724
6bd08127 725 imxdma_disable_hw(imxdmac);
9e15db7c
JM		 726 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
727 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
728
729 spin_unlock_irqrestore(&imxdmac->lock, flags);
730
731 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
732 kfree(desc);
733 imxdmac->descs_allocated--;
734 }
735 INIT_LIST_HEAD(&imxdmac->ld_free);
1f1846c6
SH		 736
737 if (imxdmac->sg_list) {
738 kfree(imxdmac->sg_list);
739 imxdmac->sg_list = NULL;
740 }
741}
742
743static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
744 struct dma_chan *chan, struct scatterlist *sgl,
db8196df 745 unsigned int sg_len, enum dma_transfer_direction direction,
185ecb5f 746 unsigned long flags, void *context)
1f1846c6
SH		 747{
748 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
749 struct scatterlist *sg;
9e15db7c
JM		 750 int i, dma_length = 0;
751 struct imxdma_desc *desc;
1f1846c6 752
9e15db7c
JM		 753 if (list_empty(&imxdmac->ld_free) ||
754 imxdma_chan_is_doing_cyclic(imxdmac))
1f1846c6
SH		 755 return NULL;
756
9e15db7c 757 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
1f1846c6
SH		 758
759 for_each_sg(sgl, sg, sg_len, i) {
760 dma_length += sg->length;
761 }
762
d07102a1
SH		 763 switch (imxdmac->word_size) {
764 case DMA_SLAVE_BUSWIDTH_4_BYTES:
765 if (sgl->length & 3 || sgl->dma_address & 3)
766 return NULL;
767 break;
768 case DMA_SLAVE_BUSWIDTH_2_BYTES:
769 if (sgl->length & 1 || sgl->dma_address & 1)
770 return NULL;
771 break;
772 case DMA_SLAVE_BUSWIDTH_1_BYTE:
773 break;
774 default:
775 return NULL;
776 }
777
9e15db7c
JM		 778 desc->type = IMXDMA_DESC_SLAVE_SG;
779 desc->sg = sgl;
780 desc->sgcount = sg_len;
781 desc->len = dma_length;
2efc3449 782 desc->direction = direction;
9e15db7c 783 if (direction == DMA_DEV_TO_MEM) {
9e15db7c
JM		 784 desc->src = imxdmac->per_address;
785 } else {
9e15db7c
JM		 786 desc->dest = imxdmac->per_address;
787 }
788 desc->desc.callback = NULL;
789 desc->desc.callback_param = NULL;
1f1846c6 790
9e15db7c 791 return &desc->desc;
1f1846c6
SH		 792}
793
794static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
795 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
185ecb5f
AB		 796 size_t period_len, enum dma_transfer_direction direction,
797 void *context)
1f1846c6
SH		 798{
799 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
800 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c
JM		 801 struct imxdma_desc *desc;
802 int i;
1f1846c6 803 unsigned int periods = buf_len / period_len;
1f1846c6
SH		 804
805 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
806 __func__, imxdmac->channel, buf_len, period_len);
807
9e15db7c
JM		 808 if (list_empty(&imxdmac->ld_free) ||
809 imxdma_chan_is_doing_cyclic(imxdmac))
1f1846c6 810 return NULL;
1f1846c6 811
9e15db7c 812 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
1f1846c6
SH		 813
814 if (imxdmac->sg_list)
815 kfree(imxdmac->sg_list);
816
817 imxdmac->sg_list = kcalloc(periods + 1,
818 sizeof(struct scatterlist), GFP_KERNEL);
819 if (!imxdmac->sg_list)
820 return NULL;
821
822 sg_init_table(imxdmac->sg_list, periods);
823
824 for (i = 0; i < periods; i++) {
825 imxdmac->sg_list[i].page_link = 0;
826 imxdmac->sg_list[i].offset = 0;
827 imxdmac->sg_list[i].dma_address = dma_addr;
828 imxdmac->sg_list[i].length = period_len;
829 dma_addr += period_len;
830 }
831
832 /* close the loop */
833 imxdmac->sg_list[periods].offset = 0;
834 imxdmac->sg_list[periods].length = 0;
835 imxdmac->sg_list[periods].page_link =
836 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
837
9e15db7c
JM		 838 desc->type = IMXDMA_DESC_CYCLIC;
839 desc->sg = imxdmac->sg_list;
840 desc->sgcount = periods;
841 desc->len = IMX_DMA_LENGTH_LOOP;
2efc3449 842 desc->direction = direction;
9e15db7c 843 if (direction == DMA_DEV_TO_MEM) {
9e15db7c
JM		 844 desc->src = imxdmac->per_address;
845 } else {
9e15db7c
JM		 846 desc->dest = imxdmac->per_address;
847 }
848 desc->desc.callback = NULL;
849 desc->desc.callback_param = NULL;
1f1846c6 850
9e15db7c 851 return &desc->desc;
1f1846c6
SH		 852}
853
6c05f091
JM		 854static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
855 struct dma_chan *chan, dma_addr_t dest,
856 dma_addr_t src, size_t len, unsigned long flags)
857{
858 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
859 struct imxdma_engine *imxdma = imxdmac->imxdma;
9e15db7c 860 struct imxdma_desc *desc;
6c05f091
JM		 861
862 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
863 __func__, imxdmac->channel, src, dest, len);
864
9e15db7c
JM		 865 if (list_empty(&imxdmac->ld_free) ||
866 imxdma_chan_is_doing_cyclic(imxdmac))
6c05f091 867 return NULL;
6c05f091 868
9e15db7c 869 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
6c05f091 870
9e15db7c
JM		 871 desc->type = IMXDMA_DESC_MEMCPY;
872 desc->src = src;
873 desc->dest = dest;
874 desc->len = len;
2efc3449 875 desc->direction = DMA_MEM_TO_MEM;
9e15db7c
JM		 876 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
877 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
878 desc->desc.callback = NULL;
879 desc->desc.callback_param = NULL;
6c05f091 880
9e15db7c 881 return &desc->desc;
6c05f091
JM		 882}
883
1f1846c6
SH		 884static void imxdma_issue_pending(struct dma_chan *chan)
885{
5b316876 886 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
9e15db7c
JM		 887 struct imxdma_engine *imxdma = imxdmac->imxdma;
888 struct imxdma_desc *desc;
889 unsigned long flags;
890
891 spin_lock_irqsave(&imxdmac->lock, flags);
892 if (list_empty(&imxdmac->ld_active) &&
893 !list_empty(&imxdmac->ld_queue)) {
894 desc = list_first_entry(&imxdmac->ld_queue,
895 struct imxdma_desc, node);
896
897 if (imxdma_xfer_desc(desc) < 0) {
898 dev_warn(imxdma->dev,
899 "%s: channel: %d couldn't issue DMA xfer\n",
900 __func__, imxdmac->channel);
901 } else {
902 list_move_tail(imxdmac->ld_queue.next,
903 &imxdmac->ld_active);
904 }
905 }
906 spin_unlock_irqrestore(&imxdmac->lock, flags);
1f1846c6
SH		 907}
908
909static int __init imxdma_probe(struct platform_device *pdev)
6bd08127 910 {
1f1846c6
SH		 911 struct imxdma_engine *imxdma;
912 int ret, i;
913
6bd08127
JM		 914 if (cpu_is_mx1())
915 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
916 else if (cpu_is_mx21())
917 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
918 else if (cpu_is_mx27())
919 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
920 else
921 return 0;
922
923 dma_clk = clk_get(NULL, "dma");
924 if (IS_ERR(dma_clk))
925 return PTR_ERR(dma_clk);
926 clk_enable(dma_clk);
927
928 /* reset DMA module */
929 imx_dmav1_writel(DCR_DRST, DMA_DCR);
930
931 if (cpu_is_mx1()) {
932 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
933 if (ret) {
934 pr_crit("Can't register IRQ for DMA\n");
935 return ret;
936 }
937
938 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
939 if (ret) {
940 pr_crit("Can't register ERRIRQ for DMA\n");
941 free_irq(MX1_DMA_INT, NULL);
942 return ret;
943 }
944 }
945
946 /* enable DMA module */
947 imx_dmav1_writel(DCR_DEN, DMA_DCR);
948
949 /* clear all interrupts */
950 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
951
952 /* disable interrupts */
953 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
954
1f1846c6
SH		 955 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
956 if (!imxdma)
957 return -ENOMEM;
958
959 INIT_LIST_HEAD(&imxdma->dma_device.channels);
960
f8a356ff
SH		 961 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
962 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
6c05f091 963 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
f8a356ff 964
1f1846c6 965 /* Initialize channel parameters */
6bd08127 966 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1f1846c6 967 struct imxdma_channel *imxdmac = &imxdma->channel[i];
6bd08127
JM		 968 memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
969 if (cpu_is_mx21() || cpu_is_mx27()) {
970 ret = request_irq(MX2x_INT_DMACH0 + i,
971 dma_irq_handler, 0, "DMA", imxdma);
972 if (ret) {
973 pr_crit("Can't register IRQ %d for DMA channel %d\n",
974 MX2x_INT_DMACH0 + i, i);
975 goto err_init;
976 }
977 init_timer(&imxdmac->internal.watchdog);
978 imxdmac->internal.watchdog.function = &imxdma_watchdog;
979 imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
8267f16e 980 }
1f1846c6 981
1f1846c6
SH		 982 imxdmac->imxdma = imxdma;
983 spin_lock_init(&imxdmac->lock);
984
9e15db7c
JM		 985 INIT_LIST_HEAD(&imxdmac->ld_queue);
986 INIT_LIST_HEAD(&imxdmac->ld_free);
987 INIT_LIST_HEAD(&imxdmac->ld_active);
988
989 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
990 (unsigned long)imxdmac);
1f1846c6 991 imxdmac->chan.device = &imxdma->dma_device;
8ac69546 992 dma_cookie_init(&imxdmac->chan);
1f1846c6
SH		 993 imxdmac->channel = i;
994
995 /* Add the channel to the DMAC list */
9e15db7c
JM		 996 list_add_tail(&imxdmac->chan.device_node,
997 &imxdma->dma_device.channels);
1f1846c6
SH		 998 }
999
1000 imxdma->dev = &pdev->dev;
1001 imxdma->dma_device.dev = &pdev->dev;
1002
1003 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1004 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1005 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1006 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1007 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
6c05f091 1008 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1f1846c6
SH		 1009 imxdma->dma_device.device_control = imxdma_control;
1010 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1011
1012 platform_set_drvdata(pdev, imxdma);
1013
6c05f091 1014 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1e070a60
SH		 1015 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1016 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1017
1f1846c6
SH		 1018 ret = dma_async_device_register(&imxdma->dma_device);
1019 if (ret) {
1020 dev_err(&pdev->dev, "unable to register\n");
1021 goto err_init;
1022 }
1023
1024 return 0;
1025
1026err_init:
6bd08127
JM		 1027
1028 if (cpu_is_mx21() || cpu_is_mx27()) {
1029 while (--i >= 0)
1030 free_irq(MX2x_INT_DMACH0 + i, NULL);
1031 } else if cpu_is_mx1() {
1032 free_irq(MX1_DMA_INT, NULL);
1033 free_irq(MX1_DMA_ERR, NULL);
1f1846c6
SH		 1034 }
1035
1036 kfree(imxdma);
1037 return ret;
1038}
1039
1040static int __exit imxdma_remove(struct platform_device *pdev)
1041{
1042 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1043 int i;
1044
1045 dma_async_device_unregister(&imxdma->dma_device);
1046
6bd08127
JM		 1047 if (cpu_is_mx21() || cpu_is_mx27()) {
1048 for (i = 0; i < IMX_DMA_CHANNELS; i++)
1049 free_irq(MX2x_INT_DMACH0 + i, NULL);
1050 } else if cpu_is_mx1() {
1051 free_irq(MX1_DMA_INT, NULL);
1052 free_irq(MX1_DMA_ERR, NULL);
1f1846c6
SH		 1053 }
1054
1055 kfree(imxdma);
1056
1057 return 0;
1058}
1059
1060static struct platform_driver imxdma_driver = {
1061 .driver = {
1062 .name = "imx-dma",
1063 },
1064 .remove = __exit_p(imxdma_remove),
1065};
1066
1067static int __init imxdma_module_init(void)
1068{
1069 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1070}
1071subsys_initcall(imxdma_module_init);
1072
1073MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1074MODULE_DESCRIPTION("i.MX dma driver");
1075MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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