Commit | Line | Data |
---|---|---|
1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
17 | #include <linux/init.h> | |
f8de8f4c | 18 | #include <linux/module.h> |
1f1846c6 SH |
19 | #include <linux/types.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5170c051 | 29 | #include <linux/module.h> |
1f1846c6 SH |
30 | |
31 | #include <asm/irq.h> | |
6bd08127 | 32 | #include <mach/dma.h> |
1f1846c6 SH |
33 | #include <mach/hardware.h> |
34 | ||
d2ebfb33 | 35 | #include "dmaengine.h" |
9e15db7c | 36 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
37 | #define IMX_DMA_CHANNELS 16 |
38 | ||
6bd08127 JM |
39 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
40 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
41 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
42 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
43 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
44 | #define IMX_DMA_TYPE_2D (1 << 10) | |
45 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
46 | ||
47 | #define IMX_DMA_ERR_BURST (1 << 0) | |
48 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
49 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
50 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
51 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
52 | ||
53 | #define DMA_DCR 0x00 /* Control Register */ | |
54 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
55 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
56 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
57 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
58 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
59 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
60 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
61 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
62 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
63 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
64 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
65 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
66 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
67 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
68 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
69 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
70 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
71 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
72 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
73 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
74 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
75 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
76 | ||
77 | #define DCR_DRST (1<<1) | |
78 | #define DCR_DEN (1<<0) | |
79 | #define DBTOCR_EN (1<<15) | |
80 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
81 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
82 | #define CCR_ACRPT (1<<14) | |
83 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
84 | #define CCR_DMOD_2D (0x1 << 12) | |
85 | #define CCR_DMOD_FIFO (0x2 << 12) | |
86 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
87 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
88 | #define CCR_SMOD_2D (0x1 << 10) | |
89 | #define CCR_SMOD_FIFO (0x2 << 10) | |
90 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
91 | #define CCR_MDIR_DEC (1<<9) | |
92 | #define CCR_MSEL_B (1<<8) | |
93 | #define CCR_DSIZ_32 (0x0 << 6) | |
94 | #define CCR_DSIZ_8 (0x1 << 6) | |
95 | #define CCR_DSIZ_16 (0x2 << 6) | |
96 | #define CCR_SSIZ_32 (0x0 << 4) | |
97 | #define CCR_SSIZ_8 (0x1 << 4) | |
98 | #define CCR_SSIZ_16 (0x2 << 4) | |
99 | #define CCR_REN (1<<3) | |
100 | #define CCR_RPT (1<<2) | |
101 | #define CCR_FRC (1<<1) | |
102 | #define CCR_CEN (1<<0) | |
103 | #define RTOR_EN (1<<15) | |
104 | #define RTOR_CLK (1<<14) | |
105 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
106 | |
107 | enum imxdma_prep_type { | |
108 | IMXDMA_DESC_MEMCPY, | |
109 | IMXDMA_DESC_INTERLEAVED, | |
110 | IMXDMA_DESC_SLAVE_SG, | |
111 | IMXDMA_DESC_CYCLIC, | |
112 | }; | |
113 | ||
114 | struct imxdma_desc { | |
115 | struct list_head node; | |
116 | struct dma_async_tx_descriptor desc; | |
117 | enum dma_status status; | |
118 | dma_addr_t src; | |
119 | dma_addr_t dest; | |
120 | size_t len; | |
2efc3449 | 121 | enum dma_transfer_direction direction; |
9e15db7c JM |
122 | enum imxdma_prep_type type; |
123 | /* For memcpy and interleaved */ | |
124 | unsigned int config_port; | |
125 | unsigned int config_mem; | |
126 | /* For interleaved transfers */ | |
127 | unsigned int x; | |
128 | unsigned int y; | |
129 | unsigned int w; | |
130 | /* For slave sg and cyclic */ | |
131 | struct scatterlist *sg; | |
132 | unsigned int sgcount; | |
133 | }; | |
134 | ||
1f1846c6 | 135 | struct imxdma_channel { |
2d9c2fc5 JM |
136 | int hw_chaining; |
137 | struct timer_list watchdog; | |
1f1846c6 SH |
138 | struct imxdma_engine *imxdma; |
139 | unsigned int channel; | |
1f1846c6 | 140 | |
9e15db7c JM |
141 | struct tasklet_struct dma_tasklet; |
142 | struct list_head ld_free; | |
143 | struct list_head ld_queue; | |
144 | struct list_head ld_active; | |
145 | int descs_allocated; | |
1f1846c6 SH |
146 | enum dma_slave_buswidth word_size; |
147 | dma_addr_t per_address; | |
148 | u32 watermark_level; | |
149 | struct dma_chan chan; | |
150 | spinlock_t lock; | |
151 | struct dma_async_tx_descriptor desc; | |
1f1846c6 SH |
152 | enum dma_status status; |
153 | int dma_request; | |
154 | struct scatterlist *sg_list; | |
359291a1 JM |
155 | u32 ccr_from_device; |
156 | u32 ccr_to_device; | |
1f1846c6 SH |
157 | }; |
158 | ||
1f1846c6 SH |
159 | struct imxdma_engine { |
160 | struct device *dev; | |
1e070a60 | 161 | struct device_dma_parameters dma_parms; |
1f1846c6 | 162 | struct dma_device dma_device; |
cd5cf9da JM |
163 | void __iomem *base; |
164 | struct clk *dma_clk; | |
6bd08127 | 165 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
1f1846c6 SH |
166 | }; |
167 | ||
168 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) | |
169 | { | |
170 | return container_of(chan, struct imxdma_channel, chan); | |
171 | } | |
172 | ||
9e15db7c | 173 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 174 | { |
9e15db7c JM |
175 | struct imxdma_desc *desc; |
176 | ||
177 | if (!list_empty(&imxdmac->ld_active)) { | |
178 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
179 | node); | |
180 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
181 | return true; | |
182 | } | |
183 | return false; | |
1f1846c6 SH |
184 | } |
185 | ||
6bd08127 | 186 | |
cd5cf9da JM |
187 | |
188 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
189 | unsigned offset) | |
6bd08127 | 190 | { |
cd5cf9da | 191 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
192 | } |
193 | ||
cd5cf9da | 194 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 195 | { |
cd5cf9da | 196 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 197 | } |
1f1846c6 | 198 | |
2d9c2fc5 | 199 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 JM |
200 | { |
201 | if (cpu_is_mx27()) | |
2d9c2fc5 | 202 | return imxdmac->hw_chaining; |
6bd08127 JM |
203 | else |
204 | return 0; | |
205 | } | |
206 | ||
207 | /* | |
208 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
209 | */ | |
a6cbb2d8 | 210 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
6bd08127 | 211 | { |
2efc3449 | 212 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 213 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 214 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
215 | unsigned long now; |
216 | ||
6b0e2f55 JM |
217 | now = min(d->len, sg->length); |
218 | if (d->len != IMX_DMA_LENGTH_LOOP) | |
219 | d->len -= now; | |
6bd08127 | 220 | |
2efc3449 | 221 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
222 | imx_dmav1_writel(imxdma, sg->dma_address, |
223 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 224 | else |
cd5cf9da JM |
225 | imx_dmav1_writel(imxdma, sg->dma_address, |
226 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 227 | |
cd5cf9da | 228 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 JM |
229 | |
230 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " | |
231 | "size 0x%08x\n", imxdmac->channel, | |
cd5cf9da JM |
232 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
233 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
234 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
235 | |
236 | return now; | |
237 | } | |
238 | ||
2efc3449 | 239 | static void imxdma_enable_hw(struct imxdma_desc *d) |
6bd08127 | 240 | { |
2efc3449 | 241 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 242 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
243 | int channel = imxdmac->channel; |
244 | unsigned long flags; | |
245 | ||
246 | pr_debug("imxdma%d: imx_dma_enable\n", channel); | |
247 | ||
6bd08127 JM |
248 | local_irq_save(flags); |
249 | ||
cd5cf9da JM |
250 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
251 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
252 | ~(1 << channel), DMA_DIMR); | |
253 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
254 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 JM |
255 | |
256 | if ((cpu_is_mx21() || cpu_is_mx27()) && | |
2d9c2fc5 | 257 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
258 | d->sg = sg_next(d->sg); |
259 | if (d->sg) { | |
6bd08127 | 260 | u32 tmp; |
a6cbb2d8 | 261 | imxdma_sg_next(d); |
cd5cf9da JM |
262 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
263 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
264 | DMA_CCR(channel)); | |
6bd08127 JM |
265 | } |
266 | } | |
6bd08127 JM |
267 | |
268 | local_irq_restore(flags); | |
269 | } | |
270 | ||
271 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
272 | { | |
cd5cf9da | 273 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
274 | int channel = imxdmac->channel; |
275 | unsigned long flags; | |
276 | ||
277 | pr_debug("imxdma%d: imx_dma_disable\n", channel); | |
278 | ||
2d9c2fc5 JM |
279 | if (imxdma_hw_chain(imxdmac)) |
280 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
281 | |
282 | local_irq_save(flags); | |
cd5cf9da JM |
283 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
284 | (1 << channel), DMA_DIMR); | |
285 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
286 | ~CCR_CEN, DMA_CCR(channel)); | |
287 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
288 | local_irq_restore(flags); |
289 | } | |
290 | ||
6bd08127 | 291 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 292 | { |
6bd08127 | 293 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
cd5cf9da | 294 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 295 | int channel = imxdmac->channel; |
1f1846c6 | 296 | |
cd5cf9da | 297 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
6bd08127 JM |
298 | |
299 | /* Tasklet watchdog error handler */ | |
9e15db7c | 300 | tasklet_schedule(&imxdmac->dma_tasklet); |
6bd08127 JM |
301 | pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel); |
302 | } | |
303 | ||
304 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) | |
305 | { | |
306 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
307 | unsigned int err_mask; |
308 | int i, disr; | |
309 | int errcode; | |
310 | ||
cd5cf9da | 311 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 312 | |
cd5cf9da JM |
313 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
314 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
315 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
316 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
317 | |
318 | if (!err_mask) | |
319 | return IRQ_HANDLED; | |
320 | ||
cd5cf9da | 321 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
322 | |
323 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
324 | if (!(err_mask & (1 << i))) | |
325 | continue; | |
6bd08127 JM |
326 | errcode = 0; |
327 | ||
cd5cf9da JM |
328 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
329 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
330 | errcode |= IMX_DMA_ERR_BURST; |
331 | } | |
cd5cf9da JM |
332 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
333 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
334 | errcode |= IMX_DMA_ERR_REQUEST; |
335 | } | |
cd5cf9da JM |
336 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
337 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
338 | errcode |= IMX_DMA_ERR_TRANSFER; |
339 | } | |
cd5cf9da JM |
340 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
341 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
342 | errcode |= IMX_DMA_ERR_BUFFER; |
343 | } | |
344 | /* Tasklet error handler */ | |
345 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
346 | ||
347 | printk(KERN_WARNING | |
348 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
349 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
350 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
351 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
352 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
353 | } | |
354 | return IRQ_HANDLED; | |
1f1846c6 SH |
355 | } |
356 | ||
6bd08127 | 357 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 358 | { |
cd5cf9da | 359 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 360 | int chno = imxdmac->channel; |
2efc3449 | 361 | struct imxdma_desc *desc; |
6bd08127 | 362 | |
833bc03b JM |
363 | spin_lock(&imxdmac->lock); |
364 | if (list_empty(&imxdmac->ld_active)) { | |
365 | spin_unlock(&imxdmac->lock); | |
366 | goto out; | |
367 | } | |
2efc3449 | 368 | |
833bc03b JM |
369 | desc = list_first_entry(&imxdmac->ld_active, |
370 | struct imxdma_desc, | |
371 | node); | |
372 | spin_unlock(&imxdmac->lock); | |
2efc3449 | 373 | |
833bc03b JM |
374 | if (desc->sg) { |
375 | u32 tmp; | |
376 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 377 | |
833bc03b | 378 | if (desc->sg) { |
a6cbb2d8 | 379 | imxdma_sg_next(desc); |
6bd08127 | 380 | |
cd5cf9da | 381 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 382 | |
2d9c2fc5 | 383 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
384 | /* FIXME: The timeout should probably be |
385 | * configurable | |
386 | */ | |
2d9c2fc5 | 387 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
388 | jiffies + msecs_to_jiffies(500)); |
389 | ||
390 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 391 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 392 | } else { |
cd5cf9da JM |
393 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
394 | DMA_CCR(chno)); | |
6bd08127 JM |
395 | tmp |= CCR_CEN; |
396 | } | |
397 | ||
cd5cf9da | 398 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
399 | |
400 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
401 | /* Tasklet progression */ | |
402 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 403 | |
6bd08127 JM |
404 | return; |
405 | } | |
406 | ||
2d9c2fc5 JM |
407 | if (imxdma_hw_chain(imxdmac)) { |
408 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
409 | return; |
410 | } | |
411 | } | |
412 | ||
2efc3449 | 413 | out: |
cd5cf9da | 414 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 415 | /* Tasklet irq */ |
9e15db7c JM |
416 | tasklet_schedule(&imxdmac->dma_tasklet); |
417 | } | |
418 | ||
6bd08127 JM |
419 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
420 | { | |
421 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
422 | int i, disr; |
423 | ||
424 | if (cpu_is_mx21() || cpu_is_mx27()) | |
425 | imxdma_err_handler(irq, dev_id); | |
426 | ||
cd5cf9da | 427 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 JM |
428 | |
429 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", | |
430 | disr); | |
431 | ||
cd5cf9da | 432 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 433 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 434 | if (disr & (1 << i)) |
6bd08127 | 435 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
436 | } |
437 | ||
438 | return IRQ_HANDLED; | |
439 | } | |
440 | ||
9e15db7c JM |
441 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
442 | { | |
443 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 444 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
445 | |
446 | /* Configure and enable */ | |
447 | switch (d->type) { | |
448 | case IMXDMA_DESC_MEMCPY: | |
cd5cf9da JM |
449 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
450 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
451 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 452 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 453 | |
cd5cf9da | 454 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc JM |
455 | |
456 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
457 | "dma_length=%d\n", __func__, imxdmac->channel, | |
458 | d->dest, d->src, d->len); | |
459 | ||
460 | break; | |
6bd08127 | 461 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 462 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 463 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 464 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 465 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 466 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 467 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
468 | DMA_CCR(imxdmac->channel)); |
469 | ||
470 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
471 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
472 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
473 | d->len, imxdmac->per_address); | |
474 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
cd5cf9da | 475 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 476 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 477 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
478 | DMA_CCR(imxdmac->channel)); |
479 | ||
480 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
481 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
482 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
483 | d->len, imxdmac->per_address); | |
484 | } else { | |
485 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
486 | __func__, imxdmac->channel); | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
a6cbb2d8 | 490 | imxdma_sg_next(d); |
359291a1 | 491 | |
9e15db7c JM |
492 | break; |
493 | default: | |
494 | return -EINVAL; | |
495 | } | |
2efc3449 | 496 | imxdma_enable_hw(d); |
9e15db7c JM |
497 | return 0; |
498 | } | |
499 | ||
500 | static void imxdma_tasklet(unsigned long data) | |
501 | { | |
502 | struct imxdma_channel *imxdmac = (void *)data; | |
503 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
504 | struct imxdma_desc *desc; | |
505 | ||
506 | spin_lock(&imxdmac->lock); | |
507 | ||
508 | if (list_empty(&imxdmac->ld_active)) { | |
509 | /* Someone might have called terminate all */ | |
510 | goto out; | |
511 | } | |
512 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
513 | ||
514 | if (desc->desc.callback) | |
515 | desc->desc.callback(desc->desc.callback_param); | |
516 | ||
1f3d6dc0 | 517 | dma_cookie_complete(&desc->desc); |
9e15db7c JM |
518 | |
519 | /* If we are dealing with a cyclic descriptor keep it on ld_active */ | |
520 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
521 | goto out; | |
522 | ||
523 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); | |
524 | ||
525 | if (!list_empty(&imxdmac->ld_queue)) { | |
526 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
527 | node); | |
528 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
529 | if (imxdma_xfer_desc(desc) < 0) | |
530 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
531 | __func__, imxdmac->channel); | |
532 | } | |
533 | out: | |
534 | spin_unlock(&imxdmac->lock); | |
1f1846c6 SH |
535 | } |
536 | ||
537 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
538 | unsigned long arg) | |
539 | { | |
540 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
541 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
cd5cf9da | 542 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 543 | unsigned long flags; |
1f1846c6 SH |
544 | unsigned int mode = 0; |
545 | ||
546 | switch (cmd) { | |
547 | case DMA_TERMINATE_ALL: | |
6bd08127 | 548 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
549 | |
550 | spin_lock_irqsave(&imxdmac->lock, flags); | |
551 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
552 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
553 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
554 | return 0; |
555 | case DMA_SLAVE_CONFIG: | |
db8196df | 556 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
557 | imxdmac->per_address = dmaengine_cfg->src_addr; |
558 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
559 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
560 | } else { | |
561 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
562 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
563 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
564 | } | |
565 | ||
566 | switch (imxdmac->word_size) { | |
567 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
568 | mode = IMX_DMA_MEMSIZE_8; | |
569 | break; | |
570 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
571 | mode = IMX_DMA_MEMSIZE_16; | |
572 | break; | |
573 | default: | |
574 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
575 | mode = IMX_DMA_MEMSIZE_32; | |
576 | break; | |
577 | } | |
1f1846c6 | 578 | |
2d9c2fc5 JM |
579 | imxdmac->hw_chaining = 1; |
580 | if (!imxdma_hw_chain(imxdmac)) | |
bdc0c753 | 581 | return -EINVAL; |
359291a1 | 582 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
583 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
584 | CCR_REN; | |
359291a1 | 585 | imxdmac->ccr_to_device = |
bdc0c753 JM |
586 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
587 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
cd5cf9da | 588 | imx_dmav1_writel(imxdma, imxdmac->dma_request, |
bdc0c753 JM |
589 | DMA_RSSR(imxdmac->channel)); |
590 | ||
6bd08127 | 591 | /* Set burst length */ |
cd5cf9da JM |
592 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * |
593 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
594 | |
595 | return 0; | |
596 | default: | |
597 | return -ENOSYS; | |
598 | } | |
599 | ||
600 | return -EINVAL; | |
601 | } | |
602 | ||
603 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
604 | dma_cookie_t cookie, | |
605 | struct dma_tx_state *txstate) | |
606 | { | |
96a2af41 | 607 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
608 | } |
609 | ||
610 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
611 | { | |
612 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
613 | dma_cookie_t cookie; | |
9e15db7c | 614 | unsigned long flags; |
1f1846c6 | 615 | |
9e15db7c | 616 | spin_lock_irqsave(&imxdmac->lock, flags); |
884485e1 | 617 | cookie = dma_cookie_assign(tx); |
9e15db7c | 618 | spin_unlock_irqrestore(&imxdmac->lock, flags); |
1f1846c6 SH |
619 | |
620 | return cookie; | |
621 | } | |
622 | ||
623 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
624 | { | |
625 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
626 | struct imx_dma_data *data = chan->private; | |
627 | ||
6c05f091 JM |
628 | if (data != NULL) |
629 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 630 | |
9e15db7c JM |
631 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
632 | struct imxdma_desc *desc; | |
1f1846c6 | 633 | |
9e15db7c JM |
634 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
635 | if (!desc) | |
636 | break; | |
637 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
638 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
639 | desc->desc.tx_submit = imxdma_tx_submit; | |
640 | /* txd.flags will be overwritten in prep funcs */ | |
641 | desc->desc.flags = DMA_CTRL_ACK; | |
642 | desc->status = DMA_SUCCESS; | |
643 | ||
644 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
645 | imxdmac->descs_allocated++; | |
646 | } | |
1f1846c6 | 647 | |
9e15db7c JM |
648 | if (!imxdmac->descs_allocated) |
649 | return -ENOMEM; | |
650 | ||
651 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
652 | } |
653 | ||
654 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
655 | { | |
656 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
9e15db7c JM |
657 | struct imxdma_desc *desc, *_desc; |
658 | unsigned long flags; | |
659 | ||
660 | spin_lock_irqsave(&imxdmac->lock, flags); | |
1f1846c6 | 661 | |
6bd08127 | 662 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
663 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
664 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
665 | ||
666 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
667 | ||
668 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
669 | kfree(desc); | |
670 | imxdmac->descs_allocated--; | |
671 | } | |
672 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
673 | |
674 | if (imxdmac->sg_list) { | |
675 | kfree(imxdmac->sg_list); | |
676 | imxdmac->sg_list = NULL; | |
677 | } | |
678 | } | |
679 | ||
680 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
681 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 682 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 683 | unsigned long flags, void *context) |
1f1846c6 SH |
684 | { |
685 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
686 | struct scatterlist *sg; | |
9e15db7c JM |
687 | int i, dma_length = 0; |
688 | struct imxdma_desc *desc; | |
1f1846c6 | 689 | |
9e15db7c JM |
690 | if (list_empty(&imxdmac->ld_free) || |
691 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
692 | return NULL; |
693 | ||
9e15db7c | 694 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
695 | |
696 | for_each_sg(sgl, sg, sg_len, i) { | |
697 | dma_length += sg->length; | |
698 | } | |
699 | ||
d07102a1 SH |
700 | switch (imxdmac->word_size) { |
701 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
702 | if (sgl->length & 3 || sgl->dma_address & 3) | |
703 | return NULL; | |
704 | break; | |
705 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
706 | if (sgl->length & 1 || sgl->dma_address & 1) | |
707 | return NULL; | |
708 | break; | |
709 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
710 | break; | |
711 | default: | |
712 | return NULL; | |
713 | } | |
714 | ||
9e15db7c JM |
715 | desc->type = IMXDMA_DESC_SLAVE_SG; |
716 | desc->sg = sgl; | |
717 | desc->sgcount = sg_len; | |
718 | desc->len = dma_length; | |
2efc3449 | 719 | desc->direction = direction; |
9e15db7c | 720 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
721 | desc->src = imxdmac->per_address; |
722 | } else { | |
9e15db7c JM |
723 | desc->dest = imxdmac->per_address; |
724 | } | |
725 | desc->desc.callback = NULL; | |
726 | desc->desc.callback_param = NULL; | |
1f1846c6 | 727 | |
9e15db7c | 728 | return &desc->desc; |
1f1846c6 SH |
729 | } |
730 | ||
731 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
732 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f AB |
733 | size_t period_len, enum dma_transfer_direction direction, |
734 | void *context) | |
1f1846c6 SH |
735 | { |
736 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
737 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
738 | struct imxdma_desc *desc; |
739 | int i; | |
1f1846c6 | 740 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
741 | |
742 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
743 | __func__, imxdmac->channel, buf_len, period_len); | |
744 | ||
9e15db7c JM |
745 | if (list_empty(&imxdmac->ld_free) || |
746 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 747 | return NULL; |
1f1846c6 | 748 | |
9e15db7c | 749 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
750 | |
751 | if (imxdmac->sg_list) | |
752 | kfree(imxdmac->sg_list); | |
753 | ||
754 | imxdmac->sg_list = kcalloc(periods + 1, | |
755 | sizeof(struct scatterlist), GFP_KERNEL); | |
756 | if (!imxdmac->sg_list) | |
757 | return NULL; | |
758 | ||
759 | sg_init_table(imxdmac->sg_list, periods); | |
760 | ||
761 | for (i = 0; i < periods; i++) { | |
762 | imxdmac->sg_list[i].page_link = 0; | |
763 | imxdmac->sg_list[i].offset = 0; | |
764 | imxdmac->sg_list[i].dma_address = dma_addr; | |
765 | imxdmac->sg_list[i].length = period_len; | |
766 | dma_addr += period_len; | |
767 | } | |
768 | ||
769 | /* close the loop */ | |
770 | imxdmac->sg_list[periods].offset = 0; | |
771 | imxdmac->sg_list[periods].length = 0; | |
772 | imxdmac->sg_list[periods].page_link = | |
773 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
774 | ||
9e15db7c JM |
775 | desc->type = IMXDMA_DESC_CYCLIC; |
776 | desc->sg = imxdmac->sg_list; | |
777 | desc->sgcount = periods; | |
778 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 779 | desc->direction = direction; |
9e15db7c | 780 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
781 | desc->src = imxdmac->per_address; |
782 | } else { | |
9e15db7c JM |
783 | desc->dest = imxdmac->per_address; |
784 | } | |
785 | desc->desc.callback = NULL; | |
786 | desc->desc.callback_param = NULL; | |
1f1846c6 | 787 | |
9e15db7c | 788 | return &desc->desc; |
1f1846c6 SH |
789 | } |
790 | ||
6c05f091 JM |
791 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
792 | struct dma_chan *chan, dma_addr_t dest, | |
793 | dma_addr_t src, size_t len, unsigned long flags) | |
794 | { | |
795 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
796 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 797 | struct imxdma_desc *desc; |
6c05f091 JM |
798 | |
799 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", | |
800 | __func__, imxdmac->channel, src, dest, len); | |
801 | ||
9e15db7c JM |
802 | if (list_empty(&imxdmac->ld_free) || |
803 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
6c05f091 | 804 | return NULL; |
6c05f091 | 805 | |
9e15db7c | 806 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 807 | |
9e15db7c JM |
808 | desc->type = IMXDMA_DESC_MEMCPY; |
809 | desc->src = src; | |
810 | desc->dest = dest; | |
811 | desc->len = len; | |
2efc3449 | 812 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
813 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
814 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
815 | desc->desc.callback = NULL; | |
816 | desc->desc.callback_param = NULL; | |
6c05f091 | 817 | |
9e15db7c | 818 | return &desc->desc; |
6c05f091 JM |
819 | } |
820 | ||
1f1846c6 SH |
821 | static void imxdma_issue_pending(struct dma_chan *chan) |
822 | { | |
5b316876 | 823 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
824 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
825 | struct imxdma_desc *desc; | |
826 | unsigned long flags; | |
827 | ||
828 | spin_lock_irqsave(&imxdmac->lock, flags); | |
829 | if (list_empty(&imxdmac->ld_active) && | |
830 | !list_empty(&imxdmac->ld_queue)) { | |
831 | desc = list_first_entry(&imxdmac->ld_queue, | |
832 | struct imxdma_desc, node); | |
833 | ||
834 | if (imxdma_xfer_desc(desc) < 0) { | |
835 | dev_warn(imxdma->dev, | |
836 | "%s: channel: %d couldn't issue DMA xfer\n", | |
837 | __func__, imxdmac->channel); | |
838 | } else { | |
839 | list_move_tail(imxdmac->ld_queue.next, | |
840 | &imxdmac->ld_active); | |
841 | } | |
842 | } | |
843 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
844 | } |
845 | ||
846 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 847 | { |
1f1846c6 SH |
848 | struct imxdma_engine *imxdma; |
849 | int ret, i; | |
850 | ||
cd5cf9da JM |
851 | |
852 | imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); | |
853 | if (!imxdma) | |
854 | return -ENOMEM; | |
855 | ||
856 | if (cpu_is_mx1()) { | |
857 | imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); | |
858 | } else if (cpu_is_mx21()) { | |
859 | imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); | |
860 | } else if (cpu_is_mx27()) { | |
861 | imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); | |
862 | } else { | |
863 | kfree(imxdma); | |
6bd08127 | 864 | return 0; |
cd5cf9da | 865 | } |
6bd08127 | 866 | |
cd5cf9da JM |
867 | imxdma->dma_clk = clk_get(NULL, "dma"); |
868 | if (IS_ERR(imxdma->dma_clk)) | |
869 | return PTR_ERR(imxdma->dma_clk); | |
870 | clk_enable(imxdma->dma_clk); | |
6bd08127 JM |
871 | |
872 | /* reset DMA module */ | |
cd5cf9da | 873 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 JM |
874 | |
875 | if (cpu_is_mx1()) { | |
876 | ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma); | |
877 | if (ret) { | |
878 | pr_crit("Can't register IRQ for DMA\n"); | |
cd5cf9da | 879 | kfree(imxdma); |
6bd08127 JM |
880 | return ret; |
881 | } | |
882 | ||
883 | ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma); | |
884 | if (ret) { | |
885 | pr_crit("Can't register ERRIRQ for DMA\n"); | |
886 | free_irq(MX1_DMA_INT, NULL); | |
cd5cf9da | 887 | kfree(imxdma); |
6bd08127 JM |
888 | return ret; |
889 | } | |
890 | } | |
891 | ||
892 | /* enable DMA module */ | |
cd5cf9da | 893 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
894 | |
895 | /* clear all interrupts */ | |
cd5cf9da | 896 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
897 | |
898 | /* disable interrupts */ | |
cd5cf9da | 899 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
900 | |
901 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
902 | ||
f8a356ff SH |
903 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
904 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 905 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f8a356ff | 906 | |
1f1846c6 | 907 | /* Initialize channel parameters */ |
6bd08127 | 908 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 | 909 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
2d9c2fc5 | 910 | |
6bd08127 JM |
911 | if (cpu_is_mx21() || cpu_is_mx27()) { |
912 | ret = request_irq(MX2x_INT_DMACH0 + i, | |
913 | dma_irq_handler, 0, "DMA", imxdma); | |
914 | if (ret) { | |
915 | pr_crit("Can't register IRQ %d for DMA channel %d\n", | |
916 | MX2x_INT_DMACH0 + i, i); | |
917 | goto err_init; | |
918 | } | |
2d9c2fc5 JM |
919 | init_timer(&imxdmac->watchdog); |
920 | imxdmac->watchdog.function = &imxdma_watchdog; | |
921 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 922 | } |
1f1846c6 | 923 | |
1f1846c6 SH |
924 | imxdmac->imxdma = imxdma; |
925 | spin_lock_init(&imxdmac->lock); | |
926 | ||
9e15db7c JM |
927 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
928 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
929 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
930 | ||
931 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
932 | (unsigned long)imxdmac); | |
1f1846c6 | 933 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 934 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
935 | imxdmac->channel = i; |
936 | ||
937 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
938 | list_add_tail(&imxdmac->chan.device_node, |
939 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
940 | } |
941 | ||
942 | imxdma->dev = &pdev->dev; | |
943 | imxdma->dma_device.dev = &pdev->dev; | |
944 | ||
945 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
946 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
947 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
948 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
949 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 950 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
1f1846c6 SH |
951 | imxdma->dma_device.device_control = imxdma_control; |
952 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
953 | ||
954 | platform_set_drvdata(pdev, imxdma); | |
955 | ||
6c05f091 | 956 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
957 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
958 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
959 | ||
1f1846c6 SH |
960 | ret = dma_async_device_register(&imxdma->dma_device); |
961 | if (ret) { | |
962 | dev_err(&pdev->dev, "unable to register\n"); | |
963 | goto err_init; | |
964 | } | |
965 | ||
966 | return 0; | |
967 | ||
968 | err_init: | |
6bd08127 JM |
969 | |
970 | if (cpu_is_mx21() || cpu_is_mx27()) { | |
971 | while (--i >= 0) | |
972 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
973 | } else if cpu_is_mx1() { | |
974 | free_irq(MX1_DMA_INT, NULL); | |
975 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
976 | } |
977 | ||
978 | kfree(imxdma); | |
979 | return ret; | |
980 | } | |
981 | ||
982 | static int __exit imxdma_remove(struct platform_device *pdev) | |
983 | { | |
984 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
985 | int i; | |
986 | ||
987 | dma_async_device_unregister(&imxdma->dma_device); | |
988 | ||
6bd08127 JM |
989 | if (cpu_is_mx21() || cpu_is_mx27()) { |
990 | for (i = 0; i < IMX_DMA_CHANNELS; i++) | |
991 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
992 | } else if cpu_is_mx1() { | |
993 | free_irq(MX1_DMA_INT, NULL); | |
994 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
995 | } |
996 | ||
997 | kfree(imxdma); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static struct platform_driver imxdma_driver = { | |
1003 | .driver = { | |
1004 | .name = "imx-dma", | |
1005 | }, | |
1006 | .remove = __exit_p(imxdma_remove), | |
1007 | }; | |
1008 | ||
1009 | static int __init imxdma_module_init(void) | |
1010 | { | |
1011 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1012 | } | |
1013 | subsys_initcall(imxdma_module_init); | |
1014 | ||
1015 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1016 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1017 | MODULE_LICENSE("GPL"); |