[deliverable/linux.git] / drivers / dma / imx-dma.c

/*
 * drivers/dma/imx-dma.c
 *
 * This file contains a driver for the Freescale i.MX DMA engine
 * found on i.MX1/21/27
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/module.h>

#include <asm/irq.h>
#include <mach/dma-v1.h>
#include <mach/hardware.h>

#include "dmaengine.h"

struct imxdma_channel {
	struct imxdma_engine		*imxdma;
	unsigned int			channel;
	unsigned int			imxdma_channel;

	enum dma_slave_buswidth		word_size;
	dma_addr_t			per_address;
	u32				watermark_level;
	struct dma_chan			chan;
	spinlock_t			lock;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	int				dma_request;
	struct scatterlist		*sg_list;
};

#define MAX_DMA_CHANNELS 8

struct imxdma_engine {
	struct device			*dev;
	struct device_dma_parameters	dma_parms;
	struct dma_device		dma_device;
	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
};

static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct imxdma_channel, chan);
}

static void imxdma_handle(struct imxdma_channel *imxdmac)
{
	if (imxdmac->desc.callback)
		imxdmac->desc.callback(imxdmac->desc.callback_param);
	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
}

static void imxdma_irq_handler(int channel, void *data)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_SUCCESS;
	imxdma_handle(imxdmac);
}

static void imxdma_err_handler(int channel, void *data, int error)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_ERROR;
	imxdma_handle(imxdmac);
}

static void imxdma_progression(int channel, void *data,
		struct scatterlist *sg)
{
	struct imxdma_channel *imxdmac = data;

	imxdmac->status = DMA_SUCCESS;
	imxdma_handle(imxdmac);
}

static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct dma_slave_config *dmaengine_cfg = (void *)arg;
	int ret;
	unsigned int mode = 0;

	switch (cmd) {
	case DMA_TERMINATE_ALL:
		imxdmac->status = DMA_ERROR;
		imx_dma_disable(imxdmac->imxdma_channel);
		return 0;
	case DMA_SLAVE_CONFIG:
		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
			imxdmac->per_address = dmaengine_cfg->src_addr;
			imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
			imxdmac->word_size = dmaengine_cfg->src_addr_width;
		} else {
			imxdmac->per_address = dmaengine_cfg->dst_addr;
			imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
			imxdmac->word_size = dmaengine_cfg->dst_addr_width;
		}

		switch (imxdmac->word_size) {
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
			mode = IMX_DMA_MEMSIZE_8;
			break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
			mode = IMX_DMA_MEMSIZE_16;
			break;
		default:
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
			mode = IMX_DMA_MEMSIZE_32;
			break;
		}
		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
				mode | IMX_DMA_TYPE_FIFO,
				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
				imxdmac->dma_request, 1);

		if (ret)
			return ret;

		imx_dma_config_burstlen(imxdmac->imxdma_channel,
				imxdmac->watermark_level * imxdmac->word_size);

		return 0;
	default:
		return -ENOSYS;
	}

	return -EINVAL;
}

static enum dma_status imxdma_tx_status(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	dma_cookie_t last_used;
	enum dma_status ret;

	last_used = chan->cookie;

	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);

	return ret;
}

static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
{
	dma_cookie_t cookie = imxdma->chan.cookie;

	if (++cookie < 0)
		cookie = 1;

	imxdma->chan.cookie = cookie;
	imxdma->desc.cookie = cookie;

	return cookie;
}

static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
	dma_cookie_t cookie;

	spin_lock_irq(&imxdmac->lock);

	cookie = imxdma_assign_cookie(imxdmac);

	spin_unlock_irq(&imxdmac->lock);

	return cookie;
}

static int imxdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imx_dma_data *data = chan->private;

	imxdmac->dma_request = data->dma_request;

	dma_async_tx_descriptor_init(&imxdmac->desc, chan);
	imxdmac->desc.tx_submit = imxdma_tx_submit;
	/* txd.flags will be overwritten in prep funcs */
	imxdmac->desc.flags = DMA_CTRL_ACK;

	imxdmac->status = DMA_SUCCESS;

	return 0;
}

static void imxdma_free_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);

	imx_dma_disable(imxdmac->imxdma_channel);

	if (imxdmac->sg_list) {
		kfree(imxdmac->sg_list);
		imxdmac->sg_list = NULL;
	}
}

static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct scatterlist *sg;
	int i, ret, dma_length = 0;
	unsigned int dmamode;

	if (imxdmac->status == DMA_IN_PROGRESS)
		return NULL;

	imxdmac->status = DMA_IN_PROGRESS;

	for_each_sg(sgl, sg, sg_len, i) {
		dma_length += sg->length;
	}

	if (direction == DMA_DEV_TO_MEM)
		dmamode = DMA_MODE_READ;
	else
		dmamode = DMA_MODE_WRITE;

	switch (imxdmac->word_size) {
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		if (sgl->length & 3 || sgl->dma_address & 3)
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
		if (sgl->length & 1 || sgl->dma_address & 1)
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		break;
	default:
		return NULL;
	}

	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
		 dma_length, imxdmac->per_address, dmamode);
	if (ret)
		return NULL;

	return &imxdmac->desc;
}

static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	int i, ret;
	unsigned int periods = buf_len / period_len;
	unsigned int dmamode;

	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
			__func__, imxdmac->channel, buf_len, period_len);

	if (imxdmac->status == DMA_IN_PROGRESS)
		return NULL;
	imxdmac->status = DMA_IN_PROGRESS;

	ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
			imxdma_progression);
	if (ret) {
		dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
		return NULL;
	}

	if (imxdmac->sg_list)
		kfree(imxdmac->sg_list);

	imxdmac->sg_list = kcalloc(periods + 1,
			sizeof(struct scatterlist), GFP_KERNEL);
	if (!imxdmac->sg_list)
		return NULL;

	sg_init_table(imxdmac->sg_list, periods);

	for (i = 0; i < periods; i++) {
		imxdmac->sg_list[i].page_link = 0;
		imxdmac->sg_list[i].offset = 0;
		imxdmac->sg_list[i].dma_address = dma_addr;
		imxdmac->sg_list[i].length = period_len;
		dma_addr += period_len;
	}

	/* close the loop */
	imxdmac->sg_list[periods].offset = 0;
	imxdmac->sg_list[periods].length = 0;
	imxdmac->sg_list[periods].page_link =
		((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;

	if (direction == DMA_DEV_TO_MEM)
		dmamode = DMA_MODE_READ;
	else
		dmamode = DMA_MODE_WRITE;

	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
		 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
	if (ret)
		return NULL;

	return &imxdmac->desc;
}

static void imxdma_issue_pending(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);

	if (imxdmac->status == DMA_IN_PROGRESS)
		imx_dma_enable(imxdmac->imxdma_channel);
}

static int __init imxdma_probe(struct platform_device *pdev)
{
	struct imxdma_engine *imxdma;
	int ret, i;

	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
	if (!imxdma)
		return -ENOMEM;

	INIT_LIST_HEAD(&imxdma->dma_device.channels);

	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);

	/* Initialize channel parameters */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
				DMA_PRIO_MEDIUM);
		if ((int)imxdmac->channel < 0) {
			ret = -ENODEV;
			goto err_init;
		}

		imx_dma_setup_handlers(imxdmac->imxdma_channel,
		       imxdma_irq_handler, imxdma_err_handler, imxdmac);

		imxdmac->imxdma = imxdma;
		spin_lock_init(&imxdmac->lock);

		imxdmac->chan.device = &imxdma->dma_device;
		imxdmac->channel = i;

		/* Add the channel to the DMAC list */
		list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
	}

	imxdma->dev = &pdev->dev;
	imxdma->dma_device.dev = &pdev->dev;

	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
	imxdma->dma_device.device_control = imxdma_control;
	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;

	platform_set_drvdata(pdev, imxdma);

	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);

	ret = dma_async_device_register(&imxdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
		goto err_init;
	}

	return 0;

err_init:
	while (--i >= 0) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];
		imx_dma_free(imxdmac->imxdma_channel);
	}

	kfree(imxdma);
	return ret;
}

static int __exit imxdma_remove(struct platform_device *pdev)
{
	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
	int i;

        dma_async_device_unregister(&imxdma->dma_device);

	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		 imx_dma_free(imxdmac->imxdma_channel);
	}

        kfree(imxdma);

        return 0;
}

static struct platform_driver imxdma_driver = {
	.driver		= {
		.name	= "imx-dma",
	},
	.remove		= __exit_p(imxdma_remove),
};

static int __init imxdma_module_init(void)
{
	return platform_driver_probe(&imxdma_driver, imxdma_probe);
}
subsys_initcall(imxdma_module_init);

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX dma driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1f1846c6 SH	1	/*
	2	* drivers/dma/imx-dma.c
	3	*
	4	* This file contains a driver for the Freescale i.MX DMA engine
	5	* found on i.MX1/21/27
	6	*
	7	* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16	#include <linux/init.h>
f8de8f4c	17	#include <linux/module.h>
1f1846c6 SH	18	#include <linux/types.h>
	19	#include <linux/mm.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/device.h>
	23	#include <linux/dma-mapping.h>
	24	#include <linux/slab.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/dmaengine.h>
5c45ad77	27	#include <linux/module.h>
1f1846c6 SH	28
	29	#include <asm/irq.h>
	30	#include <mach/dma-v1.h>
	31	#include <mach/hardware.h>
	32
d2ebfb33 RKAL	33	#include "dmaengine.h"
d2ebfb33 RKAL	34
1f1846c6 SH	35	struct imxdma_channel {
	36	struct imxdma_engine *imxdma;
	37	unsigned int channel;
	38	unsigned int imxdma_channel;
	39
	40	enum dma_slave_buswidth word_size;
	41	dma_addr_t per_address;
	42	u32 watermark_level;
	43	struct dma_chan chan;
	44	spinlock_t lock;
	45	struct dma_async_tx_descriptor desc;
1f1846c6 SH	46	enum dma_status status;
	47	int dma_request;
	48	struct scatterlist *sg_list;
	49	};
	50
	51	#define MAX_DMA_CHANNELS 8
	52
	53	struct imxdma_engine {
	54	struct device *dev;
1e070a60	55	struct device_dma_parameters dma_parms;
1f1846c6 SH	56	struct dma_device dma_device;
	57	struct imxdma_channel channel[MAX_DMA_CHANNELS];
	58	};
	59
	60	static struct imxdma_channel to_imxdma_chan(struct dma_chan chan)
	61	{
	62	return container_of(chan, struct imxdma_channel, chan);
	63	}
	64
	65	static void imxdma_handle(struct imxdma_channel *imxdmac)
	66	{
	67	if (imxdmac->desc.callback)
	68	imxdmac->desc.callback(imxdmac->desc.callback_param);
4d4e58de	69	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
1f1846c6 SH	70	}
	71
	72	static void imxdma_irq_handler(int channel, void *data)
	73	{
	74	struct imxdma_channel *imxdmac = data;
	75
	76	imxdmac->status = DMA_SUCCESS;
	77	imxdma_handle(imxdmac);
	78	}
	79
	80	static void imxdma_err_handler(int channel, void *data, int error)
	81	{
	82	struct imxdma_channel *imxdmac = data;
	83
	84	imxdmac->status = DMA_ERROR;
	85	imxdma_handle(imxdmac);
	86	}
	87
	88	static void imxdma_progression(int channel, void *data,
	89	struct scatterlist *sg)
	90	{
	91	struct imxdma_channel *imxdmac = data;
	92
	93	imxdmac->status = DMA_SUCCESS;
	94	imxdma_handle(imxdmac);
	95	}
	96
	97	static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
	98	unsigned long arg)
	99	{
	100	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	101	struct dma_slave_config dmaengine_cfg = (void )arg;
	102	int ret;
	103	unsigned int mode = 0;
	104
	105	switch (cmd) {
	106	case DMA_TERMINATE_ALL:
	107	imxdmac->status = DMA_ERROR;
	108	imx_dma_disable(imxdmac->imxdma_channel);
	109	return 0;
	110	case DMA_SLAVE_CONFIG:
db8196df	111	if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1f1846c6 SH	112	imxdmac->per_address = dmaengine_cfg->src_addr;
	113	imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
	114	imxdmac->word_size = dmaengine_cfg->src_addr_width;
	115	} else {
	116	imxdmac->per_address = dmaengine_cfg->dst_addr;
	117	imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
	118	imxdmac->word_size = dmaengine_cfg->dst_addr_width;
	119	}
	120
	121	switch (imxdmac->word_size) {
	122	case DMA_SLAVE_BUSWIDTH_1_BYTE:
	123	mode = IMX_DMA_MEMSIZE_8;
	124	break;
	125	case DMA_SLAVE_BUSWIDTH_2_BYTES:
	126	mode = IMX_DMA_MEMSIZE_16;
	127	break;
	128	default:
	129	case DMA_SLAVE_BUSWIDTH_4_BYTES:
	130	mode = IMX_DMA_MEMSIZE_32;
	131	break;
	132	}
	133	ret = imx_dma_config_channel(imxdmac->imxdma_channel,
	134	mode \| IMX_DMA_TYPE_FIFO,
	135	IMX_DMA_MEMSIZE_32 \| IMX_DMA_TYPE_LINEAR,
	136	imxdmac->dma_request, 1);
	137
	138	if (ret)
	139	return ret;
	140
6584cb88 SH	141	imx_dma_config_burstlen(imxdmac->imxdma_channel,
6584cb88 SH	142	imxdmac->watermark_level * imxdmac->word_size);
1f1846c6 SH	143
	144	return 0;
	145	default:
	146	return -ENOSYS;
	147	}
	148
	149	return -EINVAL;
	150	}
	151
	152	static enum dma_status imxdma_tx_status(struct dma_chan *chan,
	153	dma_cookie_t cookie,
	154	struct dma_tx_state *txstate)
	155	{
	156	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	157	dma_cookie_t last_used;
	158	enum dma_status ret;
	159
	160	last_used = chan->cookie;
	161
4d4e58de RKAL	162	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
4d4e58de RKAL	163	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
1f1846c6 SH	164
	165	return ret;
	166	}
	167
	168	static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
	169	{
	170	dma_cookie_t cookie = imxdma->chan.cookie;
	171
	172	if (++cookie < 0)
	173	cookie = 1;
	174
	175	imxdma->chan.cookie = cookie;
	176	imxdma->desc.cookie = cookie;
	177
	178	return cookie;
	179	}
	180
	181	static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
	182	{
	183	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
	184	dma_cookie_t cookie;
	185
	186	spin_lock_irq(&imxdmac->lock);
	187
	188	cookie = imxdma_assign_cookie(imxdmac);
	189
1f1846c6 SH	190	spin_unlock_irq(&imxdmac->lock);
	191
	192	return cookie;
	193	}
	194
	195	static int imxdma_alloc_chan_resources(struct dma_chan *chan)
	196	{
	197	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	198	struct imx_dma_data *data = chan->private;
	199
	200	imxdmac->dma_request = data->dma_request;
	201
	202	dma_async_tx_descriptor_init(&imxdmac->desc, chan);
	203	imxdmac->desc.tx_submit = imxdma_tx_submit;
	204	/* txd.flags will be overwritten in prep funcs */
	205	imxdmac->desc.flags = DMA_CTRL_ACK;
	206
	207	imxdmac->status = DMA_SUCCESS;
	208
	209	return 0;
	210	}
	211
	212	static void imxdma_free_chan_resources(struct dma_chan *chan)
	213	{
	214	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	215
	216	imx_dma_disable(imxdmac->imxdma_channel);
	217
	218	if (imxdmac->sg_list) {
	219	kfree(imxdmac->sg_list);
	220	imxdmac->sg_list = NULL;
	221	}
	222	}
	223
	224	static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
	225	struct dma_chan chan, struct scatterlist sgl,
db8196df	226	unsigned int sg_len, enum dma_transfer_direction direction,
1f1846c6 SH	227	unsigned long flags)
	228	{
	229	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	230	struct scatterlist *sg;
	231	int i, ret, dma_length = 0;
	232	unsigned int dmamode;
	233
	234	if (imxdmac->status == DMA_IN_PROGRESS)
	235	return NULL;
	236
	237	imxdmac->status = DMA_IN_PROGRESS;
	238
	239	for_each_sg(sgl, sg, sg_len, i) {
	240	dma_length += sg->length;
	241	}
	242
db8196df	243	if (direction == DMA_DEV_TO_MEM)
1f1846c6 SH	244	dmamode = DMA_MODE_READ;
	245	else
	246	dmamode = DMA_MODE_WRITE;
	247
d07102a1 SH	248	switch (imxdmac->word_size) {
	249	case DMA_SLAVE_BUSWIDTH_4_BYTES:
	250	if (sgl->length & 3 \|\| sgl->dma_address & 3)
	251	return NULL;
	252	break;
	253	case DMA_SLAVE_BUSWIDTH_2_BYTES:
	254	if (sgl->length & 1 \|\| sgl->dma_address & 1)
	255	return NULL;
	256	break;
	257	case DMA_SLAVE_BUSWIDTH_1_BYTE:
	258	break;
	259	default:
	260	return NULL;
	261	}
	262
1f1846c6 SH	263	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
	264	dma_length, imxdmac->per_address, dmamode);
	265	if (ret)
	266	return NULL;
	267
	268	return &imxdmac->desc;
	269	}
	270
	271	static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
	272	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
db8196df	273	size_t period_len, enum dma_transfer_direction direction)
1f1846c6 SH	274	{
	275	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	276	struct imxdma_engine *imxdma = imxdmac->imxdma;
	277	int i, ret;
	278	unsigned int periods = buf_len / period_len;
	279	unsigned int dmamode;
	280
	281	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
	282	__func__, imxdmac->channel, buf_len, period_len);
	283
	284	if (imxdmac->status == DMA_IN_PROGRESS)
	285	return NULL;
	286	imxdmac->status = DMA_IN_PROGRESS;
	287
	288	ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
	289	imxdma_progression);
	290	if (ret) {
	291	dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
	292	return NULL;
	293	}
	294
	295	if (imxdmac->sg_list)
	296	kfree(imxdmac->sg_list);
	297
	298	imxdmac->sg_list = kcalloc(periods + 1,
	299	sizeof(struct scatterlist), GFP_KERNEL);
	300	if (!imxdmac->sg_list)
	301	return NULL;
	302
	303	sg_init_table(imxdmac->sg_list, periods);
	304
	305	for (i = 0; i < periods; i++) {
	306	imxdmac->sg_list[i].page_link = 0;
	307	imxdmac->sg_list[i].offset = 0;
	308	imxdmac->sg_list[i].dma_address = dma_addr;
	309	imxdmac->sg_list[i].length = period_len;
	310	dma_addr += period_len;
	311	}
	312
	313	/* close the loop */
	314	imxdmac->sg_list[periods].offset = 0;
	315	imxdmac->sg_list[periods].length = 0;
	316	imxdmac->sg_list[periods].page_link =
	317	((unsigned long)imxdmac->sg_list \| 0x01) & ~0x02;
	318
db8196df	319	if (direction == DMA_DEV_TO_MEM)
1f1846c6 SH	320	dmamode = DMA_MODE_READ;
	321	else
	322	dmamode = DMA_MODE_WRITE;
	323
	324	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
	325	IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
	326	if (ret)
	327	return NULL;
	328
	329	return &imxdmac->desc;
	330	}
	331
	332	static void imxdma_issue_pending(struct dma_chan *chan)
	333	{
5b316876 SH	334	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	335
	336	if (imxdmac->status == DMA_IN_PROGRESS)
	337	imx_dma_enable(imxdmac->imxdma_channel);
1f1846c6 SH	338	}
	339
	340	static int __init imxdma_probe(struct platform_device *pdev)
	341	{
	342	struct imxdma_engine *imxdma;
	343	int ret, i;
	344
	345	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
	346	if (!imxdma)
	347	return -ENOMEM;
	348
	349	INIT_LIST_HEAD(&imxdma->dma_device.channels);
	350
f8a356ff SH	351	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	352	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
	353
1f1846c6 SH	354	/* Initialize channel parameters */
	355	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
	356	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	357
	358	imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
	359	DMA_PRIO_MEDIUM);
8267f16e SH	360	if ((int)imxdmac->channel < 0) {
8267f16e SH	361	ret = -ENODEV;
1f1846c6	362	goto err_init;
8267f16e	363	}
1f1846c6 SH	364
	365	imx_dma_setup_handlers(imxdmac->imxdma_channel,
	366	imxdma_irq_handler, imxdma_err_handler, imxdmac);
	367
	368	imxdmac->imxdma = imxdma;
	369	spin_lock_init(&imxdmac->lock);
	370
1f1846c6	371	imxdmac->chan.device = &imxdma->dma_device;
1f1846c6 SH	372	imxdmac->channel = i;
	373
	374	/* Add the channel to the DMAC list */
	375	list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
	376	}
	377
	378	imxdma->dev = &pdev->dev;
	379	imxdma->dma_device.dev = &pdev->dev;
	380
	381	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	382	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	383	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	384	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	385	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
	386	imxdma->dma_device.device_control = imxdma_control;
	387	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
	388
	389	platform_set_drvdata(pdev, imxdma);
	390
1e070a60 SH	391	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	392	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
	393
1f1846c6 SH	394	ret = dma_async_device_register(&imxdma->dma_device);
	395	if (ret) {
	396	dev_err(&pdev->dev, "unable to register\n");
	397	goto err_init;
	398	}
	399
	400	return 0;
	401
	402	err_init:
cbeae418	403	while (--i >= 0) {
1f1846c6 SH	404	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	405	imx_dma_free(imxdmac->imxdma_channel);
	406	}
	407
	408	kfree(imxdma);
	409	return ret;
	410	}
	411
	412	static int __exit imxdma_remove(struct platform_device *pdev)
	413	{
	414	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
	415	int i;
	416
	417	dma_async_device_unregister(&imxdma->dma_device);
	418
	419	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
	420	struct imxdma_channel *imxdmac = &imxdma->channel[i];
	421
	422	imx_dma_free(imxdmac->imxdma_channel);
	423	}
	424
	425	kfree(imxdma);
	426
	427	return 0;
	428	}
	429
	430	static struct platform_driver imxdma_driver = {
	431	.driver = {
	432	.name = "imx-dma",
	433	},
	434	.remove = __exit_p(imxdma_remove),
	435	};
	436
	437	static int __init imxdma_module_init(void)
	438	{
	439	return platform_driver_probe(&imxdma_driver, imxdma_probe);
	440	}
	441	subsys_initcall(imxdma_module_init);
	442
	443	MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
	444	MODULE_DESCRIPTION("i.MX dma driver");
	445	MODULE_LICENSE("GPL");