Commit | Line | Data |
---|---|---|
1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
17 | #include <linux/init.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/platform_device.h> | |
6bd08127 | 26 | #include <linux/clk.h> |
1f1846c6 | 27 | #include <linux/dmaengine.h> |
5c45ad77 | 28 | #include <linux/module.h> |
1f1846c6 SH |
29 | |
30 | #include <asm/irq.h> | |
82906b13 | 31 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 32 | |
d2ebfb33 | 33 | #include "dmaengine.h" |
9e15db7c | 34 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
35 | #define IMX_DMA_CHANNELS 16 |
36 | ||
f606ab89 JM |
37 | #define IMX_DMA_2D_SLOTS 2 |
38 | #define IMX_DMA_2D_SLOT_A 0 | |
39 | #define IMX_DMA_2D_SLOT_B 1 | |
40 | ||
6bd08127 JM |
41 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
42 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
43 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
44 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
45 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
46 | #define IMX_DMA_TYPE_2D (1 << 10) | |
47 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
48 | ||
49 | #define IMX_DMA_ERR_BURST (1 << 0) | |
50 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
51 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
52 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
53 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
54 | ||
55 | #define DMA_DCR 0x00 /* Control Register */ | |
56 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
57 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
58 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
59 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
60 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
61 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
62 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
63 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
64 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
65 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
66 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
67 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
68 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
69 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
70 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
71 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
72 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
73 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
74 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
75 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
76 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
77 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
78 | ||
79 | #define DCR_DRST (1<<1) | |
80 | #define DCR_DEN (1<<0) | |
81 | #define DBTOCR_EN (1<<15) | |
82 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
83 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
84 | #define CCR_ACRPT (1<<14) | |
85 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
86 | #define CCR_DMOD_2D (0x1 << 12) | |
87 | #define CCR_DMOD_FIFO (0x2 << 12) | |
88 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
89 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
90 | #define CCR_SMOD_2D (0x1 << 10) | |
91 | #define CCR_SMOD_FIFO (0x2 << 10) | |
92 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
93 | #define CCR_MDIR_DEC (1<<9) | |
94 | #define CCR_MSEL_B (1<<8) | |
95 | #define CCR_DSIZ_32 (0x0 << 6) | |
96 | #define CCR_DSIZ_8 (0x1 << 6) | |
97 | #define CCR_DSIZ_16 (0x2 << 6) | |
98 | #define CCR_SSIZ_32 (0x0 << 4) | |
99 | #define CCR_SSIZ_8 (0x1 << 4) | |
100 | #define CCR_SSIZ_16 (0x2 << 4) | |
101 | #define CCR_REN (1<<3) | |
102 | #define CCR_RPT (1<<2) | |
103 | #define CCR_FRC (1<<1) | |
104 | #define CCR_CEN (1<<0) | |
105 | #define RTOR_EN (1<<15) | |
106 | #define RTOR_CLK (1<<14) | |
107 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
108 | |
109 | enum imxdma_prep_type { | |
110 | IMXDMA_DESC_MEMCPY, | |
111 | IMXDMA_DESC_INTERLEAVED, | |
112 | IMXDMA_DESC_SLAVE_SG, | |
113 | IMXDMA_DESC_CYCLIC, | |
114 | }; | |
115 | ||
f606ab89 JM |
116 | struct imx_dma_2d_config { |
117 | u16 xsr; | |
118 | u16 ysr; | |
119 | u16 wsr; | |
120 | int count; | |
121 | }; | |
122 | ||
9e15db7c JM |
123 | struct imxdma_desc { |
124 | struct list_head node; | |
125 | struct dma_async_tx_descriptor desc; | |
126 | enum dma_status status; | |
127 | dma_addr_t src; | |
128 | dma_addr_t dest; | |
129 | size_t len; | |
2efc3449 | 130 | enum dma_transfer_direction direction; |
9e15db7c JM |
131 | enum imxdma_prep_type type; |
132 | /* For memcpy and interleaved */ | |
133 | unsigned int config_port; | |
134 | unsigned int config_mem; | |
135 | /* For interleaved transfers */ | |
136 | unsigned int x; | |
137 | unsigned int y; | |
138 | unsigned int w; | |
139 | /* For slave sg and cyclic */ | |
140 | struct scatterlist *sg; | |
141 | unsigned int sgcount; | |
142 | }; | |
143 | ||
1f1846c6 | 144 | struct imxdma_channel { |
2d9c2fc5 JM |
145 | int hw_chaining; |
146 | struct timer_list watchdog; | |
1f1846c6 SH |
147 | struct imxdma_engine *imxdma; |
148 | unsigned int channel; | |
1f1846c6 | 149 | |
9e15db7c JM |
150 | struct tasklet_struct dma_tasklet; |
151 | struct list_head ld_free; | |
152 | struct list_head ld_queue; | |
153 | struct list_head ld_active; | |
154 | int descs_allocated; | |
1f1846c6 SH |
155 | enum dma_slave_buswidth word_size; |
156 | dma_addr_t per_address; | |
157 | u32 watermark_level; | |
158 | struct dma_chan chan; | |
1f1846c6 | 159 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
160 | enum dma_status status; |
161 | int dma_request; | |
162 | struct scatterlist *sg_list; | |
359291a1 JM |
163 | u32 ccr_from_device; |
164 | u32 ccr_to_device; | |
f606ab89 JM |
165 | bool enabled_2d; |
166 | int slot_2d; | |
1f1846c6 SH |
167 | }; |
168 | ||
e51d0f0a SG |
169 | enum imx_dma_type { |
170 | IMX1_DMA, | |
171 | IMX21_DMA, | |
172 | IMX27_DMA, | |
173 | }; | |
174 | ||
1f1846c6 SH |
175 | struct imxdma_engine { |
176 | struct device *dev; | |
1e070a60 | 177 | struct device_dma_parameters dma_parms; |
1f1846c6 | 178 | struct dma_device dma_device; |
cd5cf9da | 179 | void __iomem *base; |
a2367db2 FE |
180 | struct clk *dma_ahb; |
181 | struct clk *dma_ipg; | |
f606ab89 JM |
182 | spinlock_t lock; |
183 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 184 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 185 | enum imx_dma_type devtype; |
1f1846c6 SH |
186 | }; |
187 | ||
e51d0f0a SG |
188 | static struct platform_device_id imx_dma_devtype[] = { |
189 | { | |
190 | .name = "imx1-dma", | |
191 | .driver_data = IMX1_DMA, | |
192 | }, { | |
193 | .name = "imx21-dma", | |
194 | .driver_data = IMX21_DMA, | |
195 | }, { | |
196 | .name = "imx27-dma", | |
197 | .driver_data = IMX27_DMA, | |
198 | }, { | |
199 | /* sentinel */ | |
200 | } | |
201 | }; | |
202 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
203 | ||
204 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) | |
205 | { | |
206 | return imxdma->devtype == IMX1_DMA; | |
207 | } | |
208 | ||
209 | static inline int is_imx21_dma(struct imxdma_engine *imxdma) | |
210 | { | |
211 | return imxdma->devtype == IMX21_DMA; | |
212 | } | |
213 | ||
214 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) | |
215 | { | |
216 | return imxdma->devtype == IMX27_DMA; | |
217 | } | |
218 | ||
1f1846c6 SH |
219 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
220 | { | |
221 | return container_of(chan, struct imxdma_channel, chan); | |
222 | } | |
223 | ||
9e15db7c | 224 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 225 | { |
9e15db7c JM |
226 | struct imxdma_desc *desc; |
227 | ||
228 | if (!list_empty(&imxdmac->ld_active)) { | |
229 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
230 | node); | |
231 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
232 | return true; | |
233 | } | |
234 | return false; | |
1f1846c6 SH |
235 | } |
236 | ||
6bd08127 | 237 | |
cd5cf9da JM |
238 | |
239 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
240 | unsigned offset) | |
6bd08127 | 241 | { |
cd5cf9da | 242 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
243 | } |
244 | ||
cd5cf9da | 245 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 246 | { |
cd5cf9da | 247 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 248 | } |
1f1846c6 | 249 | |
2d9c2fc5 | 250 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 251 | { |
e51d0f0a SG |
252 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
253 | ||
254 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 255 | return imxdmac->hw_chaining; |
6bd08127 JM |
256 | else |
257 | return 0; | |
258 | } | |
259 | ||
260 | /* | |
261 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
262 | */ | |
a6cbb2d8 | 263 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 264 | { |
2efc3449 | 265 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 266 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 267 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
268 | unsigned long now; |
269 | ||
fdaf9c4b | 270 | now = min(d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
271 | if (d->len != IMX_DMA_LENGTH_LOOP) |
272 | d->len -= now; | |
6bd08127 | 273 | |
2efc3449 | 274 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
275 | imx_dmav1_writel(imxdma, sg->dma_address, |
276 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 277 | else |
cd5cf9da JM |
278 | imx_dmav1_writel(imxdma, sg->dma_address, |
279 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 280 | |
cd5cf9da | 281 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 282 | |
f9b283a6 JM |
283 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
284 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
285 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
286 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
287 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
288 | |
289 | return now; | |
1f1846c6 SH |
290 | } |
291 | ||
2efc3449 | 292 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 293 | { |
2efc3449 | 294 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 295 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
296 | int channel = imxdmac->channel; |
297 | unsigned long flags; | |
298 | ||
f9b283a6 | 299 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 300 | |
6bd08127 JM |
301 | local_irq_save(flags); |
302 | ||
cd5cf9da JM |
303 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
304 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
305 | ~(1 << channel), DMA_DIMR); | |
306 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
307 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 308 | |
e51d0f0a | 309 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 310 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
311 | d->sg = sg_next(d->sg); |
312 | if (d->sg) { | |
6bd08127 | 313 | u32 tmp; |
a6cbb2d8 | 314 | imxdma_sg_next(d); |
cd5cf9da JM |
315 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
316 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
317 | DMA_CCR(channel)); | |
6bd08127 JM |
318 | } |
319 | } | |
6bd08127 JM |
320 | |
321 | local_irq_restore(flags); | |
322 | } | |
323 | ||
324 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
325 | { | |
cd5cf9da | 326 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
327 | int channel = imxdmac->channel; |
328 | unsigned long flags; | |
329 | ||
f9b283a6 | 330 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 331 | |
2d9c2fc5 JM |
332 | if (imxdma_hw_chain(imxdmac)) |
333 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
334 | |
335 | local_irq_save(flags); | |
cd5cf9da JM |
336 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
337 | (1 << channel), DMA_DIMR); | |
338 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
339 | ~CCR_CEN, DMA_CCR(channel)); | |
340 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
341 | local_irq_restore(flags); |
342 | } | |
343 | ||
6bd08127 | 344 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 345 | { |
6bd08127 | 346 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
cd5cf9da | 347 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 348 | int channel = imxdmac->channel; |
1f1846c6 | 349 | |
cd5cf9da | 350 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 351 | |
6bd08127 | 352 | /* Tasklet watchdog error handler */ |
9e15db7c | 353 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
354 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
355 | imxdmac->channel); | |
1f1846c6 SH |
356 | } |
357 | ||
6bd08127 | 358 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 359 | { |
6bd08127 | 360 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
361 | unsigned int err_mask; |
362 | int i, disr; | |
363 | int errcode; | |
364 | ||
cd5cf9da | 365 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 366 | |
cd5cf9da JM |
367 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
368 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
369 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
370 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
371 | |
372 | if (!err_mask) | |
373 | return IRQ_HANDLED; | |
374 | ||
cd5cf9da | 375 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
376 | |
377 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
378 | if (!(err_mask & (1 << i))) | |
379 | continue; | |
6bd08127 JM |
380 | errcode = 0; |
381 | ||
cd5cf9da JM |
382 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
383 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
384 | errcode |= IMX_DMA_ERR_BURST; |
385 | } | |
cd5cf9da JM |
386 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
387 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
388 | errcode |= IMX_DMA_ERR_REQUEST; |
389 | } | |
cd5cf9da JM |
390 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
391 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
392 | errcode |= IMX_DMA_ERR_TRANSFER; |
393 | } | |
cd5cf9da JM |
394 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
395 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
396 | errcode |= IMX_DMA_ERR_BUFFER; |
397 | } | |
398 | /* Tasklet error handler */ | |
399 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
400 | ||
401 | printk(KERN_WARNING | |
402 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
403 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
404 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
405 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
406 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
407 | } | |
408 | return IRQ_HANDLED; | |
1f1846c6 SH |
409 | } |
410 | ||
6bd08127 | 411 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 412 | { |
cd5cf9da | 413 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 414 | int chno = imxdmac->channel; |
2efc3449 | 415 | struct imxdma_desc *desc; |
6bd08127 | 416 | |
f606ab89 | 417 | spin_lock(&imxdma->lock); |
833bc03b | 418 | if (list_empty(&imxdmac->ld_active)) { |
f606ab89 | 419 | spin_unlock(&imxdma->lock); |
833bc03b JM |
420 | goto out; |
421 | } | |
2efc3449 | 422 | |
833bc03b JM |
423 | desc = list_first_entry(&imxdmac->ld_active, |
424 | struct imxdma_desc, | |
425 | node); | |
f606ab89 | 426 | spin_unlock(&imxdma->lock); |
2efc3449 | 427 | |
833bc03b JM |
428 | if (desc->sg) { |
429 | u32 tmp; | |
430 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 431 | |
833bc03b | 432 | if (desc->sg) { |
a6cbb2d8 | 433 | imxdma_sg_next(desc); |
6bd08127 | 434 | |
cd5cf9da | 435 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 436 | |
2d9c2fc5 | 437 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
438 | /* FIXME: The timeout should probably be |
439 | * configurable | |
440 | */ | |
2d9c2fc5 | 441 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
442 | jiffies + msecs_to_jiffies(500)); |
443 | ||
444 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 445 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 446 | } else { |
cd5cf9da JM |
447 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
448 | DMA_CCR(chno)); | |
6bd08127 JM |
449 | tmp |= CCR_CEN; |
450 | } | |
451 | ||
cd5cf9da | 452 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
453 | |
454 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
455 | /* Tasklet progression */ | |
456 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 457 | |
6bd08127 JM |
458 | return; |
459 | } | |
460 | ||
2d9c2fc5 JM |
461 | if (imxdma_hw_chain(imxdmac)) { |
462 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
463 | return; |
464 | } | |
465 | } | |
466 | ||
2efc3449 | 467 | out: |
cd5cf9da | 468 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 469 | /* Tasklet irq */ |
9e15db7c JM |
470 | tasklet_schedule(&imxdmac->dma_tasklet); |
471 | } | |
472 | ||
6bd08127 JM |
473 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
474 | { | |
475 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
476 | int i, disr; |
477 | ||
e51d0f0a | 478 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
479 | imxdma_err_handler(irq, dev_id); |
480 | ||
cd5cf9da | 481 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 482 | |
f9b283a6 | 483 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 484 | |
cd5cf9da | 485 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 486 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 487 | if (disr & (1 << i)) |
6bd08127 | 488 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
489 | } |
490 | ||
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
9e15db7c JM |
494 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
495 | { | |
496 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 497 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
498 | unsigned long flags; |
499 | int slot = -1; | |
500 | int i; | |
9e15db7c JM |
501 | |
502 | /* Configure and enable */ | |
503 | switch (d->type) { | |
f606ab89 JM |
504 | case IMXDMA_DESC_INTERLEAVED: |
505 | /* Try to get a free 2D slot */ | |
506 | spin_lock_irqsave(&imxdma->lock, flags); | |
507 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { | |
508 | if ((imxdma->slots_2d[i].count > 0) && | |
509 | ((imxdma->slots_2d[i].xsr != d->x) || | |
510 | (imxdma->slots_2d[i].ysr != d->y) || | |
511 | (imxdma->slots_2d[i].wsr != d->w))) | |
512 | continue; | |
513 | slot = i; | |
514 | break; | |
515 | } | |
516 | if (slot < 0) | |
517 | return -EBUSY; | |
518 | ||
519 | imxdma->slots_2d[slot].xsr = d->x; | |
520 | imxdma->slots_2d[slot].ysr = d->y; | |
521 | imxdma->slots_2d[slot].wsr = d->w; | |
522 | imxdma->slots_2d[slot].count++; | |
523 | ||
524 | imxdmac->slot_2d = slot; | |
525 | imxdmac->enabled_2d = true; | |
526 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
527 | ||
528 | if (slot == IMX_DMA_2D_SLOT_A) { | |
529 | d->config_mem &= ~CCR_MSEL_B; | |
530 | d->config_port &= ~CCR_MSEL_B; | |
531 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
532 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
533 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
534 | } else { | |
535 | d->config_mem |= CCR_MSEL_B; | |
536 | d->config_port |= CCR_MSEL_B; | |
537 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
538 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
539 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
540 | } | |
541 | /* | |
542 | * We fall-through here intentionally, since a 2D transfer is | |
543 | * similar to MEMCPY just adding the 2D slot configuration. | |
544 | */ | |
9e15db7c | 545 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
546 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
547 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
548 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 549 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 550 | |
cd5cf9da | 551 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc JM |
552 | |
553 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
554 | "dma_length=%d\n", __func__, imxdmac->channel, | |
555 | d->dest, d->src, d->len); | |
556 | ||
557 | break; | |
6bd08127 | 558 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 559 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 560 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 561 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 562 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 563 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 564 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
565 | DMA_CCR(imxdmac->channel)); |
566 | ||
567 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
568 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
569 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
570 | d->len, imxdmac->per_address); | |
571 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
cd5cf9da | 572 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 573 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 574 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
575 | DMA_CCR(imxdmac->channel)); |
576 | ||
577 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
578 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
579 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
580 | d->len, imxdmac->per_address); | |
581 | } else { | |
582 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
583 | __func__, imxdmac->channel); | |
584 | return -EINVAL; | |
585 | } | |
586 | ||
a6cbb2d8 | 587 | imxdma_sg_next(d); |
1f1846c6 | 588 | |
9e15db7c JM |
589 | break; |
590 | default: | |
591 | return -EINVAL; | |
592 | } | |
2efc3449 | 593 | imxdma_enable_hw(d); |
9e15db7c | 594 | return 0; |
1f1846c6 SH |
595 | } |
596 | ||
9e15db7c | 597 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 598 | { |
9e15db7c JM |
599 | struct imxdma_channel *imxdmac = (void *)data; |
600 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
601 | struct imxdma_desc *desc; | |
1f1846c6 | 602 | |
f606ab89 | 603 | spin_lock(&imxdma->lock); |
9e15db7c JM |
604 | |
605 | if (list_empty(&imxdmac->ld_active)) { | |
606 | /* Someone might have called terminate all */ | |
607 | goto out; | |
608 | } | |
609 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
610 | ||
611 | if (desc->desc.callback) | |
612 | desc->desc.callback(desc->desc.callback_param); | |
613 | ||
d73111c6 MI |
614 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
615 | * and dont mark the descriptor as complete. | |
60f2951e VK |
616 | * Only in non-cyclic cases it would be marked as complete |
617 | */ | |
9e15db7c JM |
618 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
619 | goto out; | |
60f2951e VK |
620 | else |
621 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 622 | |
f606ab89 JM |
623 | /* Free 2D slot if it was an interleaved transfer */ |
624 | if (imxdmac->enabled_2d) { | |
625 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
626 | imxdmac->enabled_2d = false; | |
627 | } | |
628 | ||
9e15db7c JM |
629 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
630 | ||
631 | if (!list_empty(&imxdmac->ld_queue)) { | |
632 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
633 | node); | |
634 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
635 | if (imxdma_xfer_desc(desc) < 0) | |
636 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
637 | __func__, imxdmac->channel); | |
638 | } | |
639 | out: | |
f606ab89 | 640 | spin_unlock(&imxdma->lock); |
1f1846c6 SH |
641 | } |
642 | ||
643 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
644 | unsigned long arg) | |
645 | { | |
646 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
647 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
cd5cf9da | 648 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 649 | unsigned long flags; |
1f1846c6 SH |
650 | unsigned int mode = 0; |
651 | ||
652 | switch (cmd) { | |
653 | case DMA_TERMINATE_ALL: | |
6bd08127 | 654 | imxdma_disable_hw(imxdmac); |
9e15db7c | 655 | |
f606ab89 | 656 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
657 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
658 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
f606ab89 | 659 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
660 | return 0; |
661 | case DMA_SLAVE_CONFIG: | |
db8196df | 662 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
663 | imxdmac->per_address = dmaengine_cfg->src_addr; |
664 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
665 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
666 | } else { | |
667 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
668 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
669 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
670 | } | |
671 | ||
672 | switch (imxdmac->word_size) { | |
673 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
674 | mode = IMX_DMA_MEMSIZE_8; | |
675 | break; | |
676 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
677 | mode = IMX_DMA_MEMSIZE_16; | |
678 | break; | |
679 | default: | |
680 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
681 | mode = IMX_DMA_MEMSIZE_32; | |
682 | break; | |
683 | } | |
1f1846c6 | 684 | |
2d9c2fc5 JM |
685 | imxdmac->hw_chaining = 1; |
686 | if (!imxdma_hw_chain(imxdmac)) | |
bdc0c753 | 687 | return -EINVAL; |
359291a1 | 688 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
689 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
690 | CCR_REN; | |
359291a1 | 691 | imxdmac->ccr_to_device = |
bdc0c753 JM |
692 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
693 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
cd5cf9da | 694 | imx_dmav1_writel(imxdma, imxdmac->dma_request, |
bdc0c753 JM |
695 | DMA_RSSR(imxdmac->channel)); |
696 | ||
6bd08127 | 697 | /* Set burst length */ |
cd5cf9da JM |
698 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * |
699 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
700 | |
701 | return 0; | |
702 | default: | |
703 | return -ENOSYS; | |
704 | } | |
705 | ||
706 | return -EINVAL; | |
707 | } | |
708 | ||
709 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
710 | dma_cookie_t cookie, | |
711 | struct dma_tx_state *txstate) | |
712 | { | |
96a2af41 | 713 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
714 | } |
715 | ||
716 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
717 | { | |
718 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 719 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 720 | dma_cookie_t cookie; |
9e15db7c | 721 | unsigned long flags; |
1f1846c6 | 722 | |
f606ab89 | 723 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 724 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 725 | cookie = dma_cookie_assign(tx); |
f606ab89 | 726 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
727 | |
728 | return cookie; | |
729 | } | |
730 | ||
731 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
732 | { | |
733 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
734 | struct imx_dma_data *data = chan->private; | |
735 | ||
6c05f091 JM |
736 | if (data != NULL) |
737 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 738 | |
9e15db7c JM |
739 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
740 | struct imxdma_desc *desc; | |
1f1846c6 | 741 | |
9e15db7c JM |
742 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
743 | if (!desc) | |
744 | break; | |
745 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
746 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
747 | desc->desc.tx_submit = imxdma_tx_submit; | |
748 | /* txd.flags will be overwritten in prep funcs */ | |
749 | desc->desc.flags = DMA_CTRL_ACK; | |
750 | desc->status = DMA_SUCCESS; | |
751 | ||
752 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
753 | imxdmac->descs_allocated++; | |
754 | } | |
1f1846c6 | 755 | |
9e15db7c JM |
756 | if (!imxdmac->descs_allocated) |
757 | return -ENOMEM; | |
758 | ||
759 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
760 | } |
761 | ||
762 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
763 | { | |
764 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 765 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
766 | struct imxdma_desc *desc, *_desc; |
767 | unsigned long flags; | |
768 | ||
f606ab89 | 769 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 770 | |
6bd08127 | 771 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
772 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
773 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 774 | |
f606ab89 | 775 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
776 | |
777 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
778 | kfree(desc); | |
779 | imxdmac->descs_allocated--; | |
780 | } | |
781 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
782 | |
783 | if (imxdmac->sg_list) { | |
784 | kfree(imxdmac->sg_list); | |
785 | imxdmac->sg_list = NULL; | |
786 | } | |
787 | } | |
788 | ||
789 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
790 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 791 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 792 | unsigned long flags, void *context) |
1f1846c6 SH |
793 | { |
794 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
795 | struct scatterlist *sg; | |
9e15db7c JM |
796 | int i, dma_length = 0; |
797 | struct imxdma_desc *desc; | |
1f1846c6 | 798 | |
9e15db7c JM |
799 | if (list_empty(&imxdmac->ld_free) || |
800 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
801 | return NULL; |
802 | ||
9e15db7c | 803 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
804 | |
805 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 806 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
807 | } |
808 | ||
d07102a1 SH |
809 | switch (imxdmac->word_size) { |
810 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 811 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
812 | return NULL; |
813 | break; | |
814 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 815 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
816 | return NULL; |
817 | break; | |
818 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
819 | break; | |
820 | default: | |
821 | return NULL; | |
822 | } | |
823 | ||
9e15db7c JM |
824 | desc->type = IMXDMA_DESC_SLAVE_SG; |
825 | desc->sg = sgl; | |
826 | desc->sgcount = sg_len; | |
827 | desc->len = dma_length; | |
2efc3449 | 828 | desc->direction = direction; |
9e15db7c | 829 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
830 | desc->src = imxdmac->per_address; |
831 | } else { | |
9e15db7c JM |
832 | desc->dest = imxdmac->per_address; |
833 | } | |
834 | desc->desc.callback = NULL; | |
835 | desc->desc.callback_param = NULL; | |
1f1846c6 | 836 | |
9e15db7c | 837 | return &desc->desc; |
1f1846c6 SH |
838 | } |
839 | ||
840 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
841 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 842 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 843 | unsigned long flags, void *context) |
1f1846c6 SH |
844 | { |
845 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
846 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
847 | struct imxdma_desc *desc; |
848 | int i; | |
1f1846c6 | 849 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
850 | |
851 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
852 | __func__, imxdmac->channel, buf_len, period_len); | |
853 | ||
9e15db7c JM |
854 | if (list_empty(&imxdmac->ld_free) || |
855 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 856 | return NULL; |
1f1846c6 | 857 | |
9e15db7c | 858 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
859 | |
860 | if (imxdmac->sg_list) | |
861 | kfree(imxdmac->sg_list); | |
862 | ||
863 | imxdmac->sg_list = kcalloc(periods + 1, | |
864 | sizeof(struct scatterlist), GFP_KERNEL); | |
865 | if (!imxdmac->sg_list) | |
866 | return NULL; | |
867 | ||
868 | sg_init_table(imxdmac->sg_list, periods); | |
869 | ||
870 | for (i = 0; i < periods; i++) { | |
871 | imxdmac->sg_list[i].page_link = 0; | |
872 | imxdmac->sg_list[i].offset = 0; | |
873 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 874 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
875 | dma_addr += period_len; |
876 | } | |
877 | ||
878 | /* close the loop */ | |
879 | imxdmac->sg_list[periods].offset = 0; | |
fdaf9c4b | 880 | sg_dma_len(&imxdmac->sg_list[periods]) = 0; |
1f1846c6 SH |
881 | imxdmac->sg_list[periods].page_link = |
882 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
883 | ||
9e15db7c JM |
884 | desc->type = IMXDMA_DESC_CYCLIC; |
885 | desc->sg = imxdmac->sg_list; | |
886 | desc->sgcount = periods; | |
887 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 888 | desc->direction = direction; |
9e15db7c | 889 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
890 | desc->src = imxdmac->per_address; |
891 | } else { | |
9e15db7c JM |
892 | desc->dest = imxdmac->per_address; |
893 | } | |
894 | desc->desc.callback = NULL; | |
895 | desc->desc.callback_param = NULL; | |
1f1846c6 | 896 | |
9e15db7c | 897 | return &desc->desc; |
1f1846c6 SH |
898 | } |
899 | ||
6c05f091 JM |
900 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
901 | struct dma_chan *chan, dma_addr_t dest, | |
902 | dma_addr_t src, size_t len, unsigned long flags) | |
903 | { | |
904 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
905 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 906 | struct imxdma_desc *desc; |
1f1846c6 | 907 | |
6c05f091 JM |
908 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", |
909 | __func__, imxdmac->channel, src, dest, len); | |
910 | ||
9e15db7c JM |
911 | if (list_empty(&imxdmac->ld_free) || |
912 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
913 | return NULL; |
914 | ||
9e15db7c | 915 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 916 | |
9e15db7c JM |
917 | desc->type = IMXDMA_DESC_MEMCPY; |
918 | desc->src = src; | |
919 | desc->dest = dest; | |
920 | desc->len = len; | |
2efc3449 | 921 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
922 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
923 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
924 | desc->desc.callback = NULL; | |
925 | desc->desc.callback_param = NULL; | |
6c05f091 | 926 | |
9e15db7c | 927 | return &desc->desc; |
6c05f091 JM |
928 | } |
929 | ||
f606ab89 JM |
930 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
931 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
932 | unsigned long flags) | |
933 | { | |
934 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
935 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
936 | struct imxdma_desc *desc; | |
937 | ||
938 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n" | |
939 | " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__, | |
940 | imxdmac->channel, xt->src_start, xt->dst_start, | |
941 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", | |
942 | xt->numf, xt->frame_size); | |
943 | ||
944 | if (list_empty(&imxdmac->ld_free) || | |
945 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
946 | return NULL; | |
947 | ||
948 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
949 | return NULL; | |
950 | ||
951 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
952 | ||
953 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
954 | desc->src = xt->src_start; | |
955 | desc->dest = xt->dst_start; | |
956 | desc->x = xt->sgl[0].size; | |
957 | desc->y = xt->numf; | |
958 | desc->w = xt->sgl[0].icg + desc->x; | |
959 | desc->len = desc->x * desc->y; | |
960 | desc->direction = DMA_MEM_TO_MEM; | |
961 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
962 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
963 | if (xt->src_sgl) | |
964 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
965 | if (xt->dst_sgl) | |
966 | desc->config_port |= IMX_DMA_TYPE_2D; | |
967 | desc->desc.callback = NULL; | |
968 | desc->desc.callback_param = NULL; | |
969 | ||
970 | return &desc->desc; | |
1f1846c6 SH |
971 | } |
972 | ||
973 | static void imxdma_issue_pending(struct dma_chan *chan) | |
974 | { | |
5b316876 | 975 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
976 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
977 | struct imxdma_desc *desc; | |
978 | unsigned long flags; | |
979 | ||
f606ab89 | 980 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
981 | if (list_empty(&imxdmac->ld_active) && |
982 | !list_empty(&imxdmac->ld_queue)) { | |
983 | desc = list_first_entry(&imxdmac->ld_queue, | |
984 | struct imxdma_desc, node); | |
985 | ||
986 | if (imxdma_xfer_desc(desc) < 0) { | |
987 | dev_warn(imxdma->dev, | |
988 | "%s: channel: %d couldn't issue DMA xfer\n", | |
989 | __func__, imxdmac->channel); | |
990 | } else { | |
991 | list_move_tail(imxdmac->ld_queue.next, | |
992 | &imxdmac->ld_active); | |
993 | } | |
994 | } | |
f606ab89 | 995 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
996 | } |
997 | ||
998 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 999 | { |
1f1846c6 | 1000 | struct imxdma_engine *imxdma; |
73930eb3 | 1001 | struct resource *res; |
1f1846c6 | 1002 | int ret, i; |
73930eb3 | 1003 | int irq, irq_err; |
cd5cf9da | 1004 | |
04bbd8ef | 1005 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1006 | if (!imxdma) |
1007 | return -ENOMEM; | |
1008 | ||
e51d0f0a SG |
1009 | imxdma->devtype = pdev->id_entry->driver_data; |
1010 | ||
73930eb3 SG |
1011 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1012 | imxdma->base = devm_request_and_ioremap(&pdev->dev, res); | |
1013 | if (!imxdma->base) | |
1014 | return -EADDRNOTAVAIL; | |
1015 | ||
1016 | irq = platform_get_irq(pdev, 0); | |
1017 | if (irq < 0) | |
1018 | return irq; | |
6bd08127 | 1019 | |
a2367db2 | 1020 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1021 | if (IS_ERR(imxdma->dma_ipg)) |
1022 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1023 | |
1024 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1025 | if (IS_ERR(imxdma->dma_ahb)) |
1026 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 FE |
1027 | |
1028 | clk_prepare_enable(imxdma->dma_ipg); | |
1029 | clk_prepare_enable(imxdma->dma_ahb); | |
6bd08127 JM |
1030 | |
1031 | /* reset DMA module */ | |
cd5cf9da | 1032 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1033 | |
e51d0f0a | 1034 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1035 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1036 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1037 | if (ret) { |
f9b283a6 | 1038 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
04bbd8ef | 1039 | goto err; |
6bd08127 JM |
1040 | } |
1041 | ||
73930eb3 SG |
1042 | irq_err = platform_get_irq(pdev, 1); |
1043 | if (irq_err < 0) { | |
1044 | ret = irq_err; | |
1045 | goto err; | |
1046 | } | |
1047 | ||
1048 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1049 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1050 | if (ret) { |
f9b283a6 | 1051 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
04bbd8ef | 1052 | goto err; |
6bd08127 JM |
1053 | } |
1054 | } | |
1055 | ||
1056 | /* enable DMA module */ | |
cd5cf9da | 1057 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1058 | |
1059 | /* clear all interrupts */ | |
cd5cf9da | 1060 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1061 | |
1062 | /* disable interrupts */ | |
cd5cf9da | 1063 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1064 | |
1065 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1066 | ||
f8a356ff SH |
1067 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1068 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1069 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1070 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1071 | ||
1072 | /* Initialize 2D global parameters */ | |
1073 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1074 | imxdma->slots_2d[i].count = 0; | |
1075 | ||
1076 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1077 | |
1f1846c6 | 1078 | /* Initialize channel parameters */ |
6bd08127 | 1079 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1080 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1081 | ||
e51d0f0a | 1082 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1083 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1084 | dma_irq_handler, 0, "DMA", imxdma); |
1085 | if (ret) { | |
f9b283a6 JM |
1086 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1087 | "for DMA channel %d\n", | |
73930eb3 | 1088 | irq + i, i); |
04bbd8ef | 1089 | goto err; |
6bd08127 | 1090 | } |
2d9c2fc5 JM |
1091 | init_timer(&imxdmac->watchdog); |
1092 | imxdmac->watchdog.function = &imxdma_watchdog; | |
1093 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 1094 | } |
1f1846c6 | 1095 | |
1f1846c6 | 1096 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1097 | |
9e15db7c JM |
1098 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1099 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1100 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1101 | ||
1102 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1103 | (unsigned long)imxdmac); | |
1f1846c6 | 1104 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1105 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1106 | imxdmac->channel = i; |
1107 | ||
1108 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1109 | list_add_tail(&imxdmac->chan.device_node, |
1110 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1111 | } |
1112 | ||
1113 | imxdma->dev = &pdev->dev; | |
1114 | imxdma->dma_device.dev = &pdev->dev; | |
1115 | ||
1116 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1117 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1118 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1119 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1120 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1121 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1122 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
1f1846c6 SH |
1123 | imxdma->dma_device.device_control = imxdma_control; |
1124 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
1125 | ||
1126 | platform_set_drvdata(pdev, imxdma); | |
1127 | ||
6c05f091 | 1128 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
1129 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1130 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1131 | ||
1f1846c6 SH |
1132 | ret = dma_async_device_register(&imxdma->dma_device); |
1133 | if (ret) { | |
1134 | dev_err(&pdev->dev, "unable to register\n"); | |
04bbd8ef | 1135 | goto err; |
1f1846c6 SH |
1136 | } |
1137 | ||
1138 | return 0; | |
1139 | ||
04bbd8ef | 1140 | err: |
a2367db2 FE |
1141 | clk_disable_unprepare(imxdma->dma_ipg); |
1142 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1143 | return ret; |
1144 | } | |
1145 | ||
1146 | static int __exit imxdma_remove(struct platform_device *pdev) | |
1147 | { | |
1148 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 SH |
1149 | |
1150 | dma_async_device_unregister(&imxdma->dma_device); | |
1151 | ||
a2367db2 FE |
1152 | clk_disable_unprepare(imxdma->dma_ipg); |
1153 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1154 | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static struct platform_driver imxdma_driver = { | |
1159 | .driver = { | |
1160 | .name = "imx-dma", | |
1161 | }, | |
e51d0f0a | 1162 | .id_table = imx_dma_devtype, |
1f1846c6 SH |
1163 | .remove = __exit_p(imxdma_remove), |
1164 | }; | |
1165 | ||
1166 | static int __init imxdma_module_init(void) | |
1167 | { | |
1168 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1169 | } | |
1170 | subsys_initcall(imxdma_module_init); | |
1171 | ||
1172 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1173 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1174 | MODULE_LICENSE("GPL"); |