Commit | Line | Data |
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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
7331205a | 17 | #include <linux/err.h> |
1f1846c6 SH |
18 | #include <linux/init.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5c45ad77 | 29 | #include <linux/module.h> |
290ad0f9 MP |
30 | #include <linux/of_device.h> |
31 | #include <linux/of_dma.h> | |
1f1846c6 SH |
32 | |
33 | #include <asm/irq.h> | |
82906b13 | 34 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 35 | |
d2ebfb33 | 36 | #include "dmaengine.h" |
9e15db7c | 37 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
38 | #define IMX_DMA_CHANNELS 16 |
39 | ||
f606ab89 JM |
40 | #define IMX_DMA_2D_SLOTS 2 |
41 | #define IMX_DMA_2D_SLOT_A 0 | |
42 | #define IMX_DMA_2D_SLOT_B 1 | |
43 | ||
6bd08127 JM |
44 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
45 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
46 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
47 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
48 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
49 | #define IMX_DMA_TYPE_2D (1 << 10) | |
50 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
51 | ||
52 | #define IMX_DMA_ERR_BURST (1 << 0) | |
53 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
54 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
55 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
56 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
57 | ||
58 | #define DMA_DCR 0x00 /* Control Register */ | |
59 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
60 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
61 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
62 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
63 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
64 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
65 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
66 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
67 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
68 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
69 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
70 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
71 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
72 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
73 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
74 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
75 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
76 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
77 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
78 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
79 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
80 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
81 | ||
82 | #define DCR_DRST (1<<1) | |
83 | #define DCR_DEN (1<<0) | |
84 | #define DBTOCR_EN (1<<15) | |
85 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
86 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
87 | #define CCR_ACRPT (1<<14) | |
88 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
89 | #define CCR_DMOD_2D (0x1 << 12) | |
90 | #define CCR_DMOD_FIFO (0x2 << 12) | |
91 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
92 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
93 | #define CCR_SMOD_2D (0x1 << 10) | |
94 | #define CCR_SMOD_FIFO (0x2 << 10) | |
95 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
96 | #define CCR_MDIR_DEC (1<<9) | |
97 | #define CCR_MSEL_B (1<<8) | |
98 | #define CCR_DSIZ_32 (0x0 << 6) | |
99 | #define CCR_DSIZ_8 (0x1 << 6) | |
100 | #define CCR_DSIZ_16 (0x2 << 6) | |
101 | #define CCR_SSIZ_32 (0x0 << 4) | |
102 | #define CCR_SSIZ_8 (0x1 << 4) | |
103 | #define CCR_SSIZ_16 (0x2 << 4) | |
104 | #define CCR_REN (1<<3) | |
105 | #define CCR_RPT (1<<2) | |
106 | #define CCR_FRC (1<<1) | |
107 | #define CCR_CEN (1<<0) | |
108 | #define RTOR_EN (1<<15) | |
109 | #define RTOR_CLK (1<<14) | |
110 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
111 | |
112 | enum imxdma_prep_type { | |
113 | IMXDMA_DESC_MEMCPY, | |
114 | IMXDMA_DESC_INTERLEAVED, | |
115 | IMXDMA_DESC_SLAVE_SG, | |
116 | IMXDMA_DESC_CYCLIC, | |
117 | }; | |
118 | ||
f606ab89 JM |
119 | struct imx_dma_2d_config { |
120 | u16 xsr; | |
121 | u16 ysr; | |
122 | u16 wsr; | |
123 | int count; | |
124 | }; | |
125 | ||
9e15db7c JM |
126 | struct imxdma_desc { |
127 | struct list_head node; | |
128 | struct dma_async_tx_descriptor desc; | |
129 | enum dma_status status; | |
130 | dma_addr_t src; | |
131 | dma_addr_t dest; | |
132 | size_t len; | |
2efc3449 | 133 | enum dma_transfer_direction direction; |
9e15db7c JM |
134 | enum imxdma_prep_type type; |
135 | /* For memcpy and interleaved */ | |
136 | unsigned int config_port; | |
137 | unsigned int config_mem; | |
138 | /* For interleaved transfers */ | |
139 | unsigned int x; | |
140 | unsigned int y; | |
141 | unsigned int w; | |
142 | /* For slave sg and cyclic */ | |
143 | struct scatterlist *sg; | |
144 | unsigned int sgcount; | |
145 | }; | |
146 | ||
1f1846c6 | 147 | struct imxdma_channel { |
2d9c2fc5 JM |
148 | int hw_chaining; |
149 | struct timer_list watchdog; | |
1f1846c6 SH |
150 | struct imxdma_engine *imxdma; |
151 | unsigned int channel; | |
1f1846c6 | 152 | |
9e15db7c JM |
153 | struct tasklet_struct dma_tasklet; |
154 | struct list_head ld_free; | |
155 | struct list_head ld_queue; | |
156 | struct list_head ld_active; | |
157 | int descs_allocated; | |
1f1846c6 SH |
158 | enum dma_slave_buswidth word_size; |
159 | dma_addr_t per_address; | |
160 | u32 watermark_level; | |
161 | struct dma_chan chan; | |
1f1846c6 | 162 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
163 | enum dma_status status; |
164 | int dma_request; | |
165 | struct scatterlist *sg_list; | |
359291a1 JM |
166 | u32 ccr_from_device; |
167 | u32 ccr_to_device; | |
f606ab89 JM |
168 | bool enabled_2d; |
169 | int slot_2d; | |
1f1846c6 SH |
170 | }; |
171 | ||
e51d0f0a SG |
172 | enum imx_dma_type { |
173 | IMX1_DMA, | |
174 | IMX21_DMA, | |
175 | IMX27_DMA, | |
176 | }; | |
177 | ||
1f1846c6 SH |
178 | struct imxdma_engine { |
179 | struct device *dev; | |
1e070a60 | 180 | struct device_dma_parameters dma_parms; |
1f1846c6 | 181 | struct dma_device dma_device; |
cd5cf9da | 182 | void __iomem *base; |
a2367db2 FE |
183 | struct clk *dma_ahb; |
184 | struct clk *dma_ipg; | |
f606ab89 JM |
185 | spinlock_t lock; |
186 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 187 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 188 | enum imx_dma_type devtype; |
1f1846c6 SH |
189 | }; |
190 | ||
290ad0f9 MP |
191 | struct imxdma_filter_data { |
192 | struct imxdma_engine *imxdma; | |
193 | int request; | |
194 | }; | |
195 | ||
e51d0f0a SG |
196 | static struct platform_device_id imx_dma_devtype[] = { |
197 | { | |
198 | .name = "imx1-dma", | |
199 | .driver_data = IMX1_DMA, | |
200 | }, { | |
201 | .name = "imx21-dma", | |
202 | .driver_data = IMX21_DMA, | |
203 | }, { | |
204 | .name = "imx27-dma", | |
205 | .driver_data = IMX27_DMA, | |
206 | }, { | |
207 | /* sentinel */ | |
208 | } | |
209 | }; | |
210 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
211 | ||
290ad0f9 MP |
212 | static const struct of_device_id imx_dma_of_dev_id[] = { |
213 | { | |
214 | .compatible = "fsl,imx1-dma", | |
215 | .data = &imx_dma_devtype[IMX1_DMA], | |
216 | }, { | |
217 | .compatible = "fsl,imx21-dma", | |
218 | .data = &imx_dma_devtype[IMX21_DMA], | |
219 | }, { | |
220 | .compatible = "fsl,imx27-dma", | |
221 | .data = &imx_dma_devtype[IMX27_DMA], | |
222 | }, { | |
223 | /* sentinel */ | |
224 | } | |
225 | }; | |
226 | MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); | |
227 | ||
e51d0f0a SG |
228 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) |
229 | { | |
230 | return imxdma->devtype == IMX1_DMA; | |
231 | } | |
232 | ||
233 | static inline int is_imx21_dma(struct imxdma_engine *imxdma) | |
234 | { | |
235 | return imxdma->devtype == IMX21_DMA; | |
236 | } | |
237 | ||
238 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) | |
239 | { | |
240 | return imxdma->devtype == IMX27_DMA; | |
241 | } | |
242 | ||
1f1846c6 SH |
243 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
244 | { | |
245 | return container_of(chan, struct imxdma_channel, chan); | |
246 | } | |
247 | ||
9e15db7c | 248 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 249 | { |
9e15db7c JM |
250 | struct imxdma_desc *desc; |
251 | ||
252 | if (!list_empty(&imxdmac->ld_active)) { | |
253 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
254 | node); | |
255 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
256 | return true; | |
257 | } | |
258 | return false; | |
1f1846c6 SH |
259 | } |
260 | ||
6bd08127 | 261 | |
cd5cf9da JM |
262 | |
263 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
264 | unsigned offset) | |
6bd08127 | 265 | { |
cd5cf9da | 266 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
267 | } |
268 | ||
cd5cf9da | 269 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 270 | { |
cd5cf9da | 271 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 272 | } |
1f1846c6 | 273 | |
2d9c2fc5 | 274 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 275 | { |
e51d0f0a SG |
276 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
277 | ||
278 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 279 | return imxdmac->hw_chaining; |
6bd08127 JM |
280 | else |
281 | return 0; | |
282 | } | |
283 | ||
284 | /* | |
285 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
286 | */ | |
a6cbb2d8 | 287 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 288 | { |
2efc3449 | 289 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 290 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 291 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
292 | unsigned long now; |
293 | ||
fdaf9c4b | 294 | now = min(d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
295 | if (d->len != IMX_DMA_LENGTH_LOOP) |
296 | d->len -= now; | |
6bd08127 | 297 | |
2efc3449 | 298 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
299 | imx_dmav1_writel(imxdma, sg->dma_address, |
300 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 301 | else |
cd5cf9da JM |
302 | imx_dmav1_writel(imxdma, sg->dma_address, |
303 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 304 | |
cd5cf9da | 305 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 306 | |
f9b283a6 JM |
307 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
308 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
309 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
310 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
311 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
312 | |
313 | return now; | |
1f1846c6 SH |
314 | } |
315 | ||
2efc3449 | 316 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 317 | { |
2efc3449 | 318 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 319 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
320 | int channel = imxdmac->channel; |
321 | unsigned long flags; | |
322 | ||
f9b283a6 | 323 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 324 | |
6bd08127 JM |
325 | local_irq_save(flags); |
326 | ||
cd5cf9da JM |
327 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
328 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
329 | ~(1 << channel), DMA_DIMR); | |
330 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
331 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 332 | |
e51d0f0a | 333 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 334 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
335 | d->sg = sg_next(d->sg); |
336 | if (d->sg) { | |
6bd08127 | 337 | u32 tmp; |
a6cbb2d8 | 338 | imxdma_sg_next(d); |
cd5cf9da JM |
339 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
340 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
341 | DMA_CCR(channel)); | |
6bd08127 JM |
342 | } |
343 | } | |
6bd08127 JM |
344 | |
345 | local_irq_restore(flags); | |
346 | } | |
347 | ||
348 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
349 | { | |
cd5cf9da | 350 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
351 | int channel = imxdmac->channel; |
352 | unsigned long flags; | |
353 | ||
f9b283a6 | 354 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 355 | |
2d9c2fc5 JM |
356 | if (imxdma_hw_chain(imxdmac)) |
357 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
358 | |
359 | local_irq_save(flags); | |
cd5cf9da JM |
360 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
361 | (1 << channel), DMA_DIMR); | |
362 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
363 | ~CCR_CEN, DMA_CCR(channel)); | |
364 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
365 | local_irq_restore(flags); |
366 | } | |
367 | ||
6bd08127 | 368 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 369 | { |
6bd08127 | 370 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
cd5cf9da | 371 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 372 | int channel = imxdmac->channel; |
1f1846c6 | 373 | |
cd5cf9da | 374 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 375 | |
6bd08127 | 376 | /* Tasklet watchdog error handler */ |
9e15db7c | 377 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
378 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
379 | imxdmac->channel); | |
1f1846c6 SH |
380 | } |
381 | ||
6bd08127 | 382 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 383 | { |
6bd08127 | 384 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
385 | unsigned int err_mask; |
386 | int i, disr; | |
387 | int errcode; | |
388 | ||
cd5cf9da | 389 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 390 | |
cd5cf9da JM |
391 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
392 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
393 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
394 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
395 | |
396 | if (!err_mask) | |
397 | return IRQ_HANDLED; | |
398 | ||
cd5cf9da | 399 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
400 | |
401 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
402 | if (!(err_mask & (1 << i))) | |
403 | continue; | |
6bd08127 JM |
404 | errcode = 0; |
405 | ||
cd5cf9da JM |
406 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
407 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
408 | errcode |= IMX_DMA_ERR_BURST; |
409 | } | |
cd5cf9da JM |
410 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
411 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
412 | errcode |= IMX_DMA_ERR_REQUEST; |
413 | } | |
cd5cf9da JM |
414 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
415 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
416 | errcode |= IMX_DMA_ERR_TRANSFER; |
417 | } | |
cd5cf9da JM |
418 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
419 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
420 | errcode |= IMX_DMA_ERR_BUFFER; |
421 | } | |
422 | /* Tasklet error handler */ | |
423 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
424 | ||
425 | printk(KERN_WARNING | |
426 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
427 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
428 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
429 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
430 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
431 | } | |
432 | return IRQ_HANDLED; | |
1f1846c6 SH |
433 | } |
434 | ||
6bd08127 | 435 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 436 | { |
cd5cf9da | 437 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 438 | int chno = imxdmac->channel; |
2efc3449 | 439 | struct imxdma_desc *desc; |
6bd08127 | 440 | |
f606ab89 | 441 | spin_lock(&imxdma->lock); |
833bc03b | 442 | if (list_empty(&imxdmac->ld_active)) { |
f606ab89 | 443 | spin_unlock(&imxdma->lock); |
833bc03b JM |
444 | goto out; |
445 | } | |
2efc3449 | 446 | |
833bc03b JM |
447 | desc = list_first_entry(&imxdmac->ld_active, |
448 | struct imxdma_desc, | |
449 | node); | |
f606ab89 | 450 | spin_unlock(&imxdma->lock); |
2efc3449 | 451 | |
833bc03b JM |
452 | if (desc->sg) { |
453 | u32 tmp; | |
454 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 455 | |
833bc03b | 456 | if (desc->sg) { |
a6cbb2d8 | 457 | imxdma_sg_next(desc); |
6bd08127 | 458 | |
cd5cf9da | 459 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 460 | |
2d9c2fc5 | 461 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
462 | /* FIXME: The timeout should probably be |
463 | * configurable | |
464 | */ | |
2d9c2fc5 | 465 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
466 | jiffies + msecs_to_jiffies(500)); |
467 | ||
468 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 469 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 470 | } else { |
cd5cf9da JM |
471 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
472 | DMA_CCR(chno)); | |
6bd08127 JM |
473 | tmp |= CCR_CEN; |
474 | } | |
475 | ||
cd5cf9da | 476 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
477 | |
478 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
479 | /* Tasklet progression */ | |
480 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 481 | |
6bd08127 JM |
482 | return; |
483 | } | |
484 | ||
2d9c2fc5 JM |
485 | if (imxdma_hw_chain(imxdmac)) { |
486 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
487 | return; |
488 | } | |
489 | } | |
490 | ||
2efc3449 | 491 | out: |
cd5cf9da | 492 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 493 | /* Tasklet irq */ |
9e15db7c JM |
494 | tasklet_schedule(&imxdmac->dma_tasklet); |
495 | } | |
496 | ||
6bd08127 JM |
497 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
498 | { | |
499 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
500 | int i, disr; |
501 | ||
e51d0f0a | 502 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
503 | imxdma_err_handler(irq, dev_id); |
504 | ||
cd5cf9da | 505 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 506 | |
f9b283a6 | 507 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 508 | |
cd5cf9da | 509 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 510 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 511 | if (disr & (1 << i)) |
6bd08127 | 512 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
513 | } |
514 | ||
515 | return IRQ_HANDLED; | |
516 | } | |
517 | ||
9e15db7c JM |
518 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
519 | { | |
520 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 521 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
522 | unsigned long flags; |
523 | int slot = -1; | |
524 | int i; | |
9e15db7c JM |
525 | |
526 | /* Configure and enable */ | |
527 | switch (d->type) { | |
f606ab89 JM |
528 | case IMXDMA_DESC_INTERLEAVED: |
529 | /* Try to get a free 2D slot */ | |
530 | spin_lock_irqsave(&imxdma->lock, flags); | |
531 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { | |
532 | if ((imxdma->slots_2d[i].count > 0) && | |
533 | ((imxdma->slots_2d[i].xsr != d->x) || | |
534 | (imxdma->slots_2d[i].ysr != d->y) || | |
535 | (imxdma->slots_2d[i].wsr != d->w))) | |
536 | continue; | |
537 | slot = i; | |
538 | break; | |
539 | } | |
720dfd25 WY |
540 | if (slot < 0) { |
541 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
f606ab89 | 542 | return -EBUSY; |
720dfd25 | 543 | } |
f606ab89 JM |
544 | |
545 | imxdma->slots_2d[slot].xsr = d->x; | |
546 | imxdma->slots_2d[slot].ysr = d->y; | |
547 | imxdma->slots_2d[slot].wsr = d->w; | |
548 | imxdma->slots_2d[slot].count++; | |
549 | ||
550 | imxdmac->slot_2d = slot; | |
551 | imxdmac->enabled_2d = true; | |
552 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
553 | ||
554 | if (slot == IMX_DMA_2D_SLOT_A) { | |
555 | d->config_mem &= ~CCR_MSEL_B; | |
556 | d->config_port &= ~CCR_MSEL_B; | |
557 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
558 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
559 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
560 | } else { | |
561 | d->config_mem |= CCR_MSEL_B; | |
562 | d->config_port |= CCR_MSEL_B; | |
563 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
564 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
565 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
566 | } | |
567 | /* | |
568 | * We fall-through here intentionally, since a 2D transfer is | |
569 | * similar to MEMCPY just adding the 2D slot configuration. | |
570 | */ | |
9e15db7c | 571 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
572 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
573 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
574 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 575 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 576 | |
cd5cf9da | 577 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc JM |
578 | |
579 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
580 | "dma_length=%d\n", __func__, imxdmac->channel, | |
581 | d->dest, d->src, d->len); | |
582 | ||
583 | break; | |
6bd08127 | 584 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 585 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 586 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 587 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 588 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 589 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 590 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
591 | DMA_CCR(imxdmac->channel)); |
592 | ||
593 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
594 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
595 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
596 | d->len, imxdmac->per_address); | |
597 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
cd5cf9da | 598 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 599 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 600 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
601 | DMA_CCR(imxdmac->channel)); |
602 | ||
603 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
604 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
605 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
606 | d->len, imxdmac->per_address); | |
607 | } else { | |
608 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
609 | __func__, imxdmac->channel); | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
a6cbb2d8 | 613 | imxdma_sg_next(d); |
1f1846c6 | 614 | |
9e15db7c JM |
615 | break; |
616 | default: | |
617 | return -EINVAL; | |
618 | } | |
2efc3449 | 619 | imxdma_enable_hw(d); |
9e15db7c | 620 | return 0; |
1f1846c6 SH |
621 | } |
622 | ||
9e15db7c | 623 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 624 | { |
9e15db7c JM |
625 | struct imxdma_channel *imxdmac = (void *)data; |
626 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
627 | struct imxdma_desc *desc; | |
1f1846c6 | 628 | |
f606ab89 | 629 | spin_lock(&imxdma->lock); |
9e15db7c JM |
630 | |
631 | if (list_empty(&imxdmac->ld_active)) { | |
632 | /* Someone might have called terminate all */ | |
633 | goto out; | |
634 | } | |
635 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
636 | ||
637 | if (desc->desc.callback) | |
638 | desc->desc.callback(desc->desc.callback_param); | |
639 | ||
d73111c6 MI |
640 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
641 | * and dont mark the descriptor as complete. | |
60f2951e VK |
642 | * Only in non-cyclic cases it would be marked as complete |
643 | */ | |
9e15db7c JM |
644 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
645 | goto out; | |
60f2951e VK |
646 | else |
647 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 648 | |
f606ab89 JM |
649 | /* Free 2D slot if it was an interleaved transfer */ |
650 | if (imxdmac->enabled_2d) { | |
651 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
652 | imxdmac->enabled_2d = false; | |
653 | } | |
654 | ||
9e15db7c JM |
655 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
656 | ||
657 | if (!list_empty(&imxdmac->ld_queue)) { | |
658 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
659 | node); | |
660 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
661 | if (imxdma_xfer_desc(desc) < 0) | |
662 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
663 | __func__, imxdmac->channel); | |
664 | } | |
665 | out: | |
f606ab89 | 666 | spin_unlock(&imxdma->lock); |
1f1846c6 SH |
667 | } |
668 | ||
669 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
670 | unsigned long arg) | |
671 | { | |
672 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
673 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
cd5cf9da | 674 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 675 | unsigned long flags; |
1f1846c6 SH |
676 | unsigned int mode = 0; |
677 | ||
678 | switch (cmd) { | |
679 | case DMA_TERMINATE_ALL: | |
6bd08127 | 680 | imxdma_disable_hw(imxdmac); |
9e15db7c | 681 | |
f606ab89 | 682 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
683 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
684 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
f606ab89 | 685 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
686 | return 0; |
687 | case DMA_SLAVE_CONFIG: | |
db8196df | 688 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
689 | imxdmac->per_address = dmaengine_cfg->src_addr; |
690 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
691 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
692 | } else { | |
693 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
694 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
695 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
696 | } | |
697 | ||
698 | switch (imxdmac->word_size) { | |
699 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
700 | mode = IMX_DMA_MEMSIZE_8; | |
701 | break; | |
702 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
703 | mode = IMX_DMA_MEMSIZE_16; | |
704 | break; | |
705 | default: | |
706 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
707 | mode = IMX_DMA_MEMSIZE_32; | |
708 | break; | |
709 | } | |
1f1846c6 | 710 | |
bef2a8d3 JM |
711 | imxdmac->hw_chaining = 0; |
712 | ||
359291a1 | 713 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
714 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
715 | CCR_REN; | |
359291a1 | 716 | imxdmac->ccr_to_device = |
bdc0c753 JM |
717 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
718 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
cd5cf9da | 719 | imx_dmav1_writel(imxdma, imxdmac->dma_request, |
bdc0c753 JM |
720 | DMA_RSSR(imxdmac->channel)); |
721 | ||
6bd08127 | 722 | /* Set burst length */ |
cd5cf9da JM |
723 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * |
724 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
725 | |
726 | return 0; | |
727 | default: | |
728 | return -ENOSYS; | |
729 | } | |
730 | ||
731 | return -EINVAL; | |
732 | } | |
733 | ||
734 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
735 | dma_cookie_t cookie, | |
736 | struct dma_tx_state *txstate) | |
737 | { | |
96a2af41 | 738 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
739 | } |
740 | ||
741 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
742 | { | |
743 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 744 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 745 | dma_cookie_t cookie; |
9e15db7c | 746 | unsigned long flags; |
1f1846c6 | 747 | |
f606ab89 | 748 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 749 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 750 | cookie = dma_cookie_assign(tx); |
f606ab89 | 751 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
752 | |
753 | return cookie; | |
754 | } | |
755 | ||
756 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
757 | { | |
758 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
759 | struct imx_dma_data *data = chan->private; | |
760 | ||
6c05f091 JM |
761 | if (data != NULL) |
762 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 763 | |
9e15db7c JM |
764 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
765 | struct imxdma_desc *desc; | |
1f1846c6 | 766 | |
9e15db7c JM |
767 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
768 | if (!desc) | |
769 | break; | |
770 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
771 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
772 | desc->desc.tx_submit = imxdma_tx_submit; | |
773 | /* txd.flags will be overwritten in prep funcs */ | |
774 | desc->desc.flags = DMA_CTRL_ACK; | |
775 | desc->status = DMA_SUCCESS; | |
776 | ||
777 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
778 | imxdmac->descs_allocated++; | |
779 | } | |
1f1846c6 | 780 | |
9e15db7c JM |
781 | if (!imxdmac->descs_allocated) |
782 | return -ENOMEM; | |
783 | ||
784 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
785 | } |
786 | ||
787 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
788 | { | |
789 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 790 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
791 | struct imxdma_desc *desc, *_desc; |
792 | unsigned long flags; | |
793 | ||
f606ab89 | 794 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 795 | |
6bd08127 | 796 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
797 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
798 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 799 | |
f606ab89 | 800 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
801 | |
802 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
803 | kfree(desc); | |
804 | imxdmac->descs_allocated--; | |
805 | } | |
806 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 | 807 | |
06f8db4b SK |
808 | kfree(imxdmac->sg_list); |
809 | imxdmac->sg_list = NULL; | |
1f1846c6 SH |
810 | } |
811 | ||
812 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
813 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 814 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 815 | unsigned long flags, void *context) |
1f1846c6 SH |
816 | { |
817 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
818 | struct scatterlist *sg; | |
9e15db7c JM |
819 | int i, dma_length = 0; |
820 | struct imxdma_desc *desc; | |
1f1846c6 | 821 | |
9e15db7c JM |
822 | if (list_empty(&imxdmac->ld_free) || |
823 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
824 | return NULL; |
825 | ||
9e15db7c | 826 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
827 | |
828 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 829 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
830 | } |
831 | ||
d07102a1 SH |
832 | switch (imxdmac->word_size) { |
833 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 834 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
835 | return NULL; |
836 | break; | |
837 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 838 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
839 | return NULL; |
840 | break; | |
841 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
842 | break; | |
843 | default: | |
844 | return NULL; | |
845 | } | |
846 | ||
9e15db7c JM |
847 | desc->type = IMXDMA_DESC_SLAVE_SG; |
848 | desc->sg = sgl; | |
849 | desc->sgcount = sg_len; | |
850 | desc->len = dma_length; | |
2efc3449 | 851 | desc->direction = direction; |
9e15db7c | 852 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
853 | desc->src = imxdmac->per_address; |
854 | } else { | |
9e15db7c JM |
855 | desc->dest = imxdmac->per_address; |
856 | } | |
857 | desc->desc.callback = NULL; | |
858 | desc->desc.callback_param = NULL; | |
1f1846c6 | 859 | |
9e15db7c | 860 | return &desc->desc; |
1f1846c6 SH |
861 | } |
862 | ||
863 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
864 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 865 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 866 | unsigned long flags, void *context) |
1f1846c6 SH |
867 | { |
868 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
869 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
870 | struct imxdma_desc *desc; |
871 | int i; | |
1f1846c6 | 872 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
873 | |
874 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
875 | __func__, imxdmac->channel, buf_len, period_len); | |
876 | ||
9e15db7c JM |
877 | if (list_empty(&imxdmac->ld_free) || |
878 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 879 | return NULL; |
1f1846c6 | 880 | |
9e15db7c | 881 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 | 882 | |
96a3713e | 883 | kfree(imxdmac->sg_list); |
1f1846c6 SH |
884 | |
885 | imxdmac->sg_list = kcalloc(periods + 1, | |
edc530fe | 886 | sizeof(struct scatterlist), GFP_ATOMIC); |
1f1846c6 SH |
887 | if (!imxdmac->sg_list) |
888 | return NULL; | |
889 | ||
890 | sg_init_table(imxdmac->sg_list, periods); | |
891 | ||
892 | for (i = 0; i < periods; i++) { | |
893 | imxdmac->sg_list[i].page_link = 0; | |
894 | imxdmac->sg_list[i].offset = 0; | |
895 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 896 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
897 | dma_addr += period_len; |
898 | } | |
899 | ||
900 | /* close the loop */ | |
901 | imxdmac->sg_list[periods].offset = 0; | |
fdaf9c4b | 902 | sg_dma_len(&imxdmac->sg_list[periods]) = 0; |
1f1846c6 SH |
903 | imxdmac->sg_list[periods].page_link = |
904 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
905 | ||
9e15db7c JM |
906 | desc->type = IMXDMA_DESC_CYCLIC; |
907 | desc->sg = imxdmac->sg_list; | |
908 | desc->sgcount = periods; | |
909 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 910 | desc->direction = direction; |
9e15db7c | 911 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
912 | desc->src = imxdmac->per_address; |
913 | } else { | |
9e15db7c JM |
914 | desc->dest = imxdmac->per_address; |
915 | } | |
916 | desc->desc.callback = NULL; | |
917 | desc->desc.callback_param = NULL; | |
1f1846c6 | 918 | |
9e15db7c | 919 | return &desc->desc; |
1f1846c6 SH |
920 | } |
921 | ||
6c05f091 JM |
922 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
923 | struct dma_chan *chan, dma_addr_t dest, | |
924 | dma_addr_t src, size_t len, unsigned long flags) | |
925 | { | |
926 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
927 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 928 | struct imxdma_desc *desc; |
1f1846c6 | 929 | |
6c05f091 JM |
930 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", |
931 | __func__, imxdmac->channel, src, dest, len); | |
932 | ||
9e15db7c JM |
933 | if (list_empty(&imxdmac->ld_free) || |
934 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
935 | return NULL; |
936 | ||
9e15db7c | 937 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 938 | |
9e15db7c JM |
939 | desc->type = IMXDMA_DESC_MEMCPY; |
940 | desc->src = src; | |
941 | desc->dest = dest; | |
942 | desc->len = len; | |
2efc3449 | 943 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
944 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
945 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
946 | desc->desc.callback = NULL; | |
947 | desc->desc.callback_param = NULL; | |
6c05f091 | 948 | |
9e15db7c | 949 | return &desc->desc; |
6c05f091 JM |
950 | } |
951 | ||
f606ab89 JM |
952 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
953 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
954 | unsigned long flags) | |
955 | { | |
956 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
957 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
958 | struct imxdma_desc *desc; | |
959 | ||
960 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n" | |
961 | " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__, | |
962 | imxdmac->channel, xt->src_start, xt->dst_start, | |
963 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", | |
964 | xt->numf, xt->frame_size); | |
965 | ||
966 | if (list_empty(&imxdmac->ld_free) || | |
967 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
968 | return NULL; | |
969 | ||
970 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
971 | return NULL; | |
972 | ||
973 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
974 | ||
975 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
976 | desc->src = xt->src_start; | |
977 | desc->dest = xt->dst_start; | |
978 | desc->x = xt->sgl[0].size; | |
979 | desc->y = xt->numf; | |
980 | desc->w = xt->sgl[0].icg + desc->x; | |
981 | desc->len = desc->x * desc->y; | |
982 | desc->direction = DMA_MEM_TO_MEM; | |
983 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
984 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
985 | if (xt->src_sgl) | |
986 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
987 | if (xt->dst_sgl) | |
988 | desc->config_port |= IMX_DMA_TYPE_2D; | |
989 | desc->desc.callback = NULL; | |
990 | desc->desc.callback_param = NULL; | |
991 | ||
992 | return &desc->desc; | |
1f1846c6 SH |
993 | } |
994 | ||
995 | static void imxdma_issue_pending(struct dma_chan *chan) | |
996 | { | |
5b316876 | 997 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
998 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
999 | struct imxdma_desc *desc; | |
1000 | unsigned long flags; | |
1001 | ||
f606ab89 | 1002 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
1003 | if (list_empty(&imxdmac->ld_active) && |
1004 | !list_empty(&imxdmac->ld_queue)) { | |
1005 | desc = list_first_entry(&imxdmac->ld_queue, | |
1006 | struct imxdma_desc, node); | |
1007 | ||
1008 | if (imxdma_xfer_desc(desc) < 0) { | |
1009 | dev_warn(imxdma->dev, | |
1010 | "%s: channel: %d couldn't issue DMA xfer\n", | |
1011 | __func__, imxdmac->channel); | |
1012 | } else { | |
1013 | list_move_tail(imxdmac->ld_queue.next, | |
1014 | &imxdmac->ld_active); | |
1015 | } | |
1016 | } | |
f606ab89 | 1017 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
1018 | } |
1019 | ||
290ad0f9 MP |
1020 | static bool imxdma_filter_fn(struct dma_chan *chan, void *param) |
1021 | { | |
1022 | struct imxdma_filter_data *fdata = param; | |
1023 | struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); | |
1024 | ||
1025 | if (chan->device->dev != fdata->imxdma->dev) | |
1026 | return false; | |
1027 | ||
1028 | imxdma_chan->dma_request = fdata->request; | |
1029 | chan->private = NULL; | |
1030 | ||
1031 | return true; | |
1032 | } | |
1033 | ||
1034 | static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, | |
1035 | struct of_dma *ofdma) | |
1036 | { | |
1037 | int count = dma_spec->args_count; | |
1038 | struct imxdma_engine *imxdma = ofdma->of_dma_data; | |
1039 | struct imxdma_filter_data fdata = { | |
1040 | .imxdma = imxdma, | |
1041 | }; | |
1042 | ||
1043 | if (count != 1) | |
1044 | return NULL; | |
1045 | ||
1046 | fdata.request = dma_spec->args[0]; | |
1047 | ||
1048 | return dma_request_channel(imxdma->dma_device.cap_mask, | |
1049 | imxdma_filter_fn, &fdata); | |
1050 | } | |
1051 | ||
1f1846c6 | 1052 | static int __init imxdma_probe(struct platform_device *pdev) |
6bd08127 | 1053 | { |
1f1846c6 | 1054 | struct imxdma_engine *imxdma; |
73930eb3 | 1055 | struct resource *res; |
290ad0f9 | 1056 | const struct of_device_id *of_id; |
1f1846c6 | 1057 | int ret, i; |
73930eb3 | 1058 | int irq, irq_err; |
cd5cf9da | 1059 | |
290ad0f9 MP |
1060 | of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); |
1061 | if (of_id) | |
1062 | pdev->id_entry = of_id->data; | |
1063 | ||
04bbd8ef | 1064 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1065 | if (!imxdma) |
1066 | return -ENOMEM; | |
1067 | ||
5c6b3e77 | 1068 | imxdma->dev = &pdev->dev; |
e51d0f0a SG |
1069 | imxdma->devtype = pdev->id_entry->driver_data; |
1070 | ||
73930eb3 | 1071 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1072 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1073 | if (IS_ERR(imxdma->base)) | |
1074 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1075 | |
1076 | irq = platform_get_irq(pdev, 0); | |
1077 | if (irq < 0) | |
1078 | return irq; | |
6bd08127 | 1079 | |
a2367db2 | 1080 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1081 | if (IS_ERR(imxdma->dma_ipg)) |
1082 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1083 | |
1084 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1085 | if (IS_ERR(imxdma->dma_ahb)) |
1086 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 FE |
1087 | |
1088 | clk_prepare_enable(imxdma->dma_ipg); | |
1089 | clk_prepare_enable(imxdma->dma_ahb); | |
6bd08127 JM |
1090 | |
1091 | /* reset DMA module */ | |
cd5cf9da | 1092 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1093 | |
e51d0f0a | 1094 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1095 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1096 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1097 | if (ret) { |
f9b283a6 | 1098 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
04bbd8ef | 1099 | goto err; |
6bd08127 JM |
1100 | } |
1101 | ||
73930eb3 SG |
1102 | irq_err = platform_get_irq(pdev, 1); |
1103 | if (irq_err < 0) { | |
1104 | ret = irq_err; | |
1105 | goto err; | |
1106 | } | |
1107 | ||
1108 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1109 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1110 | if (ret) { |
f9b283a6 | 1111 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
04bbd8ef | 1112 | goto err; |
6bd08127 JM |
1113 | } |
1114 | } | |
1115 | ||
1116 | /* enable DMA module */ | |
cd5cf9da | 1117 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1118 | |
1119 | /* clear all interrupts */ | |
cd5cf9da | 1120 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1121 | |
1122 | /* disable interrupts */ | |
cd5cf9da | 1123 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1124 | |
1125 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1126 | ||
f8a356ff SH |
1127 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1128 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1129 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1130 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1131 | ||
1132 | /* Initialize 2D global parameters */ | |
1133 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1134 | imxdma->slots_2d[i].count = 0; | |
1135 | ||
1136 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1137 | |
1f1846c6 | 1138 | /* Initialize channel parameters */ |
6bd08127 | 1139 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1140 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1141 | ||
e51d0f0a | 1142 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1143 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1144 | dma_irq_handler, 0, "DMA", imxdma); |
1145 | if (ret) { | |
f9b283a6 JM |
1146 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1147 | "for DMA channel %d\n", | |
73930eb3 | 1148 | irq + i, i); |
04bbd8ef | 1149 | goto err; |
6bd08127 | 1150 | } |
2d9c2fc5 JM |
1151 | init_timer(&imxdmac->watchdog); |
1152 | imxdmac->watchdog.function = &imxdma_watchdog; | |
1153 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 1154 | } |
1f1846c6 | 1155 | |
1f1846c6 | 1156 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1157 | |
9e15db7c JM |
1158 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1159 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1160 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1161 | ||
1162 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1163 | (unsigned long)imxdmac); | |
1f1846c6 | 1164 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1165 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1166 | imxdmac->channel = i; |
1167 | ||
1168 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1169 | list_add_tail(&imxdmac->chan.device_node, |
1170 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1171 | } |
1172 | ||
1f1846c6 SH |
1173 | imxdma->dma_device.dev = &pdev->dev; |
1174 | ||
1175 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1176 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1177 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1178 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1179 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1180 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1181 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
1f1846c6 SH |
1182 | imxdma->dma_device.device_control = imxdma_control; |
1183 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
1184 | ||
1185 | platform_set_drvdata(pdev, imxdma); | |
1186 | ||
6c05f091 | 1187 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
1188 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1189 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1190 | ||
1f1846c6 SH |
1191 | ret = dma_async_device_register(&imxdma->dma_device); |
1192 | if (ret) { | |
1193 | dev_err(&pdev->dev, "unable to register\n"); | |
04bbd8ef | 1194 | goto err; |
1f1846c6 SH |
1195 | } |
1196 | ||
290ad0f9 MP |
1197 | if (pdev->dev.of_node) { |
1198 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1199 | imxdma_xlate, imxdma); | |
1200 | if (ret) { | |
1201 | dev_err(&pdev->dev, "unable to register of_dma_controller\n"); | |
1202 | goto err_of_dma_controller; | |
1203 | } | |
1204 | } | |
1205 | ||
1f1846c6 SH |
1206 | return 0; |
1207 | ||
290ad0f9 MP |
1208 | err_of_dma_controller: |
1209 | dma_async_device_unregister(&imxdma->dma_device); | |
04bbd8ef | 1210 | err: |
a2367db2 FE |
1211 | clk_disable_unprepare(imxdma->dma_ipg); |
1212 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1213 | return ret; |
1214 | } | |
1215 | ||
1d1bbd30 | 1216 | static int imxdma_remove(struct platform_device *pdev) |
1f1846c6 SH |
1217 | { |
1218 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 SH |
1219 | |
1220 | dma_async_device_unregister(&imxdma->dma_device); | |
1221 | ||
290ad0f9 MP |
1222 | if (pdev->dev.of_node) |
1223 | of_dma_controller_free(pdev->dev.of_node); | |
1224 | ||
a2367db2 FE |
1225 | clk_disable_unprepare(imxdma->dma_ipg); |
1226 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1227 | |
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static struct platform_driver imxdma_driver = { | |
1232 | .driver = { | |
1233 | .name = "imx-dma", | |
290ad0f9 | 1234 | .of_match_table = imx_dma_of_dev_id, |
1f1846c6 | 1235 | }, |
e51d0f0a | 1236 | .id_table = imx_dma_devtype, |
1d1bbd30 | 1237 | .remove = imxdma_remove, |
1f1846c6 SH |
1238 | }; |
1239 | ||
1240 | static int __init imxdma_module_init(void) | |
1241 | { | |
1242 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1243 | } | |
1244 | subsys_initcall(imxdma_module_init); | |
1245 | ||
1246 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1247 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1248 | MODULE_LICENSE("GPL"); |