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dma: imx-sdma: Use struct for driver data
[deliverable/linux.git] / drivers / dma / imx-sdma.c
CommitLineData
1ec1e82f
SH		 1/*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20#include <linux/init.h>
f8de8f4c 21#include <linux/module.h>
1ec1e82f 22#include <linux/types.h>
0bbc1413 23#include <linux/bitops.h>
1ec1e82f
SH		 24#include <linux/mm.h>
25#include <linux/interrupt.h>
26#include <linux/clk.h>
2ccaef05 27#include <linux/delay.h>
1ec1e82f
SH		 28#include <linux/sched.h>
29#include <linux/semaphore.h>
30#include <linux/spinlock.h>
31#include <linux/device.h>
32#include <linux/dma-mapping.h>
33#include <linux/firmware.h>
34#include <linux/slab.h>
35#include <linux/platform_device.h>
36#include <linux/dmaengine.h>
580975d7
SG		 37#include <linux/of.h>
38#include <linux/of_device.h>
9479e17c 39#include <linux/of_dma.h>
1ec1e82f
SH		 40
41#include <asm/irq.h>
82906b13
AB		 42#include <linux/platform_data/dma-imx-sdma.h>
43#include <linux/platform_data/dma-imx.h>
1ec1e82f 44
d2ebfb33
RKAL		 45#include "dmaengine.h"
46
1ec1e82f
SH		 47/* SDMA registers */
48#define SDMA_H_C0PTR 0x000
49#define SDMA_H_INTR 0x004
50#define SDMA_H_STATSTOP 0x008
51#define SDMA_H_START 0x00c
52#define SDMA_H_EVTOVR 0x010
53#define SDMA_H_DSPOVR 0x014
54#define SDMA_H_HOSTOVR 0x018
55#define SDMA_H_EVTPEND 0x01c
56#define SDMA_H_DSPENBL 0x020
57#define SDMA_H_RESET 0x024
58#define SDMA_H_EVTERR 0x028
59#define SDMA_H_INTRMSK 0x02c
60#define SDMA_H_PSW 0x030
61#define SDMA_H_EVTERRDBG 0x034
62#define SDMA_H_CONFIG 0x038
63#define SDMA_ONCE_ENB 0x040
64#define SDMA_ONCE_DATA 0x044
65#define SDMA_ONCE_INSTR 0x048
66#define SDMA_ONCE_STAT 0x04c
67#define SDMA_ONCE_CMD 0x050
68#define SDMA_EVT_MIRROR 0x054
69#define SDMA_ILLINSTADDR 0x058
70#define SDMA_CHN0ADDR 0x05c
71#define SDMA_ONCE_RTB 0x060
72#define SDMA_XTRIG_CONF1 0x070
73#define SDMA_XTRIG_CONF2 0x074
62550cd7
SG		 74#define SDMA_CHNENBL0_IMX35 0x200
75#define SDMA_CHNENBL0_IMX31 0x080
1ec1e82f
SH		 76#define SDMA_CHNPRI_0 0x100
77
78/*
79 * Buffer descriptor status values.
80 */
81#define BD_DONE 0x01
82#define BD_WRAP 0x02
83#define BD_CONT 0x04
84#define BD_INTR 0x08
85#define BD_RROR 0x10
86#define BD_LAST 0x20
87#define BD_EXTD 0x80
88
89/*
90 * Data Node descriptor status values.
91 */
92#define DND_END_OF_FRAME 0x80
93#define DND_END_OF_XFER 0x40
94#define DND_DONE 0x20
95#define DND_UNUSED 0x01
96
97/*
98 * IPCV2 descriptor status values.
99 */
100#define BD_IPCV2_END_OF_FRAME 0x40
101
102#define IPCV2_MAX_NODES 50
103/*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107#define DATA_ERROR 0x10000000
108
109/*
110 * Buffer descriptor commands.
111 */
112#define C0_ADDR 0x01
113#define C0_LOAD 0x02
114#define C0_DUMP 0x03
115#define C0_SETCTX 0x07
116#define C0_GETCTX 0x03
117#define C0_SETDM 0x01
118#define C0_SETPM 0x04
119#define C0_GETDM 0x02
120#define C0_GETPM 0x08
121/*
122 * Change endianness indicator in the BD command field
123 */
124#define CHANGE_ENDIANNESS 0x80
125
126/*
127 * Mode/Count of data node descriptors - IPCv2
128 */
129struct sdma_mode_count {
130 u32 count : 16; /* size of the buffer pointed by this BD */
131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command : 8; /* command mostlky used for channel 0 */
133};
134
135/*
136 * Buffer descriptor
137 */
138struct sdma_buffer_descriptor {
139 struct sdma_mode_count mode;
140 u32 buffer_addr; /* address of the buffer described */
141 u32 ext_buffer_addr; /* extended buffer address */
142} __attribute__ ((packed));
143
144/**
145 * struct sdma_channel_control - Channel control Block
146 *
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
150 * control blocks
151 */
152struct sdma_channel_control {
153 u32 current_bd_ptr;
154 u32 base_bd_ptr;
155 u32 unused[2];
156} __attribute__ ((packed));
157
158/**
159 * struct sdma_state_registers - SDMA context for a channel
160 *
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
168 * @lm: loop mode
169 */
170struct sdma_state_registers {
171 u32 pc :14;
172 u32 unused1: 1;
173 u32 t : 1;
174 u32 rpc :14;
175 u32 unused0: 1;
176 u32 sf : 1;
177 u32 spc :14;
178 u32 unused2: 1;
179 u32 df : 1;
180 u32 epc :14;
181 u32 lm : 2;
182} __attribute__ ((packed));
183
184/**
185 * struct sdma_context_data - sdma context specific to a channel
186 *
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
203 */
204struct sdma_context_data {
205 struct sdma_state_registers channel_state;
206 u32 gReg[8];
207 u32 mda;
208 u32 msa;
209 u32 ms;
210 u32 md;
211 u32 pda;
212 u32 psa;
213 u32 ps;
214 u32 pd;
215 u32 ca;
216 u32 cs;
217 u32 dda;
218 u32 dsa;
219 u32 ds;
220 u32 dd;
221 u32 scratch0;
222 u32 scratch1;
223 u32 scratch2;
224 u32 scratch3;
225 u32 scratch4;
226 u32 scratch5;
227 u32 scratch6;
228 u32 scratch7;
229} __attribute__ ((packed));
230
231#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232
233struct sdma_engine;
234
235/**
236 * struct sdma_channel - housekeeping for a SDMA channel
237 *
238 * @sdma pointer to the SDMA engine for this channel
23889c63 239 * @channel the channel number, matches dmaengine chan_id + 1
1ec1e82f
SH		 240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
1ec1e82f
SH		 246 * @num_bd max NUM_BD. number of descriptors currently handling
247 */
248struct sdma_channel {
249 struct sdma_engine *sdma;
250 unsigned int channel;
db8196df 251 enum dma_transfer_direction direction;
1ec1e82f
SH		 252 enum sdma_peripheral_type peripheral_type;
253 unsigned int event_id0;
254 unsigned int event_id1;
255 enum dma_slave_buswidth word_size;
256 unsigned int buf_tail;
1ec1e82f
SH		 257 unsigned int num_bd;
258 struct sdma_buffer_descriptor *bd;
259 dma_addr_t bd_phys;
260 unsigned int pc_from_device, pc_to_device;
261 unsigned long flags;
262 dma_addr_t per_address;
0bbc1413
RZ		 263 unsigned long event_mask[2];
264 unsigned long watermark_level;
1ec1e82f
SH		 265 u32 shp_addr, per_addr;
266 struct dma_chan chan;
267 spinlock_t lock;
268 struct dma_async_tx_descriptor desc;
1ec1e82f 269 enum dma_status status;
ab59a510
HS		 270 unsigned int chn_count;
271 unsigned int chn_real_count;
abd9ccc8 272 struct tasklet_struct tasklet;
1ec1e82f
SH		 273};
274
0bbc1413 275#define IMX_DMA_SG_LOOP BIT(0)
1ec1e82f
SH		 276
277#define MAX_DMA_CHANNELS 32
278#define MXC_SDMA_DEFAULT_PRIORITY 1
279#define MXC_SDMA_MIN_PRIORITY 1
280#define MXC_SDMA_MAX_PRIORITY 7
281
1ec1e82f
SH		 282#define SDMA_FIRMWARE_MAGIC 0x414d4453
283
284/**
285 * struct sdma_firmware_header - Layout of the firmware image
286 *
287 * @magic "SDMA"
288 * @version_major increased whenever layout of struct sdma_script_start_addrs
289 * changes.
290 * @version_minor firmware minor version (for binary compatible changes)
291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
292 * @num_script_addrs Number of script addresses in this image
293 * @ram_code_start offset of SDMA ram image in this firmware image
294 * @ram_code_size size of SDMA ram image
295 * @script_addrs Stores the start address of the SDMA scripts
296 * (in SDMA memory space)
297 */
298struct sdma_firmware_header {
299 u32 magic;
300 u32 version_major;
301 u32 version_minor;
302 u32 script_addrs_start;
303 u32 num_script_addrs;
304 u32 ram_code_start;
305 u32 ram_code_size;
306};
307
17bba72f
SH		 308struct sdma_driver_data {
309 int chnenbl0;
310 int num_events;
62550cd7
SG		 311};
312
1ec1e82f
SH		 313struct sdma_engine {
314 struct device *dev;
b9b3f82f 315 struct device_dma_parameters dma_parms;
1ec1e82f
SH		 316 struct sdma_channel channel[MAX_DMA_CHANNELS];
317 struct sdma_channel_control *channel_control;
318 void __iomem *regs;
1ec1e82f
SH		 319 struct sdma_context_data *context;
320 dma_addr_t context_phys;
321 struct dma_device dma_device;
7560e3f3
SH		 322 struct clk *clk_ipg;
323 struct clk *clk_ahb;
2ccaef05 324 spinlock_t channel_0_lock;
1ec1e82f 325 struct sdma_script_start_addrs *script_addrs;
17bba72f
SH		 326 const struct sdma_driver_data *drvdata;
327};
328
329struct sdma_driver_data sdma_imx31 = {
330 .chnenbl0 = SDMA_CHNENBL0_IMX31,
331 .num_events = 32,
332};
333
334struct sdma_driver_data sdma_imx35 = {
335 .chnenbl0 = SDMA_CHNENBL0_IMX35,
336 .num_events = 48,
1ec1e82f
SH		 337};
338
62550cd7
SG		 339static struct platform_device_id sdma_devtypes[] = {
340 {
341 .name = "imx31-sdma",
17bba72f 342 .driver_data = (unsigned long)&sdma_imx31,
62550cd7
SG		 343 }, {
344 .name = "imx35-sdma",
17bba72f 345 .driver_data = (unsigned long)&sdma_imx35,
62550cd7
SG		 346 }, {
347 /* sentinel */
348 }
349};
350MODULE_DEVICE_TABLE(platform, sdma_devtypes);
351
580975d7 352static const struct of_device_id sdma_dt_ids[] = {
17bba72f
SH		 353 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
354 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
580975d7
SG		 355 { /* sentinel */ }
356};
357MODULE_DEVICE_TABLE(of, sdma_dt_ids);
358
0bbc1413
RZ		 359#define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
360#define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
361#define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
1ec1e82f
SH		 362#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
363
364static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
365{
17bba72f 366 u32 chnenbl0 = sdma->drvdata->chnenbl0;
1ec1e82f
SH		 367 return chnenbl0 + event * 4;
368}
369
370static int sdma_config_ownership(struct sdma_channel *sdmac,
371 bool event_override, bool mcu_override, bool dsp_override)
372{
373 struct sdma_engine *sdma = sdmac->sdma;
374 int channel = sdmac->channel;
0bbc1413 375 unsigned long evt, mcu, dsp;
1ec1e82f
SH		 376
377 if (event_override && mcu_override && dsp_override)
378 return -EINVAL;
379
c4b56857
RZ		 380 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
381 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
382 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
1ec1e82f
SH		 383
384 if (dsp_override)
0bbc1413 385 __clear_bit(channel, &dsp);
1ec1e82f 386 else
0bbc1413 387 __set_bit(channel, &dsp);
1ec1e82f
SH		 388
389 if (event_override)
0bbc1413 390 __clear_bit(channel, &evt);
1ec1e82f 391 else
0bbc1413 392 __set_bit(channel, &evt);
1ec1e82f
SH		 393
394 if (mcu_override)
0bbc1413 395 __clear_bit(channel, &mcu);
1ec1e82f 396 else
0bbc1413 397 __set_bit(channel, &mcu);
1ec1e82f 398
c4b56857
RZ		 399 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
400 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
401 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
1ec1e82f
SH		 402
403 return 0;
404}
405
b9a59166
RZ		 406static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
407{
0bbc1413 408 writel(BIT(channel), sdma->regs + SDMA_H_START);
b9a59166
RZ		 409}
410
1ec1e82f 411/*
2ccaef05 412 * sdma_run_channel0 - run a channel and wait till it's done
1ec1e82f 413 */
2ccaef05 414static int sdma_run_channel0(struct sdma_engine *sdma)
1ec1e82f 415{
1ec1e82f 416 int ret;
2ccaef05 417 unsigned long timeout = 500;
1ec1e82f 418
2ccaef05 419 sdma_enable_channel(sdma, 0);
1ec1e82f 420
2ccaef05
RZ		 421 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
422 if (timeout-- <= 0)
423 break;
424 udelay(1);
425 }
1ec1e82f 426
2ccaef05
RZ		 427 if (ret) {
428 /* Clear the interrupt status */
429 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
430 } else {
431 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
432 }
1ec1e82f
SH		 433
434 return ret ? 0 : -ETIMEDOUT;
435}
436
437static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
438 u32 address)
439{
440 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
441 void *buf_virt;
442 dma_addr_t buf_phys;
443 int ret;
2ccaef05 444 unsigned long flags;
73eab978 445
1ec1e82f
SH		 446 buf_virt = dma_alloc_coherent(NULL,
447 size,
448 &buf_phys, GFP_KERNEL);
73eab978 449 if (!buf_virt) {
2ccaef05 450 return -ENOMEM;
73eab978 451 }
1ec1e82f 452
2ccaef05
RZ		 453 spin_lock_irqsave(&sdma->channel_0_lock, flags);
454
1ec1e82f
SH		 455 bd0->mode.command = C0_SETPM;
456 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
457 bd0->mode.count = size / 2;
458 bd0->buffer_addr = buf_phys;
459 bd0->ext_buffer_addr = address;
460
461 memcpy(buf_virt, buf, size);
462
2ccaef05 463 ret = sdma_run_channel0(sdma);
1ec1e82f 464
2ccaef05 465 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1ec1e82f 466
2ccaef05 467 dma_free_coherent(NULL, size, buf_virt, buf_phys);
73eab978 468
1ec1e82f
SH		 469 return ret;
470}
471
472static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
473{
474 struct sdma_engine *sdma = sdmac->sdma;
475 int channel = sdmac->channel;
0bbc1413 476 unsigned long val;
1ec1e82f
SH		 477 u32 chnenbl = chnenbl_ofs(sdma, event);
478
c4b56857 479 val = readl_relaxed(sdma->regs + chnenbl);
0bbc1413 480 __set_bit(channel, &val);
c4b56857 481 writel_relaxed(val, sdma->regs + chnenbl);
1ec1e82f
SH		 482}
483
484static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
485{
486 struct sdma_engine *sdma = sdmac->sdma;
487 int channel = sdmac->channel;
488 u32 chnenbl = chnenbl_ofs(sdma, event);
0bbc1413 489 unsigned long val;
1ec1e82f 490
c4b56857 491 val = readl_relaxed(sdma->regs + chnenbl);
0bbc1413 492 __clear_bit(channel, &val);
c4b56857 493 writel_relaxed(val, sdma->regs + chnenbl);
1ec1e82f
SH		 494}
495
496static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
497{
498 struct sdma_buffer_descriptor *bd;
499
500 /*
501 * loop mode. Iterate over descriptors, re-setup them and
502 * call callback function.
503 */
504 while (1) {
505 bd = &sdmac->bd[sdmac->buf_tail];
506
507 if (bd->mode.status & BD_DONE)
508 break;
509
510 if (bd->mode.status & BD_RROR)
511 sdmac->status = DMA_ERROR;
512 else
1e9cebb4 513 sdmac->status = DMA_IN_PROGRESS;
1ec1e82f
SH		 514
515 bd->mode.status |= BD_DONE;
516 sdmac->buf_tail++;
517 sdmac->buf_tail %= sdmac->num_bd;
518
519 if (sdmac->desc.callback)
520 sdmac->desc.callback(sdmac->desc.callback_param);
521 }
522}
523
524static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
525{
526 struct sdma_buffer_descriptor *bd;
527 int i, error = 0;
528
ab59a510 529 sdmac->chn_real_count = 0;
1ec1e82f
SH		 530 /*
531 * non loop mode. Iterate over all descriptors, collect
532 * errors and call callback function
533 */
534 for (i = 0; i < sdmac->num_bd; i++) {
535 bd = &sdmac->bd[i];
536
537 if (bd->mode.status & (BD_DONE | BD_RROR))
538 error = -EIO;
ab59a510 539 sdmac->chn_real_count += bd->mode.count;
1ec1e82f
SH		 540 }
541
542 if (error)
543 sdmac->status = DMA_ERROR;
544 else
545 sdmac->status = DMA_SUCCESS;
546
f7fbce07 547 dma_cookie_complete(&sdmac->desc);
1ec1e82f
SH		 548 if (sdmac->desc.callback)
549 sdmac->desc.callback(sdmac->desc.callback_param);
1ec1e82f
SH		 550}
551
abd9ccc8 552static void sdma_tasklet(unsigned long data)
1ec1e82f 553{
abd9ccc8
HS		 554 struct sdma_channel *sdmac = (struct sdma_channel *) data;
555
1ec1e82f
SH		 556 if (sdmac->flags & IMX_DMA_SG_LOOP)
557 sdma_handle_channel_loop(sdmac);
558 else
559 mxc_sdma_handle_channel_normal(sdmac);
560}
561
562static irqreturn_t sdma_int_handler(int irq, void *dev_id)
563{
564 struct sdma_engine *sdma = dev_id;
0bbc1413 565 unsigned long stat;
1ec1e82f 566
c4b56857 567 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
2ccaef05
RZ		 568 /* not interested in channel 0 interrupts */
569 stat &= ~1;
c4b56857 570 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
1ec1e82f
SH		 571
572 while (stat) {
573 int channel = fls(stat) - 1;
574 struct sdma_channel *sdmac = &sdma->channel[channel];
575
abd9ccc8 576 tasklet_schedule(&sdmac->tasklet);
1ec1e82f 577
0bbc1413 578 __clear_bit(channel, &stat);
1ec1e82f
SH		 579 }
580
581 return IRQ_HANDLED;
582}
583
584/*
585 * sets the pc of SDMA script according to the peripheral type
586 */
587static void sdma_get_pc(struct sdma_channel *sdmac,
588 enum sdma_peripheral_type peripheral_type)
589{
590 struct sdma_engine *sdma = sdmac->sdma;
591 int per_2_emi = 0, emi_2_per = 0;
592 /*
593 * These are needed once we start to support transfers between
594 * two peripherals or memory-to-memory transfers
595 */
596 int per_2_per = 0, emi_2_emi = 0;
597
598 sdmac->pc_from_device = 0;
599 sdmac->pc_to_device = 0;
600
601 switch (peripheral_type) {
602 case IMX_DMATYPE_MEMORY:
603 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
604 break;
605 case IMX_DMATYPE_DSP:
606 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
607 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
608 break;
609 case IMX_DMATYPE_FIRI:
610 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
611 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
612 break;
613 case IMX_DMATYPE_UART:
614 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
615 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
616 break;
617 case IMX_DMATYPE_UART_SP:
618 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
619 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
620 break;
621 case IMX_DMATYPE_ATA:
622 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
623 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
624 break;
625 case IMX_DMATYPE_CSPI:
626 case IMX_DMATYPE_EXT:
627 case IMX_DMATYPE_SSI:
628 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
629 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
630 break;
631 case IMX_DMATYPE_SSI_SP:
632 case IMX_DMATYPE_MMC:
633 case IMX_DMATYPE_SDHC:
634 case IMX_DMATYPE_CSPI_SP:
635 case IMX_DMATYPE_ESAI:
636 case IMX_DMATYPE_MSHC_SP:
637 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
638 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
639 break;
640 case IMX_DMATYPE_ASRC:
641 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
642 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
643 per_2_per = sdma->script_addrs->per_2_per_addr;
644 break;
645 case IMX_DMATYPE_MSHC:
646 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
647 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
648 break;
649 case IMX_DMATYPE_CCM:
650 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
651 break;
652 case IMX_DMATYPE_SPDIF:
653 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
654 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
655 break;
656 case IMX_DMATYPE_IPU_MEMORY:
657 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
658 break;
659 default:
660 break;
661 }
662
663 sdmac->pc_from_device = per_2_emi;
664 sdmac->pc_to_device = emi_2_per;
665}
666
667static int sdma_load_context(struct sdma_channel *sdmac)
668{
669 struct sdma_engine *sdma = sdmac->sdma;
670 int channel = sdmac->channel;
671 int load_address;
672 struct sdma_context_data *context = sdma->context;
673 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
674 int ret;
2ccaef05 675 unsigned long flags;
1ec1e82f 676
db8196df 677 if (sdmac->direction == DMA_DEV_TO_MEM) {
1ec1e82f
SH		 678 load_address = sdmac->pc_from_device;
679 } else {
680 load_address = sdmac->pc_to_device;
681 }
682
683 if (load_address < 0)
684 return load_address;
685
686 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
0bbc1413 687 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1ec1e82f
SH		 688 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
689 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
0bbc1413
RZ		 690 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
691 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1ec1e82f 692
2ccaef05 693 spin_lock_irqsave(&sdma->channel_0_lock, flags);
73eab978 694
1ec1e82f
SH		 695 memset(context, 0, sizeof(*context));
696 context->channel_state.pc = load_address;
697
698 /* Send by context the event mask,base address for peripheral
699 * and watermark level
700 */
0bbc1413
RZ		 701 context->gReg[0] = sdmac->event_mask[1];
702 context->gReg[1] = sdmac->event_mask[0];
1ec1e82f
SH		 703 context->gReg[2] = sdmac->per_addr;
704 context->gReg[6] = sdmac->shp_addr;
705 context->gReg[7] = sdmac->watermark_level;
706
707 bd0->mode.command = C0_SETDM;
708 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
709 bd0->mode.count = sizeof(*context) / 4;
710 bd0->buffer_addr = sdma->context_phys;
711 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
2ccaef05 712 ret = sdma_run_channel0(sdma);
1ec1e82f 713
2ccaef05 714 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
73eab978 715
1ec1e82f
SH		 716 return ret;
717}
718
719static void sdma_disable_channel(struct sdma_channel *sdmac)
720{
721 struct sdma_engine *sdma = sdmac->sdma;
722 int channel = sdmac->channel;
723
0bbc1413 724 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1ec1e82f
SH		 725 sdmac->status = DMA_ERROR;
726}
727
728static int sdma_config_channel(struct sdma_channel *sdmac)
729{
730 int ret;
731
732 sdma_disable_channel(sdmac);
733
0bbc1413
RZ		 734 sdmac->event_mask[0] = 0;
735 sdmac->event_mask[1] = 0;
1ec1e82f
SH		 736 sdmac->shp_addr = 0;
737 sdmac->per_addr = 0;
738
739 if (sdmac->event_id0) {
17bba72f 740 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1ec1e82f
SH		 741 return -EINVAL;
742 sdma_event_enable(sdmac, sdmac->event_id0);
743 }
744
745 switch (sdmac->peripheral_type) {
746 case IMX_DMATYPE_DSP:
747 sdma_config_ownership(sdmac, false, true, true);
748 break;
749 case IMX_DMATYPE_MEMORY:
750 sdma_config_ownership(sdmac, false, true, false);
751 break;
752 default:
753 sdma_config_ownership(sdmac, true, true, false);
754 break;
755 }
756
757 sdma_get_pc(sdmac, sdmac->peripheral_type);
758
759 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
760 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
761 /* Handle multiple event channels differently */
762 if (sdmac->event_id1) {
0bbc1413 763 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
1ec1e82f 764 if (sdmac->event_id1 > 31)
0bbc1413
RZ		 765 __set_bit(31, &sdmac->watermark_level);
766 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
1ec1e82f 767 if (sdmac->event_id0 > 31)
0bbc1413 768 __set_bit(30, &sdmac->watermark_level);
1ec1e82f 769 } else {
0bbc1413 770 __set_bit(sdmac->event_id0, sdmac->event_mask);
1ec1e82f
SH		 771 }
772 /* Watermark Level */
773 sdmac->watermark_level |= sdmac->watermark_level;
774 /* Address */
775 sdmac->shp_addr = sdmac->per_address;
776 } else {
777 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
778 }
779
780 ret = sdma_load_context(sdmac);
781
782 return ret;
783}
784
785static int sdma_set_channel_priority(struct sdma_channel *sdmac,
786 unsigned int priority)
787{
788 struct sdma_engine *sdma = sdmac->sdma;
789 int channel = sdmac->channel;
790
791 if (priority < MXC_SDMA_MIN_PRIORITY
792 || priority > MXC_SDMA_MAX_PRIORITY) {
793 return -EINVAL;
794 }
795
c4b56857 796 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1ec1e82f
SH		 797
798 return 0;
799}
800
801static int sdma_request_channel(struct sdma_channel *sdmac)
802{
803 struct sdma_engine *sdma = sdmac->sdma;
804 int channel = sdmac->channel;
805 int ret = -EBUSY;
806
807 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
808 if (!sdmac->bd) {
809 ret = -ENOMEM;
810 goto out;
811 }
812
813 memset(sdmac->bd, 0, PAGE_SIZE);
814
815 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
816 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
817
1ec1e82f 818 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1ec1e82f
SH		 819 return 0;
820out:
821
822 return ret;
823}
824
1ec1e82f
SH		 825static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
826{
827 return container_of(chan, struct sdma_channel, chan);
828}
829
830static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
831{
f69f2e26 832 unsigned long flags;
1ec1e82f 833 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1ec1e82f
SH		 834 dma_cookie_t cookie;
835
f69f2e26 836 spin_lock_irqsave(&sdmac->lock, flags);
1ec1e82f 837
884485e1 838 cookie = dma_cookie_assign(tx);
1ec1e82f 839
f69f2e26 840 spin_unlock_irqrestore(&sdmac->lock, flags);
1ec1e82f
SH		 841
842 return cookie;
843}
844
845static int sdma_alloc_chan_resources(struct dma_chan *chan)
846{
847 struct sdma_channel *sdmac = to_sdma_chan(chan);
848 struct imx_dma_data *data = chan->private;
849 int prio, ret;
850
1ec1e82f
SH		 851 if (!data)
852 return -EINVAL;
853
854 switch (data->priority) {
855 case DMA_PRIO_HIGH:
856 prio = 3;
857 break;
858 case DMA_PRIO_MEDIUM:
859 prio = 2;
860 break;
861 case DMA_PRIO_LOW:
862 default:
863 prio = 1;
864 break;
865 }
866
867 sdmac->peripheral_type = data->peripheral_type;
868 sdmac->event_id0 = data->dma_request;
c2c744d3 869
7560e3f3
SH		 870 clk_enable(sdmac->sdma->clk_ipg);
871 clk_enable(sdmac->sdma->clk_ahb);
c2c744d3 872
3bb5e7ca 873 ret = sdma_request_channel(sdmac);
1ec1e82f
SH		 874 if (ret)
875 return ret;
876
3bb5e7ca 877 ret = sdma_set_channel_priority(sdmac, prio);
1ec1e82f
SH		 878 if (ret)
879 return ret;
880
881 dma_async_tx_descriptor_init(&sdmac->desc, chan);
882 sdmac->desc.tx_submit = sdma_tx_submit;
883 /* txd.flags will be overwritten in prep funcs */
884 sdmac->desc.flags = DMA_CTRL_ACK;
885
886 return 0;
887}
888
889static void sdma_free_chan_resources(struct dma_chan *chan)
890{
891 struct sdma_channel *sdmac = to_sdma_chan(chan);
892 struct sdma_engine *sdma = sdmac->sdma;
893
894 sdma_disable_channel(sdmac);
895
896 if (sdmac->event_id0)
897 sdma_event_disable(sdmac, sdmac->event_id0);
898 if (sdmac->event_id1)
899 sdma_event_disable(sdmac, sdmac->event_id1);
900
901 sdmac->event_id0 = 0;
902 sdmac->event_id1 = 0;
903
904 sdma_set_channel_priority(sdmac, 0);
905
906 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
907
7560e3f3
SH		 908 clk_disable(sdma->clk_ipg);
909 clk_disable(sdma->clk_ahb);
1ec1e82f
SH		 910}
911
912static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
913 struct dma_chan *chan, struct scatterlist *sgl,
db8196df 914 unsigned int sg_len, enum dma_transfer_direction direction,
185ecb5f 915 unsigned long flags, void *context)
1ec1e82f
SH		 916{
917 struct sdma_channel *sdmac = to_sdma_chan(chan);
918 struct sdma_engine *sdma = sdmac->sdma;
919 int ret, i, count;
23889c63 920 int channel = sdmac->channel;
1ec1e82f
SH		 921 struct scatterlist *sg;
922
923 if (sdmac->status == DMA_IN_PROGRESS)
924 return NULL;
925 sdmac->status = DMA_IN_PROGRESS;
926
927 sdmac->flags = 0;
928
8e2e27c7
RZ		 929 sdmac->buf_tail = 0;
930
1ec1e82f
SH		 931 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
932 sg_len, channel);
933
934 sdmac->direction = direction;
935 ret = sdma_load_context(sdmac);
936 if (ret)
937 goto err_out;
938
939 if (sg_len > NUM_BD) {
940 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
941 channel, sg_len, NUM_BD);
942 ret = -EINVAL;
943 goto err_out;
944 }
945
ab59a510 946 sdmac->chn_count = 0;
1ec1e82f
SH		 947 for_each_sg(sgl, sg, sg_len, i) {
948 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
949 int param;
950
d2f5c276 951 bd->buffer_addr = sg->dma_address;
1ec1e82f 952
fdaf9c4b 953 count = sg_dma_len(sg);
1ec1e82f
SH		 954
955 if (count > 0xffff) {
956 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
957 channel, count, 0xffff);
958 ret = -EINVAL;
959 goto err_out;
960 }
961
962 bd->mode.count = count;
ab59a510 963 sdmac->chn_count += count;
1ec1e82f
SH		 964
965 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
966 ret = -EINVAL;
967 goto err_out;
968 }
1fa81c27
SH		 969
970 switch (sdmac->word_size) {
971 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1ec1e82f 972 bd->mode.command = 0;
1fa81c27
SH		 973 if (count & 3 || sg->dma_address & 3)
974 return NULL;
975 break;
976 case DMA_SLAVE_BUSWIDTH_2_BYTES:
977 bd->mode.command = 2;
978 if (count & 1 || sg->dma_address & 1)
979 return NULL;
980 break;
981 case DMA_SLAVE_BUSWIDTH_1_BYTE:
982 bd->mode.command = 1;
983 break;
984 default:
985 return NULL;
986 }
1ec1e82f
SH		 987
988 param = BD_DONE | BD_EXTD | BD_CONT;
989
341b9419 990 if (i + 1 == sg_len) {
1ec1e82f 991 param |= BD_INTR;
341b9419
SG		 992 param |= BD_LAST;
993 param &= ~BD_CONT;
1ec1e82f
SH		 994 }
995
1ec1e82f
SH		 996 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
997 i, count, sg->dma_address,
998 param & BD_WRAP ? "wrap" : "",
999 param & BD_INTR ? " intr" : "");
1000
1001 bd->mode.status = param;
1002 }
1003
1004 sdmac->num_bd = sg_len;
1005 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1006
1007 return &sdmac->desc;
1008err_out:
4b2ce9dd 1009 sdmac->status = DMA_ERROR;
1ec1e82f
SH		 1010 return NULL;
1011}
1012
1013static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1014 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
185ecb5f 1015 size_t period_len, enum dma_transfer_direction direction,
ec8b5e48 1016 unsigned long flags, void *context)
1ec1e82f
SH		 1017{
1018 struct sdma_channel *sdmac = to_sdma_chan(chan);
1019 struct sdma_engine *sdma = sdmac->sdma;
1020 int num_periods = buf_len / period_len;
23889c63 1021 int channel = sdmac->channel;
1ec1e82f
SH		 1022 int ret, i = 0, buf = 0;
1023
1024 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1025
1026 if (sdmac->status == DMA_IN_PROGRESS)
1027 return NULL;
1028
1029 sdmac->status = DMA_IN_PROGRESS;
1030
8e2e27c7
RZ		 1031 sdmac->buf_tail = 0;
1032
1ec1e82f
SH		 1033 sdmac->flags |= IMX_DMA_SG_LOOP;
1034 sdmac->direction = direction;
1035 ret = sdma_load_context(sdmac);
1036 if (ret)
1037 goto err_out;
1038
1039 if (num_periods > NUM_BD) {
1040 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1041 channel, num_periods, NUM_BD);
1042 goto err_out;
1043 }
1044
1045 if (period_len > 0xffff) {
1046 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1047 channel, period_len, 0xffff);
1048 goto err_out;
1049 }
1050
1051 while (buf < buf_len) {
1052 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1053 int param;
1054
1055 bd->buffer_addr = dma_addr;
1056
1057 bd->mode.count = period_len;
1058
1059 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1060 goto err_out;
1061 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1062 bd->mode.command = 0;
1063 else
1064 bd->mode.command = sdmac->word_size;
1065
1066 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1067 if (i + 1 == num_periods)
1068 param |= BD_WRAP;
1069
1070 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1071 i, period_len, dma_addr,
1072 param & BD_WRAP ? "wrap" : "",
1073 param & BD_INTR ? " intr" : "");
1074
1075 bd->mode.status = param;
1076
1077 dma_addr += period_len;
1078 buf += period_len;
1079
1080 i++;
1081 }
1082
1083 sdmac->num_bd = num_periods;
1084 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1085
1086 return &sdmac->desc;
1087err_out:
1088 sdmac->status = DMA_ERROR;
1089 return NULL;
1090}
1091
1092static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1093 unsigned long arg)
1094{
1095 struct sdma_channel *sdmac = to_sdma_chan(chan);
1096 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1097
1098 switch (cmd) {
1099 case DMA_TERMINATE_ALL:
1100 sdma_disable_channel(sdmac);
1101 return 0;
1102 case DMA_SLAVE_CONFIG:
db8196df 1103 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1ec1e82f 1104 sdmac->per_address = dmaengine_cfg->src_addr;
94ac27a5
PR		 1105 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1106 dmaengine_cfg->src_addr_width;
1ec1e82f
SH		 1107 sdmac->word_size = dmaengine_cfg->src_addr_width;
1108 } else {
1109 sdmac->per_address = dmaengine_cfg->dst_addr;
94ac27a5
PR		 1110 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1111 dmaengine_cfg->dst_addr_width;
1ec1e82f
SH		 1112 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1113 }
e6966433 1114 sdmac->direction = dmaengine_cfg->direction;
1ec1e82f
SH		 1115 return sdma_config_channel(sdmac);
1116 default:
1117 return -ENOSYS;
1118 }
1119
1120 return -EINVAL;
1121}
1122
1123static enum dma_status sdma_tx_status(struct dma_chan *chan,
e8e3a790
AS		 1124 dma_cookie_t cookie,
1125 struct dma_tx_state *txstate)
1ec1e82f
SH		 1126{
1127 struct sdma_channel *sdmac = to_sdma_chan(chan);
1ec1e82f 1128
e8e3a790 1129 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
ab59a510 1130 sdmac->chn_count - sdmac->chn_real_count);
1ec1e82f 1131
8a965911 1132 return sdmac->status;
1ec1e82f
SH		 1133}
1134
1135static void sdma_issue_pending(struct dma_chan *chan)
1136{
2b4f130e
SH		 1137 struct sdma_channel *sdmac = to_sdma_chan(chan);
1138 struct sdma_engine *sdma = sdmac->sdma;
1139
1140 if (sdmac->status == DMA_IN_PROGRESS)
1141 sdma_enable_channel(sdma, sdmac->channel);
1ec1e82f
SH		 1142}
1143
5b28aa31
SH		 1144#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1145
1146static void sdma_add_scripts(struct sdma_engine *sdma,
1147 const struct sdma_script_start_addrs *addr)
1148{
1149 s32 *addr_arr = (u32 *)addr;
1150 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1151 int i;
1152
1153 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1154 if (addr_arr[i] > 0)
1155 saddr_arr[i] = addr_arr[i];
1156}
1157
7b4b88e0 1158static void sdma_load_firmware(const struct firmware *fw, void *context)
5b28aa31 1159{
7b4b88e0 1160 struct sdma_engine *sdma = context;
5b28aa31 1161 const struct sdma_firmware_header *header;
5b28aa31
SH		 1162 const struct sdma_script_start_addrs *addr;
1163 unsigned short *ram_code;
1164
7b4b88e0
SH		 1165 if (!fw) {
1166 dev_err(sdma->dev, "firmware not found\n");
1167 return;
1168 }
5b28aa31
SH		 1169
1170 if (fw->size < sizeof(*header))
1171 goto err_firmware;
1172
1173 header = (struct sdma_firmware_header *)fw->data;
1174
1175 if (header->magic != SDMA_FIRMWARE_MAGIC)
1176 goto err_firmware;
1177 if (header->ram_code_start + header->ram_code_size > fw->size)
1178 goto err_firmware;
1179
1180 addr = (void *)header + header->script_addrs_start;
1181 ram_code = (void *)header + header->ram_code_start;
1182
7560e3f3
SH		 1183 clk_enable(sdma->clk_ipg);
1184 clk_enable(sdma->clk_ahb);
5b28aa31
SH		 1185 /* download the RAM image for SDMA */
1186 sdma_load_script(sdma, ram_code,
1187 header->ram_code_size,
6866fd3b 1188 addr->ram_code_start_addr);
7560e3f3
SH		 1189 clk_disable(sdma->clk_ipg);
1190 clk_disable(sdma->clk_ahb);
5b28aa31
SH		 1191
1192 sdma_add_scripts(sdma, addr);
1193
1194 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1195 header->version_major,
1196 header->version_minor);
1197
1198err_firmware:
1199 release_firmware(fw);
7b4b88e0
SH		 1200}
1201
1202static int __init sdma_get_firmware(struct sdma_engine *sdma,
1203 const char *fw_name)
1204{
1205 int ret;
1206
1207 ret = request_firmware_nowait(THIS_MODULE,
1208 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1209 GFP_KERNEL, sdma, sdma_load_firmware);
5b28aa31
SH		 1210
1211 return ret;
1212}
1213
1214static int __init sdma_init(struct sdma_engine *sdma)
1ec1e82f
SH		 1215{
1216 int i, ret;
1217 dma_addr_t ccb_phys;
1218
7560e3f3
SH		 1219 clk_enable(sdma->clk_ipg);
1220 clk_enable(sdma->clk_ahb);
1ec1e82f
SH		 1221
1222 /* Be sure SDMA has not started yet */
c4b56857 1223 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1ec1e82f
SH		 1224
1225 sdma->channel_control = dma_alloc_coherent(NULL,
1226 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1227 sizeof(struct sdma_context_data),
1228 &ccb_phys, GFP_KERNEL);
1229
1230 if (!sdma->channel_control) {
1231 ret = -ENOMEM;
1232 goto err_dma_alloc;
1233 }
1234
1235 sdma->context = (void *)sdma->channel_control +
1236 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1237 sdma->context_phys = ccb_phys +
1238 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1239
1240 /* Zero-out the CCB structures array just allocated */
1241 memset(sdma->channel_control, 0,
1242 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1243
1244 /* disable all channels */
17bba72f 1245 for (i = 0; i < sdma->drvdata->num_events; i++)
c4b56857 1246 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1ec1e82f
SH		 1247
1248 /* All channels have priority 0 */
1249 for (i = 0; i < MAX_DMA_CHANNELS; i++)
c4b56857 1250 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1ec1e82f
SH		 1251
1252 ret = sdma_request_channel(&sdma->channel[0]);
1253 if (ret)
1254 goto err_dma_alloc;
1255
1256 sdma_config_ownership(&sdma->channel[0], false, true, false);
1257
1258 /* Set Command Channel (Channel Zero) */
c4b56857 1259 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1ec1e82f
SH		 1260
1261 /* Set bits of CONFIG register but with static context switching */
1262 /* FIXME: Check whether to set ACR bit depending on clock ratios */
c4b56857 1263 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1ec1e82f 1264
c4b56857 1265 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1ec1e82f 1266
1ec1e82f 1267 /* Set bits of CONFIG register with given context switching mode */
c4b56857 1268 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1ec1e82f
SH		 1269
1270 /* Initializes channel's priorities */
1271 sdma_set_channel_priority(&sdma->channel[0], 7);
1272
7560e3f3
SH		 1273 clk_disable(sdma->clk_ipg);
1274 clk_disable(sdma->clk_ahb);
1ec1e82f
SH		 1275
1276 return 0;
1277
1278err_dma_alloc:
7560e3f3
SH		 1279 clk_disable(sdma->clk_ipg);
1280 clk_disable(sdma->clk_ahb);
1ec1e82f
SH		 1281 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1282 return ret;
1283}
1284
9479e17c
SG		 1285static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1286{
1287 struct imx_dma_data *data = fn_param;
1288
1289 if (!imx_dma_is_general_purpose(chan))
1290 return false;
1291
1292 chan->private = data;
1293
1294 return true;
1295}
1296
1297static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1298 struct of_dma *ofdma)
1299{
1300 struct sdma_engine *sdma = ofdma->of_dma_data;
1301 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1302 struct imx_dma_data data;
1303
1304 if (dma_spec->args_count != 3)
1305 return NULL;
1306
1307 data.dma_request = dma_spec->args[0];
1308 data.peripheral_type = dma_spec->args[1];
1309 data.priority = dma_spec->args[2];
1310
1311 return dma_request_channel(mask, sdma_filter_fn, &data);
1312}
1313
1ec1e82f
SH		 1314static int __init sdma_probe(struct platform_device *pdev)
1315{
580975d7
SG		 1316 const struct of_device_id *of_id =
1317 of_match_device(sdma_dt_ids, &pdev->dev);
1318 struct device_node *np = pdev->dev.of_node;
1319 const char *fw_name;
1ec1e82f 1320 int ret;
1ec1e82f 1321 int irq;
1ec1e82f 1322 struct resource *iores;
d4adcc01 1323 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1ec1e82f 1324 int i;
1ec1e82f 1325 struct sdma_engine *sdma;
36e2f21a 1326 s32 *saddr_arr;
17bba72f
SH		 1327 const struct sdma_driver_data *drvdata = NULL;
1328
1329 if (of_id)
1330 drvdata = of_id->data;
1331 else if (pdev->id_entry)
1332 drvdata = (void *)pdev->id_entry->driver_data;
1333
1334 if (!drvdata) {
1335 dev_err(&pdev->dev, "unable to find driver data\n");
1336 return -EINVAL;
1337 }
1ec1e82f
SH		 1338
1339 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1340 if (!sdma)
1341 return -ENOMEM;
1342
2ccaef05 1343 spin_lock_init(&sdma->channel_0_lock);
73eab978 1344
1ec1e82f 1345 sdma->dev = &pdev->dev;
17bba72f 1346 sdma->drvdata = drvdata;
1ec1e82f
SH		 1347
1348 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349 irq = platform_get_irq(pdev, 0);
580975d7 1350 if (!iores || irq < 0) {
1ec1e82f
SH		 1351 ret = -EINVAL;
1352 goto err_irq;
1353 }
1354
1355 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1356 ret = -EBUSY;
1357 goto err_request_region;
1358 }
1359
7560e3f3
SH		 1360 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1361 if (IS_ERR(sdma->clk_ipg)) {
1362 ret = PTR_ERR(sdma->clk_ipg);
1ec1e82f
SH		 1363 goto err_clk;
1364 }
1365
7560e3f3
SH		 1366 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1367 if (IS_ERR(sdma->clk_ahb)) {
1368 ret = PTR_ERR(sdma->clk_ahb);
1369 goto err_clk;
1370 }
1371
1372 clk_prepare(sdma->clk_ipg);
1373 clk_prepare(sdma->clk_ahb);
1374
1ec1e82f
SH		 1375 sdma->regs = ioremap(iores->start, resource_size(iores));
1376 if (!sdma->regs) {
1377 ret = -ENOMEM;
1378 goto err_ioremap;
1379 }
1380
1381 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1382 if (ret)
1383 goto err_request_irq;
1384
5b28aa31 1385 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1c1d9547
AL		 1386 if (!sdma->script_addrs) {
1387 ret = -ENOMEM;
5b28aa31 1388 goto err_alloc;
1c1d9547 1389 }
1ec1e82f 1390
36e2f21a
SH		 1391 /* initially no scripts available */
1392 saddr_arr = (s32 *)sdma->script_addrs;
1393 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1394 saddr_arr[i] = -EINVAL;
1395
7214a8b1
SH		 1396 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1397 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1398
1ec1e82f
SH		 1399 INIT_LIST_HEAD(&sdma->dma_device.channels);
1400 /* Initialize channel parameters */
1401 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1402 struct sdma_channel *sdmac = &sdma->channel[i];
1403
1404 sdmac->sdma = sdma;
1405 spin_lock_init(&sdmac->lock);
1406
1ec1e82f 1407 sdmac->chan.device = &sdma->dma_device;
8ac69546 1408 dma_cookie_init(&sdmac->chan);
1ec1e82f
SH		 1409 sdmac->channel = i;
1410
abd9ccc8
HS		 1411 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1412 (unsigned long) sdmac);
23889c63
SH		 1413 /*
1414 * Add the channel to the DMAC list. Do not add channel 0 though
1415 * because we need it internally in the SDMA driver. This also means
1416 * that channel 0 in dmaengine counting matches sdma channel 1.
1417 */
1418 if (i)
1419 list_add_tail(&sdmac->chan.device_node,
1420 &sdma->dma_device.channels);
1ec1e82f
SH		 1421 }
1422
5b28aa31 1423 ret = sdma_init(sdma);
1ec1e82f
SH		 1424 if (ret)
1425 goto err_init;
1426
580975d7 1427 if (pdata && pdata->script_addrs)
5b28aa31
SH		 1428 sdma_add_scripts(sdma, pdata->script_addrs);
1429
580975d7 1430 if (pdata) {
6d0d7e2d
FE		 1431 ret = sdma_get_firmware(sdma, pdata->fw_name);
1432 if (ret)
ad1122e5 1433 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
580975d7
SG		 1434 } else {
1435 /*
1436 * Because that device tree does not encode ROM script address,
1437 * the RAM script in firmware is mandatory for device tree
1438 * probe, otherwise it fails.
1439 */
1440 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1441 &fw_name);
6602b0dd 1442 if (ret)
ad1122e5 1443 dev_warn(&pdev->dev, "failed to get firmware name\n");
6602b0dd
FE		 1444 else {
1445 ret = sdma_get_firmware(sdma, fw_name);
1446 if (ret)
ad1122e5 1447 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
580975d7
SG		 1448 }
1449 }
5b28aa31 1450
1ec1e82f
SH		 1451 sdma->dma_device.dev = &pdev->dev;
1452
1453 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1454 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1455 sdma->dma_device.device_tx_status = sdma_tx_status;
1456 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1457 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1458 sdma->dma_device.device_control = sdma_control;
1459 sdma->dma_device.device_issue_pending = sdma_issue_pending;
b9b3f82f
SH		 1460 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1461 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1ec1e82f
SH		 1462
1463 ret = dma_async_device_register(&sdma->dma_device);
1464 if (ret) {
1465 dev_err(&pdev->dev, "unable to register\n");
1466 goto err_init;
1467 }
1468
9479e17c
SG		 1469 if (np) {
1470 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1471 if (ret) {
1472 dev_err(&pdev->dev, "failed to register controller\n");
1473 goto err_register;
1474 }
1475 }
1476
5b28aa31 1477 dev_info(sdma->dev, "initialized\n");
1ec1e82f
SH		 1478
1479 return 0;
1480
9479e17c
SG		 1481err_register:
1482 dma_async_device_unregister(&sdma->dma_device);
1ec1e82f
SH		 1483err_init:
1484 kfree(sdma->script_addrs);
5b28aa31 1485err_alloc:
1ec1e82f
SH		 1486 free_irq(irq, sdma);
1487err_request_irq:
1488 iounmap(sdma->regs);
1489err_ioremap:
1ec1e82f
SH		 1490err_clk:
1491 release_mem_region(iores->start, resource_size(iores));
1492err_request_region:
1493err_irq:
1494 kfree(sdma);
939fd4f0 1495 return ret;
1ec1e82f
SH		 1496}
1497
1d1bbd30 1498static int sdma_remove(struct platform_device *pdev)
1ec1e82f
SH		 1499{
1500 return -EBUSY;
1501}
1502
1503static struct platform_driver sdma_driver = {
1504 .driver = {
1505 .name = "imx-sdma",
580975d7 1506 .of_match_table = sdma_dt_ids,
1ec1e82f 1507 },
62550cd7 1508 .id_table = sdma_devtypes,
1d1bbd30 1509 .remove = sdma_remove,
1ec1e82f
SH		 1510};
1511
1512static int __init sdma_module_init(void)
1513{
1514 return platform_driver_probe(&sdma_driver, sdma_probe);
1515}
c989a7fc 1516module_init(sdma_module_init);
1ec1e82f
SH		 1517
1518MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1519MODULE_DESCRIPTION("i.MX SDMA driver");
1520MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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