[deliverable/linux.git] / drivers / dma / ioat / dma.h

/*
 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef IOATDMA_H
#define IOATDMA_H

#include <linux/dmaengine.h>
#include "hw.h"
#include "registers.h"
#include <linux/init.h>
#include <linux/dmapool.h>
#include <linux/cache.h>
#include <linux/pci_ids.h>
#include <net/tcp.h>

#define IOAT_DMA_VERSION  "4.00"

#define IOAT_LOW_COMPLETION_MASK	0xffffffc0
#define IOAT_DMA_DCA_ANY_CPU		~0

#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)

#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)

/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

enum ioat_irq_mode {
	IOAT_NOIRQ = 0,
	IOAT_MSIX,
	IOAT_MSI,
	IOAT_INTX
};

/**
 * struct ioatdma_device - internal representation of a IOAT device
 * @pdev: PCI-Express device
 * @reg_base: MMIO register space base address
 * @dma_pool: for allocating DMA descriptors
 * @common: embedded struct dma_device
 * @version: version of ioatdma device
 * @msix_entries: irq handlers
 * @idx: per channel data
 * @dca: direct cache access context
 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
 * @enumerate_channels: hw version specific channel enumeration
 * @reset_hw: hw version specific channel (re)initialization
 * @cleanup_fn: select between the v2 and v3 cleanup routines
 * @timer_fn: select between the v2 and v3 timer watchdog routines
 * @self_test: hardware version specific self test for each supported op type
 *
 * Note: the v3 cleanup routine supports raid operations
 */
struct ioatdma_device {
	struct pci_dev *pdev;
	void __iomem *reg_base;
	struct pci_pool *dma_pool;
	struct pci_pool *completion_pool;
#define MAX_SED_POOLS	5
	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
	struct dma_device common;
	u8 version;
	struct msix_entry msix_entries[4];
	struct ioat_chan_common *idx[4];
	struct dca_provider *dca;
	enum ioat_irq_mode irq_mode;
	u32 cap;
	void (*intr_quirk)(struct ioatdma_device *device);
	int (*enumerate_channels)(struct ioatdma_device *device);
	int (*reset_hw)(struct ioat_chan_common *chan);
	void (*cleanup_fn)(unsigned long data);
	void (*timer_fn)(unsigned long data);
	int (*self_test)(struct ioatdma_device *device);
};

struct ioat_chan_common {
	struct dma_chan common;
	void __iomem *reg_base;
	dma_addr_t last_completion;
	spinlock_t cleanup_lock;
	unsigned long state;
	#define IOAT_COMPLETION_PENDING 0
	#define IOAT_COMPLETION_ACK 1
	#define IOAT_RESET_PENDING 2
	#define IOAT_KOBJ_INIT_FAIL 3
	#define IOAT_RESHAPE_PENDING 4
	#define IOAT_RUN 5
	#define IOAT_CHAN_ACTIVE 6
	struct timer_list timer;
	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
	#define RESET_DELAY msecs_to_jiffies(100)
	struct ioatdma_device *device;
	dma_addr_t completion_dma;
	u64 *completion;
	struct tasklet_struct cleanup_task;
	struct kobject kobj;
};

struct ioat_sysfs_entry {
	struct attribute attr;
	ssize_t (*show)(struct dma_chan *, char *);
};

/**
 * struct ioat_dma_chan - internal representation of a DMA channel
 */
struct ioat_dma_chan {
	struct ioat_chan_common base;

	size_t xfercap;	/* XFERCAP register value expanded out */

	spinlock_t desc_lock;
	struct list_head free_desc;
	struct list_head used_desc;

	int pending;
	u16 desccount;
	u16 active;
};

/**
 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
 * @hw: hardware SED
 * @sed_dma: dma address for the SED
 * @list: list member
 * @parent: point to the dma descriptor that's the parent
 */
struct ioat_sed_ent {
	struct ioat_sed_raw_descriptor *hw;
	dma_addr_t dma;
	struct ioat_ring_ent *parent;
	unsigned int hw_pool;
};

static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
{
	return container_of(c, struct ioat_chan_common, common);
}

static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
{
	struct ioat_chan_common *chan = to_chan_common(c);

	return container_of(chan, struct ioat_dma_chan, base);
}

/* wrapper around hardware descriptor format + additional software fields */

/**
 * struct ioat_desc_sw - wrapper around hardware descriptor
 * @hw: hardware DMA descriptor (for memcpy)
 * @node: this descriptor will either be on the free list,
 *     or attached to a transaction list (tx_list)
 * @txd: the generic software descriptor for all engines
 * @id: identifier for debug
 */
struct ioat_desc_sw {
	struct ioat_dma_descriptor *hw;
	struct list_head node;
	size_t len;
	struct list_head tx_list;
	struct dma_async_tx_descriptor txd;
	#ifdef DEBUG
	int id;
	#endif
};

#ifdef DEBUG
#define set_desc_id(desc, i) ((desc)->id = (i))
#define desc_id(desc) ((desc)->id)
#else
#define set_desc_id(desc, i)
#define desc_id(desc) (0)
#endif

static inline void
__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
		struct dma_async_tx_descriptor *tx, int id)
{
	struct device *dev = to_dev(chan);

	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
		(unsigned long long) tx->phys,
		(unsigned long long) hw->next, tx->cookie, tx->flags,
		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
}

#define dump_desc_dbg(c, d) \
	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })

static inline struct ioat_chan_common *
ioat_chan_by_index(struct ioatdma_device *device, int index)
{
	return device->idx[index];
}

static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;
	u32 status_lo;

	/* We need to read the low address first as this causes the
	 * chipset to latch the upper bits for the subsequent read
	 */
	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	status <<= 32;
	status |= status_lo;

	return status;
}

#if BITS_PER_LONG == 64

static inline u64 ioat_chansts(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;

	 /* With IOAT v3.3 the status register is 64bit.  */
	if (ver >= IOAT_VER_3_3)
		status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	else
		status = ioat_chansts_32(chan);

	return status;
}

#else
#define ioat_chansts ioat_chansts_32
#endif

static inline void ioat_start(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline u64 ioat_chansts_to_addr(u64 status)
{
	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
}

static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
{
	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
}

static inline void ioat_suspend(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline void ioat_reset(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u8 cmd;

	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
}

static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
{
	struct ioat_chan_common *chan = &ioat->base;

	writel(addr & 0x00000000FFFFFFFF,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	writel(addr >> 32,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
}

static inline bool is_ioat_active(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
}

static inline bool is_ioat_idle(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
}

static inline bool is_ioat_halted(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
}

static inline bool is_ioat_suspended(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
}

/* channel was fatally programmed */
static inline bool is_ioat_bug(unsigned long err)
{
	return !!err;
}

int ioat_probe(struct ioatdma_device *device);
int ioat_register(struct ioatdma_device *device);
int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
int ioat_dma_self_test(struct ioatdma_device *device);
void ioat_dma_remove(struct ioatdma_device *device);
struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
void ioat_init_channel(struct ioatdma_device *device,
		       struct ioat_chan_common *chan, int idx);
enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
				   struct dma_tx_state *txstate);
bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
			   dma_addr_t *phys_complete);
void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
void ioat_kobject_del(struct ioatdma_device *device);
int ioat_dma_setup_interrupts(struct ioatdma_device *device);
void ioat_stop(struct ioat_chan_common *chan);
extern const struct sysfs_ops ioat_sysfs_ops;
extern struct ioat_sysfs_entry ioat_version_attr;
extern struct ioat_sysfs_entry ioat_cap_attr;
#endif /* IOATDMA_H */
Commit	Line	Data
0bbd5f4e	1	/*
211a22ce	2	* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
0bbd5f4e CL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
0bbd5f4e CL	14	* The full GNU General Public License is included in this distribution in the
	15	* file called COPYING.
	16	*/
	17	#ifndef IOATDMA_H
	18	#define IOATDMA_H
	19
	20	#include <linux/dmaengine.h>
584ec227	21	#include "hw.h"
09c8a5b8	22	#include "registers.h"
0bbd5f4e CL	23	#include <linux/init.h>
	24	#include <linux/dmapool.h>
	25	#include <linux/cache.h>
57c651f7	26	#include <linux/pci_ids.h>
16a37aca	27	#include <net/tcp.h>
0bbd5f4e	28
3208ca52	29	#define IOAT_DMA_VERSION "4.00"
5149fd01	30
0bbd5f4e	31	#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
7bb67c14 SN	32	#define IOAT_DMA_DCA_ANY_CPU ~0
7bb67c14 SN	33
1f27adc2 DW	34	#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
1f27adc2 DW	35	#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
bc3c7025 DW	36	#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
bc3c7025 DW	37	#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
3f09ede4	38	#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
1f27adc2 DW	39
	40	#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
	41
1f27adc2 DW	42	/*
	43	* workaround for IOAT ver.3.0 null descriptor issue
	44	* (channel returns error when size is 0)
	45	*/
	46	#define NULL_DESC_BUFFER_SIZE 1
	47
8a52b9ff DJ	48	enum ioat_irq_mode {
	49	IOAT_NOIRQ = 0,
	50	IOAT_MSIX,
8a52b9ff DJ	51	IOAT_MSI,
	52	IOAT_INTX
	53	};
	54
0bbd5f4e	55	/**
8ab89567	56	* struct ioatdma_device - internal representation of a IOAT device
0bbd5f4e CL	57	* @pdev: PCI-Express device
	58	* @reg_base: MMIO register space base address
	59	* @dma_pool: for allocating DMA descriptors
	60	* @common: embedded struct dma_device
8ab89567	61	* @version: version of ioatdma device
7bb67c14 SN	62	* @msix_entries: irq handlers
7bb67c14 SN	63	* @idx: per channel data
f2427e27 DW	64	* @dca: direct cache access context
f2427e27 DW	65	* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
5cbafa65	66	* @enumerate_channels: hw version specific channel enumeration
a6d52d70	67	* @reset_hw: hw version specific channel (re)initialization
aa4d72ae	68	* @cleanup_fn: select between the v2 and v3 cleanup routines
bf40a686	69	* @timer_fn: select between the v2 and v3 timer watchdog routines
9de6fc71	70	* @self_test: hardware version specific self test for each supported op type
bf40a686 DW	71	*
bf40a686 DW	72	* Note: the v3 cleanup routine supports raid operations
0bbd5f4e	73	*/
8ab89567	74	struct ioatdma_device {
0bbd5f4e	75	struct pci_dev *pdev;
47b16539	76	void __iomem *reg_base;
0bbd5f4e CL	77	struct pci_pool *dma_pool;
0bbd5f4e CL	78	struct pci_pool *completion_pool;
7727eaa4 DJ	79	#define MAX_SED_POOLS 5
7727eaa4 DJ	80	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
0bbd5f4e	81	struct dma_device common;
8ab89567	82	u8 version;
3e037454	83	struct msix_entry msix_entries[4];
dcbc853a	84	struct ioat_chan_common *idx[4];
f2427e27	85	struct dca_provider *dca;
8a52b9ff	86	enum ioat_irq_mode irq_mode;
75c6f0ab	87	u32 cap;
f2427e27	88	void (intr_quirk)(struct ioatdma_device device);
5cbafa65	89	int (enumerate_channels)(struct ioatdma_device device);
a6d52d70	90	int (reset_hw)(struct ioat_chan_common chan);
aa4d72ae	91	void (*cleanup_fn)(unsigned long data);
bf40a686	92	void (*timer_fn)(unsigned long data);
9de6fc71	93	int (self_test)(struct ioatdma_device device);
0bbd5f4e CL	94	};
0bbd5f4e CL	95
dcbc853a	96	struct ioat_chan_common {
09c8a5b8	97	struct dma_chan common;
47b16539	98	void __iomem *reg_base;
27502935	99	dma_addr_t last_completion;
0bbd5f4e	100	spinlock_t cleanup_lock;
09c8a5b8 DW	101	unsigned long state;
	102	#define IOAT_COMPLETION_PENDING 0
	103	#define IOAT_COMPLETION_ACK 1
	104	#define IOAT_RESET_PENDING 2
5669e31c	105	#define IOAT_KOBJ_INIT_FAIL 3
074cc476	106	#define IOAT_RESHAPE_PENDING 4
556ab45f	107	#define IOAT_RUN 5
4dec23d7	108	#define IOAT_CHAN_ACTIVE 6
09c8a5b8 DW	109	struct timer_list timer;
09c8a5b8 DW	110	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
a309218a	111	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
09c8a5b8	112	#define RESET_DELAY msecs_to_jiffies(100)
8ab89567	113	struct ioatdma_device *device;
4fb9b9e8 DW	114	dma_addr_t completion_dma;
4fb9b9e8 DW	115	u64 *completion;
3e037454	116	struct tasklet_struct cleanup_task;
5669e31c	117	struct kobject kobj;
0bbd5f4e CL	118	};
0bbd5f4e CL	119
5669e31c DW	120	struct ioat_sysfs_entry {
	121	struct attribute attr;
	122	ssize_t (show)(struct dma_chan , char *);
	123	};
5cbafa65	124
dcbc853a DW	125	/**
	126	* struct ioat_dma_chan - internal representation of a DMA channel
	127	*/
	128	struct ioat_dma_chan {
	129	struct ioat_chan_common base;
	130
	131	size_t xfercap; /* XFERCAP register value expanded out */
	132
	133	spinlock_t desc_lock;
	134	struct list_head free_desc;
	135	struct list_head used_desc;
	136
	137	int pending;
dcbc853a	138	u16 desccount;
5669e31c	139	u16 active;
dcbc853a DW	140	};
dcbc853a DW	141
7727eaa4 DJ	142	/**
	143	* struct ioat_sed_ent - wrapper around super extended hardware descriptor
	144	* @hw: hardware SED
	145	* @sed_dma: dma address for the SED
	146	* @list: list member
	147	* @parent: point to the dma descriptor that's the parent
	148	*/
	149	struct ioat_sed_ent {
	150	struct ioat_sed_raw_descriptor *hw;
	151	dma_addr_t dma;
	152	struct ioat_ring_ent *parent;
	153	unsigned int hw_pool;
	154	};
	155
dcbc853a DW	156	static inline struct ioat_chan_common to_chan_common(struct dma_chan c)
	157	{
	158	return container_of(c, struct ioat_chan_common, common);
	159	}
	160
	161	static inline struct ioat_dma_chan to_ioat_chan(struct dma_chan c)
	162	{
	163	struct ioat_chan_common *chan = to_chan_common(c);
	164
	165	return container_of(chan, struct ioat_dma_chan, base);
	166	}
	167
0bbd5f4e CL	168	/* wrapper around hardware descriptor format + additional software fields */
	169
	170	/**
	171	* struct ioat_desc_sw - wrapper around hardware descriptor
2aec048c	172	* @hw: hardware DMA descriptor (for memcpy)
7405f74b	173	* @node: this descriptor will either be on the free list,
ea25968a	174	* or attached to a transaction list (tx_list)
bc3c7025	175	* @txd: the generic software descriptor for all engines
6df9183a	176	* @id: identifier for debug
0bbd5f4e	177	*/
0bbd5f4e CL	178	struct ioat_desc_sw {
	179	struct ioat_dma_descriptor *hw;
	180	struct list_head node;
7f2b291f	181	size_t len;
ea25968a	182	struct list_head tx_list;
bc3c7025	183	struct dma_async_tx_descriptor txd;
6df9183a DW	184	#ifdef DEBUG
	185	int id;
	186	#endif
0bbd5f4e CL	187	};
0bbd5f4e CL	188
6df9183a DW	189	#ifdef DEBUG
	190	#define set_desc_id(desc, i) ((desc)->id = (i))
	191	#define desc_id(desc) ((desc)->id)
	192	#else
	193	#define set_desc_id(desc, i)
	194	#define desc_id(desc) (0)
	195	#endif
	196
	197	static inline void
	198	__dump_desc_dbg(struct ioat_chan_common chan, struct ioat_dma_descriptor hw,
	199	struct dma_async_tx_descriptor *tx, int id)
	200	{
	201	struct device *dev = to_dev(chan);
	202
	203	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
50f9f97e	204	" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
6df9183a DW	205	(unsigned long long) tx->phys,
	206	(unsigned long long) hw->next, tx->cookie, tx->flags,
	207	hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
	208	}
	209
	210	#define dump_desc_dbg(c, d) \
	211	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
	212
5cbafa65 DW	213	static inline struct ioat_chan_common *
	214	ioat_chan_by_index(struct ioatdma_device *device, int index)
	215	{
	216	return device->idx[index];
	217	}
	218
d92a8d7c	219	static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
09c8a5b8 DW	220	{
	221	u8 ver = chan->device->version;
	222	u64 status;
	223	u32 status_lo;
	224
	225	/* We need to read the low address first as this causes the
	226	* chipset to latch the upper bits for the subsequent read
	227	*/
	228	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	229	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	230	status <<= 32;
	231	status \|= status_lo;
	232
	233	return status;
	234	}
	235
d92a8d7c DJ	236	#if BITS_PER_LONG == 64
	237
	238	static inline u64 ioat_chansts(struct ioat_chan_common *chan)
	239	{
	240	u8 ver = chan->device->version;
	241	u64 status;
	242
	243	/* With IOAT v3.3 the status register is 64bit. */
	244	if (ver >= IOAT_VER_3_3)
	245	status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	246	else
	247	status = ioat_chansts_32(chan);
	248
	249	return status;
	250	}
	251
	252	#else
	253	#define ioat_chansts ioat_chansts_32
	254	#endif
	255
09c8a5b8 DW	256	static inline void ioat_start(struct ioat_chan_common *chan)
	257	{
	258	u8 ver = chan->device->version;
	259
	260	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	261	}
	262
	263	static inline u64 ioat_chansts_to_addr(u64 status)
	264	{
	265	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
	266	}
	267
	268	static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
	269	{
	270	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
	271	}
	272
	273	static inline void ioat_suspend(struct ioat_chan_common *chan)
	274	{
	275	u8 ver = chan->device->version;
	276
	277	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	278	}
	279
a6d52d70 DW	280	static inline void ioat_reset(struct ioat_chan_common *chan)
	281	{
	282	u8 ver = chan->device->version;
	283
	284	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	285	}
	286
	287	static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
	288	{
	289	u8 ver = chan->device->version;
	290	u8 cmd;
	291
	292	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	293	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
	294	}
	295
09c8a5b8 DW	296	static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
	297	{
	298	struct ioat_chan_common *chan = &ioat->base;
	299
	300	writel(addr & 0x00000000FFFFFFFF,
	301	chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	302	writel(addr >> 32,
	303	chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
	304	}
	305
	306	static inline bool is_ioat_active(unsigned long status)
	307	{
	308	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
	309	}
	310
	311	static inline bool is_ioat_idle(unsigned long status)
	312	{
	313	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
	314	}
	315
	316	static inline bool is_ioat_halted(unsigned long status)
	317	{
	318	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
	319	}
	320
	321	static inline bool is_ioat_suspended(unsigned long status)
	322	{
	323	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
	324	}
	325
	326	/* channel was fatally programmed */
	327	static inline bool is_ioat_bug(unsigned long err)
	328	{
b57014de	329	return !!err;
09c8a5b8 DW	330	}
09c8a5b8 DW	331
4bf27b8b GKH	332	int ioat_probe(struct ioatdma_device *device);
	333	int ioat_register(struct ioatdma_device *device);
	334	int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
	335	int ioat_dma_self_test(struct ioatdma_device *device);
	336	void ioat_dma_remove(struct ioatdma_device *device);
	337	struct dca_provider ioat_dca_init(struct pci_dev pdev, void __iomem *iobase);
27502935	338	dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
5cbafa65	339	void ioat_init_channel(struct ioatdma_device *device,
aa4d72ae	340	struct ioat_chan_common *chan, int idx);
07934481 LW	341	enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
07934481 LW	342	struct dma_tx_state *txstate);
09c8a5b8	343	bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
27502935	344	dma_addr_t *phys_complete);
5669e31c DW	345	void ioat_kobject_add(struct ioatdma_device device, struct kobj_type type);
5669e31c DW	346	void ioat_kobject_del(struct ioatdma_device *device);
8a52b9ff	347	int ioat_dma_setup_interrupts(struct ioatdma_device *device);
da87ca4d	348	void ioat_stop(struct ioat_chan_common *chan);
52cf25d0	349	extern const struct sysfs_ops ioat_sysfs_ops;
5669e31c DW	350	extern struct ioat_sysfs_entry ioat_version_attr;
5669e31c DW	351	extern struct ioat_sysfs_entry ioat_cap_attr;
0bbd5f4e	352	#endif /* IOATDMA_H */