[deliverable/linux.git] / drivers / dma / ioat / dma.h

/*
 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef IOATDMA_H
#define IOATDMA_H

#include <linux/dmaengine.h>
#include "hw.h"
#include "registers.h"
#include <linux/init.h>
#include <linux/dmapool.h>
#include <linux/cache.h>
#include <linux/pci_ids.h>
#include <net/tcp.h>

#define IOAT_DMA_VERSION  "4.00"

#define IOAT_LOW_COMPLETION_MASK	0xffffffc0
#define IOAT_DMA_DCA_ANY_CPU		~0

#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)

#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)

/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

enum ioat_irq_mode {
	IOAT_NOIRQ = 0,
	IOAT_MSIX,
	IOAT_MSIX_SINGLE,
	IOAT_MSI,
	IOAT_INTX
};

/**
 * struct ioatdma_device - internal representation of a IOAT device
 * @pdev: PCI-Express device
 * @reg_base: MMIO register space base address
 * @dma_pool: for allocating DMA descriptors
 * @common: embedded struct dma_device
 * @version: version of ioatdma device
 * @msix_entries: irq handlers
 * @idx: per channel data
 * @dca: direct cache access context
 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
 * @enumerate_channels: hw version specific channel enumeration
 * @reset_hw: hw version specific channel (re)initialization
 * @cleanup_fn: select between the v2 and v3 cleanup routines
 * @timer_fn: select between the v2 and v3 timer watchdog routines
 * @self_test: hardware version specific self test for each supported op type
 *
 * Note: the v3 cleanup routine supports raid operations
 */
struct ioatdma_device {
	struct pci_dev *pdev;
	void __iomem *reg_base;
	struct pci_pool *dma_pool;
	struct pci_pool *completion_pool;
#define MAX_SED_POOLS	5
	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
	struct kmem_cache *sed_pool;
	struct dma_device common;
	u8 version;
	struct msix_entry msix_entries[4];
	struct ioat_chan_common *idx[4];
	struct dca_provider *dca;
	enum ioat_irq_mode irq_mode;
	u32 cap;
	void (*intr_quirk)(struct ioatdma_device *device);
	int (*enumerate_channels)(struct ioatdma_device *device);
	int (*reset_hw)(struct ioat_chan_common *chan);
	void (*cleanup_fn)(unsigned long data);
	void (*timer_fn)(unsigned long data);
	int (*self_test)(struct ioatdma_device *device);
};

struct ioat_chan_common {
	struct dma_chan common;
	void __iomem *reg_base;
	dma_addr_t last_completion;
	spinlock_t cleanup_lock;
	unsigned long state;
	#define IOAT_COMPLETION_PENDING 0
	#define IOAT_COMPLETION_ACK 1
	#define IOAT_RESET_PENDING 2
	#define IOAT_KOBJ_INIT_FAIL 3
	#define IOAT_RESHAPE_PENDING 4
	#define IOAT_RUN 5
	#define IOAT_CHAN_ACTIVE 6
	struct timer_list timer;
	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
	#define RESET_DELAY msecs_to_jiffies(100)
	struct ioatdma_device *device;
	dma_addr_t completion_dma;
	u64 *completion;
	struct tasklet_struct cleanup_task;
	struct kobject kobj;
};

struct ioat_sysfs_entry {
	struct attribute attr;
	ssize_t (*show)(struct dma_chan *, char *);
};

/**
 * struct ioat_dma_chan - internal representation of a DMA channel
 */
struct ioat_dma_chan {
	struct ioat_chan_common base;

	size_t xfercap;	/* XFERCAP register value expanded out */

	spinlock_t desc_lock;
	struct list_head free_desc;
	struct list_head used_desc;

	int pending;
	u16 desccount;
	u16 active;
};

/**
 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
 * @hw: hardware SED
 * @sed_dma: dma address for the SED
 * @list: list member
 * @parent: point to the dma descriptor that's the parent
 */
struct ioat_sed_ent {
	struct ioat_sed_raw_descriptor *hw;
	dma_addr_t dma;
	struct ioat_ring_ent *parent;
	unsigned int hw_pool;
};

static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
{
	return container_of(c, struct ioat_chan_common, common);
}

static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
{
	struct ioat_chan_common *chan = to_chan_common(c);

	return container_of(chan, struct ioat_dma_chan, base);
}

/* wrapper around hardware descriptor format + additional software fields */

/**
 * struct ioat_desc_sw - wrapper around hardware descriptor
 * @hw: hardware DMA descriptor (for memcpy)
 * @node: this descriptor will either be on the free list,
 *     or attached to a transaction list (tx_list)
 * @txd: the generic software descriptor for all engines
 * @id: identifier for debug
 */
struct ioat_desc_sw {
	struct ioat_dma_descriptor *hw;
	struct list_head node;
	size_t len;
	struct list_head tx_list;
	struct dma_async_tx_descriptor txd;
	#ifdef DEBUG
	int id;
	#endif
};

#ifdef DEBUG
#define set_desc_id(desc, i) ((desc)->id = (i))
#define desc_id(desc) ((desc)->id)
#else
#define set_desc_id(desc, i)
#define desc_id(desc) (0)
#endif

static inline void
__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
		struct dma_async_tx_descriptor *tx, int id)
{
	struct device *dev = to_dev(chan);

	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
		(unsigned long long) tx->phys,
		(unsigned long long) hw->next, tx->cookie, tx->flags,
		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
}

#define dump_desc_dbg(c, d) \
	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })

static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
{
	#ifdef CONFIG_NET_DMA
	sysctl_tcp_dma_copybreak = copybreak;
	#endif
}

static inline struct ioat_chan_common *
ioat_chan_by_index(struct ioatdma_device *device, int index)
{
	return device->idx[index];
}

static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;
	u32 status_lo;

	/* We need to read the low address first as this causes the
	 * chipset to latch the upper bits for the subsequent read
	 */
	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	status <<= 32;
	status |= status_lo;

	return status;
}

#if BITS_PER_LONG == 64

static inline u64 ioat_chansts(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;

	 /* With IOAT v3.3 the status register is 64bit.  */
	if (ver >= IOAT_VER_3_3)
		status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	else
		status = ioat_chansts_32(chan);

	return status;
}

#else
#define ioat_chansts ioat_chansts_32
#endif

static inline void ioat_start(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline u64 ioat_chansts_to_addr(u64 status)
{
	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
}

static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
{
	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
}

static inline void ioat_suspend(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline void ioat_reset(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u8 cmd;

	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
}

static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
{
	struct ioat_chan_common *chan = &ioat->base;

	writel(addr & 0x00000000FFFFFFFF,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	writel(addr >> 32,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
}

static inline bool is_ioat_active(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
}

static inline bool is_ioat_idle(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
}

static inline bool is_ioat_halted(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
}

static inline bool is_ioat_suspended(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
}

/* channel was fatally programmed */
static inline bool is_ioat_bug(unsigned long err)
{
	return !!err;
}

static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
			      int direction, enum dma_ctrl_flags flags, bool dst)
{
	if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
	    (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
		pci_unmap_single(pdev, addr, len, direction);
	else
		pci_unmap_page(pdev, addr, len, direction);
}

int ioat_probe(struct ioatdma_device *device);
int ioat_register(struct ioatdma_device *device);
int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
int ioat_dma_self_test(struct ioatdma_device *device);
void ioat_dma_remove(struct ioatdma_device *device);
struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
void ioat_init_channel(struct ioatdma_device *device,
		       struct ioat_chan_common *chan, int idx);
enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
				   struct dma_tx_state *txstate);
void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
		    size_t len, struct ioat_dma_descriptor *hw);
bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
			   dma_addr_t *phys_complete);
void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
void ioat_kobject_del(struct ioatdma_device *device);
int ioat_dma_setup_interrupts(struct ioatdma_device *device);
extern const struct sysfs_ops ioat_sysfs_ops;
extern struct ioat_sysfs_entry ioat_version_attr;
extern struct ioat_sysfs_entry ioat_cap_attr;
#endif /* IOATDMA_H */
Commit	Line	Data
0bbd5f4e	1	/*
211a22ce	2	* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
0bbd5f4e CL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef IOATDMA_H
	22	#define IOATDMA_H
	23
	24	#include <linux/dmaengine.h>
584ec227	25	#include "hw.h"
09c8a5b8	26	#include "registers.h"
0bbd5f4e CL	27	#include <linux/init.h>
	28	#include <linux/dmapool.h>
	29	#include <linux/cache.h>
57c651f7	30	#include <linux/pci_ids.h>
16a37aca	31	#include <net/tcp.h>
0bbd5f4e	32
3208ca52	33	#define IOAT_DMA_VERSION "4.00"
5149fd01	34
0bbd5f4e	35	#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
7bb67c14 SN	36	#define IOAT_DMA_DCA_ANY_CPU ~0
7bb67c14 SN	37
1f27adc2 DW	38	#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
1f27adc2 DW	39	#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
bc3c7025 DW	40	#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
bc3c7025 DW	41	#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
3f09ede4	42	#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
1f27adc2 DW	43
	44	#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
	45
1f27adc2 DW	46	/*
	47	* workaround for IOAT ver.3.0 null descriptor issue
	48	* (channel returns error when size is 0)
	49	*/
	50	#define NULL_DESC_BUFFER_SIZE 1
	51
8a52b9ff DJ	52	enum ioat_irq_mode {
	53	IOAT_NOIRQ = 0,
	54	IOAT_MSIX,
	55	IOAT_MSIX_SINGLE,
	56	IOAT_MSI,
	57	IOAT_INTX
	58	};
	59
0bbd5f4e	60	/**
8ab89567	61	* struct ioatdma_device - internal representation of a IOAT device
0bbd5f4e CL	62	* @pdev: PCI-Express device
	63	* @reg_base: MMIO register space base address
	64	* @dma_pool: for allocating DMA descriptors
	65	* @common: embedded struct dma_device
8ab89567	66	* @version: version of ioatdma device
7bb67c14 SN	67	* @msix_entries: irq handlers
7bb67c14 SN	68	* @idx: per channel data
f2427e27 DW	69	* @dca: direct cache access context
f2427e27 DW	70	* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
5cbafa65	71	* @enumerate_channels: hw version specific channel enumeration
a6d52d70	72	* @reset_hw: hw version specific channel (re)initialization
aa4d72ae	73	* @cleanup_fn: select between the v2 and v3 cleanup routines
bf40a686	74	* @timer_fn: select between the v2 and v3 timer watchdog routines
9de6fc71	75	* @self_test: hardware version specific self test for each supported op type
bf40a686 DW	76	*
bf40a686 DW	77	* Note: the v3 cleanup routine supports raid operations
0bbd5f4e	78	*/
8ab89567	79	struct ioatdma_device {
0bbd5f4e	80	struct pci_dev *pdev;
47b16539	81	void __iomem *reg_base;
0bbd5f4e CL	82	struct pci_pool *dma_pool;
0bbd5f4e CL	83	struct pci_pool *completion_pool;
7727eaa4 DJ	84	#define MAX_SED_POOLS 5
	85	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
	86	struct kmem_cache *sed_pool;
0bbd5f4e	87	struct dma_device common;
8ab89567	88	u8 version;
3e037454	89	struct msix_entry msix_entries[4];
dcbc853a	90	struct ioat_chan_common *idx[4];
f2427e27	91	struct dca_provider *dca;
8a52b9ff	92	enum ioat_irq_mode irq_mode;
75c6f0ab	93	u32 cap;
f2427e27	94	void (intr_quirk)(struct ioatdma_device device);
5cbafa65	95	int (enumerate_channels)(struct ioatdma_device device);
a6d52d70	96	int (reset_hw)(struct ioat_chan_common chan);
aa4d72ae	97	void (*cleanup_fn)(unsigned long data);
bf40a686	98	void (*timer_fn)(unsigned long data);
9de6fc71	99	int (self_test)(struct ioatdma_device device);
0bbd5f4e CL	100	};
0bbd5f4e CL	101
dcbc853a	102	struct ioat_chan_common {
09c8a5b8	103	struct dma_chan common;
47b16539	104	void __iomem *reg_base;
27502935	105	dma_addr_t last_completion;
0bbd5f4e	106	spinlock_t cleanup_lock;
09c8a5b8 DW	107	unsigned long state;
	108	#define IOAT_COMPLETION_PENDING 0
	109	#define IOAT_COMPLETION_ACK 1
	110	#define IOAT_RESET_PENDING 2
5669e31c	111	#define IOAT_KOBJ_INIT_FAIL 3
074cc476	112	#define IOAT_RESHAPE_PENDING 4
556ab45f	113	#define IOAT_RUN 5
4dec23d7	114	#define IOAT_CHAN_ACTIVE 6
09c8a5b8 DW	115	struct timer_list timer;
09c8a5b8 DW	116	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
a309218a	117	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
09c8a5b8	118	#define RESET_DELAY msecs_to_jiffies(100)
8ab89567	119	struct ioatdma_device *device;
4fb9b9e8 DW	120	dma_addr_t completion_dma;
4fb9b9e8 DW	121	u64 *completion;
3e037454	122	struct tasklet_struct cleanup_task;
5669e31c	123	struct kobject kobj;
0bbd5f4e CL	124	};
0bbd5f4e CL	125
5669e31c DW	126	struct ioat_sysfs_entry {
	127	struct attribute attr;
	128	ssize_t (show)(struct dma_chan , char *);
	129	};
5cbafa65	130
dcbc853a DW	131	/**
	132	* struct ioat_dma_chan - internal representation of a DMA channel
	133	*/
	134	struct ioat_dma_chan {
	135	struct ioat_chan_common base;
	136
	137	size_t xfercap; /* XFERCAP register value expanded out */
	138
	139	spinlock_t desc_lock;
	140	struct list_head free_desc;
	141	struct list_head used_desc;
	142
	143	int pending;
dcbc853a	144	u16 desccount;
5669e31c	145	u16 active;
dcbc853a DW	146	};
dcbc853a DW	147
7727eaa4 DJ	148	/**
	149	* struct ioat_sed_ent - wrapper around super extended hardware descriptor
	150	* @hw: hardware SED
	151	* @sed_dma: dma address for the SED
	152	* @list: list member
	153	* @parent: point to the dma descriptor that's the parent
	154	*/
	155	struct ioat_sed_ent {
	156	struct ioat_sed_raw_descriptor *hw;
	157	dma_addr_t dma;
	158	struct ioat_ring_ent *parent;
	159	unsigned int hw_pool;
	160	};
	161
dcbc853a DW	162	static inline struct ioat_chan_common to_chan_common(struct dma_chan c)
	163	{
	164	return container_of(c, struct ioat_chan_common, common);
	165	}
	166
	167	static inline struct ioat_dma_chan to_ioat_chan(struct dma_chan c)
	168	{
	169	struct ioat_chan_common *chan = to_chan_common(c);
	170
	171	return container_of(chan, struct ioat_dma_chan, base);
	172	}
	173
0bbd5f4e CL	174	/* wrapper around hardware descriptor format + additional software fields */
	175
	176	/**
	177	* struct ioat_desc_sw - wrapper around hardware descriptor
2aec048c	178	* @hw: hardware DMA descriptor (for memcpy)
7405f74b	179	* @node: this descriptor will either be on the free list,
ea25968a	180	* or attached to a transaction list (tx_list)
bc3c7025	181	* @txd: the generic software descriptor for all engines
6df9183a	182	* @id: identifier for debug
0bbd5f4e	183	*/
0bbd5f4e CL	184	struct ioat_desc_sw {
	185	struct ioat_dma_descriptor *hw;
	186	struct list_head node;
7f2b291f	187	size_t len;
ea25968a	188	struct list_head tx_list;
bc3c7025	189	struct dma_async_tx_descriptor txd;
6df9183a DW	190	#ifdef DEBUG
	191	int id;
	192	#endif
0bbd5f4e CL	193	};
0bbd5f4e CL	194
6df9183a DW	195	#ifdef DEBUG
	196	#define set_desc_id(desc, i) ((desc)->id = (i))
	197	#define desc_id(desc) ((desc)->id)
	198	#else
	199	#define set_desc_id(desc, i)
	200	#define desc_id(desc) (0)
	201	#endif
	202
	203	static inline void
	204	__dump_desc_dbg(struct ioat_chan_common chan, struct ioat_dma_descriptor hw,
	205	struct dma_async_tx_descriptor *tx, int id)
	206	{
	207	struct device *dev = to_dev(chan);
	208
	209	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
50f9f97e	210	" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
6df9183a DW	211	(unsigned long long) tx->phys,
	212	(unsigned long long) hw->next, tx->cookie, tx->flags,
	213	hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
	214	}
	215
	216	#define dump_desc_dbg(c, d) \
	217	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
	218
f2427e27	219	static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
16a37aca MS	220	{
16a37aca MS	221	#ifdef CONFIG_NET_DMA
f2427e27	222	sysctl_tcp_dma_copybreak = copybreak;
16a37aca MS	223	#endif
	224	}
	225
5cbafa65 DW	226	static inline struct ioat_chan_common *
	227	ioat_chan_by_index(struct ioatdma_device *device, int index)
	228	{
	229	return device->idx[index];
	230	}
	231
d92a8d7c	232	static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
09c8a5b8 DW	233	{
	234	u8 ver = chan->device->version;
	235	u64 status;
	236	u32 status_lo;
	237
	238	/* We need to read the low address first as this causes the
	239	* chipset to latch the upper bits for the subsequent read
	240	*/
	241	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	242	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	243	status <<= 32;
	244	status \|= status_lo;
	245
	246	return status;
	247	}
	248
d92a8d7c DJ	249	#if BITS_PER_LONG == 64
	250
	251	static inline u64 ioat_chansts(struct ioat_chan_common *chan)
	252	{
	253	u8 ver = chan->device->version;
	254	u64 status;
	255
	256	/* With IOAT v3.3 the status register is 64bit. */
	257	if (ver >= IOAT_VER_3_3)
	258	status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	259	else
	260	status = ioat_chansts_32(chan);
	261
	262	return status;
	263	}
	264
	265	#else
	266	#define ioat_chansts ioat_chansts_32
	267	#endif
	268
09c8a5b8 DW	269	static inline void ioat_start(struct ioat_chan_common *chan)
	270	{
	271	u8 ver = chan->device->version;
	272
	273	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	274	}
	275
	276	static inline u64 ioat_chansts_to_addr(u64 status)
	277	{
	278	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
	279	}
	280
	281	static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
	282	{
	283	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
	284	}
	285
	286	static inline void ioat_suspend(struct ioat_chan_common *chan)
	287	{
	288	u8 ver = chan->device->version;
	289
	290	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	291	}
	292
a6d52d70 DW	293	static inline void ioat_reset(struct ioat_chan_common *chan)
	294	{
	295	u8 ver = chan->device->version;
	296
	297	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	298	}
	299
	300	static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
	301	{
	302	u8 ver = chan->device->version;
	303	u8 cmd;
	304
	305	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	306	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
	307	}
	308
09c8a5b8 DW	309	static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
	310	{
	311	struct ioat_chan_common *chan = &ioat->base;
	312
	313	writel(addr & 0x00000000FFFFFFFF,
	314	chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	315	writel(addr >> 32,
	316	chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
	317	}
	318
	319	static inline bool is_ioat_active(unsigned long status)
	320	{
	321	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
	322	}
	323
	324	static inline bool is_ioat_idle(unsigned long status)
	325	{
	326	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
	327	}
	328
	329	static inline bool is_ioat_halted(unsigned long status)
	330	{
	331	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
	332	}
	333
	334	static inline bool is_ioat_suspended(unsigned long status)
	335	{
	336	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
	337	}
	338
	339	/* channel was fatally programmed */
	340	static inline bool is_ioat_bug(unsigned long err)
	341	{
b57014de	342	return !!err;
09c8a5b8 DW	343	}
09c8a5b8 DW	344
bf40a686 DW	345	static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
	346	int direction, enum dma_ctrl_flags flags, bool dst)
	347	{
	348	if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) \|\|
	349	(!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
	350	pci_unmap_single(pdev, addr, len, direction);
	351	else
	352	pci_unmap_page(pdev, addr, len, direction);
	353	}
	354
4bf27b8b GKH	355	int ioat_probe(struct ioatdma_device *device);
	356	int ioat_register(struct ioatdma_device *device);
	357	int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
	358	int ioat_dma_self_test(struct ioatdma_device *device);
	359	void ioat_dma_remove(struct ioatdma_device *device);
	360	struct dca_provider ioat_dca_init(struct pci_dev pdev, void __iomem *iobase);
27502935	361	dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
5cbafa65	362	void ioat_init_channel(struct ioatdma_device *device,
aa4d72ae	363	struct ioat_chan_common *chan, int idx);
07934481 LW	364	enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
07934481 LW	365	struct dma_tx_state *txstate);
5cbafa65 DW	366	void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
5cbafa65 DW	367	size_t len, struct ioat_dma_descriptor *hw);
09c8a5b8	368	bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
27502935	369	dma_addr_t *phys_complete);
5669e31c DW	370	void ioat_kobject_add(struct ioatdma_device device, struct kobj_type type);
5669e31c DW	371	void ioat_kobject_del(struct ioatdma_device *device);
8a52b9ff	372	int ioat_dma_setup_interrupts(struct ioatdma_device *device);
52cf25d0	373	extern const struct sysfs_ops ioat_sysfs_ops;
5669e31c DW	374	extern struct ioat_sysfs_entry ioat_version_attr;
5669e31c DW	375	extern struct ioat_sysfs_entry ioat_cap_attr;
0bbd5f4e	376	#endif /* IOATDMA_H */