[deliverable/linux.git] / drivers / dma / ioat / dma.h

/*
 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef IOATDMA_H
#define IOATDMA_H

#include <linux/dmaengine.h>
#include "hw.h"
#include "registers.h"
#include <linux/init.h>
#include <linux/dmapool.h>
#include <linux/cache.h>
#include <linux/pci_ids.h>
#include <net/tcp.h>

#define IOAT_DMA_VERSION  "4.00"

#define IOAT_LOW_COMPLETION_MASK	0xffffffc0
#define IOAT_DMA_DCA_ANY_CPU		~0

#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)

#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)

/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

enum ioat_irq_mode {
	IOAT_NOIRQ = 0,
	IOAT_MSIX,
	IOAT_MSI,
	IOAT_INTX
};

/**
 * struct ioatdma_device - internal representation of a IOAT device
 * @pdev: PCI-Express device
 * @reg_base: MMIO register space base address
 * @dma_pool: for allocating DMA descriptors
 * @common: embedded struct dma_device
 * @version: version of ioatdma device
 * @msix_entries: irq handlers
 * @idx: per channel data
 * @dca: direct cache access context
 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
 * @enumerate_channels: hw version specific channel enumeration
 * @reset_hw: hw version specific channel (re)initialization
 * @cleanup_fn: select between the v2 and v3 cleanup routines
 * @timer_fn: select between the v2 and v3 timer watchdog routines
 * @self_test: hardware version specific self test for each supported op type
 *
 * Note: the v3 cleanup routine supports raid operations
 */
struct ioatdma_device {
	struct pci_dev *pdev;
	void __iomem *reg_base;
	struct pci_pool *dma_pool;
	struct pci_pool *completion_pool;
#define MAX_SED_POOLS	5
	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
	struct dma_device common;
	u8 version;
	struct msix_entry msix_entries[4];
	struct ioat_chan_common *idx[4];
	struct dca_provider *dca;
	enum ioat_irq_mode irq_mode;
	u32 cap;
	void (*intr_quirk)(struct ioatdma_device *device);
	int (*enumerate_channels)(struct ioatdma_device *device);
	int (*reset_hw)(struct ioat_chan_common *chan);
	void (*cleanup_fn)(unsigned long data);
	void (*timer_fn)(unsigned long data);
	int (*self_test)(struct ioatdma_device *device);
};

struct ioat_chan_common {
	struct dma_chan common;
	void __iomem *reg_base;
	dma_addr_t last_completion;
	spinlock_t cleanup_lock;
	unsigned long state;
	#define IOAT_COMPLETION_PENDING 0
	#define IOAT_COMPLETION_ACK 1
	#define IOAT_RESET_PENDING 2
	#define IOAT_KOBJ_INIT_FAIL 3
	#define IOAT_RESHAPE_PENDING 4
	#define IOAT_RUN 5
	#define IOAT_CHAN_ACTIVE 6
	struct timer_list timer;
	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
	#define RESET_DELAY msecs_to_jiffies(100)
	struct ioatdma_device *device;
	dma_addr_t completion_dma;
	u64 *completion;
	struct tasklet_struct cleanup_task;
	struct kobject kobj;
};

struct ioat_sysfs_entry {
	struct attribute attr;
	ssize_t (*show)(struct dma_chan *, char *);
};

/**
 * struct ioat_dma_chan - internal representation of a DMA channel
 */
struct ioat_dma_chan {
	struct ioat_chan_common base;

	size_t xfercap;	/* XFERCAP register value expanded out */

	spinlock_t desc_lock;
	struct list_head free_desc;
	struct list_head used_desc;

	int pending;
	u16 desccount;
	u16 active;
};

/**
 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
 * @hw: hardware SED
 * @sed_dma: dma address for the SED
 * @list: list member
 * @parent: point to the dma descriptor that's the parent
 */
struct ioat_sed_ent {
	struct ioat_sed_raw_descriptor *hw;
	dma_addr_t dma;
	struct ioat_ring_ent *parent;
	unsigned int hw_pool;
};

static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
{
	return container_of(c, struct ioat_chan_common, common);
}

static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
{
	struct ioat_chan_common *chan = to_chan_common(c);

	return container_of(chan, struct ioat_dma_chan, base);
}

/* wrapper around hardware descriptor format + additional software fields */

/**
 * struct ioat_desc_sw - wrapper around hardware descriptor
 * @hw: hardware DMA descriptor (for memcpy)
 * @node: this descriptor will either be on the free list,
 *     or attached to a transaction list (tx_list)
 * @txd: the generic software descriptor for all engines
 * @id: identifier for debug
 */
struct ioat_desc_sw {
	struct ioat_dma_descriptor *hw;
	struct list_head node;
	size_t len;
	struct list_head tx_list;
	struct dma_async_tx_descriptor txd;
	#ifdef DEBUG
	int id;
	#endif
};

#ifdef DEBUG
#define set_desc_id(desc, i) ((desc)->id = (i))
#define desc_id(desc) ((desc)->id)
#else
#define set_desc_id(desc, i)
#define desc_id(desc) (0)
#endif

static inline void
__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
		struct dma_async_tx_descriptor *tx, int id)
{
	struct device *dev = to_dev(chan);

	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
		(unsigned long long) tx->phys,
		(unsigned long long) hw->next, tx->cookie, tx->flags,
		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
}

#define dump_desc_dbg(c, d) \
	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })

static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
{
	#ifdef CONFIG_NET_DMA
	sysctl_tcp_dma_copybreak = copybreak;
	#endif
}

static inline struct ioat_chan_common *
ioat_chan_by_index(struct ioatdma_device *device, int index)
{
	return device->idx[index];
}

static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;
	u32 status_lo;

	/* We need to read the low address first as this causes the
	 * chipset to latch the upper bits for the subsequent read
	 */
	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	status <<= 32;
	status |= status_lo;

	return status;
}

#if BITS_PER_LONG == 64

static inline u64 ioat_chansts(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;

	 /* With IOAT v3.3 the status register is 64bit.  */
	if (ver >= IOAT_VER_3_3)
		status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	else
		status = ioat_chansts_32(chan);

	return status;
}

#else
#define ioat_chansts ioat_chansts_32
#endif

static inline void ioat_start(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline u64 ioat_chansts_to_addr(u64 status)
{
	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
}

static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
{
	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
}

static inline void ioat_suspend(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline void ioat_reset(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u8 cmd;

	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
}

static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
{
	struct ioat_chan_common *chan = &ioat->base;

	writel(addr & 0x00000000FFFFFFFF,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	writel(addr >> 32,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
}

static inline bool is_ioat_active(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
}

static inline bool is_ioat_idle(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
}

static inline bool is_ioat_halted(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
}

static inline bool is_ioat_suspended(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
}

/* channel was fatally programmed */
static inline bool is_ioat_bug(unsigned long err)
{
	return !!err;
}

int ioat_probe(struct ioatdma_device *device);
int ioat_register(struct ioatdma_device *device);
int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
int ioat_dma_self_test(struct ioatdma_device *device);
void ioat_dma_remove(struct ioatdma_device *device);
struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
void ioat_init_channel(struct ioatdma_device *device,
		       struct ioat_chan_common *chan, int idx);
enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
				   struct dma_tx_state *txstate);
bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
			   dma_addr_t *phys_complete);
void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
void ioat_kobject_del(struct ioatdma_device *device);
int ioat_dma_setup_interrupts(struct ioatdma_device *device);
void ioat_stop(struct ioat_chan_common *chan);
extern const struct sysfs_ops ioat_sysfs_ops;
extern struct ioat_sysfs_entry ioat_version_attr;
extern struct ioat_sysfs_entry ioat_cap_attr;
#endif /* IOATDMA_H */
Commit	Line	Data
0bbd5f4e	1	/*
211a22ce	2	* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
0bbd5f4e CL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef IOATDMA_H
	22	#define IOATDMA_H
	23
	24	#include <linux/dmaengine.h>
584ec227	25	#include "hw.h"
09c8a5b8	26	#include "registers.h"
0bbd5f4e CL	27	#include <linux/init.h>
	28	#include <linux/dmapool.h>
	29	#include <linux/cache.h>
57c651f7	30	#include <linux/pci_ids.h>
16a37aca	31	#include <net/tcp.h>
0bbd5f4e	32
3208ca52	33	#define IOAT_DMA_VERSION "4.00"
5149fd01	34
0bbd5f4e	35	#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
7bb67c14 SN	36	#define IOAT_DMA_DCA_ANY_CPU ~0
7bb67c14 SN	37
1f27adc2 DW	38	#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
1f27adc2 DW	39	#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
bc3c7025 DW	40	#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
bc3c7025 DW	41	#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
3f09ede4	42	#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
1f27adc2 DW	43
	44	#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
	45
1f27adc2 DW	46	/*
	47	* workaround for IOAT ver.3.0 null descriptor issue
	48	* (channel returns error when size is 0)
	49	*/
	50	#define NULL_DESC_BUFFER_SIZE 1
	51
8a52b9ff DJ	52	enum ioat_irq_mode {
	53	IOAT_NOIRQ = 0,
	54	IOAT_MSIX,
8a52b9ff DJ	55	IOAT_MSI,
	56	IOAT_INTX
	57	};
	58
0bbd5f4e	59	/**
8ab89567	60	* struct ioatdma_device - internal representation of a IOAT device
0bbd5f4e CL	61	* @pdev: PCI-Express device
	62	* @reg_base: MMIO register space base address
	63	* @dma_pool: for allocating DMA descriptors
	64	* @common: embedded struct dma_device
8ab89567	65	* @version: version of ioatdma device
7bb67c14 SN	66	* @msix_entries: irq handlers
7bb67c14 SN	67	* @idx: per channel data
f2427e27 DW	68	* @dca: direct cache access context
f2427e27 DW	69	* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
5cbafa65	70	* @enumerate_channels: hw version specific channel enumeration
a6d52d70	71	* @reset_hw: hw version specific channel (re)initialization
aa4d72ae	72	* @cleanup_fn: select between the v2 and v3 cleanup routines
bf40a686	73	* @timer_fn: select between the v2 and v3 timer watchdog routines
9de6fc71	74	* @self_test: hardware version specific self test for each supported op type
bf40a686 DW	75	*
bf40a686 DW	76	* Note: the v3 cleanup routine supports raid operations
0bbd5f4e	77	*/
8ab89567	78	struct ioatdma_device {
0bbd5f4e	79	struct pci_dev *pdev;
47b16539	80	void __iomem *reg_base;
0bbd5f4e CL	81	struct pci_pool *dma_pool;
0bbd5f4e CL	82	struct pci_pool *completion_pool;
7727eaa4 DJ	83	#define MAX_SED_POOLS 5
7727eaa4 DJ	84	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
0bbd5f4e	85	struct dma_device common;
8ab89567	86	u8 version;
3e037454	87	struct msix_entry msix_entries[4];
dcbc853a	88	struct ioat_chan_common *idx[4];
f2427e27	89	struct dca_provider *dca;
8a52b9ff	90	enum ioat_irq_mode irq_mode;
75c6f0ab	91	u32 cap;
f2427e27	92	void (intr_quirk)(struct ioatdma_device device);
5cbafa65	93	int (enumerate_channels)(struct ioatdma_device device);
a6d52d70	94	int (reset_hw)(struct ioat_chan_common chan);
aa4d72ae	95	void (*cleanup_fn)(unsigned long data);
bf40a686	96	void (*timer_fn)(unsigned long data);
9de6fc71	97	int (self_test)(struct ioatdma_device device);
0bbd5f4e CL	98	};
0bbd5f4e CL	99
dcbc853a	100	struct ioat_chan_common {
09c8a5b8	101	struct dma_chan common;
47b16539	102	void __iomem *reg_base;
27502935	103	dma_addr_t last_completion;
0bbd5f4e	104	spinlock_t cleanup_lock;
09c8a5b8 DW	105	unsigned long state;
	106	#define IOAT_COMPLETION_PENDING 0
	107	#define IOAT_COMPLETION_ACK 1
	108	#define IOAT_RESET_PENDING 2
5669e31c	109	#define IOAT_KOBJ_INIT_FAIL 3
074cc476	110	#define IOAT_RESHAPE_PENDING 4
556ab45f	111	#define IOAT_RUN 5
4dec23d7	112	#define IOAT_CHAN_ACTIVE 6
09c8a5b8 DW	113	struct timer_list timer;
09c8a5b8 DW	114	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
a309218a	115	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
09c8a5b8	116	#define RESET_DELAY msecs_to_jiffies(100)
8ab89567	117	struct ioatdma_device *device;
4fb9b9e8 DW	118	dma_addr_t completion_dma;
4fb9b9e8 DW	119	u64 *completion;
3e037454	120	struct tasklet_struct cleanup_task;
5669e31c	121	struct kobject kobj;
0bbd5f4e CL	122	};
0bbd5f4e CL	123
5669e31c DW	124	struct ioat_sysfs_entry {
	125	struct attribute attr;
	126	ssize_t (show)(struct dma_chan , char *);
	127	};
5cbafa65	128
dcbc853a DW	129	/**
	130	* struct ioat_dma_chan - internal representation of a DMA channel
	131	*/
	132	struct ioat_dma_chan {
	133	struct ioat_chan_common base;
	134
	135	size_t xfercap; /* XFERCAP register value expanded out */
	136
	137	spinlock_t desc_lock;
	138	struct list_head free_desc;
	139	struct list_head used_desc;
	140
	141	int pending;
dcbc853a	142	u16 desccount;
5669e31c	143	u16 active;
dcbc853a DW	144	};
dcbc853a DW	145
7727eaa4 DJ	146	/**
	147	* struct ioat_sed_ent - wrapper around super extended hardware descriptor
	148	* @hw: hardware SED
	149	* @sed_dma: dma address for the SED
	150	* @list: list member
	151	* @parent: point to the dma descriptor that's the parent
	152	*/
	153	struct ioat_sed_ent {
	154	struct ioat_sed_raw_descriptor *hw;
	155	dma_addr_t dma;
	156	struct ioat_ring_ent *parent;
	157	unsigned int hw_pool;
	158	};
	159
dcbc853a DW	160	static inline struct ioat_chan_common to_chan_common(struct dma_chan c)
	161	{
	162	return container_of(c, struct ioat_chan_common, common);
	163	}
	164
	165	static inline struct ioat_dma_chan to_ioat_chan(struct dma_chan c)
	166	{
	167	struct ioat_chan_common *chan = to_chan_common(c);
	168
	169	return container_of(chan, struct ioat_dma_chan, base);
	170	}
	171
0bbd5f4e CL	172	/* wrapper around hardware descriptor format + additional software fields */
	173
	174	/**
	175	* struct ioat_desc_sw - wrapper around hardware descriptor
2aec048c	176	* @hw: hardware DMA descriptor (for memcpy)
7405f74b	177	* @node: this descriptor will either be on the free list,
ea25968a	178	* or attached to a transaction list (tx_list)
bc3c7025	179	* @txd: the generic software descriptor for all engines
6df9183a	180	* @id: identifier for debug
0bbd5f4e	181	*/
0bbd5f4e CL	182	struct ioat_desc_sw {
	183	struct ioat_dma_descriptor *hw;
	184	struct list_head node;
7f2b291f	185	size_t len;
ea25968a	186	struct list_head tx_list;
bc3c7025	187	struct dma_async_tx_descriptor txd;
6df9183a DW	188	#ifdef DEBUG
	189	int id;
	190	#endif
0bbd5f4e CL	191	};
0bbd5f4e CL	192
6df9183a DW	193	#ifdef DEBUG
	194	#define set_desc_id(desc, i) ((desc)->id = (i))
	195	#define desc_id(desc) ((desc)->id)
	196	#else
	197	#define set_desc_id(desc, i)
	198	#define desc_id(desc) (0)
	199	#endif
	200
	201	static inline void
	202	__dump_desc_dbg(struct ioat_chan_common chan, struct ioat_dma_descriptor hw,
	203	struct dma_async_tx_descriptor *tx, int id)
	204	{
	205	struct device *dev = to_dev(chan);
	206
	207	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
50f9f97e	208	" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
6df9183a DW	209	(unsigned long long) tx->phys,
	210	(unsigned long long) hw->next, tx->cookie, tx->flags,
	211	hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
	212	}
	213
	214	#define dump_desc_dbg(c, d) \
	215	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
	216
f2427e27	217	static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
16a37aca MS	218	{
16a37aca MS	219	#ifdef CONFIG_NET_DMA
f2427e27	220	sysctl_tcp_dma_copybreak = copybreak;
16a37aca MS	221	#endif
	222	}
	223
5cbafa65 DW	224	static inline struct ioat_chan_common *
	225	ioat_chan_by_index(struct ioatdma_device *device, int index)
	226	{
	227	return device->idx[index];
	228	}
	229
d92a8d7c	230	static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
09c8a5b8 DW	231	{
	232	u8 ver = chan->device->version;
	233	u64 status;
	234	u32 status_lo;
	235
	236	/* We need to read the low address first as this causes the
	237	* chipset to latch the upper bits for the subsequent read
	238	*/
	239	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	240	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	241	status <<= 32;
	242	status \|= status_lo;
	243
	244	return status;
	245	}
	246
d92a8d7c DJ	247	#if BITS_PER_LONG == 64
	248
	249	static inline u64 ioat_chansts(struct ioat_chan_common *chan)
	250	{
	251	u8 ver = chan->device->version;
	252	u64 status;
	253
	254	/* With IOAT v3.3 the status register is 64bit. */
	255	if (ver >= IOAT_VER_3_3)
	256	status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
	257	else
	258	status = ioat_chansts_32(chan);
	259
	260	return status;
	261	}
	262
	263	#else
	264	#define ioat_chansts ioat_chansts_32
	265	#endif
	266
09c8a5b8 DW	267	static inline void ioat_start(struct ioat_chan_common *chan)
	268	{
	269	u8 ver = chan->device->version;
	270
	271	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	272	}
	273
	274	static inline u64 ioat_chansts_to_addr(u64 status)
	275	{
	276	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
	277	}
	278
	279	static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
	280	{
	281	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
	282	}
	283
	284	static inline void ioat_suspend(struct ioat_chan_common *chan)
	285	{
	286	u8 ver = chan->device->version;
	287
	288	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	289	}
	290
a6d52d70 DW	291	static inline void ioat_reset(struct ioat_chan_common *chan)
	292	{
	293	u8 ver = chan->device->version;
	294
	295	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	296	}
	297
	298	static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
	299	{
	300	u8 ver = chan->device->version;
	301	u8 cmd;
	302
	303	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	304	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
	305	}
	306
09c8a5b8 DW	307	static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
	308	{
	309	struct ioat_chan_common *chan = &ioat->base;
	310
	311	writel(addr & 0x00000000FFFFFFFF,
	312	chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	313	writel(addr >> 32,
	314	chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
	315	}
	316
	317	static inline bool is_ioat_active(unsigned long status)
	318	{
	319	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
	320	}
	321
	322	static inline bool is_ioat_idle(unsigned long status)
	323	{
	324	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
	325	}
	326
	327	static inline bool is_ioat_halted(unsigned long status)
	328	{
	329	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
	330	}
	331
	332	static inline bool is_ioat_suspended(unsigned long status)
	333	{
	334	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
	335	}
	336
	337	/* channel was fatally programmed */
	338	static inline bool is_ioat_bug(unsigned long err)
	339	{
b57014de	340	return !!err;
09c8a5b8 DW	341	}
09c8a5b8 DW	342
4bf27b8b GKH	343	int ioat_probe(struct ioatdma_device *device);
	344	int ioat_register(struct ioatdma_device *device);
	345	int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
	346	int ioat_dma_self_test(struct ioatdma_device *device);
	347	void ioat_dma_remove(struct ioatdma_device *device);
	348	struct dca_provider ioat_dca_init(struct pci_dev pdev, void __iomem *iobase);
27502935	349	dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
5cbafa65	350	void ioat_init_channel(struct ioatdma_device *device,
aa4d72ae	351	struct ioat_chan_common *chan, int idx);
07934481 LW	352	enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
07934481 LW	353	struct dma_tx_state *txstate);
09c8a5b8	354	bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
27502935	355	dma_addr_t *phys_complete);
5669e31c DW	356	void ioat_kobject_add(struct ioatdma_device device, struct kobj_type type);
5669e31c DW	357	void ioat_kobject_del(struct ioatdma_device *device);
8a52b9ff	358	int ioat_dma_setup_interrupts(struct ioatdma_device *device);
da87ca4d	359	void ioat_stop(struct ioat_chan_common *chan);
52cf25d0	360	extern const struct sysfs_ops ioat_sysfs_ops;
5669e31c DW	361	extern struct ioat_sysfs_entry ioat_version_attr;
5669e31c DW	362	extern struct ioat_sysfs_entry ioat_cap_attr;
0bbd5f4e	363	#endif /* IOATDMA_H */