Commit | Line | Data |
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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
7727eaa4 | 58 | #include <linux/module.h> |
bf40a686 | 59 | #include <linux/pci.h> |
5a0e3ad6 | 60 | #include <linux/gfp.h> |
bf40a686 DW |
61 | #include <linux/dmaengine.h> |
62 | #include <linux/dma-mapping.h> | |
70c71606 | 63 | #include <linux/prefetch.h> |
949ff5b8 | 64 | #include "../dmaengine.h" |
bf40a686 DW |
65 | #include "registers.h" |
66 | #include "hw.h" | |
67 | #include "dma.h" | |
68 | #include "dma_v2.h" | |
69 | ||
b094ad3b DW |
70 | /* ioat hardware assumes at least two sources for raid operations */ |
71 | #define src_cnt_to_sw(x) ((x) + 2) | |
72 | #define src_cnt_to_hw(x) ((x) - 2) | |
7727eaa4 DJ |
73 | #define ndest_to_sw(x) ((x) + 1) |
74 | #define ndest_to_hw(x) ((x) - 1) | |
75 | #define src16_cnt_to_sw(x) ((x) + 9) | |
76 | #define src16_cnt_to_hw(x) ((x) - 9) | |
b094ad3b DW |
77 | |
78 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 79 | * extended descriptor of an xor or pq descriptor |
b094ad3b | 80 | */ |
d0b0c8c7 | 81 | static const u8 xor_idx_to_desc = 0xe0; |
9b487ced AK |
82 | static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
83 | static const u8 pq_idx_to_desc = 0xf8; | |
7727eaa4 DJ |
84 | static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1, |
85 | 2, 2, 2, 2, 2, 2, 2 }; | |
9b487ced | 86 | static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; |
7727eaa4 DJ |
87 | static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7, |
88 | 0, 1, 2, 3, 4, 5, 6 }; | |
89 | ||
90 | /* | |
91 | * technically sources 1 and 2 do not require SED, but the op will have | |
92 | * at least 9 descriptors so that's irrelevant. | |
93 | */ | |
94 | static const u8 pq16_idx_to_sed[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
95 | 1, 1, 1, 1, 1, 1, 1 }; | |
b094ad3b | 96 | |
3f09ede4 DJ |
97 | static void ioat3_eh(struct ioat2_dma_chan *ioat); |
98 | ||
b094ad3b DW |
99 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
100 | { | |
101 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
102 | ||
103 | return raw->field[xor_idx_to_field[idx]]; | |
104 | } | |
105 | ||
106 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
107 | dma_addr_t addr, u32 offset, int idx) | |
108 | { | |
109 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
110 | ||
111 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
112 | } | |
113 | ||
d69d235b DW |
114 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
115 | { | |
116 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
117 | ||
118 | return raw->field[pq_idx_to_field[idx]]; | |
119 | } | |
120 | ||
7727eaa4 DJ |
121 | static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx) |
122 | { | |
123 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
124 | ||
125 | return raw->field[pq16_idx_to_field[idx]]; | |
126 | } | |
127 | ||
d69d235b DW |
128 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], |
129 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
130 | { | |
131 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
132 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
133 | ||
134 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
135 | pq->coef[idx] = coef; | |
136 | } | |
137 | ||
7727eaa4 DJ |
138 | static int sed_get_pq16_pool_idx(int src_cnt) |
139 | { | |
140 | ||
141 | return pq16_idx_to_sed[src_cnt]; | |
142 | } | |
143 | ||
8a52b9ff DJ |
144 | static bool is_jf_ioat(struct pci_dev *pdev) |
145 | { | |
146 | switch (pdev->device) { | |
147 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: | |
148 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: | |
149 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: | |
150 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: | |
151 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: | |
152 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: | |
153 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: | |
154 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: | |
155 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: | |
156 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: | |
157 | return true; | |
158 | default: | |
159 | return false; | |
160 | } | |
161 | } | |
162 | ||
163 | static bool is_snb_ioat(struct pci_dev *pdev) | |
164 | { | |
165 | switch (pdev->device) { | |
166 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: | |
167 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: | |
168 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: | |
169 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: | |
170 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: | |
171 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: | |
172 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: | |
173 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: | |
174 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: | |
175 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: | |
176 | return true; | |
177 | default: | |
178 | return false; | |
179 | } | |
180 | } | |
181 | ||
182 | static bool is_ivb_ioat(struct pci_dev *pdev) | |
183 | { | |
184 | switch (pdev->device) { | |
185 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: | |
186 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: | |
187 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: | |
188 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: | |
189 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: | |
190 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: | |
191 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: | |
192 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: | |
193 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: | |
194 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: | |
195 | return true; | |
196 | default: | |
197 | return false; | |
198 | } | |
199 | ||
200 | } | |
201 | ||
202 | static bool is_hsw_ioat(struct pci_dev *pdev) | |
203 | { | |
204 | switch (pdev->device) { | |
205 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: | |
206 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: | |
207 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: | |
208 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: | |
209 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: | |
210 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: | |
211 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: | |
212 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: | |
213 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: | |
214 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: | |
215 | return true; | |
216 | default: | |
217 | return false; | |
218 | } | |
219 | ||
220 | } | |
221 | ||
222 | static bool is_xeon_cb32(struct pci_dev *pdev) | |
223 | { | |
224 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || | |
225 | is_hsw_ioat(pdev); | |
226 | } | |
227 | ||
228 | static bool is_bwd_ioat(struct pci_dev *pdev) | |
229 | { | |
230 | switch (pdev->device) { | |
231 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: | |
232 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: | |
233 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
234 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
235 | return true; | |
236 | default: | |
237 | return false; | |
238 | } | |
239 | } | |
240 | ||
d302398d DJ |
241 | static bool is_bwd_noraid(struct pci_dev *pdev) |
242 | { | |
243 | switch (pdev->device) { | |
244 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
245 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
246 | return true; | |
247 | default: | |
248 | return false; | |
249 | } | |
250 | ||
251 | } | |
252 | ||
7727eaa4 DJ |
253 | static void pq16_set_src(struct ioat_raw_descriptor *desc[3], |
254 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
255 | { | |
256 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0]; | |
257 | struct ioat_pq16a_descriptor *pq16 = | |
258 | (struct ioat_pq16a_descriptor *)desc[1]; | |
259 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
260 | ||
261 | raw->field[pq16_idx_to_field[idx]] = addr + offset; | |
262 | ||
263 | if (idx < 8) | |
264 | pq->coef[idx] = coef; | |
265 | else | |
266 | pq16->coef[idx - 8] = coef; | |
267 | } | |
268 | ||
e6a30fec | 269 | static struct ioat_sed_ent * |
7727eaa4 DJ |
270 | ioat3_alloc_sed(struct ioatdma_device *device, unsigned int hw_pool) |
271 | { | |
272 | struct ioat_sed_ent *sed; | |
273 | gfp_t flags = __GFP_ZERO | GFP_ATOMIC; | |
274 | ||
275 | sed = kmem_cache_alloc(device->sed_pool, flags); | |
276 | if (!sed) | |
277 | return NULL; | |
278 | ||
279 | sed->hw_pool = hw_pool; | |
280 | sed->hw = dma_pool_alloc(device->sed_hw_pool[hw_pool], | |
281 | flags, &sed->dma); | |
282 | if (!sed->hw) { | |
283 | kmem_cache_free(device->sed_pool, sed); | |
284 | return NULL; | |
285 | } | |
286 | ||
287 | return sed; | |
288 | } | |
289 | ||
e6a30fec | 290 | static void ioat3_free_sed(struct ioatdma_device *device, struct ioat_sed_ent *sed) |
7727eaa4 DJ |
291 | { |
292 | if (!sed) | |
293 | return; | |
294 | ||
295 | dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
296 | kmem_cache_free(device->sed_pool, sed); | |
297 | } | |
298 | ||
bf40a686 | 299 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 300 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
301 | { |
302 | struct ioat_chan_common *chan = &ioat->base; | |
303 | struct pci_dev *pdev = chan->device->pdev; | |
304 | size_t len = desc->len; | |
305 | size_t offset = len - desc->hw->size; | |
306 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
307 | enum dma_ctrl_flags flags = tx->flags; | |
308 | ||
309 | switch (desc->hw->ctl_f.op) { | |
310 | case IOAT_OP_COPY: | |
58c8649e DW |
311 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
312 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 | 313 | break; |
b094ad3b DW |
314 | case IOAT_OP_XOR_VAL: |
315 | case IOAT_OP_XOR: { | |
316 | struct ioat_xor_descriptor *xor = desc->xor; | |
317 | struct ioat_ring_ent *ext; | |
318 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
319 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
320 | struct ioat_raw_descriptor *descs[2]; | |
321 | int i; | |
322 | ||
323 | if (src_cnt > 5) { | |
324 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
325 | xor_ex = ext->xor_ex; | |
326 | } | |
327 | ||
328 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
329 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
330 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
331 | for (i = 0; i < src_cnt; i++) { | |
332 | dma_addr_t src = xor_get_src(descs, i); | |
333 | ||
334 | ioat_unmap(pdev, src - offset, len, | |
335 | PCI_DMA_TODEVICE, flags, 0); | |
336 | } | |
337 | ||
338 | /* dest is a source in xor validate operations */ | |
339 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
340 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
341 | PCI_DMA_TODEVICE, flags, 1); | |
342 | break; | |
343 | } | |
344 | } | |
345 | ||
346 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
347 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
348 | PCI_DMA_FROMDEVICE, flags, 1); | |
349 | break; | |
350 | } | |
d69d235b DW |
351 | case IOAT_OP_PQ_VAL: |
352 | case IOAT_OP_PQ: { | |
353 | struct ioat_pq_descriptor *pq = desc->pq; | |
354 | struct ioat_ring_ent *ext; | |
355 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
356 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
357 | struct ioat_raw_descriptor *descs[2]; | |
358 | int i; | |
359 | ||
360 | if (src_cnt > 3) { | |
361 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
362 | pq_ex = ext->pq_ex; | |
363 | } | |
364 | ||
365 | /* in the 'continue' case don't unmap the dests as sources */ | |
366 | if (dmaf_p_disabled_continue(flags)) | |
367 | src_cnt--; | |
368 | else if (dmaf_continue(flags)) | |
369 | src_cnt -= 3; | |
370 | ||
371 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
372 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
373 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
374 | for (i = 0; i < src_cnt; i++) { | |
375 | dma_addr_t src = pq_get_src(descs, i); | |
376 | ||
377 | ioat_unmap(pdev, src - offset, len, | |
378 | PCI_DMA_TODEVICE, flags, 0); | |
379 | } | |
380 | ||
381 | /* the dests are sources in pq validate operations */ | |
382 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
383 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
384 | ioat_unmap(pdev, pq->p_addr - offset, | |
385 | len, PCI_DMA_TODEVICE, flags, 0); | |
386 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
387 | ioat_unmap(pdev, pq->q_addr - offset, | |
388 | len, PCI_DMA_TODEVICE, flags, 0); | |
389 | break; | |
390 | } | |
391 | } | |
392 | ||
393 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
394 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
395 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
396 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
397 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
398 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
399 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
400 | } | |
401 | break; | |
402 | } | |
7727eaa4 DJ |
403 | case IOAT_OP_PQ_16S: |
404 | case IOAT_OP_PQ_VAL_16S: { | |
405 | struct ioat_pq_descriptor *pq = desc->pq; | |
406 | int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); | |
407 | struct ioat_raw_descriptor *descs[4]; | |
408 | int i; | |
409 | ||
410 | /* in the 'continue' case don't unmap the dests as sources */ | |
411 | if (dmaf_p_disabled_continue(flags)) | |
412 | src_cnt--; | |
413 | else if (dmaf_continue(flags)) | |
414 | src_cnt -= 3; | |
415 | ||
416 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
417 | descs[0] = (struct ioat_raw_descriptor *)pq; | |
418 | descs[1] = (struct ioat_raw_descriptor *)(desc->sed->hw); | |
419 | descs[2] = (struct ioat_raw_descriptor *)(&desc->sed->hw->b[0]); | |
420 | for (i = 0; i < src_cnt; i++) { | |
421 | dma_addr_t src = pq16_get_src(descs, i); | |
422 | ||
423 | ioat_unmap(pdev, src - offset, len, | |
424 | PCI_DMA_TODEVICE, flags, 0); | |
425 | } | |
426 | ||
427 | /* the dests are sources in pq validate operations */ | |
428 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
429 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
430 | ioat_unmap(pdev, pq->p_addr - offset, | |
431 | len, PCI_DMA_TODEVICE, | |
432 | flags, 0); | |
433 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
434 | ioat_unmap(pdev, pq->q_addr - offset, | |
435 | len, PCI_DMA_TODEVICE, | |
436 | flags, 0); | |
437 | break; | |
438 | } | |
439 | } | |
440 | ||
441 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
442 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
443 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
444 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
445 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
446 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
447 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
448 | } | |
449 | break; | |
450 | } | |
bf40a686 DW |
451 | default: |
452 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
453 | __func__, desc->hw->ctl_f.op); | |
454 | } | |
455 | } | |
456 | ||
b094ad3b DW |
457 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
458 | { | |
459 | struct ioat_dma_descriptor *hw = desc->hw; | |
460 | ||
461 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
462 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
463 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 464 | |
b094ad3b DW |
465 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
466 | return true; | |
d69d235b DW |
467 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
468 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
469 | struct ioat_pq_descriptor *pq = desc->pq; | |
470 | ||
471 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
472 | return true; | |
b094ad3b DW |
473 | } |
474 | ||
475 | return false; | |
476 | } | |
477 | ||
3f09ede4 DJ |
478 | static u64 ioat3_get_current_completion(struct ioat_chan_common *chan) |
479 | { | |
480 | u64 phys_complete; | |
481 | u64 completion; | |
482 | ||
483 | completion = *chan->completion; | |
484 | phys_complete = ioat_chansts_to_addr(completion); | |
485 | ||
486 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, | |
487 | (unsigned long long) phys_complete); | |
488 | ||
489 | return phys_complete; | |
490 | } | |
491 | ||
492 | static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan, | |
493 | u64 *phys_complete) | |
494 | { | |
495 | *phys_complete = ioat3_get_current_completion(chan); | |
496 | if (*phys_complete == chan->last_completion) | |
497 | return false; | |
498 | ||
499 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); | |
500 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
501 | ||
502 | return true; | |
503 | } | |
504 | ||
75c6f0ab DJ |
505 | static void |
506 | desc_get_errstat(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc) | |
507 | { | |
508 | struct ioat_dma_descriptor *hw = desc->hw; | |
509 | ||
510 | switch (hw->ctl_f.op) { | |
511 | case IOAT_OP_PQ_VAL: | |
512 | case IOAT_OP_PQ_VAL_16S: | |
513 | { | |
514 | struct ioat_pq_descriptor *pq = desc->pq; | |
515 | ||
516 | /* check if there's error written */ | |
517 | if (!pq->dwbes_f.wbes) | |
518 | return; | |
519 | ||
520 | /* need to set a chanerr var for checking to clear later */ | |
521 | ||
522 | if (pq->dwbes_f.p_val_err) | |
523 | *desc->result |= SUM_CHECK_P_RESULT; | |
524 | ||
525 | if (pq->dwbes_f.q_val_err) | |
526 | *desc->result |= SUM_CHECK_Q_RESULT; | |
527 | ||
528 | return; | |
529 | } | |
530 | default: | |
531 | return; | |
532 | } | |
533 | } | |
534 | ||
b094ad3b DW |
535 | /** |
536 | * __cleanup - reclaim used descriptors | |
537 | * @ioat: channel (ring) to clean | |
538 | * | |
539 | * The difference from the dma_v2.c __cleanup() is that this routine | |
540 | * handles extended descriptors and dma-unmapping raid operations. | |
541 | */ | |
27502935 | 542 | static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete) |
bf40a686 DW |
543 | { |
544 | struct ioat_chan_common *chan = &ioat->base; | |
7727eaa4 | 545 | struct ioatdma_device *device = chan->device; |
bf40a686 DW |
546 | struct ioat_ring_ent *desc; |
547 | bool seen_current = false; | |
074cc476 | 548 | int idx = ioat->tail, i; |
bf40a686 | 549 | u16 active; |
bf40a686 DW |
550 | |
551 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
552 | __func__, ioat->head, ioat->tail, ioat->issued); | |
553 | ||
3f09ede4 DJ |
554 | /* |
555 | * At restart of the channel, the completion address and the | |
556 | * channel status will be 0 due to starting a new chain. Since | |
557 | * it's new chain and the first descriptor "fails", there is | |
558 | * nothing to clean up. We do not want to reap the entire submitted | |
559 | * chain due to this 0 address value and then BUG. | |
560 | */ | |
561 | if (!phys_complete) | |
562 | return; | |
563 | ||
bf40a686 DW |
564 | active = ioat2_ring_active(ioat); |
565 | for (i = 0; i < active && !seen_current; i++) { | |
566 | struct dma_async_tx_descriptor *tx; | |
567 | ||
074cc476 DW |
568 | smp_read_barrier_depends(); |
569 | prefetch(ioat2_get_ring_ent(ioat, idx + i + 1)); | |
570 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
bf40a686 | 571 | dump_desc_dbg(ioat, desc); |
75c6f0ab DJ |
572 | |
573 | /* set err stat if we are using dwbes */ | |
574 | if (device->cap & IOAT_CAP_DWBES) | |
575 | desc_get_errstat(ioat, desc); | |
576 | ||
bf40a686 DW |
577 | tx = &desc->txd; |
578 | if (tx->cookie) { | |
f7fbce07 | 579 | dma_cookie_complete(tx); |
074cc476 | 580 | ioat3_dma_unmap(ioat, desc, idx + i); |
bf40a686 DW |
581 | if (tx->callback) { |
582 | tx->callback(tx->callback_param); | |
583 | tx->callback = NULL; | |
584 | } | |
585 | } | |
586 | ||
587 | if (tx->phys == phys_complete) | |
588 | seen_current = true; | |
b094ad3b DW |
589 | |
590 | /* skip extended descriptors */ | |
591 | if (desc_has_ext(desc)) { | |
592 | BUG_ON(i + 1 >= active); | |
593 | i++; | |
594 | } | |
7727eaa4 DJ |
595 | |
596 | /* cleanup super extended descriptors */ | |
597 | if (desc->sed) { | |
598 | ioat3_free_sed(device, desc->sed); | |
599 | desc->sed = NULL; | |
600 | } | |
bf40a686 | 601 | } |
074cc476 DW |
602 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
603 | ioat->tail = idx + i; | |
aa75db00 | 604 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
bf40a686 | 605 | chan->last_completion = phys_complete; |
b9cc9869 | 606 | |
074cc476 | 607 | if (active - i == 0) { |
bf40a686 DW |
608 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
609 | __func__); | |
610 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
611 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
612 | } | |
b9cc9869 | 613 | /* 5 microsecond delay per pending descriptor */ |
074cc476 | 614 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
b9cc9869 | 615 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); |
bf40a686 DW |
616 | } |
617 | ||
074cc476 | 618 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) |
bf40a686 DW |
619 | { |
620 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 621 | u64 phys_complete; |
bf40a686 | 622 | |
b9cc9869 | 623 | spin_lock_bh(&chan->cleanup_lock); |
3f09ede4 DJ |
624 | |
625 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
074cc476 | 626 | __cleanup(ioat, phys_complete); |
3f09ede4 DJ |
627 | |
628 | if (is_ioat_halted(*chan->completion)) { | |
629 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
630 | ||
631 | if (chanerr & IOAT_CHANERR_HANDLE_MASK) { | |
632 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
633 | ioat3_eh(ioat); | |
634 | } | |
635 | } | |
636 | ||
b9cc9869 DW |
637 | spin_unlock_bh(&chan->cleanup_lock); |
638 | } | |
639 | ||
aa4d72ae | 640 | static void ioat3_cleanup_event(unsigned long data) |
bf40a686 | 641 | { |
aa4d72ae | 642 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
bf40a686 | 643 | |
074cc476 | 644 | ioat3_cleanup(ioat); |
773d9e2d | 645 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
646 | } |
647 | ||
648 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
649 | { | |
650 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 651 | u64 phys_complete; |
bf40a686 | 652 | |
b372ec2d | 653 | ioat2_quiesce(chan, 0); |
3f09ede4 | 654 | if (ioat3_cleanup_preamble(chan, &phys_complete)) |
bf40a686 DW |
655 | __cleanup(ioat, phys_complete); |
656 | ||
657 | __ioat2_restart_chan(ioat); | |
658 | } | |
659 | ||
3f09ede4 DJ |
660 | static void ioat3_eh(struct ioat2_dma_chan *ioat) |
661 | { | |
662 | struct ioat_chan_common *chan = &ioat->base; | |
663 | struct pci_dev *pdev = to_pdev(chan); | |
664 | struct ioat_dma_descriptor *hw; | |
665 | u64 phys_complete; | |
666 | struct ioat_ring_ent *desc; | |
667 | u32 err_handled = 0; | |
668 | u32 chanerr_int; | |
669 | u32 chanerr; | |
670 | ||
671 | /* cleanup so tail points to descriptor that caused the error */ | |
672 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
673 | __cleanup(ioat, phys_complete); | |
674 | ||
675 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
676 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
677 | ||
678 | dev_dbg(to_dev(chan), "%s: error = %x:%x\n", | |
679 | __func__, chanerr, chanerr_int); | |
680 | ||
681 | desc = ioat2_get_ring_ent(ioat, ioat->tail); | |
682 | hw = desc->hw; | |
683 | dump_desc_dbg(ioat, desc); | |
684 | ||
685 | switch (hw->ctl_f.op) { | |
686 | case IOAT_OP_XOR_VAL: | |
687 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
688 | *desc->result |= SUM_CHECK_P_RESULT; | |
689 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
690 | } | |
691 | break; | |
692 | case IOAT_OP_PQ_VAL: | |
7727eaa4 | 693 | case IOAT_OP_PQ_VAL_16S: |
3f09ede4 DJ |
694 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { |
695 | *desc->result |= SUM_CHECK_P_RESULT; | |
696 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
697 | } | |
698 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
699 | *desc->result |= SUM_CHECK_Q_RESULT; | |
700 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
701 | } | |
702 | break; | |
703 | } | |
704 | ||
705 | /* fault on unhandled error or spurious halt */ | |
706 | if (chanerr ^ err_handled || chanerr == 0) { | |
707 | dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n", | |
708 | __func__, chanerr, err_handled); | |
709 | BUG(); | |
710 | } | |
711 | ||
712 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
713 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
714 | ||
715 | /* mark faulting descriptor as complete */ | |
716 | *chan->completion = desc->txd.phys; | |
717 | ||
718 | spin_lock_bh(&ioat->prep_lock); | |
719 | ioat3_restart_channel(ioat); | |
720 | spin_unlock_bh(&ioat->prep_lock); | |
721 | } | |
722 | ||
4dec23d7 | 723 | static void check_active(struct ioat2_dma_chan *ioat) |
bf40a686 | 724 | { |
bf40a686 DW |
725 | struct ioat_chan_common *chan = &ioat->base; |
726 | ||
4dec23d7 DJ |
727 | if (ioat2_ring_active(ioat)) { |
728 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
729 | return; | |
730 | } | |
bf40a686 | 731 | |
4dec23d7 DJ |
732 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state)) |
733 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
734 | else if (ioat->alloc_order > ioat_get_alloc_order()) { | |
bf40a686 DW |
735 | /* if the ring is idle, empty, and oversized try to step |
736 | * down the size | |
737 | */ | |
4dec23d7 | 738 | reshape_ring(ioat, ioat->alloc_order - 1); |
bf40a686 DW |
739 | |
740 | /* keep shrinking until we get back to our minimum | |
741 | * default size | |
742 | */ | |
743 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
744 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
745 | } | |
4dec23d7 DJ |
746 | |
747 | } | |
748 | ||
a20702b8 | 749 | static void ioat3_timer_event(unsigned long data) |
4dec23d7 DJ |
750 | { |
751 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); | |
752 | struct ioat_chan_common *chan = &ioat->base; | |
753 | dma_addr_t phys_complete; | |
754 | u64 status; | |
755 | ||
756 | status = ioat_chansts(chan); | |
757 | ||
758 | /* when halted due to errors check for channel | |
759 | * programming errors before advancing the completion state | |
760 | */ | |
761 | if (is_ioat_halted(status)) { | |
762 | u32 chanerr; | |
763 | ||
764 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
765 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", | |
766 | __func__, chanerr); | |
767 | if (test_bit(IOAT_RUN, &chan->state)) | |
768 | BUG_ON(is_ioat_bug(chanerr)); | |
769 | else /* we never got off the ground */ | |
770 | return; | |
771 | } | |
772 | ||
773 | /* if we haven't made progress and we have already | |
774 | * acknowledged a pending completion once, then be more | |
775 | * forceful with a restart | |
776 | */ | |
777 | spin_lock_bh(&chan->cleanup_lock); | |
778 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
779 | __cleanup(ioat, phys_complete); | |
780 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) { | |
781 | spin_lock_bh(&ioat->prep_lock); | |
782 | ioat3_restart_channel(ioat); | |
783 | spin_unlock_bh(&ioat->prep_lock); | |
784 | spin_unlock_bh(&chan->cleanup_lock); | |
785 | return; | |
786 | } else { | |
787 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
788 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
789 | } | |
790 | ||
791 | ||
792 | if (ioat2_ring_active(ioat)) | |
793 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
794 | else { | |
795 | spin_lock_bh(&ioat->prep_lock); | |
796 | check_active(ioat); | |
797 | spin_unlock_bh(&ioat->prep_lock); | |
798 | } | |
799 | spin_unlock_bh(&chan->cleanup_lock); | |
bf40a686 DW |
800 | } |
801 | ||
802 | static enum dma_status | |
07934481 LW |
803 | ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
804 | struct dma_tx_state *txstate) | |
bf40a686 DW |
805 | { |
806 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
96a2af41 | 807 | enum dma_status ret; |
bf40a686 | 808 | |
96a2af41 RKAL |
809 | ret = dma_cookie_status(c, cookie, txstate); |
810 | if (ret == DMA_SUCCESS) | |
811 | return ret; | |
bf40a686 | 812 | |
074cc476 | 813 | ioat3_cleanup(ioat); |
bf40a686 | 814 | |
96a2af41 | 815 | return dma_cookie_status(c, cookie, txstate); |
bf40a686 DW |
816 | } |
817 | ||
b094ad3b DW |
818 | static struct dma_async_tx_descriptor * |
819 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
820 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
821 | size_t len, unsigned long flags) | |
822 | { | |
823 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
824 | struct ioat_ring_ent *compl_desc; | |
825 | struct ioat_ring_ent *desc; | |
826 | struct ioat_ring_ent *ext; | |
827 | size_t total_len = len; | |
828 | struct ioat_xor_descriptor *xor; | |
829 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
830 | struct ioat_dma_descriptor *hw; | |
074cc476 | 831 | int num_descs, with_ext, idx, i; |
b094ad3b | 832 | u32 offset = 0; |
b094ad3b DW |
833 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
834 | ||
835 | BUG_ON(src_cnt < 2); | |
836 | ||
837 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
838 | /* we need 2x the number of descriptors to cover greater than 5 | |
839 | * sources | |
840 | */ | |
841 | if (src_cnt > 5) { | |
842 | with_ext = 1; | |
843 | num_descs *= 2; | |
844 | } else | |
845 | with_ext = 0; | |
846 | ||
847 | /* completion writes from the raid engine may pass completion | |
848 | * writes from the legacy engine, so we need one extra null | |
849 | * (legacy) descriptor to ensure all completion writes arrive in | |
850 | * order. | |
851 | */ | |
074cc476 DW |
852 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0) |
853 | idx = ioat->head; | |
b094ad3b DW |
854 | else |
855 | return NULL; | |
cdef57db DW |
856 | i = 0; |
857 | do { | |
b094ad3b DW |
858 | struct ioat_raw_descriptor *descs[2]; |
859 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
860 | int s; | |
861 | ||
862 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
863 | xor = desc->xor; | |
864 | ||
865 | /* save a branch by unconditionally retrieving the | |
866 | * extended descriptor xor_set_src() knows to not write | |
867 | * to it in the single descriptor case | |
868 | */ | |
869 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
870 | xor_ex = ext->xor_ex; | |
871 | ||
872 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
873 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
874 | for (s = 0; s < src_cnt; s++) | |
875 | xor_set_src(descs, src[s], offset, s); | |
876 | xor->size = xfer_size; | |
877 | xor->dst_addr = dest + offset; | |
878 | xor->ctl = 0; | |
879 | xor->ctl_f.op = op; | |
880 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
881 | ||
882 | len -= xfer_size; | |
883 | offset += xfer_size; | |
884 | dump_desc_dbg(ioat, desc); | |
cdef57db | 885 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
886 | |
887 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
888 | desc->txd.flags = flags; | |
889 | desc->len = total_len; | |
890 | if (result) | |
891 | desc->result = result; | |
892 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
893 | ||
894 | /* completion descriptor carries interrupt bit */ | |
895 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
896 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
897 | hw = compl_desc->hw; | |
898 | hw->ctl = 0; | |
899 | hw->ctl_f.null = 1; | |
900 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
901 | hw->ctl_f.compl_write = 1; | |
902 | hw->size = NULL_DESC_BUFFER_SIZE; | |
903 | dump_desc_dbg(ioat, compl_desc); | |
904 | ||
905 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 906 | return &compl_desc->txd; |
b094ad3b DW |
907 | } |
908 | ||
909 | static struct dma_async_tx_descriptor * | |
910 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
911 | unsigned int src_cnt, size_t len, unsigned long flags) | |
912 | { | |
913 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
914 | } | |
915 | ||
916 | struct dma_async_tx_descriptor * | |
917 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
918 | unsigned int src_cnt, size_t len, | |
919 | enum sum_check_flags *result, unsigned long flags) | |
920 | { | |
921 | /* the cleanup routine only sets bits on validate failure, it | |
922 | * does not clear bits on validate success... so clear it here | |
923 | */ | |
924 | *result = 0; | |
925 | ||
926 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
927 | src_cnt - 1, len, flags); | |
928 | } | |
929 | ||
d69d235b DW |
930 | static void |
931 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
932 | { | |
933 | struct device *dev = to_dev(&ioat->base); | |
934 | struct ioat_pq_descriptor *pq = desc->pq; | |
935 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
936 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
937 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
938 | int i; | |
939 | ||
940 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
7727eaa4 DJ |
941 | " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" |
942 | " src_cnt: %d)\n", | |
d69d235b DW |
943 | desc_id(desc), (unsigned long long) desc->txd.phys, |
944 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
945 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
946 | pq->ctl_f.compl_write, | |
947 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
948 | pq->ctl_f.src_cnt); | |
949 | for (i = 0; i < src_cnt; i++) | |
950 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
951 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
952 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
953 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
50f9f97e | 954 | dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
d69d235b DW |
955 | } |
956 | ||
7727eaa4 DJ |
957 | static void dump_pq16_desc_dbg(struct ioat2_dma_chan *ioat, |
958 | struct ioat_ring_ent *desc) | |
959 | { | |
960 | struct device *dev = to_dev(&ioat->base); | |
961 | struct ioat_pq_descriptor *pq = desc->pq; | |
962 | struct ioat_raw_descriptor *descs[] = { (void *)pq, | |
963 | (void *)pq, | |
964 | (void *)pq }; | |
965 | int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); | |
966 | int i; | |
967 | ||
968 | if (desc->sed) { | |
969 | descs[1] = (void *)desc->sed->hw; | |
970 | descs[2] = (void *)desc->sed->hw + 64; | |
971 | } | |
972 | ||
973 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
974 | " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" | |
975 | " src_cnt: %d)\n", | |
976 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
977 | (unsigned long long) pq->next, | |
978 | desc->txd.flags, pq->size, pq->ctl, | |
979 | pq->ctl_f.op, pq->ctl_f.int_en, | |
980 | pq->ctl_f.compl_write, | |
981 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
982 | pq->ctl_f.src_cnt); | |
983 | for (i = 0; i < src_cnt; i++) { | |
984 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
985 | (unsigned long long) pq16_get_src(descs, i), | |
986 | pq->coef[i]); | |
987 | } | |
988 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
989 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
990 | } | |
991 | ||
d69d235b DW |
992 | static struct dma_async_tx_descriptor * |
993 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
994 | const dma_addr_t *dst, const dma_addr_t *src, | |
995 | unsigned int src_cnt, const unsigned char *scf, | |
996 | size_t len, unsigned long flags) | |
997 | { | |
998 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
999 | struct ioat_chan_common *chan = &ioat->base; | |
e0884772 | 1000 | struct ioatdma_device *device = chan->device; |
d69d235b DW |
1001 | struct ioat_ring_ent *compl_desc; |
1002 | struct ioat_ring_ent *desc; | |
1003 | struct ioat_ring_ent *ext; | |
1004 | size_t total_len = len; | |
1005 | struct ioat_pq_descriptor *pq; | |
1006 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
1007 | struct ioat_dma_descriptor *hw; | |
1008 | u32 offset = 0; | |
d69d235b | 1009 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
074cc476 | 1010 | int i, s, idx, with_ext, num_descs; |
e0884772 | 1011 | int cb32 = (device->version < IOAT_VER_3_3) ? 1 : 0; |
d69d235b DW |
1012 | |
1013 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
1014 | /* the engine requires at least two sources (we provide | |
1015 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
1016 | */ | |
1017 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
1018 | ||
1019 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
1020 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
1021 | * sources (we need 1 extra source in the q-only continuation |
1022 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 1023 | */ |
cd78809f DW |
1024 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
1025 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
1026 | with_ext = 1; |
1027 | num_descs *= 2; | |
1028 | } else | |
1029 | with_ext = 0; | |
1030 | ||
1031 | /* completion writes from the raid engine may pass completion | |
1032 | * writes from the legacy engine, so we need one extra null | |
1033 | * (legacy) descriptor to ensure all completion writes arrive in | |
1034 | * order. | |
1035 | */ | |
1036 | if (likely(num_descs) && | |
e0884772 | 1037 | ioat2_check_space_lock(ioat, num_descs + cb32) == 0) |
074cc476 | 1038 | idx = ioat->head; |
d69d235b DW |
1039 | else |
1040 | return NULL; | |
cdef57db DW |
1041 | i = 0; |
1042 | do { | |
d69d235b DW |
1043 | struct ioat_raw_descriptor *descs[2]; |
1044 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
1045 | ||
1046 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
1047 | pq = desc->pq; | |
1048 | ||
1049 | /* save a branch by unconditionally retrieving the | |
1050 | * extended descriptor pq_set_src() knows to not write | |
1051 | * to it in the single descriptor case | |
1052 | */ | |
1053 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
1054 | pq_ex = ext->pq_ex; | |
1055 | ||
1056 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
1057 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
1058 | ||
1059 | for (s = 0; s < src_cnt; s++) | |
1060 | pq_set_src(descs, src[s], offset, scf[s], s); | |
1061 | ||
1062 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
1063 | if (dmaf_p_disabled_continue(flags)) | |
1064 | pq_set_src(descs, dst[1], offset, 1, s++); | |
1065 | else if (dmaf_continue(flags)) { | |
1066 | pq_set_src(descs, dst[0], offset, 0, s++); | |
1067 | pq_set_src(descs, dst[1], offset, 1, s++); | |
1068 | pq_set_src(descs, dst[1], offset, 0, s++); | |
1069 | } | |
1070 | pq->size = xfer_size; | |
1071 | pq->p_addr = dst[0] + offset; | |
1072 | pq->q_addr = dst[1] + offset; | |
1073 | pq->ctl = 0; | |
1074 | pq->ctl_f.op = op; | |
75c6f0ab DJ |
1075 | /* we turn on descriptor write back error status */ |
1076 | if (device->cap & IOAT_CAP_DWBES) | |
1077 | pq->ctl_f.wb_en = result ? 1 : 0; | |
d69d235b DW |
1078 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); |
1079 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
1080 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
1081 | ||
1082 | len -= xfer_size; | |
1083 | offset += xfer_size; | |
cdef57db | 1084 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
1085 | |
1086 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
1087 | desc->txd.flags = flags; | |
1088 | desc->len = total_len; | |
1089 | if (result) | |
1090 | desc->result = result; | |
1091 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1092 | dump_pq_desc_dbg(ioat, desc, ext); | |
1093 | ||
e0884772 DJ |
1094 | if (!cb32) { |
1095 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1096 | pq->ctl_f.compl_write = 1; | |
1097 | compl_desc = desc; | |
1098 | } else { | |
1099 | /* completion descriptor carries interrupt bit */ | |
1100 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
1101 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
1102 | hw = compl_desc->hw; | |
1103 | hw->ctl = 0; | |
1104 | hw->ctl_f.null = 1; | |
1105 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1106 | hw->ctl_f.compl_write = 1; | |
1107 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1108 | dump_desc_dbg(ioat, compl_desc); | |
1109 | } | |
1110 | ||
d69d235b DW |
1111 | |
1112 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 1113 | return &compl_desc->txd; |
d69d235b DW |
1114 | } |
1115 | ||
7727eaa4 DJ |
1116 | static struct dma_async_tx_descriptor * |
1117 | __ioat3_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result, | |
1118 | const dma_addr_t *dst, const dma_addr_t *src, | |
1119 | unsigned int src_cnt, const unsigned char *scf, | |
1120 | size_t len, unsigned long flags) | |
1121 | { | |
1122 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1123 | struct ioat_chan_common *chan = &ioat->base; | |
1124 | struct ioatdma_device *device = chan->device; | |
1125 | struct ioat_ring_ent *desc; | |
1126 | size_t total_len = len; | |
1127 | struct ioat_pq_descriptor *pq; | |
1128 | u32 offset = 0; | |
1129 | u8 op; | |
1130 | int i, s, idx, num_descs; | |
1131 | ||
1132 | /* this function only handles src_cnt 9 - 16 */ | |
1133 | BUG_ON(src_cnt < 9); | |
1134 | ||
1135 | /* this function is only called with 9-16 sources */ | |
1136 | op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S; | |
1137 | ||
1138 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
1139 | ||
1140 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
1141 | ||
1142 | /* | |
1143 | * 16 source pq is only available on cb3.3 and has no completion | |
1144 | * write hw bug. | |
1145 | */ | |
1146 | if (num_descs && ioat2_check_space_lock(ioat, num_descs) == 0) | |
1147 | idx = ioat->head; | |
1148 | else | |
1149 | return NULL; | |
1150 | ||
1151 | i = 0; | |
1152 | ||
1153 | do { | |
1154 | struct ioat_raw_descriptor *descs[4]; | |
1155 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
1156 | ||
1157 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
1158 | pq = desc->pq; | |
1159 | ||
1160 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
1161 | ||
1162 | desc->sed = ioat3_alloc_sed(device, | |
1163 | sed_get_pq16_pool_idx(src_cnt)); | |
1164 | if (!desc->sed) { | |
1165 | dev_err(to_dev(chan), | |
1166 | "%s: no free sed entries\n", __func__); | |
1167 | return NULL; | |
1168 | } | |
1169 | ||
1170 | pq->sed_addr = desc->sed->dma; | |
1171 | desc->sed->parent = desc; | |
1172 | ||
1173 | descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw; | |
1174 | descs[2] = (void *)descs[1] + 64; | |
1175 | ||
1176 | for (s = 0; s < src_cnt; s++) | |
1177 | pq16_set_src(descs, src[s], offset, scf[s], s); | |
1178 | ||
1179 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
1180 | if (dmaf_p_disabled_continue(flags)) | |
1181 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1182 | else if (dmaf_continue(flags)) { | |
1183 | pq16_set_src(descs, dst[0], offset, 0, s++); | |
1184 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1185 | pq16_set_src(descs, dst[1], offset, 0, s++); | |
1186 | } | |
1187 | ||
1188 | pq->size = xfer_size; | |
1189 | pq->p_addr = dst[0] + offset; | |
1190 | pq->q_addr = dst[1] + offset; | |
1191 | pq->ctl = 0; | |
1192 | pq->ctl_f.op = op; | |
1193 | pq->ctl_f.src_cnt = src16_cnt_to_hw(s); | |
75c6f0ab DJ |
1194 | /* we turn on descriptor write back error status */ |
1195 | if (device->cap & IOAT_CAP_DWBES) | |
1196 | pq->ctl_f.wb_en = result ? 1 : 0; | |
7727eaa4 DJ |
1197 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); |
1198 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
1199 | ||
1200 | len -= xfer_size; | |
1201 | offset += xfer_size; | |
1202 | } while (++i < num_descs); | |
1203 | ||
1204 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
1205 | desc->txd.flags = flags; | |
1206 | desc->len = total_len; | |
1207 | if (result) | |
1208 | desc->result = result; | |
1209 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1210 | ||
1211 | /* with cb3.3 we should be able to do completion w/o a null desc */ | |
1212 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1213 | pq->ctl_f.compl_write = 1; | |
1214 | ||
1215 | dump_pq16_desc_dbg(ioat, desc); | |
1216 | ||
1217 | /* we leave the channel locked to ensure in order submission */ | |
1218 | return &desc->txd; | |
1219 | } | |
1220 | ||
d69d235b DW |
1221 | static struct dma_async_tx_descriptor * |
1222 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
1223 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1224 | unsigned long flags) | |
1225 | { | |
7727eaa4 DJ |
1226 | struct dma_device *dma = chan->device; |
1227 | ||
de581b65 DW |
1228 | /* specify valid address for disabled result */ |
1229 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1230 | dst[0] = dst[1]; | |
1231 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1232 | dst[1] = dst[0]; | |
1233 | ||
d69d235b DW |
1234 | /* handle the single source multiply case from the raid6 |
1235 | * recovery path | |
1236 | */ | |
de581b65 | 1237 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
1238 | dma_addr_t single_source[2]; |
1239 | unsigned char single_source_coef[2]; | |
1240 | ||
1241 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
1242 | single_source[0] = src[0]; | |
1243 | single_source[1] = src[0]; | |
1244 | single_source_coef[0] = scf[0]; | |
1245 | single_source_coef[1] = 0; | |
1246 | ||
7727eaa4 DJ |
1247 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1248 | __ioat3_prep_pq16_lock(chan, NULL, dst, single_source, | |
1249 | 2, single_source_coef, len, | |
1250 | flags) : | |
1251 | __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
1252 | single_source_coef, len, flags); | |
1253 | ||
1254 | } else { | |
1255 | return (src_cnt > 8) && (dma->max_pq > 8) ? | |
1256 | __ioat3_prep_pq16_lock(chan, NULL, dst, src, src_cnt, | |
1257 | scf, len, flags) : | |
1258 | __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, | |
1259 | scf, len, flags); | |
1260 | } | |
d69d235b DW |
1261 | } |
1262 | ||
1263 | struct dma_async_tx_descriptor * | |
1264 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
1265 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1266 | enum sum_check_flags *pqres, unsigned long flags) | |
1267 | { | |
7727eaa4 DJ |
1268 | struct dma_device *dma = chan->device; |
1269 | ||
de581b65 DW |
1270 | /* specify valid address for disabled result */ |
1271 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1272 | pq[0] = pq[1]; | |
1273 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1274 | pq[1] = pq[0]; | |
1275 | ||
d69d235b DW |
1276 | /* the cleanup routine only sets bits on validate failure, it |
1277 | * does not clear bits on validate success... so clear it here | |
1278 | */ | |
1279 | *pqres = 0; | |
1280 | ||
7727eaa4 DJ |
1281 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1282 | __ioat3_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
1283 | flags) : | |
1284 | __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
1285 | flags); | |
d69d235b DW |
1286 | } |
1287 | ||
ae786624 DW |
1288 | static struct dma_async_tx_descriptor * |
1289 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
1290 | unsigned int src_cnt, size_t len, unsigned long flags) | |
1291 | { | |
7727eaa4 | 1292 | struct dma_device *dma = chan->device; |
ae786624 DW |
1293 | unsigned char scf[src_cnt]; |
1294 | dma_addr_t pq[2]; | |
1295 | ||
1296 | memset(scf, 0, src_cnt); | |
ae786624 | 1297 | pq[0] = dst; |
de581b65 DW |
1298 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1299 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 | 1300 | |
7727eaa4 DJ |
1301 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1302 | __ioat3_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1303 | flags) : | |
1304 | __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1305 | flags); | |
ae786624 DW |
1306 | } |
1307 | ||
1308 | struct dma_async_tx_descriptor * | |
1309 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
1310 | unsigned int src_cnt, size_t len, | |
1311 | enum sum_check_flags *result, unsigned long flags) | |
1312 | { | |
7727eaa4 | 1313 | struct dma_device *dma = chan->device; |
ae786624 DW |
1314 | unsigned char scf[src_cnt]; |
1315 | dma_addr_t pq[2]; | |
1316 | ||
1317 | /* the cleanup routine only sets bits on validate failure, it | |
1318 | * does not clear bits on validate success... so clear it here | |
1319 | */ | |
1320 | *result = 0; | |
1321 | ||
1322 | memset(scf, 0, src_cnt); | |
ae786624 | 1323 | pq[0] = src[0]; |
de581b65 DW |
1324 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1325 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 | 1326 | |
7727eaa4 DJ |
1327 | |
1328 | return (src_cnt > 8) && (dma->max_pq > 8) ? | |
1329 | __ioat3_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1, | |
1330 | scf, len, flags) : | |
1331 | __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, | |
1332 | scf, len, flags); | |
ae786624 DW |
1333 | } |
1334 | ||
58c8649e DW |
1335 | static struct dma_async_tx_descriptor * |
1336 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
1337 | { | |
1338 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1339 | struct ioat_ring_ent *desc; | |
1340 | struct ioat_dma_descriptor *hw; | |
58c8649e | 1341 | |
074cc476 DW |
1342 | if (ioat2_check_space_lock(ioat, 1) == 0) |
1343 | desc = ioat2_get_ring_ent(ioat, ioat->head); | |
58c8649e DW |
1344 | else |
1345 | return NULL; | |
1346 | ||
1347 | hw = desc->hw; | |
1348 | hw->ctl = 0; | |
1349 | hw->ctl_f.null = 1; | |
1350 | hw->ctl_f.int_en = 1; | |
1351 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1352 | hw->ctl_f.compl_write = 1; | |
1353 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1354 | hw->src_addr = 0; | |
1355 | hw->dst_addr = 0; | |
1356 | ||
1357 | desc->txd.flags = flags; | |
1358 | desc->len = 1; | |
1359 | ||
1360 | dump_desc_dbg(ioat, desc); | |
1361 | ||
1362 | /* we leave the channel locked to ensure in order submission */ | |
1363 | return &desc->txd; | |
1364 | } | |
1365 | ||
4bf27b8b | 1366 | static void ioat3_dma_test_callback(void *dma_async_param) |
9de6fc71 DW |
1367 | { |
1368 | struct completion *cmp = dma_async_param; | |
1369 | ||
1370 | complete(cmp); | |
1371 | } | |
1372 | ||
1373 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
4bf27b8b | 1374 | static int ioat_xor_val_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1375 | { |
1376 | int i, src_idx; | |
1377 | struct page *dest; | |
1378 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
1379 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1380 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
48a9db46 | 1381 | dma_addr_t dest_dma; |
9de6fc71 DW |
1382 | struct dma_async_tx_descriptor *tx; |
1383 | struct dma_chan *dma_chan; | |
1384 | dma_cookie_t cookie; | |
1385 | u8 cmp_byte = 0; | |
1386 | u32 cmp_word; | |
1387 | u32 xor_val_result; | |
1388 | int err = 0; | |
1389 | struct completion cmp; | |
1390 | unsigned long tmo; | |
1391 | struct device *dev = &device->pdev->dev; | |
1392 | struct dma_device *dma = &device->common; | |
7369f56e | 1393 | u8 op = 0; |
9de6fc71 DW |
1394 | |
1395 | dev_dbg(dev, "%s\n", __func__); | |
1396 | ||
1397 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
1398 | return 0; | |
1399 | ||
1400 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1401 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
1402 | if (!xor_srcs[src_idx]) { | |
1403 | while (src_idx--) | |
1404 | __free_page(xor_srcs[src_idx]); | |
1405 | return -ENOMEM; | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | dest = alloc_page(GFP_KERNEL); | |
1410 | if (!dest) { | |
1411 | while (src_idx--) | |
1412 | __free_page(xor_srcs[src_idx]); | |
1413 | return -ENOMEM; | |
1414 | } | |
1415 | ||
1416 | /* Fill in src buffers */ | |
1417 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1418 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
1419 | for (i = 0; i < PAGE_SIZE; i++) | |
1420 | ptr[i] = (1 << src_idx); | |
1421 | } | |
1422 | ||
1423 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
1424 | cmp_byte ^= (u8) (1 << src_idx); | |
1425 | ||
1426 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
1427 | (cmp_byte << 8) | cmp_byte; | |
1428 | ||
1429 | memset(page_address(dest), 0, PAGE_SIZE); | |
1430 | ||
1431 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
1432 | device_node); | |
1433 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
1434 | err = -ENODEV; | |
1435 | goto out; | |
1436 | } | |
1437 | ||
1438 | /* test xor */ | |
7369f56e BZ |
1439 | op = IOAT_OP_XOR; |
1440 | ||
9de6fc71 DW |
1441 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
1442 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1443 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
1444 | DMA_TO_DEVICE); | |
1445 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
1446 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
7369f56e BZ |
1447 | DMA_PREP_INTERRUPT | |
1448 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1449 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1450 | |
1451 | if (!tx) { | |
1452 | dev_err(dev, "Self-test xor prep failed\n"); | |
1453 | err = -ENODEV; | |
7369f56e | 1454 | goto dma_unmap; |
9de6fc71 DW |
1455 | } |
1456 | ||
1457 | async_tx_ack(tx); | |
1458 | init_completion(&cmp); | |
1459 | tx->callback = ioat3_dma_test_callback; | |
1460 | tx->callback_param = &cmp; | |
1461 | cookie = tx->tx_submit(tx); | |
1462 | if (cookie < 0) { | |
1463 | dev_err(dev, "Self-test xor setup failed\n"); | |
1464 | err = -ENODEV; | |
7369f56e | 1465 | goto dma_unmap; |
9de6fc71 DW |
1466 | } |
1467 | dma->device_issue_pending(dma_chan); | |
1468 | ||
1469 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1470 | ||
07934481 | 1471 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1472 | dev_err(dev, "Self-test xor timed out\n"); |
1473 | err = -ENODEV; | |
7369f56e | 1474 | goto dma_unmap; |
9de6fc71 DW |
1475 | } |
1476 | ||
7369f56e BZ |
1477 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1478 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1479 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1480 | ||
9de6fc71 DW |
1481 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1482 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
1483 | u32 *ptr = page_address(dest); | |
1484 | if (ptr[i] != cmp_word) { | |
1485 | dev_err(dev, "Self-test xor failed compare\n"); | |
1486 | err = -ENODEV; | |
1487 | goto free_resources; | |
1488 | } | |
1489 | } | |
ac498987 | 1490 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
9de6fc71 DW |
1491 | |
1492 | /* skip validate if the capability is not present */ | |
1493 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
1494 | goto free_resources; | |
1495 | ||
7369f56e BZ |
1496 | op = IOAT_OP_XOR_VAL; |
1497 | ||
9de6fc71 DW |
1498 | /* validate the sources with the destintation page */ |
1499 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1500 | xor_val_srcs[i] = xor_srcs[i]; | |
1501 | xor_val_srcs[i] = dest; | |
1502 | ||
1503 | xor_val_result = 1; | |
1504 | ||
1505 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1506 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1507 | DMA_TO_DEVICE); | |
1508 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1509 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1510 | &xor_val_result, DMA_PREP_INTERRUPT | |
1511 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1512 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1513 | if (!tx) { |
1514 | dev_err(dev, "Self-test zero prep failed\n"); | |
1515 | err = -ENODEV; | |
7369f56e | 1516 | goto dma_unmap; |
9de6fc71 DW |
1517 | } |
1518 | ||
1519 | async_tx_ack(tx); | |
1520 | init_completion(&cmp); | |
1521 | tx->callback = ioat3_dma_test_callback; | |
1522 | tx->callback_param = &cmp; | |
1523 | cookie = tx->tx_submit(tx); | |
1524 | if (cookie < 0) { | |
1525 | dev_err(dev, "Self-test zero setup failed\n"); | |
1526 | err = -ENODEV; | |
7369f56e | 1527 | goto dma_unmap; |
9de6fc71 DW |
1528 | } |
1529 | dma->device_issue_pending(dma_chan); | |
1530 | ||
1531 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1532 | ||
07934481 | 1533 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1534 | dev_err(dev, "Self-test validate timed out\n"); |
1535 | err = -ENODEV; | |
7369f56e | 1536 | goto dma_unmap; |
9de6fc71 DW |
1537 | } |
1538 | ||
7369f56e BZ |
1539 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1540 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1541 | ||
9de6fc71 DW |
1542 | if (xor_val_result != 0) { |
1543 | dev_err(dev, "Self-test validate failed compare\n"); | |
1544 | err = -ENODEV; | |
1545 | goto free_resources; | |
1546 | } | |
1547 | ||
9de6fc71 | 1548 | /* test for non-zero parity sum */ |
7369f56e BZ |
1549 | op = IOAT_OP_XOR_VAL; |
1550 | ||
9de6fc71 DW |
1551 | xor_val_result = 0; |
1552 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1553 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1554 | DMA_TO_DEVICE); | |
1555 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1556 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1557 | &xor_val_result, DMA_PREP_INTERRUPT | |
1558 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1559 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1560 | if (!tx) { |
1561 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1562 | err = -ENODEV; | |
7369f56e | 1563 | goto dma_unmap; |
9de6fc71 DW |
1564 | } |
1565 | ||
1566 | async_tx_ack(tx); | |
1567 | init_completion(&cmp); | |
1568 | tx->callback = ioat3_dma_test_callback; | |
1569 | tx->callback_param = &cmp; | |
1570 | cookie = tx->tx_submit(tx); | |
1571 | if (cookie < 0) { | |
1572 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1573 | err = -ENODEV; | |
7369f56e | 1574 | goto dma_unmap; |
9de6fc71 DW |
1575 | } |
1576 | dma->device_issue_pending(dma_chan); | |
1577 | ||
1578 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1579 | ||
07934481 | 1580 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1581 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
1582 | err = -ENODEV; | |
7369f56e | 1583 | goto dma_unmap; |
9de6fc71 DW |
1584 | } |
1585 | ||
1586 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1587 | dev_err(dev, "Self-test validate failed compare\n"); | |
1588 | err = -ENODEV; | |
7369f56e | 1589 | goto dma_unmap; |
9de6fc71 DW |
1590 | } |
1591 | ||
7369f56e BZ |
1592 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1593 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1594 | ||
1595 | goto free_resources; | |
1596 | dma_unmap: | |
1597 | if (op == IOAT_OP_XOR) { | |
1598 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
1599 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1600 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1601 | DMA_TO_DEVICE); | |
1602 | } else if (op == IOAT_OP_XOR_VAL) { | |
1603 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1604 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1605 | DMA_TO_DEVICE); | |
48a9db46 | 1606 | } |
9de6fc71 DW |
1607 | free_resources: |
1608 | dma->device_free_chan_resources(dma_chan); | |
1609 | out: | |
1610 | src_idx = IOAT_NUM_SRC_TEST; | |
1611 | while (src_idx--) | |
1612 | __free_page(xor_srcs[src_idx]); | |
1613 | __free_page(dest); | |
1614 | return err; | |
1615 | } | |
1616 | ||
4bf27b8b | 1617 | static int ioat3_dma_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1618 | { |
1619 | int rc = ioat_dma_self_test(device); | |
1620 | ||
1621 | if (rc) | |
1622 | return rc; | |
1623 | ||
1624 | rc = ioat_xor_val_self_test(device); | |
1625 | if (rc) | |
1626 | return rc; | |
1627 | ||
1628 | return 0; | |
1629 | } | |
1630 | ||
8a52b9ff DJ |
1631 | static int ioat3_irq_reinit(struct ioatdma_device *device) |
1632 | { | |
1633 | int msixcnt = device->common.chancnt; | |
1634 | struct pci_dev *pdev = device->pdev; | |
1635 | int i; | |
1636 | struct msix_entry *msix; | |
1637 | struct ioat_chan_common *chan; | |
1638 | int err = 0; | |
1639 | ||
1640 | switch (device->irq_mode) { | |
1641 | case IOAT_MSIX: | |
1642 | ||
1643 | for (i = 0; i < msixcnt; i++) { | |
1644 | msix = &device->msix_entries[i]; | |
1645 | chan = ioat_chan_by_index(device, i); | |
1646 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1647 | } | |
1648 | ||
1649 | pci_disable_msix(pdev); | |
1650 | break; | |
1651 | ||
1652 | case IOAT_MSIX_SINGLE: | |
1653 | msix = &device->msix_entries[0]; | |
1654 | chan = ioat_chan_by_index(device, 0); | |
1655 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1656 | pci_disable_msix(pdev); | |
1657 | break; | |
1658 | ||
1659 | case IOAT_MSI: | |
1660 | chan = ioat_chan_by_index(device, 0); | |
1661 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1662 | pci_disable_msi(pdev); | |
1663 | break; | |
1664 | ||
1665 | case IOAT_INTX: | |
1666 | chan = ioat_chan_by_index(device, 0); | |
1667 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1668 | break; | |
1669 | ||
1670 | default: | |
1671 | return 0; | |
1672 | } | |
1673 | ||
1674 | device->irq_mode = IOAT_NOIRQ; | |
1675 | ||
1676 | err = ioat_dma_setup_interrupts(device); | |
1677 | ||
1678 | return err; | |
1679 | } | |
1680 | ||
a6d52d70 DW |
1681 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1682 | { | |
1683 | /* throw away whatever the channel was doing and get it | |
1684 | * initialized, with ioat3 specific workarounds | |
1685 | */ | |
1686 | struct ioatdma_device *device = chan->device; | |
1687 | struct pci_dev *pdev = device->pdev; | |
1688 | u32 chanerr; | |
1689 | u16 dev_id; | |
1690 | int err; | |
1691 | ||
1692 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1693 | ||
1694 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1695 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1696 | ||
6ead7e48 DJ |
1697 | if (device->version < IOAT_VER_3_3) { |
1698 | /* clear any pending errors */ | |
1699 | err = pci_read_config_dword(pdev, | |
1700 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1701 | if (err) { | |
1702 | dev_err(&pdev->dev, | |
1703 | "channel error register unreachable\n"); | |
1704 | return err; | |
1705 | } | |
1706 | pci_write_config_dword(pdev, | |
1707 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
a6d52d70 | 1708 | |
6ead7e48 DJ |
1709 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
1710 | * (workaround for spurious config parity error after restart) | |
1711 | */ | |
1712 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1713 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1714 | pci_write_config_dword(pdev, | |
1715 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1716 | 0x10); | |
1717 | } | |
1718 | } | |
a6d52d70 | 1719 | |
8a52b9ff DJ |
1720 | err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
1721 | if (err) { | |
1722 | dev_err(&pdev->dev, "Failed to reset!\n"); | |
1723 | return err; | |
570727b5 DJ |
1724 | } |
1725 | ||
8a52b9ff DJ |
1726 | if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev)) |
1727 | err = ioat3_irq_reinit(device); | |
570727b5 | 1728 | |
8a52b9ff | 1729 | return err; |
570727b5 DJ |
1730 | } |
1731 | ||
75c6f0ab DJ |
1732 | static void ioat3_intr_quirk(struct ioatdma_device *device) |
1733 | { | |
1734 | struct dma_device *dma; | |
1735 | struct dma_chan *c; | |
1736 | struct ioat_chan_common *chan; | |
1737 | u32 errmask; | |
1738 | ||
1739 | dma = &device->common; | |
1740 | ||
1741 | /* | |
1742 | * if we have descriptor write back error status, we mask the | |
1743 | * error interrupts | |
1744 | */ | |
1745 | if (device->cap & IOAT_CAP_DWBES) { | |
1746 | list_for_each_entry(c, &dma->channels, device_node) { | |
1747 | chan = to_chan_common(c); | |
1748 | errmask = readl(chan->reg_base + | |
1749 | IOAT_CHANERR_MASK_OFFSET); | |
1750 | errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | | |
1751 | IOAT_CHANERR_XOR_Q_ERR; | |
1752 | writel(errmask, chan->reg_base + | |
1753 | IOAT_CHANERR_MASK_OFFSET); | |
1754 | } | |
1755 | } | |
1756 | } | |
1757 | ||
4bf27b8b | 1758 | int ioat3_dma_probe(struct ioatdma_device *device, int dca) |
bf40a686 DW |
1759 | { |
1760 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1761 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1762 | struct dma_device *dma; |
1763 | struct dma_chan *c; | |
1764 | struct ioat_chan_common *chan; | |
e3232714 | 1765 | bool is_raid_device = false; |
bf40a686 | 1766 | int err; |
bf40a686 DW |
1767 | |
1768 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1769 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1770 | device->self_test = ioat3_dma_self_test; |
75c6f0ab | 1771 | device->intr_quirk = ioat3_intr_quirk; |
bf40a686 DW |
1772 | dma = &device->common; |
1773 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1774 | dma->device_issue_pending = ioat2_issue_pending; | |
1775 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1776 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e | 1777 | |
570727b5 | 1778 | if (is_xeon_cb32(pdev)) |
f26df1a1 DJ |
1779 | dma->copy_align = 6; |
1780 | ||
58c8649e DW |
1781 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); |
1782 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1783 | ||
75c6f0ab | 1784 | device->cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c | 1785 | |
d302398d | 1786 | if (is_bwd_noraid(pdev)) |
75c6f0ab | 1787 | device->cap &= ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); |
d302398d | 1788 | |
228c4f5c | 1789 | /* dca is incompatible with raid operations */ |
75c6f0ab DJ |
1790 | if (dca_en && (device->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) |
1791 | device->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
228c4f5c | 1792 | |
75c6f0ab | 1793 | if (device->cap & IOAT_CAP_XOR) { |
e3232714 | 1794 | is_raid_device = true; |
b094ad3b | 1795 | dma->max_xor = 8; |
2adfc550 | 1796 | dma->xor_align = 6; |
b094ad3b DW |
1797 | |
1798 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1799 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1800 | ||
1801 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1802 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1803 | } | |
eceec44e | 1804 | |
75c6f0ab | 1805 | if (device->cap & IOAT_CAP_PQ) { |
e3232714 | 1806 | is_raid_device = true; |
7727eaa4 | 1807 | |
75c6f0ab DJ |
1808 | dma->device_prep_dma_pq = ioat3_prep_pq; |
1809 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
1810 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1811 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1812 | ||
1813 | if (device->cap & IOAT_CAP_RAID16SS) { | |
7727eaa4 | 1814 | dma_set_maxpq(dma, 16, 0); |
eceec44e | 1815 | dma->pq_align = 0; |
7727eaa4 DJ |
1816 | } else { |
1817 | dma_set_maxpq(dma, 8, 0); | |
1818 | if (is_xeon_cb32(pdev)) | |
1819 | dma->pq_align = 6; | |
1820 | else | |
1821 | dma->pq_align = 0; | |
1822 | } | |
d69d235b | 1823 | |
75c6f0ab DJ |
1824 | if (!(device->cap & IOAT_CAP_XOR)) { |
1825 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1826 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1827 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1828 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
ae786624 | 1829 | |
75c6f0ab | 1830 | if (device->cap & IOAT_CAP_RAID16SS) { |
7727eaa4 | 1831 | dma->max_xor = 16; |
eceec44e | 1832 | dma->xor_align = 0; |
7727eaa4 DJ |
1833 | } else { |
1834 | dma->max_xor = 8; | |
1835 | if (is_xeon_cb32(pdev)) | |
1836 | dma->xor_align = 6; | |
1837 | else | |
1838 | dma->xor_align = 0; | |
1839 | } | |
ae786624 | 1840 | } |
d69d235b | 1841 | } |
eceec44e | 1842 | |
9a37f644 DJ |
1843 | dma->device_tx_status = ioat3_tx_status; |
1844 | device->cleanup_fn = ioat3_cleanup_event; | |
1845 | device->timer_fn = ioat3_timer_event; | |
bf40a686 | 1846 | |
3f09ede4 DJ |
1847 | if (is_xeon_cb32(pdev)) { |
1848 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); | |
1849 | dma->device_prep_dma_xor_val = NULL; | |
7b3cc2b1 | 1850 | |
3f09ede4 DJ |
1851 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); |
1852 | dma->device_prep_dma_pq_val = NULL; | |
1853 | } | |
7b3cc2b1 | 1854 | |
7727eaa4 | 1855 | /* starting with CB3.3 super extended descriptors are supported */ |
75c6f0ab | 1856 | if (device->cap & IOAT_CAP_RAID16SS) { |
7727eaa4 DJ |
1857 | char pool_name[14]; |
1858 | int i; | |
1859 | ||
1860 | /* allocate sw descriptor pool for SED */ | |
1861 | device->sed_pool = kmem_cache_create("ioat_sed", | |
1862 | sizeof(struct ioat_sed_ent), 0, 0, NULL); | |
1863 | if (!device->sed_pool) | |
1864 | return -ENOMEM; | |
1865 | ||
1866 | for (i = 0; i < MAX_SED_POOLS; i++) { | |
1867 | snprintf(pool_name, 14, "ioat_hw%d_sed", i); | |
1868 | ||
1869 | /* allocate SED DMA pool */ | |
1870 | device->sed_hw_pool[i] = dma_pool_create(pool_name, | |
1871 | &pdev->dev, | |
1872 | SED_SIZE * (i + 1), 64, 0); | |
1873 | if (!device->sed_hw_pool[i]) | |
1874 | goto sed_pool_cleanup; | |
1875 | ||
1876 | } | |
1877 | } | |
1878 | ||
bf40a686 DW |
1879 | err = ioat_probe(device); |
1880 | if (err) | |
1881 | return err; | |
1882 | ioat_set_tcp_copy_break(262144); | |
1883 | ||
1884 | list_for_each_entry(c, &dma->channels, device_node) { | |
1885 | chan = to_chan_common(c); | |
1886 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1887 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1888 | } | |
1889 | ||
1890 | err = ioat_register(device); | |
1891 | if (err) | |
1892 | return err; | |
5669e31c DW |
1893 | |
1894 | ioat_kobject_add(device, &ioat2_ktype); | |
1895 | ||
bf40a686 DW |
1896 | if (dca) |
1897 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1898 | ||
1899 | return 0; | |
7727eaa4 DJ |
1900 | |
1901 | sed_pool_cleanup: | |
1902 | if (device->sed_pool) { | |
1903 | int i; | |
1904 | kmem_cache_destroy(device->sed_pool); | |
1905 | ||
1906 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1907 | if (device->sed_hw_pool[i]) | |
1908 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1909 | } | |
1910 | ||
1911 | return -ENOMEM; | |
1912 | } | |
1913 | ||
1914 | void ioat3_dma_remove(struct ioatdma_device *device) | |
1915 | { | |
1916 | if (device->sed_pool) { | |
1917 | int i; | |
1918 | kmem_cache_destroy(device->sed_pool); | |
1919 | ||
1920 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1921 | if (device->sed_hw_pool[i]) | |
1922 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1923 | } | |
bf40a686 | 1924 | } |