Commit | Line | Data |
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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
7727eaa4 | 58 | #include <linux/module.h> |
bf40a686 | 59 | #include <linux/pci.h> |
5a0e3ad6 | 60 | #include <linux/gfp.h> |
bf40a686 DW |
61 | #include <linux/dmaengine.h> |
62 | #include <linux/dma-mapping.h> | |
70c71606 | 63 | #include <linux/prefetch.h> |
949ff5b8 | 64 | #include "../dmaengine.h" |
bf40a686 DW |
65 | #include "registers.h" |
66 | #include "hw.h" | |
67 | #include "dma.h" | |
68 | #include "dma_v2.h" | |
69 | ||
b094ad3b DW |
70 | /* ioat hardware assumes at least two sources for raid operations */ |
71 | #define src_cnt_to_sw(x) ((x) + 2) | |
72 | #define src_cnt_to_hw(x) ((x) - 2) | |
7727eaa4 DJ |
73 | #define ndest_to_sw(x) ((x) + 1) |
74 | #define ndest_to_hw(x) ((x) - 1) | |
75 | #define src16_cnt_to_sw(x) ((x) + 9) | |
76 | #define src16_cnt_to_hw(x) ((x) - 9) | |
b094ad3b DW |
77 | |
78 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 79 | * extended descriptor of an xor or pq descriptor |
b094ad3b | 80 | */ |
d0b0c8c7 | 81 | static const u8 xor_idx_to_desc = 0xe0; |
9b487ced AK |
82 | static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
83 | static const u8 pq_idx_to_desc = 0xf8; | |
7727eaa4 DJ |
84 | static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1, |
85 | 2, 2, 2, 2, 2, 2, 2 }; | |
9b487ced | 86 | static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; |
7727eaa4 DJ |
87 | static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7, |
88 | 0, 1, 2, 3, 4, 5, 6 }; | |
89 | ||
3f09ede4 DJ |
90 | static void ioat3_eh(struct ioat2_dma_chan *ioat); |
91 | ||
b094ad3b DW |
92 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], |
93 | dma_addr_t addr, u32 offset, int idx) | |
94 | { | |
95 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
96 | ||
97 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
98 | } | |
99 | ||
d69d235b DW |
100 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
101 | { | |
102 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
103 | ||
104 | return raw->field[pq_idx_to_field[idx]]; | |
105 | } | |
106 | ||
7727eaa4 DJ |
107 | static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx) |
108 | { | |
109 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
110 | ||
111 | return raw->field[pq16_idx_to_field[idx]]; | |
112 | } | |
113 | ||
d69d235b DW |
114 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], |
115 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
116 | { | |
117 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
118 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
119 | ||
120 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
121 | pq->coef[idx] = coef; | |
122 | } | |
123 | ||
8a52b9ff DJ |
124 | static bool is_jf_ioat(struct pci_dev *pdev) |
125 | { | |
126 | switch (pdev->device) { | |
127 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: | |
128 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: | |
129 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: | |
130 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: | |
131 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: | |
132 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: | |
133 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: | |
134 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: | |
135 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: | |
136 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: | |
137 | return true; | |
138 | default: | |
139 | return false; | |
140 | } | |
141 | } | |
142 | ||
143 | static bool is_snb_ioat(struct pci_dev *pdev) | |
144 | { | |
145 | switch (pdev->device) { | |
146 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: | |
147 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: | |
148 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: | |
149 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: | |
150 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: | |
151 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: | |
152 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: | |
153 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: | |
154 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: | |
155 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: | |
156 | return true; | |
157 | default: | |
158 | return false; | |
159 | } | |
160 | } | |
161 | ||
162 | static bool is_ivb_ioat(struct pci_dev *pdev) | |
163 | { | |
164 | switch (pdev->device) { | |
165 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: | |
166 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: | |
167 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: | |
168 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: | |
169 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: | |
170 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: | |
171 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: | |
172 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: | |
173 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: | |
174 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: | |
175 | return true; | |
176 | default: | |
177 | return false; | |
178 | } | |
179 | ||
180 | } | |
181 | ||
182 | static bool is_hsw_ioat(struct pci_dev *pdev) | |
183 | { | |
184 | switch (pdev->device) { | |
185 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: | |
186 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: | |
187 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: | |
188 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: | |
189 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: | |
190 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: | |
191 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: | |
192 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: | |
193 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: | |
194 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: | |
195 | return true; | |
196 | default: | |
197 | return false; | |
198 | } | |
199 | ||
200 | } | |
201 | ||
202 | static bool is_xeon_cb32(struct pci_dev *pdev) | |
203 | { | |
204 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || | |
205 | is_hsw_ioat(pdev); | |
206 | } | |
207 | ||
208 | static bool is_bwd_ioat(struct pci_dev *pdev) | |
209 | { | |
210 | switch (pdev->device) { | |
211 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: | |
212 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: | |
213 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
214 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
215 | return true; | |
216 | default: | |
217 | return false; | |
218 | } | |
219 | } | |
220 | ||
d302398d DJ |
221 | static bool is_bwd_noraid(struct pci_dev *pdev) |
222 | { | |
223 | switch (pdev->device) { | |
224 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
225 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
226 | return true; | |
227 | default: | |
228 | return false; | |
229 | } | |
230 | ||
231 | } | |
232 | ||
7727eaa4 | 233 | static void pq16_set_src(struct ioat_raw_descriptor *desc[3], |
e6a5fa63 | 234 | dma_addr_t addr, u32 offset, u8 coef, unsigned idx) |
7727eaa4 DJ |
235 | { |
236 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0]; | |
237 | struct ioat_pq16a_descriptor *pq16 = | |
238 | (struct ioat_pq16a_descriptor *)desc[1]; | |
239 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
240 | ||
241 | raw->field[pq16_idx_to_field[idx]] = addr + offset; | |
242 | ||
243 | if (idx < 8) | |
244 | pq->coef[idx] = coef; | |
245 | else | |
246 | pq16->coef[idx - 8] = coef; | |
247 | } | |
248 | ||
e6a30fec | 249 | static struct ioat_sed_ent * |
7727eaa4 DJ |
250 | ioat3_alloc_sed(struct ioatdma_device *device, unsigned int hw_pool) |
251 | { | |
252 | struct ioat_sed_ent *sed; | |
253 | gfp_t flags = __GFP_ZERO | GFP_ATOMIC; | |
254 | ||
255 | sed = kmem_cache_alloc(device->sed_pool, flags); | |
256 | if (!sed) | |
257 | return NULL; | |
258 | ||
259 | sed->hw_pool = hw_pool; | |
260 | sed->hw = dma_pool_alloc(device->sed_hw_pool[hw_pool], | |
261 | flags, &sed->dma); | |
262 | if (!sed->hw) { | |
263 | kmem_cache_free(device->sed_pool, sed); | |
264 | return NULL; | |
265 | } | |
266 | ||
267 | return sed; | |
268 | } | |
269 | ||
e6a30fec | 270 | static void ioat3_free_sed(struct ioatdma_device *device, struct ioat_sed_ent *sed) |
7727eaa4 DJ |
271 | { |
272 | if (!sed) | |
273 | return; | |
274 | ||
275 | dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
276 | kmem_cache_free(device->sed_pool, sed); | |
277 | } | |
278 | ||
b094ad3b DW |
279 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
280 | { | |
281 | struct ioat_dma_descriptor *hw = desc->hw; | |
282 | ||
283 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
284 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
285 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 286 | |
b094ad3b DW |
287 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
288 | return true; | |
d69d235b DW |
289 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
290 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
291 | struct ioat_pq_descriptor *pq = desc->pq; | |
292 | ||
293 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
294 | return true; | |
b094ad3b DW |
295 | } |
296 | ||
297 | return false; | |
298 | } | |
299 | ||
3f09ede4 DJ |
300 | static u64 ioat3_get_current_completion(struct ioat_chan_common *chan) |
301 | { | |
302 | u64 phys_complete; | |
303 | u64 completion; | |
304 | ||
305 | completion = *chan->completion; | |
306 | phys_complete = ioat_chansts_to_addr(completion); | |
307 | ||
308 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, | |
309 | (unsigned long long) phys_complete); | |
310 | ||
311 | return phys_complete; | |
312 | } | |
313 | ||
314 | static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan, | |
315 | u64 *phys_complete) | |
316 | { | |
317 | *phys_complete = ioat3_get_current_completion(chan); | |
318 | if (*phys_complete == chan->last_completion) | |
319 | return false; | |
320 | ||
321 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); | |
322 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
323 | ||
324 | return true; | |
325 | } | |
326 | ||
75c6f0ab DJ |
327 | static void |
328 | desc_get_errstat(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc) | |
329 | { | |
330 | struct ioat_dma_descriptor *hw = desc->hw; | |
331 | ||
332 | switch (hw->ctl_f.op) { | |
333 | case IOAT_OP_PQ_VAL: | |
334 | case IOAT_OP_PQ_VAL_16S: | |
335 | { | |
336 | struct ioat_pq_descriptor *pq = desc->pq; | |
337 | ||
338 | /* check if there's error written */ | |
339 | if (!pq->dwbes_f.wbes) | |
340 | return; | |
341 | ||
342 | /* need to set a chanerr var for checking to clear later */ | |
343 | ||
344 | if (pq->dwbes_f.p_val_err) | |
345 | *desc->result |= SUM_CHECK_P_RESULT; | |
346 | ||
347 | if (pq->dwbes_f.q_val_err) | |
348 | *desc->result |= SUM_CHECK_Q_RESULT; | |
349 | ||
350 | return; | |
351 | } | |
352 | default: | |
353 | return; | |
354 | } | |
355 | } | |
356 | ||
b094ad3b DW |
357 | /** |
358 | * __cleanup - reclaim used descriptors | |
359 | * @ioat: channel (ring) to clean | |
360 | * | |
361 | * The difference from the dma_v2.c __cleanup() is that this routine | |
362 | * handles extended descriptors and dma-unmapping raid operations. | |
363 | */ | |
27502935 | 364 | static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete) |
bf40a686 DW |
365 | { |
366 | struct ioat_chan_common *chan = &ioat->base; | |
7727eaa4 | 367 | struct ioatdma_device *device = chan->device; |
bf40a686 DW |
368 | struct ioat_ring_ent *desc; |
369 | bool seen_current = false; | |
074cc476 | 370 | int idx = ioat->tail, i; |
bf40a686 | 371 | u16 active; |
bf40a686 DW |
372 | |
373 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
374 | __func__, ioat->head, ioat->tail, ioat->issued); | |
375 | ||
3f09ede4 DJ |
376 | /* |
377 | * At restart of the channel, the completion address and the | |
378 | * channel status will be 0 due to starting a new chain. Since | |
379 | * it's new chain and the first descriptor "fails", there is | |
380 | * nothing to clean up. We do not want to reap the entire submitted | |
381 | * chain due to this 0 address value and then BUG. | |
382 | */ | |
383 | if (!phys_complete) | |
384 | return; | |
385 | ||
bf40a686 DW |
386 | active = ioat2_ring_active(ioat); |
387 | for (i = 0; i < active && !seen_current; i++) { | |
388 | struct dma_async_tx_descriptor *tx; | |
389 | ||
074cc476 DW |
390 | smp_read_barrier_depends(); |
391 | prefetch(ioat2_get_ring_ent(ioat, idx + i + 1)); | |
392 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
bf40a686 | 393 | dump_desc_dbg(ioat, desc); |
75c6f0ab DJ |
394 | |
395 | /* set err stat if we are using dwbes */ | |
396 | if (device->cap & IOAT_CAP_DWBES) | |
397 | desc_get_errstat(ioat, desc); | |
398 | ||
bf40a686 DW |
399 | tx = &desc->txd; |
400 | if (tx->cookie) { | |
f7fbce07 | 401 | dma_cookie_complete(tx); |
d38a8c62 | 402 | dma_descriptor_unmap(tx); |
bf40a686 DW |
403 | if (tx->callback) { |
404 | tx->callback(tx->callback_param); | |
405 | tx->callback = NULL; | |
406 | } | |
407 | } | |
408 | ||
409 | if (tx->phys == phys_complete) | |
410 | seen_current = true; | |
b094ad3b DW |
411 | |
412 | /* skip extended descriptors */ | |
413 | if (desc_has_ext(desc)) { | |
414 | BUG_ON(i + 1 >= active); | |
415 | i++; | |
416 | } | |
7727eaa4 DJ |
417 | |
418 | /* cleanup super extended descriptors */ | |
419 | if (desc->sed) { | |
420 | ioat3_free_sed(device, desc->sed); | |
421 | desc->sed = NULL; | |
422 | } | |
bf40a686 | 423 | } |
074cc476 DW |
424 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
425 | ioat->tail = idx + i; | |
aa75db00 | 426 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
bf40a686 | 427 | chan->last_completion = phys_complete; |
b9cc9869 | 428 | |
074cc476 | 429 | if (active - i == 0) { |
bf40a686 DW |
430 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
431 | __func__); | |
432 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
433 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
434 | } | |
b9cc9869 | 435 | /* 5 microsecond delay per pending descriptor */ |
074cc476 | 436 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
b9cc9869 | 437 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); |
bf40a686 DW |
438 | } |
439 | ||
074cc476 | 440 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) |
bf40a686 DW |
441 | { |
442 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 443 | u64 phys_complete; |
bf40a686 | 444 | |
b9cc9869 | 445 | spin_lock_bh(&chan->cleanup_lock); |
3f09ede4 DJ |
446 | |
447 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
074cc476 | 448 | __cleanup(ioat, phys_complete); |
3f09ede4 DJ |
449 | |
450 | if (is_ioat_halted(*chan->completion)) { | |
451 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
452 | ||
453 | if (chanerr & IOAT_CHANERR_HANDLE_MASK) { | |
454 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
455 | ioat3_eh(ioat); | |
456 | } | |
457 | } | |
458 | ||
b9cc9869 DW |
459 | spin_unlock_bh(&chan->cleanup_lock); |
460 | } | |
461 | ||
aa4d72ae | 462 | static void ioat3_cleanup_event(unsigned long data) |
bf40a686 | 463 | { |
aa4d72ae | 464 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
bf40a686 | 465 | |
074cc476 | 466 | ioat3_cleanup(ioat); |
773d9e2d | 467 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
468 | } |
469 | ||
470 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
471 | { | |
472 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 473 | u64 phys_complete; |
bf40a686 | 474 | |
b372ec2d | 475 | ioat2_quiesce(chan, 0); |
3f09ede4 | 476 | if (ioat3_cleanup_preamble(chan, &phys_complete)) |
bf40a686 DW |
477 | __cleanup(ioat, phys_complete); |
478 | ||
479 | __ioat2_restart_chan(ioat); | |
480 | } | |
481 | ||
3f09ede4 DJ |
482 | static void ioat3_eh(struct ioat2_dma_chan *ioat) |
483 | { | |
484 | struct ioat_chan_common *chan = &ioat->base; | |
485 | struct pci_dev *pdev = to_pdev(chan); | |
486 | struct ioat_dma_descriptor *hw; | |
487 | u64 phys_complete; | |
488 | struct ioat_ring_ent *desc; | |
489 | u32 err_handled = 0; | |
490 | u32 chanerr_int; | |
491 | u32 chanerr; | |
492 | ||
493 | /* cleanup so tail points to descriptor that caused the error */ | |
494 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
495 | __cleanup(ioat, phys_complete); | |
496 | ||
497 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
498 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
499 | ||
500 | dev_dbg(to_dev(chan), "%s: error = %x:%x\n", | |
501 | __func__, chanerr, chanerr_int); | |
502 | ||
503 | desc = ioat2_get_ring_ent(ioat, ioat->tail); | |
504 | hw = desc->hw; | |
505 | dump_desc_dbg(ioat, desc); | |
506 | ||
507 | switch (hw->ctl_f.op) { | |
508 | case IOAT_OP_XOR_VAL: | |
509 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
510 | *desc->result |= SUM_CHECK_P_RESULT; | |
511 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
512 | } | |
513 | break; | |
514 | case IOAT_OP_PQ_VAL: | |
7727eaa4 | 515 | case IOAT_OP_PQ_VAL_16S: |
3f09ede4 DJ |
516 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { |
517 | *desc->result |= SUM_CHECK_P_RESULT; | |
518 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
519 | } | |
520 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
521 | *desc->result |= SUM_CHECK_Q_RESULT; | |
522 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
523 | } | |
524 | break; | |
525 | } | |
526 | ||
527 | /* fault on unhandled error or spurious halt */ | |
528 | if (chanerr ^ err_handled || chanerr == 0) { | |
529 | dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n", | |
530 | __func__, chanerr, err_handled); | |
531 | BUG(); | |
532 | } | |
533 | ||
534 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
535 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
536 | ||
537 | /* mark faulting descriptor as complete */ | |
538 | *chan->completion = desc->txd.phys; | |
539 | ||
540 | spin_lock_bh(&ioat->prep_lock); | |
541 | ioat3_restart_channel(ioat); | |
542 | spin_unlock_bh(&ioat->prep_lock); | |
543 | } | |
544 | ||
4dec23d7 | 545 | static void check_active(struct ioat2_dma_chan *ioat) |
bf40a686 | 546 | { |
bf40a686 DW |
547 | struct ioat_chan_common *chan = &ioat->base; |
548 | ||
4dec23d7 DJ |
549 | if (ioat2_ring_active(ioat)) { |
550 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
551 | return; | |
552 | } | |
bf40a686 | 553 | |
4dec23d7 DJ |
554 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state)) |
555 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
556 | else if (ioat->alloc_order > ioat_get_alloc_order()) { | |
bf40a686 DW |
557 | /* if the ring is idle, empty, and oversized try to step |
558 | * down the size | |
559 | */ | |
4dec23d7 | 560 | reshape_ring(ioat, ioat->alloc_order - 1); |
bf40a686 DW |
561 | |
562 | /* keep shrinking until we get back to our minimum | |
563 | * default size | |
564 | */ | |
565 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
566 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
567 | } | |
4dec23d7 DJ |
568 | |
569 | } | |
570 | ||
a20702b8 | 571 | static void ioat3_timer_event(unsigned long data) |
4dec23d7 DJ |
572 | { |
573 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); | |
574 | struct ioat_chan_common *chan = &ioat->base; | |
575 | dma_addr_t phys_complete; | |
576 | u64 status; | |
577 | ||
578 | status = ioat_chansts(chan); | |
579 | ||
580 | /* when halted due to errors check for channel | |
581 | * programming errors before advancing the completion state | |
582 | */ | |
583 | if (is_ioat_halted(status)) { | |
584 | u32 chanerr; | |
585 | ||
586 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
587 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", | |
588 | __func__, chanerr); | |
589 | if (test_bit(IOAT_RUN, &chan->state)) | |
590 | BUG_ON(is_ioat_bug(chanerr)); | |
591 | else /* we never got off the ground */ | |
592 | return; | |
593 | } | |
594 | ||
595 | /* if we haven't made progress and we have already | |
596 | * acknowledged a pending completion once, then be more | |
597 | * forceful with a restart | |
598 | */ | |
599 | spin_lock_bh(&chan->cleanup_lock); | |
600 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
601 | __cleanup(ioat, phys_complete); | |
602 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) { | |
603 | spin_lock_bh(&ioat->prep_lock); | |
604 | ioat3_restart_channel(ioat); | |
605 | spin_unlock_bh(&ioat->prep_lock); | |
606 | spin_unlock_bh(&chan->cleanup_lock); | |
607 | return; | |
608 | } else { | |
609 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
610 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
611 | } | |
612 | ||
613 | ||
614 | if (ioat2_ring_active(ioat)) | |
615 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
616 | else { | |
617 | spin_lock_bh(&ioat->prep_lock); | |
618 | check_active(ioat); | |
619 | spin_unlock_bh(&ioat->prep_lock); | |
620 | } | |
621 | spin_unlock_bh(&chan->cleanup_lock); | |
bf40a686 DW |
622 | } |
623 | ||
624 | static enum dma_status | |
07934481 LW |
625 | ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
626 | struct dma_tx_state *txstate) | |
bf40a686 DW |
627 | { |
628 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
96a2af41 | 629 | enum dma_status ret; |
bf40a686 | 630 | |
96a2af41 RKAL |
631 | ret = dma_cookie_status(c, cookie, txstate); |
632 | if (ret == DMA_SUCCESS) | |
633 | return ret; | |
bf40a686 | 634 | |
074cc476 | 635 | ioat3_cleanup(ioat); |
bf40a686 | 636 | |
96a2af41 | 637 | return dma_cookie_status(c, cookie, txstate); |
bf40a686 DW |
638 | } |
639 | ||
b094ad3b DW |
640 | static struct dma_async_tx_descriptor * |
641 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
642 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
643 | size_t len, unsigned long flags) | |
644 | { | |
645 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
646 | struct ioat_ring_ent *compl_desc; | |
647 | struct ioat_ring_ent *desc; | |
648 | struct ioat_ring_ent *ext; | |
649 | size_t total_len = len; | |
650 | struct ioat_xor_descriptor *xor; | |
651 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
652 | struct ioat_dma_descriptor *hw; | |
074cc476 | 653 | int num_descs, with_ext, idx, i; |
b094ad3b | 654 | u32 offset = 0; |
b094ad3b DW |
655 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
656 | ||
657 | BUG_ON(src_cnt < 2); | |
658 | ||
659 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
660 | /* we need 2x the number of descriptors to cover greater than 5 | |
661 | * sources | |
662 | */ | |
663 | if (src_cnt > 5) { | |
664 | with_ext = 1; | |
665 | num_descs *= 2; | |
666 | } else | |
667 | with_ext = 0; | |
668 | ||
669 | /* completion writes from the raid engine may pass completion | |
670 | * writes from the legacy engine, so we need one extra null | |
671 | * (legacy) descriptor to ensure all completion writes arrive in | |
672 | * order. | |
673 | */ | |
074cc476 DW |
674 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0) |
675 | idx = ioat->head; | |
b094ad3b DW |
676 | else |
677 | return NULL; | |
cdef57db DW |
678 | i = 0; |
679 | do { | |
b094ad3b DW |
680 | struct ioat_raw_descriptor *descs[2]; |
681 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
682 | int s; | |
683 | ||
684 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
685 | xor = desc->xor; | |
686 | ||
687 | /* save a branch by unconditionally retrieving the | |
688 | * extended descriptor xor_set_src() knows to not write | |
689 | * to it in the single descriptor case | |
690 | */ | |
691 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
692 | xor_ex = ext->xor_ex; | |
693 | ||
694 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
695 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
696 | for (s = 0; s < src_cnt; s++) | |
697 | xor_set_src(descs, src[s], offset, s); | |
698 | xor->size = xfer_size; | |
699 | xor->dst_addr = dest + offset; | |
700 | xor->ctl = 0; | |
701 | xor->ctl_f.op = op; | |
702 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
703 | ||
704 | len -= xfer_size; | |
705 | offset += xfer_size; | |
706 | dump_desc_dbg(ioat, desc); | |
cdef57db | 707 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
708 | |
709 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
710 | desc->txd.flags = flags; | |
711 | desc->len = total_len; | |
712 | if (result) | |
713 | desc->result = result; | |
714 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
715 | ||
716 | /* completion descriptor carries interrupt bit */ | |
717 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
718 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
719 | hw = compl_desc->hw; | |
720 | hw->ctl = 0; | |
721 | hw->ctl_f.null = 1; | |
722 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
723 | hw->ctl_f.compl_write = 1; | |
724 | hw->size = NULL_DESC_BUFFER_SIZE; | |
725 | dump_desc_dbg(ioat, compl_desc); | |
726 | ||
727 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 728 | return &compl_desc->txd; |
b094ad3b DW |
729 | } |
730 | ||
731 | static struct dma_async_tx_descriptor * | |
732 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
733 | unsigned int src_cnt, size_t len, unsigned long flags) | |
734 | { | |
735 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
736 | } | |
737 | ||
738 | struct dma_async_tx_descriptor * | |
739 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
740 | unsigned int src_cnt, size_t len, | |
741 | enum sum_check_flags *result, unsigned long flags) | |
742 | { | |
743 | /* the cleanup routine only sets bits on validate failure, it | |
744 | * does not clear bits on validate success... so clear it here | |
745 | */ | |
746 | *result = 0; | |
747 | ||
748 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
749 | src_cnt - 1, len, flags); | |
750 | } | |
751 | ||
d69d235b DW |
752 | static void |
753 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
754 | { | |
755 | struct device *dev = to_dev(&ioat->base); | |
756 | struct ioat_pq_descriptor *pq = desc->pq; | |
757 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
758 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
759 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
760 | int i; | |
761 | ||
762 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
7727eaa4 DJ |
763 | " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" |
764 | " src_cnt: %d)\n", | |
d69d235b DW |
765 | desc_id(desc), (unsigned long long) desc->txd.phys, |
766 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
767 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
768 | pq->ctl_f.compl_write, | |
769 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
770 | pq->ctl_f.src_cnt); | |
771 | for (i = 0; i < src_cnt; i++) | |
772 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
773 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
774 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
775 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
50f9f97e | 776 | dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
d69d235b DW |
777 | } |
778 | ||
7727eaa4 DJ |
779 | static void dump_pq16_desc_dbg(struct ioat2_dma_chan *ioat, |
780 | struct ioat_ring_ent *desc) | |
781 | { | |
782 | struct device *dev = to_dev(&ioat->base); | |
783 | struct ioat_pq_descriptor *pq = desc->pq; | |
784 | struct ioat_raw_descriptor *descs[] = { (void *)pq, | |
785 | (void *)pq, | |
786 | (void *)pq }; | |
787 | int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); | |
788 | int i; | |
789 | ||
790 | if (desc->sed) { | |
791 | descs[1] = (void *)desc->sed->hw; | |
792 | descs[2] = (void *)desc->sed->hw + 64; | |
793 | } | |
794 | ||
795 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
796 | " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" | |
797 | " src_cnt: %d)\n", | |
798 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
799 | (unsigned long long) pq->next, | |
800 | desc->txd.flags, pq->size, pq->ctl, | |
801 | pq->ctl_f.op, pq->ctl_f.int_en, | |
802 | pq->ctl_f.compl_write, | |
803 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
804 | pq->ctl_f.src_cnt); | |
805 | for (i = 0; i < src_cnt; i++) { | |
806 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
807 | (unsigned long long) pq16_get_src(descs, i), | |
808 | pq->coef[i]); | |
809 | } | |
810 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
811 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
812 | } | |
813 | ||
d69d235b DW |
814 | static struct dma_async_tx_descriptor * |
815 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
816 | const dma_addr_t *dst, const dma_addr_t *src, | |
817 | unsigned int src_cnt, const unsigned char *scf, | |
818 | size_t len, unsigned long flags) | |
819 | { | |
820 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
821 | struct ioat_chan_common *chan = &ioat->base; | |
e0884772 | 822 | struct ioatdma_device *device = chan->device; |
d69d235b DW |
823 | struct ioat_ring_ent *compl_desc; |
824 | struct ioat_ring_ent *desc; | |
825 | struct ioat_ring_ent *ext; | |
826 | size_t total_len = len; | |
827 | struct ioat_pq_descriptor *pq; | |
828 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
829 | struct ioat_dma_descriptor *hw; | |
830 | u32 offset = 0; | |
d69d235b | 831 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
074cc476 | 832 | int i, s, idx, with_ext, num_descs; |
e0884772 | 833 | int cb32 = (device->version < IOAT_VER_3_3) ? 1 : 0; |
d69d235b DW |
834 | |
835 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
836 | /* the engine requires at least two sources (we provide | |
837 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
838 | */ | |
839 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
840 | ||
841 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
842 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
843 | * sources (we need 1 extra source in the q-only continuation |
844 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 845 | */ |
cd78809f DW |
846 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
847 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
848 | with_ext = 1; |
849 | num_descs *= 2; | |
850 | } else | |
851 | with_ext = 0; | |
852 | ||
853 | /* completion writes from the raid engine may pass completion | |
854 | * writes from the legacy engine, so we need one extra null | |
855 | * (legacy) descriptor to ensure all completion writes arrive in | |
856 | * order. | |
857 | */ | |
858 | if (likely(num_descs) && | |
e0884772 | 859 | ioat2_check_space_lock(ioat, num_descs + cb32) == 0) |
074cc476 | 860 | idx = ioat->head; |
d69d235b DW |
861 | else |
862 | return NULL; | |
cdef57db DW |
863 | i = 0; |
864 | do { | |
d69d235b DW |
865 | struct ioat_raw_descriptor *descs[2]; |
866 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
867 | ||
868 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
869 | pq = desc->pq; | |
870 | ||
871 | /* save a branch by unconditionally retrieving the | |
872 | * extended descriptor pq_set_src() knows to not write | |
873 | * to it in the single descriptor case | |
874 | */ | |
875 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
876 | pq_ex = ext->pq_ex; | |
877 | ||
878 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
879 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
880 | ||
881 | for (s = 0; s < src_cnt; s++) | |
882 | pq_set_src(descs, src[s], offset, scf[s], s); | |
883 | ||
884 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
885 | if (dmaf_p_disabled_continue(flags)) | |
886 | pq_set_src(descs, dst[1], offset, 1, s++); | |
887 | else if (dmaf_continue(flags)) { | |
888 | pq_set_src(descs, dst[0], offset, 0, s++); | |
889 | pq_set_src(descs, dst[1], offset, 1, s++); | |
890 | pq_set_src(descs, dst[1], offset, 0, s++); | |
891 | } | |
892 | pq->size = xfer_size; | |
893 | pq->p_addr = dst[0] + offset; | |
894 | pq->q_addr = dst[1] + offset; | |
895 | pq->ctl = 0; | |
896 | pq->ctl_f.op = op; | |
75c6f0ab DJ |
897 | /* we turn on descriptor write back error status */ |
898 | if (device->cap & IOAT_CAP_DWBES) | |
899 | pq->ctl_f.wb_en = result ? 1 : 0; | |
d69d235b DW |
900 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); |
901 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
902 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
903 | ||
904 | len -= xfer_size; | |
905 | offset += xfer_size; | |
cdef57db | 906 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
907 | |
908 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
909 | desc->txd.flags = flags; | |
910 | desc->len = total_len; | |
911 | if (result) | |
912 | desc->result = result; | |
913 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
914 | dump_pq_desc_dbg(ioat, desc, ext); | |
915 | ||
e0884772 DJ |
916 | if (!cb32) { |
917 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
918 | pq->ctl_f.compl_write = 1; | |
919 | compl_desc = desc; | |
920 | } else { | |
921 | /* completion descriptor carries interrupt bit */ | |
922 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
923 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
924 | hw = compl_desc->hw; | |
925 | hw->ctl = 0; | |
926 | hw->ctl_f.null = 1; | |
927 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
928 | hw->ctl_f.compl_write = 1; | |
929 | hw->size = NULL_DESC_BUFFER_SIZE; | |
930 | dump_desc_dbg(ioat, compl_desc); | |
931 | } | |
932 | ||
d69d235b DW |
933 | |
934 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 935 | return &compl_desc->txd; |
d69d235b DW |
936 | } |
937 | ||
7727eaa4 DJ |
938 | static struct dma_async_tx_descriptor * |
939 | __ioat3_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result, | |
940 | const dma_addr_t *dst, const dma_addr_t *src, | |
941 | unsigned int src_cnt, const unsigned char *scf, | |
942 | size_t len, unsigned long flags) | |
943 | { | |
944 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
945 | struct ioat_chan_common *chan = &ioat->base; | |
946 | struct ioatdma_device *device = chan->device; | |
947 | struct ioat_ring_ent *desc; | |
948 | size_t total_len = len; | |
949 | struct ioat_pq_descriptor *pq; | |
950 | u32 offset = 0; | |
951 | u8 op; | |
952 | int i, s, idx, num_descs; | |
953 | ||
7727eaa4 DJ |
954 | /* this function is only called with 9-16 sources */ |
955 | op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S; | |
956 | ||
957 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
958 | ||
959 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
960 | ||
961 | /* | |
962 | * 16 source pq is only available on cb3.3 and has no completion | |
963 | * write hw bug. | |
964 | */ | |
965 | if (num_descs && ioat2_check_space_lock(ioat, num_descs) == 0) | |
966 | idx = ioat->head; | |
967 | else | |
968 | return NULL; | |
969 | ||
970 | i = 0; | |
971 | ||
972 | do { | |
973 | struct ioat_raw_descriptor *descs[4]; | |
974 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
975 | ||
976 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
977 | pq = desc->pq; | |
978 | ||
979 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
980 | ||
5d48b9b5 | 981 | desc->sed = ioat3_alloc_sed(device, (src_cnt-2) >> 3); |
7727eaa4 DJ |
982 | if (!desc->sed) { |
983 | dev_err(to_dev(chan), | |
984 | "%s: no free sed entries\n", __func__); | |
985 | return NULL; | |
986 | } | |
987 | ||
988 | pq->sed_addr = desc->sed->dma; | |
989 | desc->sed->parent = desc; | |
990 | ||
991 | descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw; | |
992 | descs[2] = (void *)descs[1] + 64; | |
993 | ||
994 | for (s = 0; s < src_cnt; s++) | |
995 | pq16_set_src(descs, src[s], offset, scf[s], s); | |
996 | ||
997 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
998 | if (dmaf_p_disabled_continue(flags)) | |
999 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1000 | else if (dmaf_continue(flags)) { | |
1001 | pq16_set_src(descs, dst[0], offset, 0, s++); | |
1002 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1003 | pq16_set_src(descs, dst[1], offset, 0, s++); | |
1004 | } | |
1005 | ||
1006 | pq->size = xfer_size; | |
1007 | pq->p_addr = dst[0] + offset; | |
1008 | pq->q_addr = dst[1] + offset; | |
1009 | pq->ctl = 0; | |
1010 | pq->ctl_f.op = op; | |
1011 | pq->ctl_f.src_cnt = src16_cnt_to_hw(s); | |
75c6f0ab DJ |
1012 | /* we turn on descriptor write back error status */ |
1013 | if (device->cap & IOAT_CAP_DWBES) | |
1014 | pq->ctl_f.wb_en = result ? 1 : 0; | |
7727eaa4 DJ |
1015 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); |
1016 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
1017 | ||
1018 | len -= xfer_size; | |
1019 | offset += xfer_size; | |
1020 | } while (++i < num_descs); | |
1021 | ||
1022 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
1023 | desc->txd.flags = flags; | |
1024 | desc->len = total_len; | |
1025 | if (result) | |
1026 | desc->result = result; | |
1027 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1028 | ||
1029 | /* with cb3.3 we should be able to do completion w/o a null desc */ | |
1030 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1031 | pq->ctl_f.compl_write = 1; | |
1032 | ||
1033 | dump_pq16_desc_dbg(ioat, desc); | |
1034 | ||
1035 | /* we leave the channel locked to ensure in order submission */ | |
1036 | return &desc->txd; | |
1037 | } | |
1038 | ||
21e96c73 DW |
1039 | static int src_cnt_flags(unsigned int src_cnt, unsigned long flags) |
1040 | { | |
1041 | if (dmaf_p_disabled_continue(flags)) | |
1042 | return src_cnt + 1; | |
1043 | else if (dmaf_continue(flags)) | |
1044 | return src_cnt + 3; | |
1045 | else | |
1046 | return src_cnt; | |
1047 | } | |
1048 | ||
d69d235b DW |
1049 | static struct dma_async_tx_descriptor * |
1050 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
1051 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1052 | unsigned long flags) | |
1053 | { | |
de581b65 DW |
1054 | /* specify valid address for disabled result */ |
1055 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1056 | dst[0] = dst[1]; | |
1057 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1058 | dst[1] = dst[0]; | |
1059 | ||
d69d235b DW |
1060 | /* handle the single source multiply case from the raid6 |
1061 | * recovery path | |
1062 | */ | |
de581b65 | 1063 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
1064 | dma_addr_t single_source[2]; |
1065 | unsigned char single_source_coef[2]; | |
1066 | ||
1067 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
1068 | single_source[0] = src[0]; | |
1069 | single_source[1] = src[0]; | |
1070 | single_source_coef[0] = scf[0]; | |
1071 | single_source_coef[1] = 0; | |
1072 | ||
21e96c73 | 1073 | return src_cnt_flags(src_cnt, flags) > 8 ? |
7727eaa4 DJ |
1074 | __ioat3_prep_pq16_lock(chan, NULL, dst, single_source, |
1075 | 2, single_source_coef, len, | |
1076 | flags) : | |
1077 | __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
1078 | single_source_coef, len, flags); | |
1079 | ||
1080 | } else { | |
21e96c73 | 1081 | return src_cnt_flags(src_cnt, flags) > 8 ? |
7727eaa4 DJ |
1082 | __ioat3_prep_pq16_lock(chan, NULL, dst, src, src_cnt, |
1083 | scf, len, flags) : | |
1084 | __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, | |
1085 | scf, len, flags); | |
1086 | } | |
d69d235b DW |
1087 | } |
1088 | ||
1089 | struct dma_async_tx_descriptor * | |
1090 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
1091 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1092 | enum sum_check_flags *pqres, unsigned long flags) | |
1093 | { | |
de581b65 DW |
1094 | /* specify valid address for disabled result */ |
1095 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1096 | pq[0] = pq[1]; | |
1097 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1098 | pq[1] = pq[0]; | |
1099 | ||
d69d235b DW |
1100 | /* the cleanup routine only sets bits on validate failure, it |
1101 | * does not clear bits on validate success... so clear it here | |
1102 | */ | |
1103 | *pqres = 0; | |
1104 | ||
21e96c73 | 1105 | return src_cnt_flags(src_cnt, flags) > 8 ? |
7727eaa4 DJ |
1106 | __ioat3_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len, |
1107 | flags) : | |
1108 | __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
1109 | flags); | |
d69d235b DW |
1110 | } |
1111 | ||
ae786624 DW |
1112 | static struct dma_async_tx_descriptor * |
1113 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
1114 | unsigned int src_cnt, size_t len, unsigned long flags) | |
1115 | { | |
1116 | unsigned char scf[src_cnt]; | |
1117 | dma_addr_t pq[2]; | |
1118 | ||
1119 | memset(scf, 0, src_cnt); | |
ae786624 | 1120 | pq[0] = dst; |
de581b65 DW |
1121 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1122 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 | 1123 | |
21e96c73 | 1124 | return src_cnt_flags(src_cnt, flags) > 8 ? |
7727eaa4 DJ |
1125 | __ioat3_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len, |
1126 | flags) : | |
1127 | __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1128 | flags); | |
ae786624 DW |
1129 | } |
1130 | ||
1131 | struct dma_async_tx_descriptor * | |
1132 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
1133 | unsigned int src_cnt, size_t len, | |
1134 | enum sum_check_flags *result, unsigned long flags) | |
1135 | { | |
1136 | unsigned char scf[src_cnt]; | |
1137 | dma_addr_t pq[2]; | |
1138 | ||
1139 | /* the cleanup routine only sets bits on validate failure, it | |
1140 | * does not clear bits on validate success... so clear it here | |
1141 | */ | |
1142 | *result = 0; | |
1143 | ||
1144 | memset(scf, 0, src_cnt); | |
ae786624 | 1145 | pq[0] = src[0]; |
de581b65 DW |
1146 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1147 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 | 1148 | |
21e96c73 | 1149 | return src_cnt_flags(src_cnt, flags) > 8 ? |
7727eaa4 DJ |
1150 | __ioat3_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1, |
1151 | scf, len, flags) : | |
1152 | __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, | |
1153 | scf, len, flags); | |
ae786624 DW |
1154 | } |
1155 | ||
58c8649e DW |
1156 | static struct dma_async_tx_descriptor * |
1157 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
1158 | { | |
1159 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1160 | struct ioat_ring_ent *desc; | |
1161 | struct ioat_dma_descriptor *hw; | |
58c8649e | 1162 | |
074cc476 DW |
1163 | if (ioat2_check_space_lock(ioat, 1) == 0) |
1164 | desc = ioat2_get_ring_ent(ioat, ioat->head); | |
58c8649e DW |
1165 | else |
1166 | return NULL; | |
1167 | ||
1168 | hw = desc->hw; | |
1169 | hw->ctl = 0; | |
1170 | hw->ctl_f.null = 1; | |
1171 | hw->ctl_f.int_en = 1; | |
1172 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1173 | hw->ctl_f.compl_write = 1; | |
1174 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1175 | hw->src_addr = 0; | |
1176 | hw->dst_addr = 0; | |
1177 | ||
1178 | desc->txd.flags = flags; | |
1179 | desc->len = 1; | |
1180 | ||
1181 | dump_desc_dbg(ioat, desc); | |
1182 | ||
1183 | /* we leave the channel locked to ensure in order submission */ | |
1184 | return &desc->txd; | |
1185 | } | |
1186 | ||
4bf27b8b | 1187 | static void ioat3_dma_test_callback(void *dma_async_param) |
9de6fc71 DW |
1188 | { |
1189 | struct completion *cmp = dma_async_param; | |
1190 | ||
1191 | complete(cmp); | |
1192 | } | |
1193 | ||
1194 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
4bf27b8b | 1195 | static int ioat_xor_val_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1196 | { |
1197 | int i, src_idx; | |
1198 | struct page *dest; | |
1199 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
1200 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1201 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
48a9db46 | 1202 | dma_addr_t dest_dma; |
9de6fc71 DW |
1203 | struct dma_async_tx_descriptor *tx; |
1204 | struct dma_chan *dma_chan; | |
1205 | dma_cookie_t cookie; | |
1206 | u8 cmp_byte = 0; | |
1207 | u32 cmp_word; | |
1208 | u32 xor_val_result; | |
1209 | int err = 0; | |
1210 | struct completion cmp; | |
1211 | unsigned long tmo; | |
1212 | struct device *dev = &device->pdev->dev; | |
1213 | struct dma_device *dma = &device->common; | |
7369f56e | 1214 | u8 op = 0; |
9de6fc71 DW |
1215 | |
1216 | dev_dbg(dev, "%s\n", __func__); | |
1217 | ||
1218 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
1219 | return 0; | |
1220 | ||
1221 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1222 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
1223 | if (!xor_srcs[src_idx]) { | |
1224 | while (src_idx--) | |
1225 | __free_page(xor_srcs[src_idx]); | |
1226 | return -ENOMEM; | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | dest = alloc_page(GFP_KERNEL); | |
1231 | if (!dest) { | |
1232 | while (src_idx--) | |
1233 | __free_page(xor_srcs[src_idx]); | |
1234 | return -ENOMEM; | |
1235 | } | |
1236 | ||
1237 | /* Fill in src buffers */ | |
1238 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1239 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
1240 | for (i = 0; i < PAGE_SIZE; i++) | |
1241 | ptr[i] = (1 << src_idx); | |
1242 | } | |
1243 | ||
1244 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
1245 | cmp_byte ^= (u8) (1 << src_idx); | |
1246 | ||
1247 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
1248 | (cmp_byte << 8) | cmp_byte; | |
1249 | ||
1250 | memset(page_address(dest), 0, PAGE_SIZE); | |
1251 | ||
1252 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
1253 | device_node); | |
1254 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
1255 | err = -ENODEV; | |
1256 | goto out; | |
1257 | } | |
1258 | ||
1259 | /* test xor */ | |
7369f56e BZ |
1260 | op = IOAT_OP_XOR; |
1261 | ||
9de6fc71 DW |
1262 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
1263 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1264 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
1265 | DMA_TO_DEVICE); | |
1266 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
1267 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
0776ae7b | 1268 | DMA_PREP_INTERRUPT); |
9de6fc71 DW |
1269 | |
1270 | if (!tx) { | |
1271 | dev_err(dev, "Self-test xor prep failed\n"); | |
1272 | err = -ENODEV; | |
7369f56e | 1273 | goto dma_unmap; |
9de6fc71 DW |
1274 | } |
1275 | ||
1276 | async_tx_ack(tx); | |
1277 | init_completion(&cmp); | |
1278 | tx->callback = ioat3_dma_test_callback; | |
1279 | tx->callback_param = &cmp; | |
1280 | cookie = tx->tx_submit(tx); | |
1281 | if (cookie < 0) { | |
1282 | dev_err(dev, "Self-test xor setup failed\n"); | |
1283 | err = -ENODEV; | |
7369f56e | 1284 | goto dma_unmap; |
9de6fc71 DW |
1285 | } |
1286 | dma->device_issue_pending(dma_chan); | |
1287 | ||
1288 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1289 | ||
07934481 | 1290 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1291 | dev_err(dev, "Self-test xor timed out\n"); |
1292 | err = -ENODEV; | |
7369f56e | 1293 | goto dma_unmap; |
9de6fc71 DW |
1294 | } |
1295 | ||
7369f56e BZ |
1296 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1297 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1298 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1299 | ||
9de6fc71 DW |
1300 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1301 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
1302 | u32 *ptr = page_address(dest); | |
1303 | if (ptr[i] != cmp_word) { | |
1304 | dev_err(dev, "Self-test xor failed compare\n"); | |
1305 | err = -ENODEV; | |
1306 | goto free_resources; | |
1307 | } | |
1308 | } | |
ac498987 | 1309 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
9de6fc71 DW |
1310 | |
1311 | /* skip validate if the capability is not present */ | |
1312 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
1313 | goto free_resources; | |
1314 | ||
7369f56e BZ |
1315 | op = IOAT_OP_XOR_VAL; |
1316 | ||
9de6fc71 DW |
1317 | /* validate the sources with the destintation page */ |
1318 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1319 | xor_val_srcs[i] = xor_srcs[i]; | |
1320 | xor_val_srcs[i] = dest; | |
1321 | ||
1322 | xor_val_result = 1; | |
1323 | ||
1324 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1325 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1326 | DMA_TO_DEVICE); | |
1327 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1328 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
0776ae7b | 1329 | &xor_val_result, DMA_PREP_INTERRUPT); |
9de6fc71 DW |
1330 | if (!tx) { |
1331 | dev_err(dev, "Self-test zero prep failed\n"); | |
1332 | err = -ENODEV; | |
7369f56e | 1333 | goto dma_unmap; |
9de6fc71 DW |
1334 | } |
1335 | ||
1336 | async_tx_ack(tx); | |
1337 | init_completion(&cmp); | |
1338 | tx->callback = ioat3_dma_test_callback; | |
1339 | tx->callback_param = &cmp; | |
1340 | cookie = tx->tx_submit(tx); | |
1341 | if (cookie < 0) { | |
1342 | dev_err(dev, "Self-test zero setup failed\n"); | |
1343 | err = -ENODEV; | |
7369f56e | 1344 | goto dma_unmap; |
9de6fc71 DW |
1345 | } |
1346 | dma->device_issue_pending(dma_chan); | |
1347 | ||
1348 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1349 | ||
07934481 | 1350 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1351 | dev_err(dev, "Self-test validate timed out\n"); |
1352 | err = -ENODEV; | |
7369f56e | 1353 | goto dma_unmap; |
9de6fc71 DW |
1354 | } |
1355 | ||
7369f56e BZ |
1356 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1357 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1358 | ||
9de6fc71 DW |
1359 | if (xor_val_result != 0) { |
1360 | dev_err(dev, "Self-test validate failed compare\n"); | |
1361 | err = -ENODEV; | |
1362 | goto free_resources; | |
1363 | } | |
1364 | ||
ac7d631f DJ |
1365 | memset(page_address(dest), 0, PAGE_SIZE); |
1366 | ||
9de6fc71 | 1367 | /* test for non-zero parity sum */ |
7369f56e BZ |
1368 | op = IOAT_OP_XOR_VAL; |
1369 | ||
9de6fc71 DW |
1370 | xor_val_result = 0; |
1371 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1372 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1373 | DMA_TO_DEVICE); | |
1374 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1375 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
0776ae7b | 1376 | &xor_val_result, DMA_PREP_INTERRUPT); |
9de6fc71 DW |
1377 | if (!tx) { |
1378 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1379 | err = -ENODEV; | |
7369f56e | 1380 | goto dma_unmap; |
9de6fc71 DW |
1381 | } |
1382 | ||
1383 | async_tx_ack(tx); | |
1384 | init_completion(&cmp); | |
1385 | tx->callback = ioat3_dma_test_callback; | |
1386 | tx->callback_param = &cmp; | |
1387 | cookie = tx->tx_submit(tx); | |
1388 | if (cookie < 0) { | |
1389 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1390 | err = -ENODEV; | |
7369f56e | 1391 | goto dma_unmap; |
9de6fc71 DW |
1392 | } |
1393 | dma->device_issue_pending(dma_chan); | |
1394 | ||
1395 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1396 | ||
07934481 | 1397 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1398 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
1399 | err = -ENODEV; | |
7369f56e | 1400 | goto dma_unmap; |
9de6fc71 DW |
1401 | } |
1402 | ||
1403 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1404 | dev_err(dev, "Self-test validate failed compare\n"); | |
1405 | err = -ENODEV; | |
7369f56e | 1406 | goto dma_unmap; |
9de6fc71 DW |
1407 | } |
1408 | ||
7369f56e BZ |
1409 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1410 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1411 | ||
1412 | goto free_resources; | |
1413 | dma_unmap: | |
1414 | if (op == IOAT_OP_XOR) { | |
1415 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
1416 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1417 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1418 | DMA_TO_DEVICE); | |
1419 | } else if (op == IOAT_OP_XOR_VAL) { | |
1420 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1421 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1422 | DMA_TO_DEVICE); | |
48a9db46 | 1423 | } |
9de6fc71 DW |
1424 | free_resources: |
1425 | dma->device_free_chan_resources(dma_chan); | |
1426 | out: | |
1427 | src_idx = IOAT_NUM_SRC_TEST; | |
1428 | while (src_idx--) | |
1429 | __free_page(xor_srcs[src_idx]); | |
1430 | __free_page(dest); | |
1431 | return err; | |
1432 | } | |
1433 | ||
4bf27b8b | 1434 | static int ioat3_dma_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1435 | { |
1436 | int rc = ioat_dma_self_test(device); | |
1437 | ||
1438 | if (rc) | |
1439 | return rc; | |
1440 | ||
1441 | rc = ioat_xor_val_self_test(device); | |
1442 | if (rc) | |
1443 | return rc; | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
8a52b9ff DJ |
1448 | static int ioat3_irq_reinit(struct ioatdma_device *device) |
1449 | { | |
1450 | int msixcnt = device->common.chancnt; | |
1451 | struct pci_dev *pdev = device->pdev; | |
1452 | int i; | |
1453 | struct msix_entry *msix; | |
1454 | struct ioat_chan_common *chan; | |
1455 | int err = 0; | |
1456 | ||
1457 | switch (device->irq_mode) { | |
1458 | case IOAT_MSIX: | |
1459 | ||
1460 | for (i = 0; i < msixcnt; i++) { | |
1461 | msix = &device->msix_entries[i]; | |
1462 | chan = ioat_chan_by_index(device, i); | |
1463 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1464 | } | |
1465 | ||
1466 | pci_disable_msix(pdev); | |
1467 | break; | |
1468 | ||
1469 | case IOAT_MSIX_SINGLE: | |
1470 | msix = &device->msix_entries[0]; | |
1471 | chan = ioat_chan_by_index(device, 0); | |
1472 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1473 | pci_disable_msix(pdev); | |
1474 | break; | |
1475 | ||
1476 | case IOAT_MSI: | |
1477 | chan = ioat_chan_by_index(device, 0); | |
1478 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1479 | pci_disable_msi(pdev); | |
1480 | break; | |
1481 | ||
1482 | case IOAT_INTX: | |
1483 | chan = ioat_chan_by_index(device, 0); | |
1484 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1485 | break; | |
1486 | ||
1487 | default: | |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | device->irq_mode = IOAT_NOIRQ; | |
1492 | ||
1493 | err = ioat_dma_setup_interrupts(device); | |
1494 | ||
1495 | return err; | |
1496 | } | |
1497 | ||
a6d52d70 DW |
1498 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1499 | { | |
1500 | /* throw away whatever the channel was doing and get it | |
1501 | * initialized, with ioat3 specific workarounds | |
1502 | */ | |
1503 | struct ioatdma_device *device = chan->device; | |
1504 | struct pci_dev *pdev = device->pdev; | |
1505 | u32 chanerr; | |
1506 | u16 dev_id; | |
1507 | int err; | |
1508 | ||
1509 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1510 | ||
1511 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1512 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1513 | ||
6ead7e48 DJ |
1514 | if (device->version < IOAT_VER_3_3) { |
1515 | /* clear any pending errors */ | |
1516 | err = pci_read_config_dword(pdev, | |
1517 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1518 | if (err) { | |
1519 | dev_err(&pdev->dev, | |
1520 | "channel error register unreachable\n"); | |
1521 | return err; | |
1522 | } | |
1523 | pci_write_config_dword(pdev, | |
1524 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
a6d52d70 | 1525 | |
6ead7e48 DJ |
1526 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
1527 | * (workaround for spurious config parity error after restart) | |
1528 | */ | |
1529 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1530 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1531 | pci_write_config_dword(pdev, | |
1532 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1533 | 0x10); | |
1534 | } | |
1535 | } | |
a6d52d70 | 1536 | |
8a52b9ff DJ |
1537 | err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
1538 | if (err) { | |
1539 | dev_err(&pdev->dev, "Failed to reset!\n"); | |
1540 | return err; | |
570727b5 DJ |
1541 | } |
1542 | ||
8a52b9ff DJ |
1543 | if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev)) |
1544 | err = ioat3_irq_reinit(device); | |
570727b5 | 1545 | |
8a52b9ff | 1546 | return err; |
570727b5 DJ |
1547 | } |
1548 | ||
75c6f0ab DJ |
1549 | static void ioat3_intr_quirk(struct ioatdma_device *device) |
1550 | { | |
1551 | struct dma_device *dma; | |
1552 | struct dma_chan *c; | |
1553 | struct ioat_chan_common *chan; | |
1554 | u32 errmask; | |
1555 | ||
1556 | dma = &device->common; | |
1557 | ||
1558 | /* | |
1559 | * if we have descriptor write back error status, we mask the | |
1560 | * error interrupts | |
1561 | */ | |
1562 | if (device->cap & IOAT_CAP_DWBES) { | |
1563 | list_for_each_entry(c, &dma->channels, device_node) { | |
1564 | chan = to_chan_common(c); | |
1565 | errmask = readl(chan->reg_base + | |
1566 | IOAT_CHANERR_MASK_OFFSET); | |
1567 | errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | | |
1568 | IOAT_CHANERR_XOR_Q_ERR; | |
1569 | writel(errmask, chan->reg_base + | |
1570 | IOAT_CHANERR_MASK_OFFSET); | |
1571 | } | |
1572 | } | |
1573 | } | |
1574 | ||
4bf27b8b | 1575 | int ioat3_dma_probe(struct ioatdma_device *device, int dca) |
bf40a686 DW |
1576 | { |
1577 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1578 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1579 | struct dma_device *dma; |
1580 | struct dma_chan *c; | |
1581 | struct ioat_chan_common *chan; | |
e3232714 | 1582 | bool is_raid_device = false; |
bf40a686 | 1583 | int err; |
bf40a686 DW |
1584 | |
1585 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1586 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1587 | device->self_test = ioat3_dma_self_test; |
75c6f0ab | 1588 | device->intr_quirk = ioat3_intr_quirk; |
bf40a686 DW |
1589 | dma = &device->common; |
1590 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1591 | dma->device_issue_pending = ioat2_issue_pending; | |
1592 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1593 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e DW |
1594 | |
1595 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); | |
1596 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1597 | ||
75c6f0ab | 1598 | device->cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c | 1599 | |
c4dcf0e2 | 1600 | if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) |
75c6f0ab | 1601 | device->cap &= ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); |
d302398d | 1602 | |
228c4f5c | 1603 | /* dca is incompatible with raid operations */ |
75c6f0ab DJ |
1604 | if (dca_en && (device->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) |
1605 | device->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
228c4f5c | 1606 | |
75c6f0ab | 1607 | if (device->cap & IOAT_CAP_XOR) { |
e3232714 | 1608 | is_raid_device = true; |
b094ad3b | 1609 | dma->max_xor = 8; |
b094ad3b DW |
1610 | |
1611 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1612 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1613 | ||
1614 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1615 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1616 | } | |
eceec44e | 1617 | |
75c6f0ab | 1618 | if (device->cap & IOAT_CAP_PQ) { |
e3232714 | 1619 | is_raid_device = true; |
7727eaa4 | 1620 | |
75c6f0ab DJ |
1621 | dma->device_prep_dma_pq = ioat3_prep_pq; |
1622 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
1623 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1624 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1625 | ||
1626 | if (device->cap & IOAT_CAP_RAID16SS) { | |
7727eaa4 | 1627 | dma_set_maxpq(dma, 16, 0); |
7727eaa4 DJ |
1628 | } else { |
1629 | dma_set_maxpq(dma, 8, 0); | |
7727eaa4 | 1630 | } |
d69d235b | 1631 | |
75c6f0ab DJ |
1632 | if (!(device->cap & IOAT_CAP_XOR)) { |
1633 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1634 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1635 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1636 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
ae786624 | 1637 | |
75c6f0ab | 1638 | if (device->cap & IOAT_CAP_RAID16SS) { |
7727eaa4 | 1639 | dma->max_xor = 16; |
7727eaa4 DJ |
1640 | } else { |
1641 | dma->max_xor = 8; | |
7727eaa4 | 1642 | } |
ae786624 | 1643 | } |
d69d235b | 1644 | } |
eceec44e | 1645 | |
9a37f644 DJ |
1646 | dma->device_tx_status = ioat3_tx_status; |
1647 | device->cleanup_fn = ioat3_cleanup_event; | |
1648 | device->timer_fn = ioat3_timer_event; | |
bf40a686 | 1649 | |
7727eaa4 | 1650 | /* starting with CB3.3 super extended descriptors are supported */ |
75c6f0ab | 1651 | if (device->cap & IOAT_CAP_RAID16SS) { |
7727eaa4 DJ |
1652 | char pool_name[14]; |
1653 | int i; | |
1654 | ||
1655 | /* allocate sw descriptor pool for SED */ | |
1656 | device->sed_pool = kmem_cache_create("ioat_sed", | |
1657 | sizeof(struct ioat_sed_ent), 0, 0, NULL); | |
1658 | if (!device->sed_pool) | |
1659 | return -ENOMEM; | |
1660 | ||
1661 | for (i = 0; i < MAX_SED_POOLS; i++) { | |
1662 | snprintf(pool_name, 14, "ioat_hw%d_sed", i); | |
1663 | ||
1664 | /* allocate SED DMA pool */ | |
1665 | device->sed_hw_pool[i] = dma_pool_create(pool_name, | |
1666 | &pdev->dev, | |
1667 | SED_SIZE * (i + 1), 64, 0); | |
1668 | if (!device->sed_hw_pool[i]) | |
1669 | goto sed_pool_cleanup; | |
1670 | ||
1671 | } | |
1672 | } | |
1673 | ||
bf40a686 DW |
1674 | err = ioat_probe(device); |
1675 | if (err) | |
1676 | return err; | |
1677 | ioat_set_tcp_copy_break(262144); | |
1678 | ||
1679 | list_for_each_entry(c, &dma->channels, device_node) { | |
1680 | chan = to_chan_common(c); | |
1681 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1682 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1683 | } | |
1684 | ||
1685 | err = ioat_register(device); | |
1686 | if (err) | |
1687 | return err; | |
5669e31c DW |
1688 | |
1689 | ioat_kobject_add(device, &ioat2_ktype); | |
1690 | ||
bf40a686 DW |
1691 | if (dca) |
1692 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1693 | ||
1694 | return 0; | |
7727eaa4 DJ |
1695 | |
1696 | sed_pool_cleanup: | |
1697 | if (device->sed_pool) { | |
1698 | int i; | |
1699 | kmem_cache_destroy(device->sed_pool); | |
1700 | ||
1701 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1702 | if (device->sed_hw_pool[i]) | |
1703 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1704 | } | |
1705 | ||
1706 | return -ENOMEM; | |
1707 | } | |
1708 | ||
1709 | void ioat3_dma_remove(struct ioatdma_device *device) | |
1710 | { | |
1711 | if (device->sed_pool) { | |
1712 | int i; | |
1713 | kmem_cache_destroy(device->sed_pool); | |
1714 | ||
1715 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1716 | if (device->sed_hw_pool[i]) | |
1717 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1718 | } | |
bf40a686 | 1719 | } |