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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
58 | ||
59 | #include <linux/pci.h> | |
5a0e3ad6 | 60 | #include <linux/gfp.h> |
bf40a686 DW |
61 | #include <linux/dmaengine.h> |
62 | #include <linux/dma-mapping.h> | |
70c71606 | 63 | #include <linux/prefetch.h> |
949ff5b8 | 64 | #include "../dmaengine.h" |
bf40a686 DW |
65 | #include "registers.h" |
66 | #include "hw.h" | |
67 | #include "dma.h" | |
68 | #include "dma_v2.h" | |
69 | ||
b094ad3b DW |
70 | /* ioat hardware assumes at least two sources for raid operations */ |
71 | #define src_cnt_to_sw(x) ((x) + 2) | |
72 | #define src_cnt_to_hw(x) ((x) - 2) | |
73 | ||
74 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 75 | * extended descriptor of an xor or pq descriptor |
b094ad3b | 76 | */ |
d0b0c8c7 | 77 | static const u8 xor_idx_to_desc = 0xe0; |
9b487ced AK |
78 | static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
79 | static const u8 pq_idx_to_desc = 0xf8; | |
80 | static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; | |
b094ad3b | 81 | |
3f09ede4 DJ |
82 | static void ioat3_eh(struct ioat2_dma_chan *ioat); |
83 | ||
b094ad3b DW |
84 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
85 | { | |
86 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
87 | ||
88 | return raw->field[xor_idx_to_field[idx]]; | |
89 | } | |
90 | ||
91 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
92 | dma_addr_t addr, u32 offset, int idx) | |
93 | { | |
94 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
95 | ||
96 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
97 | } | |
98 | ||
d69d235b DW |
99 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
100 | { | |
101 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
102 | ||
103 | return raw->field[pq_idx_to_field[idx]]; | |
104 | } | |
105 | ||
106 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], | |
107 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
108 | { | |
109 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
110 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
111 | ||
112 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
113 | pq->coef[idx] = coef; | |
114 | } | |
115 | ||
8a52b9ff DJ |
116 | static bool is_jf_ioat(struct pci_dev *pdev) |
117 | { | |
118 | switch (pdev->device) { | |
119 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: | |
120 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: | |
121 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: | |
122 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: | |
123 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: | |
124 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: | |
125 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: | |
126 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: | |
127 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: | |
128 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: | |
129 | return true; | |
130 | default: | |
131 | return false; | |
132 | } | |
133 | } | |
134 | ||
135 | static bool is_snb_ioat(struct pci_dev *pdev) | |
136 | { | |
137 | switch (pdev->device) { | |
138 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: | |
139 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: | |
140 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: | |
141 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: | |
142 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: | |
143 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: | |
144 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: | |
145 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: | |
146 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: | |
147 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: | |
148 | return true; | |
149 | default: | |
150 | return false; | |
151 | } | |
152 | } | |
153 | ||
154 | static bool is_ivb_ioat(struct pci_dev *pdev) | |
155 | { | |
156 | switch (pdev->device) { | |
157 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: | |
158 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: | |
159 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: | |
160 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: | |
161 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: | |
162 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: | |
163 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: | |
164 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: | |
165 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: | |
166 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: | |
167 | return true; | |
168 | default: | |
169 | return false; | |
170 | } | |
171 | ||
172 | } | |
173 | ||
174 | static bool is_hsw_ioat(struct pci_dev *pdev) | |
175 | { | |
176 | switch (pdev->device) { | |
177 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: | |
178 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: | |
179 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: | |
180 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: | |
181 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: | |
182 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: | |
183 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: | |
184 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: | |
185 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: | |
186 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: | |
187 | return true; | |
188 | default: | |
189 | return false; | |
190 | } | |
191 | ||
192 | } | |
193 | ||
194 | static bool is_xeon_cb32(struct pci_dev *pdev) | |
195 | { | |
196 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || | |
197 | is_hsw_ioat(pdev); | |
198 | } | |
199 | ||
200 | static bool is_bwd_ioat(struct pci_dev *pdev) | |
201 | { | |
202 | switch (pdev->device) { | |
203 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: | |
204 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: | |
205 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
206 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
207 | return true; | |
208 | default: | |
209 | return false; | |
210 | } | |
211 | } | |
212 | ||
bf40a686 | 213 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 214 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
215 | { |
216 | struct ioat_chan_common *chan = &ioat->base; | |
217 | struct pci_dev *pdev = chan->device->pdev; | |
218 | size_t len = desc->len; | |
219 | size_t offset = len - desc->hw->size; | |
220 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
221 | enum dma_ctrl_flags flags = tx->flags; | |
222 | ||
223 | switch (desc->hw->ctl_f.op) { | |
224 | case IOAT_OP_COPY: | |
58c8649e DW |
225 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
226 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 DW |
227 | break; |
228 | case IOAT_OP_FILL: { | |
229 | struct ioat_fill_descriptor *hw = desc->fill; | |
230 | ||
231 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
232 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
233 | PCI_DMA_FROMDEVICE, flags, 1); | |
234 | break; | |
235 | } | |
b094ad3b DW |
236 | case IOAT_OP_XOR_VAL: |
237 | case IOAT_OP_XOR: { | |
238 | struct ioat_xor_descriptor *xor = desc->xor; | |
239 | struct ioat_ring_ent *ext; | |
240 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
241 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
242 | struct ioat_raw_descriptor *descs[2]; | |
243 | int i; | |
244 | ||
245 | if (src_cnt > 5) { | |
246 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
247 | xor_ex = ext->xor_ex; | |
248 | } | |
249 | ||
250 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
251 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
252 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
253 | for (i = 0; i < src_cnt; i++) { | |
254 | dma_addr_t src = xor_get_src(descs, i); | |
255 | ||
256 | ioat_unmap(pdev, src - offset, len, | |
257 | PCI_DMA_TODEVICE, flags, 0); | |
258 | } | |
259 | ||
260 | /* dest is a source in xor validate operations */ | |
261 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
262 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
263 | PCI_DMA_TODEVICE, flags, 1); | |
264 | break; | |
265 | } | |
266 | } | |
267 | ||
268 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
269 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
270 | PCI_DMA_FROMDEVICE, flags, 1); | |
271 | break; | |
272 | } | |
d69d235b DW |
273 | case IOAT_OP_PQ_VAL: |
274 | case IOAT_OP_PQ: { | |
275 | struct ioat_pq_descriptor *pq = desc->pq; | |
276 | struct ioat_ring_ent *ext; | |
277 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
278 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
279 | struct ioat_raw_descriptor *descs[2]; | |
280 | int i; | |
281 | ||
282 | if (src_cnt > 3) { | |
283 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
284 | pq_ex = ext->pq_ex; | |
285 | } | |
286 | ||
287 | /* in the 'continue' case don't unmap the dests as sources */ | |
288 | if (dmaf_p_disabled_continue(flags)) | |
289 | src_cnt--; | |
290 | else if (dmaf_continue(flags)) | |
291 | src_cnt -= 3; | |
292 | ||
293 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
294 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
295 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
296 | for (i = 0; i < src_cnt; i++) { | |
297 | dma_addr_t src = pq_get_src(descs, i); | |
298 | ||
299 | ioat_unmap(pdev, src - offset, len, | |
300 | PCI_DMA_TODEVICE, flags, 0); | |
301 | } | |
302 | ||
303 | /* the dests are sources in pq validate operations */ | |
304 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
305 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
306 | ioat_unmap(pdev, pq->p_addr - offset, | |
307 | len, PCI_DMA_TODEVICE, flags, 0); | |
308 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
309 | ioat_unmap(pdev, pq->q_addr - offset, | |
310 | len, PCI_DMA_TODEVICE, flags, 0); | |
311 | break; | |
312 | } | |
313 | } | |
314 | ||
315 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
316 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
317 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
318 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
319 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
320 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
321 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
322 | } | |
323 | break; | |
324 | } | |
bf40a686 DW |
325 | default: |
326 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
327 | __func__, desc->hw->ctl_f.op); | |
328 | } | |
329 | } | |
330 | ||
b094ad3b DW |
331 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
332 | { | |
333 | struct ioat_dma_descriptor *hw = desc->hw; | |
334 | ||
335 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
336 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
337 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 338 | |
b094ad3b DW |
339 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
340 | return true; | |
d69d235b DW |
341 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
342 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
343 | struct ioat_pq_descriptor *pq = desc->pq; | |
344 | ||
345 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
346 | return true; | |
b094ad3b DW |
347 | } |
348 | ||
349 | return false; | |
350 | } | |
351 | ||
3f09ede4 DJ |
352 | static u64 ioat3_get_current_completion(struct ioat_chan_common *chan) |
353 | { | |
354 | u64 phys_complete; | |
355 | u64 completion; | |
356 | ||
357 | completion = *chan->completion; | |
358 | phys_complete = ioat_chansts_to_addr(completion); | |
359 | ||
360 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, | |
361 | (unsigned long long) phys_complete); | |
362 | ||
363 | return phys_complete; | |
364 | } | |
365 | ||
366 | static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan, | |
367 | u64 *phys_complete) | |
368 | { | |
369 | *phys_complete = ioat3_get_current_completion(chan); | |
370 | if (*phys_complete == chan->last_completion) | |
371 | return false; | |
372 | ||
373 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); | |
374 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
375 | ||
376 | return true; | |
377 | } | |
378 | ||
b094ad3b DW |
379 | /** |
380 | * __cleanup - reclaim used descriptors | |
381 | * @ioat: channel (ring) to clean | |
382 | * | |
383 | * The difference from the dma_v2.c __cleanup() is that this routine | |
384 | * handles extended descriptors and dma-unmapping raid operations. | |
385 | */ | |
27502935 | 386 | static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete) |
bf40a686 DW |
387 | { |
388 | struct ioat_chan_common *chan = &ioat->base; | |
389 | struct ioat_ring_ent *desc; | |
390 | bool seen_current = false; | |
074cc476 | 391 | int idx = ioat->tail, i; |
bf40a686 | 392 | u16 active; |
bf40a686 DW |
393 | |
394 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
395 | __func__, ioat->head, ioat->tail, ioat->issued); | |
396 | ||
3f09ede4 DJ |
397 | /* |
398 | * At restart of the channel, the completion address and the | |
399 | * channel status will be 0 due to starting a new chain. Since | |
400 | * it's new chain and the first descriptor "fails", there is | |
401 | * nothing to clean up. We do not want to reap the entire submitted | |
402 | * chain due to this 0 address value and then BUG. | |
403 | */ | |
404 | if (!phys_complete) | |
405 | return; | |
406 | ||
bf40a686 DW |
407 | active = ioat2_ring_active(ioat); |
408 | for (i = 0; i < active && !seen_current; i++) { | |
409 | struct dma_async_tx_descriptor *tx; | |
410 | ||
074cc476 DW |
411 | smp_read_barrier_depends(); |
412 | prefetch(ioat2_get_ring_ent(ioat, idx + i + 1)); | |
413 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
bf40a686 DW |
414 | dump_desc_dbg(ioat, desc); |
415 | tx = &desc->txd; | |
416 | if (tx->cookie) { | |
f7fbce07 | 417 | dma_cookie_complete(tx); |
074cc476 | 418 | ioat3_dma_unmap(ioat, desc, idx + i); |
bf40a686 DW |
419 | if (tx->callback) { |
420 | tx->callback(tx->callback_param); | |
421 | tx->callback = NULL; | |
422 | } | |
423 | } | |
424 | ||
425 | if (tx->phys == phys_complete) | |
426 | seen_current = true; | |
b094ad3b DW |
427 | |
428 | /* skip extended descriptors */ | |
429 | if (desc_has_ext(desc)) { | |
430 | BUG_ON(i + 1 >= active); | |
431 | i++; | |
432 | } | |
bf40a686 | 433 | } |
074cc476 DW |
434 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
435 | ioat->tail = idx + i; | |
aa75db00 | 436 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
bf40a686 | 437 | chan->last_completion = phys_complete; |
b9cc9869 | 438 | |
074cc476 | 439 | if (active - i == 0) { |
bf40a686 DW |
440 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
441 | __func__); | |
442 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
443 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
444 | } | |
b9cc9869 | 445 | /* 5 microsecond delay per pending descriptor */ |
074cc476 | 446 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
b9cc9869 | 447 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); |
bf40a686 DW |
448 | } |
449 | ||
074cc476 | 450 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) |
bf40a686 DW |
451 | { |
452 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 453 | u64 phys_complete; |
bf40a686 | 454 | |
b9cc9869 | 455 | spin_lock_bh(&chan->cleanup_lock); |
3f09ede4 DJ |
456 | |
457 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
074cc476 | 458 | __cleanup(ioat, phys_complete); |
3f09ede4 DJ |
459 | |
460 | if (is_ioat_halted(*chan->completion)) { | |
461 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
462 | ||
463 | if (chanerr & IOAT_CHANERR_HANDLE_MASK) { | |
464 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
465 | ioat3_eh(ioat); | |
466 | } | |
467 | } | |
468 | ||
b9cc9869 DW |
469 | spin_unlock_bh(&chan->cleanup_lock); |
470 | } | |
471 | ||
aa4d72ae | 472 | static void ioat3_cleanup_event(unsigned long data) |
bf40a686 | 473 | { |
aa4d72ae | 474 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
bf40a686 | 475 | |
074cc476 | 476 | ioat3_cleanup(ioat); |
773d9e2d | 477 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
478 | } |
479 | ||
480 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
481 | { | |
482 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 483 | u64 phys_complete; |
bf40a686 | 484 | |
b372ec2d | 485 | ioat2_quiesce(chan, 0); |
3f09ede4 | 486 | if (ioat3_cleanup_preamble(chan, &phys_complete)) |
bf40a686 DW |
487 | __cleanup(ioat, phys_complete); |
488 | ||
489 | __ioat2_restart_chan(ioat); | |
490 | } | |
491 | ||
3f09ede4 DJ |
492 | static void ioat3_eh(struct ioat2_dma_chan *ioat) |
493 | { | |
494 | struct ioat_chan_common *chan = &ioat->base; | |
495 | struct pci_dev *pdev = to_pdev(chan); | |
496 | struct ioat_dma_descriptor *hw; | |
497 | u64 phys_complete; | |
498 | struct ioat_ring_ent *desc; | |
499 | u32 err_handled = 0; | |
500 | u32 chanerr_int; | |
501 | u32 chanerr; | |
502 | ||
503 | /* cleanup so tail points to descriptor that caused the error */ | |
504 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
505 | __cleanup(ioat, phys_complete); | |
506 | ||
507 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
508 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
509 | ||
510 | dev_dbg(to_dev(chan), "%s: error = %x:%x\n", | |
511 | __func__, chanerr, chanerr_int); | |
512 | ||
513 | desc = ioat2_get_ring_ent(ioat, ioat->tail); | |
514 | hw = desc->hw; | |
515 | dump_desc_dbg(ioat, desc); | |
516 | ||
517 | switch (hw->ctl_f.op) { | |
518 | case IOAT_OP_XOR_VAL: | |
519 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
520 | *desc->result |= SUM_CHECK_P_RESULT; | |
521 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
522 | } | |
523 | break; | |
524 | case IOAT_OP_PQ_VAL: | |
525 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
526 | *desc->result |= SUM_CHECK_P_RESULT; | |
527 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
528 | } | |
529 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
530 | *desc->result |= SUM_CHECK_Q_RESULT; | |
531 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
532 | } | |
533 | break; | |
534 | } | |
535 | ||
536 | /* fault on unhandled error or spurious halt */ | |
537 | if (chanerr ^ err_handled || chanerr == 0) { | |
538 | dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n", | |
539 | __func__, chanerr, err_handled); | |
540 | BUG(); | |
541 | } | |
542 | ||
543 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
544 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
545 | ||
546 | /* mark faulting descriptor as complete */ | |
547 | *chan->completion = desc->txd.phys; | |
548 | ||
549 | spin_lock_bh(&ioat->prep_lock); | |
550 | ioat3_restart_channel(ioat); | |
551 | spin_unlock_bh(&ioat->prep_lock); | |
552 | } | |
553 | ||
4dec23d7 | 554 | static void check_active(struct ioat2_dma_chan *ioat) |
bf40a686 | 555 | { |
bf40a686 DW |
556 | struct ioat_chan_common *chan = &ioat->base; |
557 | ||
4dec23d7 DJ |
558 | if (ioat2_ring_active(ioat)) { |
559 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
560 | return; | |
561 | } | |
bf40a686 | 562 | |
4dec23d7 DJ |
563 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state)) |
564 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
565 | else if (ioat->alloc_order > ioat_get_alloc_order()) { | |
bf40a686 DW |
566 | /* if the ring is idle, empty, and oversized try to step |
567 | * down the size | |
568 | */ | |
4dec23d7 | 569 | reshape_ring(ioat, ioat->alloc_order - 1); |
bf40a686 DW |
570 | |
571 | /* keep shrinking until we get back to our minimum | |
572 | * default size | |
573 | */ | |
574 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
575 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
576 | } | |
4dec23d7 DJ |
577 | |
578 | } | |
579 | ||
a20702b8 | 580 | static void ioat3_timer_event(unsigned long data) |
4dec23d7 DJ |
581 | { |
582 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); | |
583 | struct ioat_chan_common *chan = &ioat->base; | |
584 | dma_addr_t phys_complete; | |
585 | u64 status; | |
586 | ||
587 | status = ioat_chansts(chan); | |
588 | ||
589 | /* when halted due to errors check for channel | |
590 | * programming errors before advancing the completion state | |
591 | */ | |
592 | if (is_ioat_halted(status)) { | |
593 | u32 chanerr; | |
594 | ||
595 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
596 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", | |
597 | __func__, chanerr); | |
598 | if (test_bit(IOAT_RUN, &chan->state)) | |
599 | BUG_ON(is_ioat_bug(chanerr)); | |
600 | else /* we never got off the ground */ | |
601 | return; | |
602 | } | |
603 | ||
604 | /* if we haven't made progress and we have already | |
605 | * acknowledged a pending completion once, then be more | |
606 | * forceful with a restart | |
607 | */ | |
608 | spin_lock_bh(&chan->cleanup_lock); | |
609 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
610 | __cleanup(ioat, phys_complete); | |
611 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) { | |
612 | spin_lock_bh(&ioat->prep_lock); | |
613 | ioat3_restart_channel(ioat); | |
614 | spin_unlock_bh(&ioat->prep_lock); | |
615 | spin_unlock_bh(&chan->cleanup_lock); | |
616 | return; | |
617 | } else { | |
618 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
619 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
620 | } | |
621 | ||
622 | ||
623 | if (ioat2_ring_active(ioat)) | |
624 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
625 | else { | |
626 | spin_lock_bh(&ioat->prep_lock); | |
627 | check_active(ioat); | |
628 | spin_unlock_bh(&ioat->prep_lock); | |
629 | } | |
630 | spin_unlock_bh(&chan->cleanup_lock); | |
bf40a686 DW |
631 | } |
632 | ||
633 | static enum dma_status | |
07934481 LW |
634 | ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
635 | struct dma_tx_state *txstate) | |
bf40a686 DW |
636 | { |
637 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
96a2af41 | 638 | enum dma_status ret; |
bf40a686 | 639 | |
96a2af41 RKAL |
640 | ret = dma_cookie_status(c, cookie, txstate); |
641 | if (ret == DMA_SUCCESS) | |
642 | return ret; | |
bf40a686 | 643 | |
074cc476 | 644 | ioat3_cleanup(ioat); |
bf40a686 | 645 | |
96a2af41 | 646 | return dma_cookie_status(c, cookie, txstate); |
bf40a686 DW |
647 | } |
648 | ||
649 | static struct dma_async_tx_descriptor * | |
650 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, | |
651 | size_t len, unsigned long flags) | |
652 | { | |
653 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
654 | struct ioat_ring_ent *desc; | |
655 | size_t total_len = len; | |
656 | struct ioat_fill_descriptor *fill; | |
bf40a686 | 657 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); |
074cc476 | 658 | int num_descs, idx, i; |
bf40a686 DW |
659 | |
660 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
074cc476 DW |
661 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0) |
662 | idx = ioat->head; | |
bf40a686 DW |
663 | else |
664 | return NULL; | |
cdef57db DW |
665 | i = 0; |
666 | do { | |
bf40a686 DW |
667 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
668 | ||
669 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
670 | fill = desc->fill; | |
671 | ||
672 | fill->size = xfer_size; | |
673 | fill->src_data = src_data; | |
674 | fill->dst_addr = dest; | |
675 | fill->ctl = 0; | |
676 | fill->ctl_f.op = IOAT_OP_FILL; | |
677 | ||
678 | len -= xfer_size; | |
679 | dest += xfer_size; | |
680 | dump_desc_dbg(ioat, desc); | |
cdef57db | 681 | } while (++i < num_descs); |
bf40a686 DW |
682 | |
683 | desc->txd.flags = flags; | |
684 | desc->len = total_len; | |
685 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
686 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
687 | fill->ctl_f.compl_write = 1; | |
688 | dump_desc_dbg(ioat, desc); | |
689 | ||
690 | /* we leave the channel locked to ensure in order submission */ | |
691 | return &desc->txd; | |
692 | } | |
693 | ||
b094ad3b DW |
694 | static struct dma_async_tx_descriptor * |
695 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
696 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
697 | size_t len, unsigned long flags) | |
698 | { | |
699 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
700 | struct ioat_ring_ent *compl_desc; | |
701 | struct ioat_ring_ent *desc; | |
702 | struct ioat_ring_ent *ext; | |
703 | size_t total_len = len; | |
704 | struct ioat_xor_descriptor *xor; | |
705 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
706 | struct ioat_dma_descriptor *hw; | |
074cc476 | 707 | int num_descs, with_ext, idx, i; |
b094ad3b | 708 | u32 offset = 0; |
b094ad3b DW |
709 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
710 | ||
711 | BUG_ON(src_cnt < 2); | |
712 | ||
713 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
714 | /* we need 2x the number of descriptors to cover greater than 5 | |
715 | * sources | |
716 | */ | |
717 | if (src_cnt > 5) { | |
718 | with_ext = 1; | |
719 | num_descs *= 2; | |
720 | } else | |
721 | with_ext = 0; | |
722 | ||
723 | /* completion writes from the raid engine may pass completion | |
724 | * writes from the legacy engine, so we need one extra null | |
725 | * (legacy) descriptor to ensure all completion writes arrive in | |
726 | * order. | |
727 | */ | |
074cc476 DW |
728 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0) |
729 | idx = ioat->head; | |
b094ad3b DW |
730 | else |
731 | return NULL; | |
cdef57db DW |
732 | i = 0; |
733 | do { | |
b094ad3b DW |
734 | struct ioat_raw_descriptor *descs[2]; |
735 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
736 | int s; | |
737 | ||
738 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
739 | xor = desc->xor; | |
740 | ||
741 | /* save a branch by unconditionally retrieving the | |
742 | * extended descriptor xor_set_src() knows to not write | |
743 | * to it in the single descriptor case | |
744 | */ | |
745 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
746 | xor_ex = ext->xor_ex; | |
747 | ||
748 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
749 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
750 | for (s = 0; s < src_cnt; s++) | |
751 | xor_set_src(descs, src[s], offset, s); | |
752 | xor->size = xfer_size; | |
753 | xor->dst_addr = dest + offset; | |
754 | xor->ctl = 0; | |
755 | xor->ctl_f.op = op; | |
756 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
757 | ||
758 | len -= xfer_size; | |
759 | offset += xfer_size; | |
760 | dump_desc_dbg(ioat, desc); | |
cdef57db | 761 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
762 | |
763 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
764 | desc->txd.flags = flags; | |
765 | desc->len = total_len; | |
766 | if (result) | |
767 | desc->result = result; | |
768 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
769 | ||
770 | /* completion descriptor carries interrupt bit */ | |
771 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
772 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
773 | hw = compl_desc->hw; | |
774 | hw->ctl = 0; | |
775 | hw->ctl_f.null = 1; | |
776 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
777 | hw->ctl_f.compl_write = 1; | |
778 | hw->size = NULL_DESC_BUFFER_SIZE; | |
779 | dump_desc_dbg(ioat, compl_desc); | |
780 | ||
781 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 782 | return &compl_desc->txd; |
b094ad3b DW |
783 | } |
784 | ||
785 | static struct dma_async_tx_descriptor * | |
786 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
787 | unsigned int src_cnt, size_t len, unsigned long flags) | |
788 | { | |
789 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
790 | } | |
791 | ||
792 | struct dma_async_tx_descriptor * | |
793 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
794 | unsigned int src_cnt, size_t len, | |
795 | enum sum_check_flags *result, unsigned long flags) | |
796 | { | |
797 | /* the cleanup routine only sets bits on validate failure, it | |
798 | * does not clear bits on validate success... so clear it here | |
799 | */ | |
800 | *result = 0; | |
801 | ||
802 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
803 | src_cnt - 1, len, flags); | |
804 | } | |
805 | ||
d69d235b DW |
806 | static void |
807 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
808 | { | |
809 | struct device *dev = to_dev(&ioat->base); | |
810 | struct ioat_pq_descriptor *pq = desc->pq; | |
811 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
812 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
813 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
814 | int i; | |
815 | ||
816 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
50f9f97e | 817 | " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", |
d69d235b DW |
818 | desc_id(desc), (unsigned long long) desc->txd.phys, |
819 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
820 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
821 | pq->ctl_f.compl_write, | |
822 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
823 | pq->ctl_f.src_cnt); | |
824 | for (i = 0; i < src_cnt; i++) | |
825 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
826 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
827 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
828 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
50f9f97e | 829 | dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
d69d235b DW |
830 | } |
831 | ||
832 | static struct dma_async_tx_descriptor * | |
833 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
834 | const dma_addr_t *dst, const dma_addr_t *src, | |
835 | unsigned int src_cnt, const unsigned char *scf, | |
836 | size_t len, unsigned long flags) | |
837 | { | |
838 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
839 | struct ioat_chan_common *chan = &ioat->base; | |
840 | struct ioat_ring_ent *compl_desc; | |
841 | struct ioat_ring_ent *desc; | |
842 | struct ioat_ring_ent *ext; | |
843 | size_t total_len = len; | |
844 | struct ioat_pq_descriptor *pq; | |
845 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
846 | struct ioat_dma_descriptor *hw; | |
847 | u32 offset = 0; | |
d69d235b | 848 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
074cc476 | 849 | int i, s, idx, with_ext, num_descs; |
d69d235b DW |
850 | |
851 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
852 | /* the engine requires at least two sources (we provide | |
853 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
854 | */ | |
855 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
856 | ||
857 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
858 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
859 | * sources (we need 1 extra source in the q-only continuation |
860 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 861 | */ |
cd78809f DW |
862 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
863 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
864 | with_ext = 1; |
865 | num_descs *= 2; | |
866 | } else | |
867 | with_ext = 0; | |
868 | ||
869 | /* completion writes from the raid engine may pass completion | |
870 | * writes from the legacy engine, so we need one extra null | |
871 | * (legacy) descriptor to ensure all completion writes arrive in | |
872 | * order. | |
873 | */ | |
874 | if (likely(num_descs) && | |
074cc476 DW |
875 | ioat2_check_space_lock(ioat, num_descs+1) == 0) |
876 | idx = ioat->head; | |
d69d235b DW |
877 | else |
878 | return NULL; | |
cdef57db DW |
879 | i = 0; |
880 | do { | |
d69d235b DW |
881 | struct ioat_raw_descriptor *descs[2]; |
882 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
883 | ||
884 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
885 | pq = desc->pq; | |
886 | ||
887 | /* save a branch by unconditionally retrieving the | |
888 | * extended descriptor pq_set_src() knows to not write | |
889 | * to it in the single descriptor case | |
890 | */ | |
891 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
892 | pq_ex = ext->pq_ex; | |
893 | ||
894 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
895 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
896 | ||
897 | for (s = 0; s < src_cnt; s++) | |
898 | pq_set_src(descs, src[s], offset, scf[s], s); | |
899 | ||
900 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
901 | if (dmaf_p_disabled_continue(flags)) | |
902 | pq_set_src(descs, dst[1], offset, 1, s++); | |
903 | else if (dmaf_continue(flags)) { | |
904 | pq_set_src(descs, dst[0], offset, 0, s++); | |
905 | pq_set_src(descs, dst[1], offset, 1, s++); | |
906 | pq_set_src(descs, dst[1], offset, 0, s++); | |
907 | } | |
908 | pq->size = xfer_size; | |
909 | pq->p_addr = dst[0] + offset; | |
910 | pq->q_addr = dst[1] + offset; | |
911 | pq->ctl = 0; | |
912 | pq->ctl_f.op = op; | |
913 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); | |
914 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
915 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
916 | ||
917 | len -= xfer_size; | |
918 | offset += xfer_size; | |
cdef57db | 919 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
920 | |
921 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
922 | desc->txd.flags = flags; | |
923 | desc->len = total_len; | |
924 | if (result) | |
925 | desc->result = result; | |
926 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
927 | dump_pq_desc_dbg(ioat, desc, ext); | |
928 | ||
929 | /* completion descriptor carries interrupt bit */ | |
930 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
931 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
932 | hw = compl_desc->hw; | |
933 | hw->ctl = 0; | |
934 | hw->ctl_f.null = 1; | |
935 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
936 | hw->ctl_f.compl_write = 1; | |
937 | hw->size = NULL_DESC_BUFFER_SIZE; | |
938 | dump_desc_dbg(ioat, compl_desc); | |
939 | ||
940 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 941 | return &compl_desc->txd; |
d69d235b DW |
942 | } |
943 | ||
944 | static struct dma_async_tx_descriptor * | |
945 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
946 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
947 | unsigned long flags) | |
948 | { | |
de581b65 DW |
949 | /* specify valid address for disabled result */ |
950 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
951 | dst[0] = dst[1]; | |
952 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
953 | dst[1] = dst[0]; | |
954 | ||
d69d235b DW |
955 | /* handle the single source multiply case from the raid6 |
956 | * recovery path | |
957 | */ | |
de581b65 | 958 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
959 | dma_addr_t single_source[2]; |
960 | unsigned char single_source_coef[2]; | |
961 | ||
962 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
963 | single_source[0] = src[0]; | |
964 | single_source[1] = src[0]; | |
965 | single_source_coef[0] = scf[0]; | |
966 | single_source_coef[1] = 0; | |
967 | ||
968 | return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
969 | single_source_coef, len, flags); | |
970 | } else | |
971 | return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, | |
972 | len, flags); | |
973 | } | |
974 | ||
975 | struct dma_async_tx_descriptor * | |
976 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
977 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
978 | enum sum_check_flags *pqres, unsigned long flags) | |
979 | { | |
de581b65 DW |
980 | /* specify valid address for disabled result */ |
981 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
982 | pq[0] = pq[1]; | |
983 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
984 | pq[1] = pq[0]; | |
985 | ||
d69d235b DW |
986 | /* the cleanup routine only sets bits on validate failure, it |
987 | * does not clear bits on validate success... so clear it here | |
988 | */ | |
989 | *pqres = 0; | |
990 | ||
991 | return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
992 | flags); | |
993 | } | |
994 | ||
ae786624 DW |
995 | static struct dma_async_tx_descriptor * |
996 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
997 | unsigned int src_cnt, size_t len, unsigned long flags) | |
998 | { | |
999 | unsigned char scf[src_cnt]; | |
1000 | dma_addr_t pq[2]; | |
1001 | ||
1002 | memset(scf, 0, src_cnt); | |
ae786624 | 1003 | pq[0] = dst; |
de581b65 DW |
1004 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1005 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 DW |
1006 | |
1007 | return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1008 | flags); | |
1009 | } | |
1010 | ||
1011 | struct dma_async_tx_descriptor * | |
1012 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
1013 | unsigned int src_cnt, size_t len, | |
1014 | enum sum_check_flags *result, unsigned long flags) | |
1015 | { | |
1016 | unsigned char scf[src_cnt]; | |
1017 | dma_addr_t pq[2]; | |
1018 | ||
1019 | /* the cleanup routine only sets bits on validate failure, it | |
1020 | * does not clear bits on validate success... so clear it here | |
1021 | */ | |
1022 | *result = 0; | |
1023 | ||
1024 | memset(scf, 0, src_cnt); | |
ae786624 | 1025 | pq[0] = src[0]; |
de581b65 DW |
1026 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1027 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 DW |
1028 | |
1029 | return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, | |
1030 | len, flags); | |
1031 | } | |
1032 | ||
58c8649e DW |
1033 | static struct dma_async_tx_descriptor * |
1034 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
1035 | { | |
1036 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1037 | struct ioat_ring_ent *desc; | |
1038 | struct ioat_dma_descriptor *hw; | |
58c8649e | 1039 | |
074cc476 DW |
1040 | if (ioat2_check_space_lock(ioat, 1) == 0) |
1041 | desc = ioat2_get_ring_ent(ioat, ioat->head); | |
58c8649e DW |
1042 | else |
1043 | return NULL; | |
1044 | ||
1045 | hw = desc->hw; | |
1046 | hw->ctl = 0; | |
1047 | hw->ctl_f.null = 1; | |
1048 | hw->ctl_f.int_en = 1; | |
1049 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1050 | hw->ctl_f.compl_write = 1; | |
1051 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1052 | hw->src_addr = 0; | |
1053 | hw->dst_addr = 0; | |
1054 | ||
1055 | desc->txd.flags = flags; | |
1056 | desc->len = 1; | |
1057 | ||
1058 | dump_desc_dbg(ioat, desc); | |
1059 | ||
1060 | /* we leave the channel locked to ensure in order submission */ | |
1061 | return &desc->txd; | |
1062 | } | |
1063 | ||
4bf27b8b | 1064 | static void ioat3_dma_test_callback(void *dma_async_param) |
9de6fc71 DW |
1065 | { |
1066 | struct completion *cmp = dma_async_param; | |
1067 | ||
1068 | complete(cmp); | |
1069 | } | |
1070 | ||
1071 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
4bf27b8b | 1072 | static int ioat_xor_val_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1073 | { |
1074 | int i, src_idx; | |
1075 | struct page *dest; | |
1076 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
1077 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1078 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1079 | dma_addr_t dma_addr, dest_dma; | |
1080 | struct dma_async_tx_descriptor *tx; | |
1081 | struct dma_chan *dma_chan; | |
1082 | dma_cookie_t cookie; | |
1083 | u8 cmp_byte = 0; | |
1084 | u32 cmp_word; | |
1085 | u32 xor_val_result; | |
1086 | int err = 0; | |
1087 | struct completion cmp; | |
1088 | unsigned long tmo; | |
1089 | struct device *dev = &device->pdev->dev; | |
1090 | struct dma_device *dma = &device->common; | |
7369f56e | 1091 | u8 op = 0; |
9de6fc71 DW |
1092 | |
1093 | dev_dbg(dev, "%s\n", __func__); | |
1094 | ||
1095 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
1096 | return 0; | |
1097 | ||
1098 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1099 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
1100 | if (!xor_srcs[src_idx]) { | |
1101 | while (src_idx--) | |
1102 | __free_page(xor_srcs[src_idx]); | |
1103 | return -ENOMEM; | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | dest = alloc_page(GFP_KERNEL); | |
1108 | if (!dest) { | |
1109 | while (src_idx--) | |
1110 | __free_page(xor_srcs[src_idx]); | |
1111 | return -ENOMEM; | |
1112 | } | |
1113 | ||
1114 | /* Fill in src buffers */ | |
1115 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1116 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
1117 | for (i = 0; i < PAGE_SIZE; i++) | |
1118 | ptr[i] = (1 << src_idx); | |
1119 | } | |
1120 | ||
1121 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
1122 | cmp_byte ^= (u8) (1 << src_idx); | |
1123 | ||
1124 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
1125 | (cmp_byte << 8) | cmp_byte; | |
1126 | ||
1127 | memset(page_address(dest), 0, PAGE_SIZE); | |
1128 | ||
1129 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
1130 | device_node); | |
1131 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
1132 | err = -ENODEV; | |
1133 | goto out; | |
1134 | } | |
1135 | ||
1136 | /* test xor */ | |
7369f56e BZ |
1137 | op = IOAT_OP_XOR; |
1138 | ||
9de6fc71 DW |
1139 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
1140 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1141 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
1142 | DMA_TO_DEVICE); | |
1143 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
1144 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
7369f56e BZ |
1145 | DMA_PREP_INTERRUPT | |
1146 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1147 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1148 | |
1149 | if (!tx) { | |
1150 | dev_err(dev, "Self-test xor prep failed\n"); | |
1151 | err = -ENODEV; | |
7369f56e | 1152 | goto dma_unmap; |
9de6fc71 DW |
1153 | } |
1154 | ||
1155 | async_tx_ack(tx); | |
1156 | init_completion(&cmp); | |
1157 | tx->callback = ioat3_dma_test_callback; | |
1158 | tx->callback_param = &cmp; | |
1159 | cookie = tx->tx_submit(tx); | |
1160 | if (cookie < 0) { | |
1161 | dev_err(dev, "Self-test xor setup failed\n"); | |
1162 | err = -ENODEV; | |
7369f56e | 1163 | goto dma_unmap; |
9de6fc71 DW |
1164 | } |
1165 | dma->device_issue_pending(dma_chan); | |
1166 | ||
1167 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1168 | ||
07934481 | 1169 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1170 | dev_err(dev, "Self-test xor timed out\n"); |
1171 | err = -ENODEV; | |
7369f56e | 1172 | goto dma_unmap; |
9de6fc71 DW |
1173 | } |
1174 | ||
7369f56e BZ |
1175 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1176 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1177 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1178 | ||
9de6fc71 DW |
1179 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1180 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
1181 | u32 *ptr = page_address(dest); | |
1182 | if (ptr[i] != cmp_word) { | |
1183 | dev_err(dev, "Self-test xor failed compare\n"); | |
1184 | err = -ENODEV; | |
1185 | goto free_resources; | |
1186 | } | |
1187 | } | |
ac498987 | 1188 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
9de6fc71 DW |
1189 | |
1190 | /* skip validate if the capability is not present */ | |
1191 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
1192 | goto free_resources; | |
1193 | ||
7369f56e BZ |
1194 | op = IOAT_OP_XOR_VAL; |
1195 | ||
9de6fc71 DW |
1196 | /* validate the sources with the destintation page */ |
1197 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1198 | xor_val_srcs[i] = xor_srcs[i]; | |
1199 | xor_val_srcs[i] = dest; | |
1200 | ||
1201 | xor_val_result = 1; | |
1202 | ||
1203 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1204 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1205 | DMA_TO_DEVICE); | |
1206 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1207 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1208 | &xor_val_result, DMA_PREP_INTERRUPT | |
1209 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1210 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1211 | if (!tx) { |
1212 | dev_err(dev, "Self-test zero prep failed\n"); | |
1213 | err = -ENODEV; | |
7369f56e | 1214 | goto dma_unmap; |
9de6fc71 DW |
1215 | } |
1216 | ||
1217 | async_tx_ack(tx); | |
1218 | init_completion(&cmp); | |
1219 | tx->callback = ioat3_dma_test_callback; | |
1220 | tx->callback_param = &cmp; | |
1221 | cookie = tx->tx_submit(tx); | |
1222 | if (cookie < 0) { | |
1223 | dev_err(dev, "Self-test zero setup failed\n"); | |
1224 | err = -ENODEV; | |
7369f56e | 1225 | goto dma_unmap; |
9de6fc71 DW |
1226 | } |
1227 | dma->device_issue_pending(dma_chan); | |
1228 | ||
1229 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1230 | ||
07934481 | 1231 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1232 | dev_err(dev, "Self-test validate timed out\n"); |
1233 | err = -ENODEV; | |
7369f56e | 1234 | goto dma_unmap; |
9de6fc71 DW |
1235 | } |
1236 | ||
7369f56e BZ |
1237 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1238 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1239 | ||
9de6fc71 DW |
1240 | if (xor_val_result != 0) { |
1241 | dev_err(dev, "Self-test validate failed compare\n"); | |
1242 | err = -ENODEV; | |
1243 | goto free_resources; | |
1244 | } | |
1245 | ||
1246 | /* skip memset if the capability is not present */ | |
1247 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) | |
1248 | goto free_resources; | |
1249 | ||
1250 | /* test memset */ | |
7369f56e BZ |
1251 | op = IOAT_OP_FILL; |
1252 | ||
9de6fc71 DW |
1253 | dma_addr = dma_map_page(dev, dest, 0, |
1254 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1255 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, | |
7369f56e BZ |
1256 | DMA_PREP_INTERRUPT | |
1257 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1258 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1259 | if (!tx) { |
1260 | dev_err(dev, "Self-test memset prep failed\n"); | |
1261 | err = -ENODEV; | |
7369f56e | 1262 | goto dma_unmap; |
9de6fc71 DW |
1263 | } |
1264 | ||
1265 | async_tx_ack(tx); | |
1266 | init_completion(&cmp); | |
1267 | tx->callback = ioat3_dma_test_callback; | |
1268 | tx->callback_param = &cmp; | |
1269 | cookie = tx->tx_submit(tx); | |
1270 | if (cookie < 0) { | |
1271 | dev_err(dev, "Self-test memset setup failed\n"); | |
1272 | err = -ENODEV; | |
7369f56e | 1273 | goto dma_unmap; |
9de6fc71 DW |
1274 | } |
1275 | dma->device_issue_pending(dma_chan); | |
1276 | ||
1277 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1278 | ||
07934481 | 1279 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1280 | dev_err(dev, "Self-test memset timed out\n"); |
1281 | err = -ENODEV; | |
7369f56e | 1282 | goto dma_unmap; |
9de6fc71 DW |
1283 | } |
1284 | ||
7369f56e BZ |
1285 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); |
1286 | ||
9de6fc71 DW |
1287 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { |
1288 | u32 *ptr = page_address(dest); | |
1289 | if (ptr[i]) { | |
1290 | dev_err(dev, "Self-test memset failed compare\n"); | |
1291 | err = -ENODEV; | |
1292 | goto free_resources; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | /* test for non-zero parity sum */ | |
7369f56e BZ |
1297 | op = IOAT_OP_XOR_VAL; |
1298 | ||
9de6fc71 DW |
1299 | xor_val_result = 0; |
1300 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1301 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1302 | DMA_TO_DEVICE); | |
1303 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1304 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1305 | &xor_val_result, DMA_PREP_INTERRUPT | |
1306 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1307 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1308 | if (!tx) { |
1309 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1310 | err = -ENODEV; | |
7369f56e | 1311 | goto dma_unmap; |
9de6fc71 DW |
1312 | } |
1313 | ||
1314 | async_tx_ack(tx); | |
1315 | init_completion(&cmp); | |
1316 | tx->callback = ioat3_dma_test_callback; | |
1317 | tx->callback_param = &cmp; | |
1318 | cookie = tx->tx_submit(tx); | |
1319 | if (cookie < 0) { | |
1320 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1321 | err = -ENODEV; | |
7369f56e | 1322 | goto dma_unmap; |
9de6fc71 DW |
1323 | } |
1324 | dma->device_issue_pending(dma_chan); | |
1325 | ||
1326 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1327 | ||
07934481 | 1328 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1329 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
1330 | err = -ENODEV; | |
7369f56e | 1331 | goto dma_unmap; |
9de6fc71 DW |
1332 | } |
1333 | ||
1334 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1335 | dev_err(dev, "Self-test validate failed compare\n"); | |
1336 | err = -ENODEV; | |
7369f56e | 1337 | goto dma_unmap; |
9de6fc71 DW |
1338 | } |
1339 | ||
7369f56e BZ |
1340 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1341 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1342 | ||
1343 | goto free_resources; | |
1344 | dma_unmap: | |
1345 | if (op == IOAT_OP_XOR) { | |
1346 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
1347 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1348 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1349 | DMA_TO_DEVICE); | |
1350 | } else if (op == IOAT_OP_XOR_VAL) { | |
1351 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1352 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1353 | DMA_TO_DEVICE); | |
1354 | } else if (op == IOAT_OP_FILL) | |
1355 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); | |
9de6fc71 DW |
1356 | free_resources: |
1357 | dma->device_free_chan_resources(dma_chan); | |
1358 | out: | |
1359 | src_idx = IOAT_NUM_SRC_TEST; | |
1360 | while (src_idx--) | |
1361 | __free_page(xor_srcs[src_idx]); | |
1362 | __free_page(dest); | |
1363 | return err; | |
1364 | } | |
1365 | ||
4bf27b8b | 1366 | static int ioat3_dma_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1367 | { |
1368 | int rc = ioat_dma_self_test(device); | |
1369 | ||
1370 | if (rc) | |
1371 | return rc; | |
1372 | ||
1373 | rc = ioat_xor_val_self_test(device); | |
1374 | if (rc) | |
1375 | return rc; | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
8a52b9ff DJ |
1380 | static int ioat3_irq_reinit(struct ioatdma_device *device) |
1381 | { | |
1382 | int msixcnt = device->common.chancnt; | |
1383 | struct pci_dev *pdev = device->pdev; | |
1384 | int i; | |
1385 | struct msix_entry *msix; | |
1386 | struct ioat_chan_common *chan; | |
1387 | int err = 0; | |
1388 | ||
1389 | switch (device->irq_mode) { | |
1390 | case IOAT_MSIX: | |
1391 | ||
1392 | for (i = 0; i < msixcnt; i++) { | |
1393 | msix = &device->msix_entries[i]; | |
1394 | chan = ioat_chan_by_index(device, i); | |
1395 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1396 | } | |
1397 | ||
1398 | pci_disable_msix(pdev); | |
1399 | break; | |
1400 | ||
1401 | case IOAT_MSIX_SINGLE: | |
1402 | msix = &device->msix_entries[0]; | |
1403 | chan = ioat_chan_by_index(device, 0); | |
1404 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1405 | pci_disable_msix(pdev); | |
1406 | break; | |
1407 | ||
1408 | case IOAT_MSI: | |
1409 | chan = ioat_chan_by_index(device, 0); | |
1410 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1411 | pci_disable_msi(pdev); | |
1412 | break; | |
1413 | ||
1414 | case IOAT_INTX: | |
1415 | chan = ioat_chan_by_index(device, 0); | |
1416 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1417 | break; | |
1418 | ||
1419 | default: | |
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | device->irq_mode = IOAT_NOIRQ; | |
1424 | ||
1425 | err = ioat_dma_setup_interrupts(device); | |
1426 | ||
1427 | return err; | |
1428 | } | |
1429 | ||
a6d52d70 DW |
1430 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1431 | { | |
1432 | /* throw away whatever the channel was doing and get it | |
1433 | * initialized, with ioat3 specific workarounds | |
1434 | */ | |
1435 | struct ioatdma_device *device = chan->device; | |
1436 | struct pci_dev *pdev = device->pdev; | |
1437 | u32 chanerr; | |
1438 | u16 dev_id; | |
1439 | int err; | |
1440 | ||
1441 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1442 | ||
1443 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1444 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1445 | ||
6ead7e48 DJ |
1446 | if (device->version < IOAT_VER_3_3) { |
1447 | /* clear any pending errors */ | |
1448 | err = pci_read_config_dword(pdev, | |
1449 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1450 | if (err) { | |
1451 | dev_err(&pdev->dev, | |
1452 | "channel error register unreachable\n"); | |
1453 | return err; | |
1454 | } | |
1455 | pci_write_config_dword(pdev, | |
1456 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
a6d52d70 | 1457 | |
6ead7e48 DJ |
1458 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
1459 | * (workaround for spurious config parity error after restart) | |
1460 | */ | |
1461 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1462 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1463 | pci_write_config_dword(pdev, | |
1464 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1465 | 0x10); | |
1466 | } | |
1467 | } | |
a6d52d70 | 1468 | |
8a52b9ff DJ |
1469 | err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
1470 | if (err) { | |
1471 | dev_err(&pdev->dev, "Failed to reset!\n"); | |
1472 | return err; | |
570727b5 DJ |
1473 | } |
1474 | ||
8a52b9ff DJ |
1475 | if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev)) |
1476 | err = ioat3_irq_reinit(device); | |
570727b5 | 1477 | |
8a52b9ff | 1478 | return err; |
570727b5 DJ |
1479 | } |
1480 | ||
4bf27b8b | 1481 | int ioat3_dma_probe(struct ioatdma_device *device, int dca) |
bf40a686 DW |
1482 | { |
1483 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1484 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1485 | struct dma_device *dma; |
1486 | struct dma_chan *c; | |
1487 | struct ioat_chan_common *chan; | |
e3232714 | 1488 | bool is_raid_device = false; |
bf40a686 | 1489 | int err; |
bf40a686 DW |
1490 | u32 cap; |
1491 | ||
1492 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1493 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1494 | device->self_test = ioat3_dma_self_test; |
bf40a686 DW |
1495 | dma = &device->common; |
1496 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1497 | dma->device_issue_pending = ioat2_issue_pending; | |
1498 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1499 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e | 1500 | |
570727b5 | 1501 | if (is_xeon_cb32(pdev)) |
f26df1a1 DJ |
1502 | dma->copy_align = 6; |
1503 | ||
58c8649e DW |
1504 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); |
1505 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1506 | ||
bf40a686 | 1507 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c DW |
1508 | |
1509 | /* dca is incompatible with raid operations */ | |
1510 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) | |
1511 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
1512 | ||
b094ad3b | 1513 | if (cap & IOAT_CAP_XOR) { |
e3232714 | 1514 | is_raid_device = true; |
b094ad3b | 1515 | dma->max_xor = 8; |
2adfc550 | 1516 | dma->xor_align = 6; |
b094ad3b DW |
1517 | |
1518 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1519 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1520 | ||
1521 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1522 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1523 | } | |
eceec44e | 1524 | |
d69d235b | 1525 | if (cap & IOAT_CAP_PQ) { |
e3232714 | 1526 | is_raid_device = true; |
d69d235b | 1527 | dma_set_maxpq(dma, 8, 0); |
eceec44e DJ |
1528 | if (is_xeon_cb32(pdev)) |
1529 | dma->pq_align = 6; | |
1530 | else | |
1531 | dma->pq_align = 0; | |
d69d235b DW |
1532 | |
1533 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1534 | dma->device_prep_dma_pq = ioat3_prep_pq; | |
1535 | ||
1536 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1537 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
ae786624 DW |
1538 | |
1539 | if (!(cap & IOAT_CAP_XOR)) { | |
1540 | dma->max_xor = 8; | |
eceec44e DJ |
1541 | if (is_xeon_cb32(pdev)) |
1542 | dma->xor_align = 6; | |
1543 | else | |
1544 | dma->xor_align = 0; | |
ae786624 DW |
1545 | |
1546 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1547 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1548 | ||
1549 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1550 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1551 | } | |
d69d235b | 1552 | } |
eceec44e | 1553 | |
e3232714 DW |
1554 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
1555 | dma_cap_set(DMA_MEMSET, dma->cap_mask); | |
1556 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; | |
1557 | } | |
1558 | ||
1559 | ||
9a37f644 DJ |
1560 | dma->device_tx_status = ioat3_tx_status; |
1561 | device->cleanup_fn = ioat3_cleanup_event; | |
1562 | device->timer_fn = ioat3_timer_event; | |
bf40a686 | 1563 | |
3f09ede4 DJ |
1564 | if (is_xeon_cb32(pdev)) { |
1565 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); | |
1566 | dma->device_prep_dma_xor_val = NULL; | |
7b3cc2b1 | 1567 | |
3f09ede4 DJ |
1568 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); |
1569 | dma->device_prep_dma_pq_val = NULL; | |
1570 | } | |
7b3cc2b1 | 1571 | |
bf40a686 DW |
1572 | err = ioat_probe(device); |
1573 | if (err) | |
1574 | return err; | |
1575 | ioat_set_tcp_copy_break(262144); | |
1576 | ||
1577 | list_for_each_entry(c, &dma->channels, device_node) { | |
1578 | chan = to_chan_common(c); | |
1579 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1580 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1581 | } | |
1582 | ||
1583 | err = ioat_register(device); | |
1584 | if (err) | |
1585 | return err; | |
5669e31c DW |
1586 | |
1587 | ioat_kobject_add(device, &ioat2_ktype); | |
1588 | ||
bf40a686 DW |
1589 | if (dca) |
1590 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1591 | ||
1592 | return 0; | |
1593 | } |