Commit | Line | Data |
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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
7727eaa4 | 58 | #include <linux/module.h> |
bf40a686 | 59 | #include <linux/pci.h> |
5a0e3ad6 | 60 | #include <linux/gfp.h> |
bf40a686 DW |
61 | #include <linux/dmaengine.h> |
62 | #include <linux/dma-mapping.h> | |
70c71606 | 63 | #include <linux/prefetch.h> |
949ff5b8 | 64 | #include "../dmaengine.h" |
bf40a686 DW |
65 | #include "registers.h" |
66 | #include "hw.h" | |
67 | #include "dma.h" | |
68 | #include "dma_v2.h" | |
69 | ||
b094ad3b DW |
70 | /* ioat hardware assumes at least two sources for raid operations */ |
71 | #define src_cnt_to_sw(x) ((x) + 2) | |
72 | #define src_cnt_to_hw(x) ((x) - 2) | |
7727eaa4 DJ |
73 | #define ndest_to_sw(x) ((x) + 1) |
74 | #define ndest_to_hw(x) ((x) - 1) | |
75 | #define src16_cnt_to_sw(x) ((x) + 9) | |
76 | #define src16_cnt_to_hw(x) ((x) - 9) | |
b094ad3b DW |
77 | |
78 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 79 | * extended descriptor of an xor or pq descriptor |
b094ad3b | 80 | */ |
d0b0c8c7 | 81 | static const u8 xor_idx_to_desc = 0xe0; |
9b487ced AK |
82 | static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
83 | static const u8 pq_idx_to_desc = 0xf8; | |
7727eaa4 DJ |
84 | static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1, |
85 | 2, 2, 2, 2, 2, 2, 2 }; | |
9b487ced | 86 | static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; |
7727eaa4 DJ |
87 | static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7, |
88 | 0, 1, 2, 3, 4, 5, 6 }; | |
89 | ||
90 | /* | |
91 | * technically sources 1 and 2 do not require SED, but the op will have | |
92 | * at least 9 descriptors so that's irrelevant. | |
93 | */ | |
94 | static const u8 pq16_idx_to_sed[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
95 | 1, 1, 1, 1, 1, 1, 1 }; | |
b094ad3b | 96 | |
3f09ede4 DJ |
97 | static void ioat3_eh(struct ioat2_dma_chan *ioat); |
98 | ||
b094ad3b DW |
99 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
100 | { | |
101 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
102 | ||
103 | return raw->field[xor_idx_to_field[idx]]; | |
104 | } | |
105 | ||
106 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
107 | dma_addr_t addr, u32 offset, int idx) | |
108 | { | |
109 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
110 | ||
111 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
112 | } | |
113 | ||
d69d235b DW |
114 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
115 | { | |
116 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
117 | ||
118 | return raw->field[pq_idx_to_field[idx]]; | |
119 | } | |
120 | ||
7727eaa4 DJ |
121 | static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx) |
122 | { | |
123 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
124 | ||
125 | return raw->field[pq16_idx_to_field[idx]]; | |
126 | } | |
127 | ||
d69d235b DW |
128 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], |
129 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
130 | { | |
131 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
132 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
133 | ||
134 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
135 | pq->coef[idx] = coef; | |
136 | } | |
137 | ||
7727eaa4 DJ |
138 | static int sed_get_pq16_pool_idx(int src_cnt) |
139 | { | |
140 | ||
141 | return pq16_idx_to_sed[src_cnt]; | |
142 | } | |
143 | ||
8a52b9ff DJ |
144 | static bool is_jf_ioat(struct pci_dev *pdev) |
145 | { | |
146 | switch (pdev->device) { | |
147 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: | |
148 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: | |
149 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: | |
150 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: | |
151 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: | |
152 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: | |
153 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: | |
154 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: | |
155 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: | |
156 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: | |
157 | return true; | |
158 | default: | |
159 | return false; | |
160 | } | |
161 | } | |
162 | ||
163 | static bool is_snb_ioat(struct pci_dev *pdev) | |
164 | { | |
165 | switch (pdev->device) { | |
166 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: | |
167 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: | |
168 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: | |
169 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: | |
170 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: | |
171 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: | |
172 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: | |
173 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: | |
174 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: | |
175 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: | |
176 | return true; | |
177 | default: | |
178 | return false; | |
179 | } | |
180 | } | |
181 | ||
182 | static bool is_ivb_ioat(struct pci_dev *pdev) | |
183 | { | |
184 | switch (pdev->device) { | |
185 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: | |
186 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: | |
187 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: | |
188 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: | |
189 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: | |
190 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: | |
191 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: | |
192 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: | |
193 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: | |
194 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: | |
195 | return true; | |
196 | default: | |
197 | return false; | |
198 | } | |
199 | ||
200 | } | |
201 | ||
202 | static bool is_hsw_ioat(struct pci_dev *pdev) | |
203 | { | |
204 | switch (pdev->device) { | |
205 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: | |
206 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: | |
207 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: | |
208 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: | |
209 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: | |
210 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: | |
211 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: | |
212 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: | |
213 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: | |
214 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: | |
215 | return true; | |
216 | default: | |
217 | return false; | |
218 | } | |
219 | ||
220 | } | |
221 | ||
222 | static bool is_xeon_cb32(struct pci_dev *pdev) | |
223 | { | |
224 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || | |
225 | is_hsw_ioat(pdev); | |
226 | } | |
227 | ||
228 | static bool is_bwd_ioat(struct pci_dev *pdev) | |
229 | { | |
230 | switch (pdev->device) { | |
231 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: | |
232 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: | |
233 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: | |
234 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: | |
235 | return true; | |
236 | default: | |
237 | return false; | |
238 | } | |
239 | } | |
240 | ||
7727eaa4 DJ |
241 | static void pq16_set_src(struct ioat_raw_descriptor *desc[3], |
242 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
243 | { | |
244 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0]; | |
245 | struct ioat_pq16a_descriptor *pq16 = | |
246 | (struct ioat_pq16a_descriptor *)desc[1]; | |
247 | struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; | |
248 | ||
249 | raw->field[pq16_idx_to_field[idx]] = addr + offset; | |
250 | ||
251 | if (idx < 8) | |
252 | pq->coef[idx] = coef; | |
253 | else | |
254 | pq16->coef[idx - 8] = coef; | |
255 | } | |
256 | ||
257 | struct ioat_sed_ent * | |
258 | ioat3_alloc_sed(struct ioatdma_device *device, unsigned int hw_pool) | |
259 | { | |
260 | struct ioat_sed_ent *sed; | |
261 | gfp_t flags = __GFP_ZERO | GFP_ATOMIC; | |
262 | ||
263 | sed = kmem_cache_alloc(device->sed_pool, flags); | |
264 | if (!sed) | |
265 | return NULL; | |
266 | ||
267 | sed->hw_pool = hw_pool; | |
268 | sed->hw = dma_pool_alloc(device->sed_hw_pool[hw_pool], | |
269 | flags, &sed->dma); | |
270 | if (!sed->hw) { | |
271 | kmem_cache_free(device->sed_pool, sed); | |
272 | return NULL; | |
273 | } | |
274 | ||
275 | return sed; | |
276 | } | |
277 | ||
278 | void ioat3_free_sed(struct ioatdma_device *device, struct ioat_sed_ent *sed) | |
279 | { | |
280 | if (!sed) | |
281 | return; | |
282 | ||
283 | dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
284 | kmem_cache_free(device->sed_pool, sed); | |
285 | } | |
286 | ||
bf40a686 | 287 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 288 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
289 | { |
290 | struct ioat_chan_common *chan = &ioat->base; | |
291 | struct pci_dev *pdev = chan->device->pdev; | |
292 | size_t len = desc->len; | |
293 | size_t offset = len - desc->hw->size; | |
294 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
295 | enum dma_ctrl_flags flags = tx->flags; | |
296 | ||
297 | switch (desc->hw->ctl_f.op) { | |
298 | case IOAT_OP_COPY: | |
58c8649e DW |
299 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
300 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 DW |
301 | break; |
302 | case IOAT_OP_FILL: { | |
303 | struct ioat_fill_descriptor *hw = desc->fill; | |
304 | ||
305 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
306 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
307 | PCI_DMA_FROMDEVICE, flags, 1); | |
308 | break; | |
309 | } | |
b094ad3b DW |
310 | case IOAT_OP_XOR_VAL: |
311 | case IOAT_OP_XOR: { | |
312 | struct ioat_xor_descriptor *xor = desc->xor; | |
313 | struct ioat_ring_ent *ext; | |
314 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
315 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
316 | struct ioat_raw_descriptor *descs[2]; | |
317 | int i; | |
318 | ||
319 | if (src_cnt > 5) { | |
320 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
321 | xor_ex = ext->xor_ex; | |
322 | } | |
323 | ||
324 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
325 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
326 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
327 | for (i = 0; i < src_cnt; i++) { | |
328 | dma_addr_t src = xor_get_src(descs, i); | |
329 | ||
330 | ioat_unmap(pdev, src - offset, len, | |
331 | PCI_DMA_TODEVICE, flags, 0); | |
332 | } | |
333 | ||
334 | /* dest is a source in xor validate operations */ | |
335 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
336 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
337 | PCI_DMA_TODEVICE, flags, 1); | |
338 | break; | |
339 | } | |
340 | } | |
341 | ||
342 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
343 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
344 | PCI_DMA_FROMDEVICE, flags, 1); | |
345 | break; | |
346 | } | |
d69d235b DW |
347 | case IOAT_OP_PQ_VAL: |
348 | case IOAT_OP_PQ: { | |
349 | struct ioat_pq_descriptor *pq = desc->pq; | |
350 | struct ioat_ring_ent *ext; | |
351 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
352 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
353 | struct ioat_raw_descriptor *descs[2]; | |
354 | int i; | |
355 | ||
356 | if (src_cnt > 3) { | |
357 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
358 | pq_ex = ext->pq_ex; | |
359 | } | |
360 | ||
361 | /* in the 'continue' case don't unmap the dests as sources */ | |
362 | if (dmaf_p_disabled_continue(flags)) | |
363 | src_cnt--; | |
364 | else if (dmaf_continue(flags)) | |
365 | src_cnt -= 3; | |
366 | ||
367 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
368 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
369 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
370 | for (i = 0; i < src_cnt; i++) { | |
371 | dma_addr_t src = pq_get_src(descs, i); | |
372 | ||
373 | ioat_unmap(pdev, src - offset, len, | |
374 | PCI_DMA_TODEVICE, flags, 0); | |
375 | } | |
376 | ||
377 | /* the dests are sources in pq validate operations */ | |
378 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
379 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
380 | ioat_unmap(pdev, pq->p_addr - offset, | |
381 | len, PCI_DMA_TODEVICE, flags, 0); | |
382 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
383 | ioat_unmap(pdev, pq->q_addr - offset, | |
384 | len, PCI_DMA_TODEVICE, flags, 0); | |
385 | break; | |
386 | } | |
387 | } | |
388 | ||
389 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
390 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
391 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
392 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
393 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
394 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
395 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
396 | } | |
397 | break; | |
398 | } | |
7727eaa4 DJ |
399 | case IOAT_OP_PQ_16S: |
400 | case IOAT_OP_PQ_VAL_16S: { | |
401 | struct ioat_pq_descriptor *pq = desc->pq; | |
402 | int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); | |
403 | struct ioat_raw_descriptor *descs[4]; | |
404 | int i; | |
405 | ||
406 | /* in the 'continue' case don't unmap the dests as sources */ | |
407 | if (dmaf_p_disabled_continue(flags)) | |
408 | src_cnt--; | |
409 | else if (dmaf_continue(flags)) | |
410 | src_cnt -= 3; | |
411 | ||
412 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
413 | descs[0] = (struct ioat_raw_descriptor *)pq; | |
414 | descs[1] = (struct ioat_raw_descriptor *)(desc->sed->hw); | |
415 | descs[2] = (struct ioat_raw_descriptor *)(&desc->sed->hw->b[0]); | |
416 | for (i = 0; i < src_cnt; i++) { | |
417 | dma_addr_t src = pq16_get_src(descs, i); | |
418 | ||
419 | ioat_unmap(pdev, src - offset, len, | |
420 | PCI_DMA_TODEVICE, flags, 0); | |
421 | } | |
422 | ||
423 | /* the dests are sources in pq validate operations */ | |
424 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
425 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
426 | ioat_unmap(pdev, pq->p_addr - offset, | |
427 | len, PCI_DMA_TODEVICE, | |
428 | flags, 0); | |
429 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
430 | ioat_unmap(pdev, pq->q_addr - offset, | |
431 | len, PCI_DMA_TODEVICE, | |
432 | flags, 0); | |
433 | break; | |
434 | } | |
435 | } | |
436 | ||
437 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
438 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
439 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
440 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
441 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
442 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
443 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
444 | } | |
445 | break; | |
446 | } | |
bf40a686 DW |
447 | default: |
448 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
449 | __func__, desc->hw->ctl_f.op); | |
450 | } | |
451 | } | |
452 | ||
b094ad3b DW |
453 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
454 | { | |
455 | struct ioat_dma_descriptor *hw = desc->hw; | |
456 | ||
457 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
458 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
459 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 460 | |
b094ad3b DW |
461 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
462 | return true; | |
d69d235b DW |
463 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
464 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
465 | struct ioat_pq_descriptor *pq = desc->pq; | |
466 | ||
467 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
468 | return true; | |
b094ad3b DW |
469 | } |
470 | ||
471 | return false; | |
472 | } | |
473 | ||
3f09ede4 DJ |
474 | static u64 ioat3_get_current_completion(struct ioat_chan_common *chan) |
475 | { | |
476 | u64 phys_complete; | |
477 | u64 completion; | |
478 | ||
479 | completion = *chan->completion; | |
480 | phys_complete = ioat_chansts_to_addr(completion); | |
481 | ||
482 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, | |
483 | (unsigned long long) phys_complete); | |
484 | ||
485 | return phys_complete; | |
486 | } | |
487 | ||
488 | static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan, | |
489 | u64 *phys_complete) | |
490 | { | |
491 | *phys_complete = ioat3_get_current_completion(chan); | |
492 | if (*phys_complete == chan->last_completion) | |
493 | return false; | |
494 | ||
495 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); | |
496 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
497 | ||
498 | return true; | |
499 | } | |
500 | ||
b094ad3b DW |
501 | /** |
502 | * __cleanup - reclaim used descriptors | |
503 | * @ioat: channel (ring) to clean | |
504 | * | |
505 | * The difference from the dma_v2.c __cleanup() is that this routine | |
506 | * handles extended descriptors and dma-unmapping raid operations. | |
507 | */ | |
27502935 | 508 | static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete) |
bf40a686 DW |
509 | { |
510 | struct ioat_chan_common *chan = &ioat->base; | |
7727eaa4 | 511 | struct ioatdma_device *device = chan->device; |
bf40a686 DW |
512 | struct ioat_ring_ent *desc; |
513 | bool seen_current = false; | |
074cc476 | 514 | int idx = ioat->tail, i; |
bf40a686 | 515 | u16 active; |
bf40a686 DW |
516 | |
517 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
518 | __func__, ioat->head, ioat->tail, ioat->issued); | |
519 | ||
3f09ede4 DJ |
520 | /* |
521 | * At restart of the channel, the completion address and the | |
522 | * channel status will be 0 due to starting a new chain. Since | |
523 | * it's new chain and the first descriptor "fails", there is | |
524 | * nothing to clean up. We do not want to reap the entire submitted | |
525 | * chain due to this 0 address value and then BUG. | |
526 | */ | |
527 | if (!phys_complete) | |
528 | return; | |
529 | ||
bf40a686 DW |
530 | active = ioat2_ring_active(ioat); |
531 | for (i = 0; i < active && !seen_current; i++) { | |
532 | struct dma_async_tx_descriptor *tx; | |
533 | ||
074cc476 DW |
534 | smp_read_barrier_depends(); |
535 | prefetch(ioat2_get_ring_ent(ioat, idx + i + 1)); | |
536 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
bf40a686 DW |
537 | dump_desc_dbg(ioat, desc); |
538 | tx = &desc->txd; | |
539 | if (tx->cookie) { | |
f7fbce07 | 540 | dma_cookie_complete(tx); |
074cc476 | 541 | ioat3_dma_unmap(ioat, desc, idx + i); |
bf40a686 DW |
542 | if (tx->callback) { |
543 | tx->callback(tx->callback_param); | |
544 | tx->callback = NULL; | |
545 | } | |
546 | } | |
547 | ||
548 | if (tx->phys == phys_complete) | |
549 | seen_current = true; | |
b094ad3b DW |
550 | |
551 | /* skip extended descriptors */ | |
552 | if (desc_has_ext(desc)) { | |
553 | BUG_ON(i + 1 >= active); | |
554 | i++; | |
555 | } | |
7727eaa4 DJ |
556 | |
557 | /* cleanup super extended descriptors */ | |
558 | if (desc->sed) { | |
559 | ioat3_free_sed(device, desc->sed); | |
560 | desc->sed = NULL; | |
561 | } | |
bf40a686 | 562 | } |
074cc476 DW |
563 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
564 | ioat->tail = idx + i; | |
aa75db00 | 565 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
bf40a686 | 566 | chan->last_completion = phys_complete; |
b9cc9869 | 567 | |
074cc476 | 568 | if (active - i == 0) { |
bf40a686 DW |
569 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
570 | __func__); | |
571 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
572 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
573 | } | |
b9cc9869 | 574 | /* 5 microsecond delay per pending descriptor */ |
074cc476 | 575 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
b9cc9869 | 576 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); |
bf40a686 DW |
577 | } |
578 | ||
074cc476 | 579 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) |
bf40a686 DW |
580 | { |
581 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 582 | u64 phys_complete; |
bf40a686 | 583 | |
b9cc9869 | 584 | spin_lock_bh(&chan->cleanup_lock); |
3f09ede4 DJ |
585 | |
586 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
074cc476 | 587 | __cleanup(ioat, phys_complete); |
3f09ede4 DJ |
588 | |
589 | if (is_ioat_halted(*chan->completion)) { | |
590 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
591 | ||
592 | if (chanerr & IOAT_CHANERR_HANDLE_MASK) { | |
593 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
594 | ioat3_eh(ioat); | |
595 | } | |
596 | } | |
597 | ||
b9cc9869 DW |
598 | spin_unlock_bh(&chan->cleanup_lock); |
599 | } | |
600 | ||
aa4d72ae | 601 | static void ioat3_cleanup_event(unsigned long data) |
bf40a686 | 602 | { |
aa4d72ae | 603 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
bf40a686 | 604 | |
074cc476 | 605 | ioat3_cleanup(ioat); |
773d9e2d | 606 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
607 | } |
608 | ||
609 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
610 | { | |
611 | struct ioat_chan_common *chan = &ioat->base; | |
3f09ede4 | 612 | u64 phys_complete; |
bf40a686 | 613 | |
b372ec2d | 614 | ioat2_quiesce(chan, 0); |
3f09ede4 | 615 | if (ioat3_cleanup_preamble(chan, &phys_complete)) |
bf40a686 DW |
616 | __cleanup(ioat, phys_complete); |
617 | ||
618 | __ioat2_restart_chan(ioat); | |
619 | } | |
620 | ||
3f09ede4 DJ |
621 | static void ioat3_eh(struct ioat2_dma_chan *ioat) |
622 | { | |
623 | struct ioat_chan_common *chan = &ioat->base; | |
624 | struct pci_dev *pdev = to_pdev(chan); | |
625 | struct ioat_dma_descriptor *hw; | |
626 | u64 phys_complete; | |
627 | struct ioat_ring_ent *desc; | |
628 | u32 err_handled = 0; | |
629 | u32 chanerr_int; | |
630 | u32 chanerr; | |
631 | ||
632 | /* cleanup so tail points to descriptor that caused the error */ | |
633 | if (ioat3_cleanup_preamble(chan, &phys_complete)) | |
634 | __cleanup(ioat, phys_complete); | |
635 | ||
636 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
637 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
638 | ||
639 | dev_dbg(to_dev(chan), "%s: error = %x:%x\n", | |
640 | __func__, chanerr, chanerr_int); | |
641 | ||
642 | desc = ioat2_get_ring_ent(ioat, ioat->tail); | |
643 | hw = desc->hw; | |
644 | dump_desc_dbg(ioat, desc); | |
645 | ||
646 | switch (hw->ctl_f.op) { | |
647 | case IOAT_OP_XOR_VAL: | |
648 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
649 | *desc->result |= SUM_CHECK_P_RESULT; | |
650 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
651 | } | |
652 | break; | |
653 | case IOAT_OP_PQ_VAL: | |
7727eaa4 | 654 | case IOAT_OP_PQ_VAL_16S: |
3f09ede4 DJ |
655 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { |
656 | *desc->result |= SUM_CHECK_P_RESULT; | |
657 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
658 | } | |
659 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
660 | *desc->result |= SUM_CHECK_Q_RESULT; | |
661 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
662 | } | |
663 | break; | |
664 | } | |
665 | ||
666 | /* fault on unhandled error or spurious halt */ | |
667 | if (chanerr ^ err_handled || chanerr == 0) { | |
668 | dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n", | |
669 | __func__, chanerr, err_handled); | |
670 | BUG(); | |
671 | } | |
672 | ||
673 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
674 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
675 | ||
676 | /* mark faulting descriptor as complete */ | |
677 | *chan->completion = desc->txd.phys; | |
678 | ||
679 | spin_lock_bh(&ioat->prep_lock); | |
680 | ioat3_restart_channel(ioat); | |
681 | spin_unlock_bh(&ioat->prep_lock); | |
682 | } | |
683 | ||
4dec23d7 | 684 | static void check_active(struct ioat2_dma_chan *ioat) |
bf40a686 | 685 | { |
bf40a686 DW |
686 | struct ioat_chan_common *chan = &ioat->base; |
687 | ||
4dec23d7 DJ |
688 | if (ioat2_ring_active(ioat)) { |
689 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
690 | return; | |
691 | } | |
bf40a686 | 692 | |
4dec23d7 DJ |
693 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state)) |
694 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
695 | else if (ioat->alloc_order > ioat_get_alloc_order()) { | |
bf40a686 DW |
696 | /* if the ring is idle, empty, and oversized try to step |
697 | * down the size | |
698 | */ | |
4dec23d7 | 699 | reshape_ring(ioat, ioat->alloc_order - 1); |
bf40a686 DW |
700 | |
701 | /* keep shrinking until we get back to our minimum | |
702 | * default size | |
703 | */ | |
704 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
705 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
706 | } | |
4dec23d7 DJ |
707 | |
708 | } | |
709 | ||
a20702b8 | 710 | static void ioat3_timer_event(unsigned long data) |
4dec23d7 DJ |
711 | { |
712 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); | |
713 | struct ioat_chan_common *chan = &ioat->base; | |
714 | dma_addr_t phys_complete; | |
715 | u64 status; | |
716 | ||
717 | status = ioat_chansts(chan); | |
718 | ||
719 | /* when halted due to errors check for channel | |
720 | * programming errors before advancing the completion state | |
721 | */ | |
722 | if (is_ioat_halted(status)) { | |
723 | u32 chanerr; | |
724 | ||
725 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
726 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", | |
727 | __func__, chanerr); | |
728 | if (test_bit(IOAT_RUN, &chan->state)) | |
729 | BUG_ON(is_ioat_bug(chanerr)); | |
730 | else /* we never got off the ground */ | |
731 | return; | |
732 | } | |
733 | ||
734 | /* if we haven't made progress and we have already | |
735 | * acknowledged a pending completion once, then be more | |
736 | * forceful with a restart | |
737 | */ | |
738 | spin_lock_bh(&chan->cleanup_lock); | |
739 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
740 | __cleanup(ioat, phys_complete); | |
741 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) { | |
742 | spin_lock_bh(&ioat->prep_lock); | |
743 | ioat3_restart_channel(ioat); | |
744 | spin_unlock_bh(&ioat->prep_lock); | |
745 | spin_unlock_bh(&chan->cleanup_lock); | |
746 | return; | |
747 | } else { | |
748 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
749 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
750 | } | |
751 | ||
752 | ||
753 | if (ioat2_ring_active(ioat)) | |
754 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
755 | else { | |
756 | spin_lock_bh(&ioat->prep_lock); | |
757 | check_active(ioat); | |
758 | spin_unlock_bh(&ioat->prep_lock); | |
759 | } | |
760 | spin_unlock_bh(&chan->cleanup_lock); | |
bf40a686 DW |
761 | } |
762 | ||
763 | static enum dma_status | |
07934481 LW |
764 | ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
765 | struct dma_tx_state *txstate) | |
bf40a686 DW |
766 | { |
767 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
96a2af41 | 768 | enum dma_status ret; |
bf40a686 | 769 | |
96a2af41 RKAL |
770 | ret = dma_cookie_status(c, cookie, txstate); |
771 | if (ret == DMA_SUCCESS) | |
772 | return ret; | |
bf40a686 | 773 | |
074cc476 | 774 | ioat3_cleanup(ioat); |
bf40a686 | 775 | |
96a2af41 | 776 | return dma_cookie_status(c, cookie, txstate); |
bf40a686 DW |
777 | } |
778 | ||
779 | static struct dma_async_tx_descriptor * | |
780 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, | |
781 | size_t len, unsigned long flags) | |
782 | { | |
783 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
784 | struct ioat_ring_ent *desc; | |
785 | size_t total_len = len; | |
786 | struct ioat_fill_descriptor *fill; | |
bf40a686 | 787 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); |
074cc476 | 788 | int num_descs, idx, i; |
bf40a686 DW |
789 | |
790 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
074cc476 DW |
791 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0) |
792 | idx = ioat->head; | |
bf40a686 DW |
793 | else |
794 | return NULL; | |
cdef57db DW |
795 | i = 0; |
796 | do { | |
bf40a686 DW |
797 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
798 | ||
799 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
800 | fill = desc->fill; | |
801 | ||
802 | fill->size = xfer_size; | |
803 | fill->src_data = src_data; | |
804 | fill->dst_addr = dest; | |
805 | fill->ctl = 0; | |
806 | fill->ctl_f.op = IOAT_OP_FILL; | |
807 | ||
808 | len -= xfer_size; | |
809 | dest += xfer_size; | |
810 | dump_desc_dbg(ioat, desc); | |
cdef57db | 811 | } while (++i < num_descs); |
bf40a686 DW |
812 | |
813 | desc->txd.flags = flags; | |
814 | desc->len = total_len; | |
815 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
816 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
817 | fill->ctl_f.compl_write = 1; | |
818 | dump_desc_dbg(ioat, desc); | |
819 | ||
820 | /* we leave the channel locked to ensure in order submission */ | |
821 | return &desc->txd; | |
822 | } | |
823 | ||
b094ad3b DW |
824 | static struct dma_async_tx_descriptor * |
825 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
826 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
827 | size_t len, unsigned long flags) | |
828 | { | |
829 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
830 | struct ioat_ring_ent *compl_desc; | |
831 | struct ioat_ring_ent *desc; | |
832 | struct ioat_ring_ent *ext; | |
833 | size_t total_len = len; | |
834 | struct ioat_xor_descriptor *xor; | |
835 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
836 | struct ioat_dma_descriptor *hw; | |
074cc476 | 837 | int num_descs, with_ext, idx, i; |
b094ad3b | 838 | u32 offset = 0; |
b094ad3b DW |
839 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
840 | ||
841 | BUG_ON(src_cnt < 2); | |
842 | ||
843 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
844 | /* we need 2x the number of descriptors to cover greater than 5 | |
845 | * sources | |
846 | */ | |
847 | if (src_cnt > 5) { | |
848 | with_ext = 1; | |
849 | num_descs *= 2; | |
850 | } else | |
851 | with_ext = 0; | |
852 | ||
853 | /* completion writes from the raid engine may pass completion | |
854 | * writes from the legacy engine, so we need one extra null | |
855 | * (legacy) descriptor to ensure all completion writes arrive in | |
856 | * order. | |
857 | */ | |
074cc476 DW |
858 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0) |
859 | idx = ioat->head; | |
b094ad3b DW |
860 | else |
861 | return NULL; | |
cdef57db DW |
862 | i = 0; |
863 | do { | |
b094ad3b DW |
864 | struct ioat_raw_descriptor *descs[2]; |
865 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
866 | int s; | |
867 | ||
868 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
869 | xor = desc->xor; | |
870 | ||
871 | /* save a branch by unconditionally retrieving the | |
872 | * extended descriptor xor_set_src() knows to not write | |
873 | * to it in the single descriptor case | |
874 | */ | |
875 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
876 | xor_ex = ext->xor_ex; | |
877 | ||
878 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
879 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
880 | for (s = 0; s < src_cnt; s++) | |
881 | xor_set_src(descs, src[s], offset, s); | |
882 | xor->size = xfer_size; | |
883 | xor->dst_addr = dest + offset; | |
884 | xor->ctl = 0; | |
885 | xor->ctl_f.op = op; | |
886 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
887 | ||
888 | len -= xfer_size; | |
889 | offset += xfer_size; | |
890 | dump_desc_dbg(ioat, desc); | |
cdef57db | 891 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
892 | |
893 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
894 | desc->txd.flags = flags; | |
895 | desc->len = total_len; | |
896 | if (result) | |
897 | desc->result = result; | |
898 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
899 | ||
900 | /* completion descriptor carries interrupt bit */ | |
901 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
902 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
903 | hw = compl_desc->hw; | |
904 | hw->ctl = 0; | |
905 | hw->ctl_f.null = 1; | |
906 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
907 | hw->ctl_f.compl_write = 1; | |
908 | hw->size = NULL_DESC_BUFFER_SIZE; | |
909 | dump_desc_dbg(ioat, compl_desc); | |
910 | ||
911 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 912 | return &compl_desc->txd; |
b094ad3b DW |
913 | } |
914 | ||
915 | static struct dma_async_tx_descriptor * | |
916 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
917 | unsigned int src_cnt, size_t len, unsigned long flags) | |
918 | { | |
919 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
920 | } | |
921 | ||
922 | struct dma_async_tx_descriptor * | |
923 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
924 | unsigned int src_cnt, size_t len, | |
925 | enum sum_check_flags *result, unsigned long flags) | |
926 | { | |
927 | /* the cleanup routine only sets bits on validate failure, it | |
928 | * does not clear bits on validate success... so clear it here | |
929 | */ | |
930 | *result = 0; | |
931 | ||
932 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
933 | src_cnt - 1, len, flags); | |
934 | } | |
935 | ||
d69d235b DW |
936 | static void |
937 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
938 | { | |
939 | struct device *dev = to_dev(&ioat->base); | |
940 | struct ioat_pq_descriptor *pq = desc->pq; | |
941 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
942 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
943 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
944 | int i; | |
945 | ||
946 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
7727eaa4 DJ |
947 | " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" |
948 | " src_cnt: %d)\n", | |
d69d235b DW |
949 | desc_id(desc), (unsigned long long) desc->txd.phys, |
950 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
951 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
952 | pq->ctl_f.compl_write, | |
953 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
954 | pq->ctl_f.src_cnt); | |
955 | for (i = 0; i < src_cnt; i++) | |
956 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
957 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
958 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
959 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
50f9f97e | 960 | dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
d69d235b DW |
961 | } |
962 | ||
7727eaa4 DJ |
963 | static void dump_pq16_desc_dbg(struct ioat2_dma_chan *ioat, |
964 | struct ioat_ring_ent *desc) | |
965 | { | |
966 | struct device *dev = to_dev(&ioat->base); | |
967 | struct ioat_pq_descriptor *pq = desc->pq; | |
968 | struct ioat_raw_descriptor *descs[] = { (void *)pq, | |
969 | (void *)pq, | |
970 | (void *)pq }; | |
971 | int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); | |
972 | int i; | |
973 | ||
974 | if (desc->sed) { | |
975 | descs[1] = (void *)desc->sed->hw; | |
976 | descs[2] = (void *)desc->sed->hw + 64; | |
977 | } | |
978 | ||
979 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
980 | " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" | |
981 | " src_cnt: %d)\n", | |
982 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
983 | (unsigned long long) pq->next, | |
984 | desc->txd.flags, pq->size, pq->ctl, | |
985 | pq->ctl_f.op, pq->ctl_f.int_en, | |
986 | pq->ctl_f.compl_write, | |
987 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
988 | pq->ctl_f.src_cnt); | |
989 | for (i = 0; i < src_cnt; i++) { | |
990 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
991 | (unsigned long long) pq16_get_src(descs, i), | |
992 | pq->coef[i]); | |
993 | } | |
994 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
995 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
996 | } | |
997 | ||
d69d235b DW |
998 | static struct dma_async_tx_descriptor * |
999 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
1000 | const dma_addr_t *dst, const dma_addr_t *src, | |
1001 | unsigned int src_cnt, const unsigned char *scf, | |
1002 | size_t len, unsigned long flags) | |
1003 | { | |
1004 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1005 | struct ioat_chan_common *chan = &ioat->base; | |
e0884772 | 1006 | struct ioatdma_device *device = chan->device; |
d69d235b DW |
1007 | struct ioat_ring_ent *compl_desc; |
1008 | struct ioat_ring_ent *desc; | |
1009 | struct ioat_ring_ent *ext; | |
1010 | size_t total_len = len; | |
1011 | struct ioat_pq_descriptor *pq; | |
1012 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
1013 | struct ioat_dma_descriptor *hw; | |
1014 | u32 offset = 0; | |
d69d235b | 1015 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
074cc476 | 1016 | int i, s, idx, with_ext, num_descs; |
e0884772 | 1017 | int cb32 = (device->version < IOAT_VER_3_3) ? 1 : 0; |
d69d235b DW |
1018 | |
1019 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
1020 | /* the engine requires at least two sources (we provide | |
1021 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
1022 | */ | |
1023 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
1024 | ||
1025 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
1026 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
1027 | * sources (we need 1 extra source in the q-only continuation |
1028 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 1029 | */ |
cd78809f DW |
1030 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
1031 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
1032 | with_ext = 1; |
1033 | num_descs *= 2; | |
1034 | } else | |
1035 | with_ext = 0; | |
1036 | ||
1037 | /* completion writes from the raid engine may pass completion | |
1038 | * writes from the legacy engine, so we need one extra null | |
1039 | * (legacy) descriptor to ensure all completion writes arrive in | |
1040 | * order. | |
1041 | */ | |
1042 | if (likely(num_descs) && | |
e0884772 | 1043 | ioat2_check_space_lock(ioat, num_descs + cb32) == 0) |
074cc476 | 1044 | idx = ioat->head; |
d69d235b DW |
1045 | else |
1046 | return NULL; | |
cdef57db DW |
1047 | i = 0; |
1048 | do { | |
d69d235b DW |
1049 | struct ioat_raw_descriptor *descs[2]; |
1050 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
1051 | ||
1052 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
1053 | pq = desc->pq; | |
1054 | ||
1055 | /* save a branch by unconditionally retrieving the | |
1056 | * extended descriptor pq_set_src() knows to not write | |
1057 | * to it in the single descriptor case | |
1058 | */ | |
1059 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
1060 | pq_ex = ext->pq_ex; | |
1061 | ||
1062 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
1063 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
1064 | ||
1065 | for (s = 0; s < src_cnt; s++) | |
1066 | pq_set_src(descs, src[s], offset, scf[s], s); | |
1067 | ||
1068 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
1069 | if (dmaf_p_disabled_continue(flags)) | |
1070 | pq_set_src(descs, dst[1], offset, 1, s++); | |
1071 | else if (dmaf_continue(flags)) { | |
1072 | pq_set_src(descs, dst[0], offset, 0, s++); | |
1073 | pq_set_src(descs, dst[1], offset, 1, s++); | |
1074 | pq_set_src(descs, dst[1], offset, 0, s++); | |
1075 | } | |
1076 | pq->size = xfer_size; | |
1077 | pq->p_addr = dst[0] + offset; | |
1078 | pq->q_addr = dst[1] + offset; | |
1079 | pq->ctl = 0; | |
1080 | pq->ctl_f.op = op; | |
1081 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); | |
1082 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
1083 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
1084 | ||
1085 | len -= xfer_size; | |
1086 | offset += xfer_size; | |
cdef57db | 1087 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
1088 | |
1089 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
1090 | desc->txd.flags = flags; | |
1091 | desc->len = total_len; | |
1092 | if (result) | |
1093 | desc->result = result; | |
1094 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1095 | dump_pq_desc_dbg(ioat, desc, ext); | |
1096 | ||
e0884772 DJ |
1097 | if (!cb32) { |
1098 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1099 | pq->ctl_f.compl_write = 1; | |
1100 | compl_desc = desc; | |
1101 | } else { | |
1102 | /* completion descriptor carries interrupt bit */ | |
1103 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
1104 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
1105 | hw = compl_desc->hw; | |
1106 | hw->ctl = 0; | |
1107 | hw->ctl_f.null = 1; | |
1108 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1109 | hw->ctl_f.compl_write = 1; | |
1110 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1111 | dump_desc_dbg(ioat, compl_desc); | |
1112 | } | |
1113 | ||
d69d235b DW |
1114 | |
1115 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 1116 | return &compl_desc->txd; |
d69d235b DW |
1117 | } |
1118 | ||
7727eaa4 DJ |
1119 | static struct dma_async_tx_descriptor * |
1120 | __ioat3_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result, | |
1121 | const dma_addr_t *dst, const dma_addr_t *src, | |
1122 | unsigned int src_cnt, const unsigned char *scf, | |
1123 | size_t len, unsigned long flags) | |
1124 | { | |
1125 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1126 | struct ioat_chan_common *chan = &ioat->base; | |
1127 | struct ioatdma_device *device = chan->device; | |
1128 | struct ioat_ring_ent *desc; | |
1129 | size_t total_len = len; | |
1130 | struct ioat_pq_descriptor *pq; | |
1131 | u32 offset = 0; | |
1132 | u8 op; | |
1133 | int i, s, idx, num_descs; | |
1134 | ||
1135 | /* this function only handles src_cnt 9 - 16 */ | |
1136 | BUG_ON(src_cnt < 9); | |
1137 | ||
1138 | /* this function is only called with 9-16 sources */ | |
1139 | op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S; | |
1140 | ||
1141 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
1142 | ||
1143 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
1144 | ||
1145 | /* | |
1146 | * 16 source pq is only available on cb3.3 and has no completion | |
1147 | * write hw bug. | |
1148 | */ | |
1149 | if (num_descs && ioat2_check_space_lock(ioat, num_descs) == 0) | |
1150 | idx = ioat->head; | |
1151 | else | |
1152 | return NULL; | |
1153 | ||
1154 | i = 0; | |
1155 | ||
1156 | do { | |
1157 | struct ioat_raw_descriptor *descs[4]; | |
1158 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
1159 | ||
1160 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
1161 | pq = desc->pq; | |
1162 | ||
1163 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
1164 | ||
1165 | desc->sed = ioat3_alloc_sed(device, | |
1166 | sed_get_pq16_pool_idx(src_cnt)); | |
1167 | if (!desc->sed) { | |
1168 | dev_err(to_dev(chan), | |
1169 | "%s: no free sed entries\n", __func__); | |
1170 | return NULL; | |
1171 | } | |
1172 | ||
1173 | pq->sed_addr = desc->sed->dma; | |
1174 | desc->sed->parent = desc; | |
1175 | ||
1176 | descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw; | |
1177 | descs[2] = (void *)descs[1] + 64; | |
1178 | ||
1179 | for (s = 0; s < src_cnt; s++) | |
1180 | pq16_set_src(descs, src[s], offset, scf[s], s); | |
1181 | ||
1182 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
1183 | if (dmaf_p_disabled_continue(flags)) | |
1184 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1185 | else if (dmaf_continue(flags)) { | |
1186 | pq16_set_src(descs, dst[0], offset, 0, s++); | |
1187 | pq16_set_src(descs, dst[1], offset, 1, s++); | |
1188 | pq16_set_src(descs, dst[1], offset, 0, s++); | |
1189 | } | |
1190 | ||
1191 | pq->size = xfer_size; | |
1192 | pq->p_addr = dst[0] + offset; | |
1193 | pq->q_addr = dst[1] + offset; | |
1194 | pq->ctl = 0; | |
1195 | pq->ctl_f.op = op; | |
1196 | pq->ctl_f.src_cnt = src16_cnt_to_hw(s); | |
1197 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
1198 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
1199 | ||
1200 | len -= xfer_size; | |
1201 | offset += xfer_size; | |
1202 | } while (++i < num_descs); | |
1203 | ||
1204 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
1205 | desc->txd.flags = flags; | |
1206 | desc->len = total_len; | |
1207 | if (result) | |
1208 | desc->result = result; | |
1209 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1210 | ||
1211 | /* with cb3.3 we should be able to do completion w/o a null desc */ | |
1212 | pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
1213 | pq->ctl_f.compl_write = 1; | |
1214 | ||
1215 | dump_pq16_desc_dbg(ioat, desc); | |
1216 | ||
1217 | /* we leave the channel locked to ensure in order submission */ | |
1218 | return &desc->txd; | |
1219 | } | |
1220 | ||
d69d235b DW |
1221 | static struct dma_async_tx_descriptor * |
1222 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
1223 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1224 | unsigned long flags) | |
1225 | { | |
7727eaa4 DJ |
1226 | struct dma_device *dma = chan->device; |
1227 | ||
de581b65 DW |
1228 | /* specify valid address for disabled result */ |
1229 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1230 | dst[0] = dst[1]; | |
1231 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1232 | dst[1] = dst[0]; | |
1233 | ||
d69d235b DW |
1234 | /* handle the single source multiply case from the raid6 |
1235 | * recovery path | |
1236 | */ | |
de581b65 | 1237 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
1238 | dma_addr_t single_source[2]; |
1239 | unsigned char single_source_coef[2]; | |
1240 | ||
1241 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
1242 | single_source[0] = src[0]; | |
1243 | single_source[1] = src[0]; | |
1244 | single_source_coef[0] = scf[0]; | |
1245 | single_source_coef[1] = 0; | |
1246 | ||
7727eaa4 DJ |
1247 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1248 | __ioat3_prep_pq16_lock(chan, NULL, dst, single_source, | |
1249 | 2, single_source_coef, len, | |
1250 | flags) : | |
1251 | __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
1252 | single_source_coef, len, flags); | |
1253 | ||
1254 | } else { | |
1255 | return (src_cnt > 8) && (dma->max_pq > 8) ? | |
1256 | __ioat3_prep_pq16_lock(chan, NULL, dst, src, src_cnt, | |
1257 | scf, len, flags) : | |
1258 | __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, | |
1259 | scf, len, flags); | |
1260 | } | |
d69d235b DW |
1261 | } |
1262 | ||
1263 | struct dma_async_tx_descriptor * | |
1264 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
1265 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
1266 | enum sum_check_flags *pqres, unsigned long flags) | |
1267 | { | |
7727eaa4 DJ |
1268 | struct dma_device *dma = chan->device; |
1269 | ||
de581b65 DW |
1270 | /* specify valid address for disabled result */ |
1271 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1272 | pq[0] = pq[1]; | |
1273 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1274 | pq[1] = pq[0]; | |
1275 | ||
d69d235b DW |
1276 | /* the cleanup routine only sets bits on validate failure, it |
1277 | * does not clear bits on validate success... so clear it here | |
1278 | */ | |
1279 | *pqres = 0; | |
1280 | ||
7727eaa4 DJ |
1281 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1282 | __ioat3_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
1283 | flags) : | |
1284 | __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
1285 | flags); | |
d69d235b DW |
1286 | } |
1287 | ||
ae786624 DW |
1288 | static struct dma_async_tx_descriptor * |
1289 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
1290 | unsigned int src_cnt, size_t len, unsigned long flags) | |
1291 | { | |
7727eaa4 | 1292 | struct dma_device *dma = chan->device; |
ae786624 DW |
1293 | unsigned char scf[src_cnt]; |
1294 | dma_addr_t pq[2]; | |
1295 | ||
1296 | memset(scf, 0, src_cnt); | |
ae786624 | 1297 | pq[0] = dst; |
de581b65 DW |
1298 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1299 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 | 1300 | |
7727eaa4 DJ |
1301 | return (src_cnt > 8) && (dma->max_pq > 8) ? |
1302 | __ioat3_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1303 | flags) : | |
1304 | __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
1305 | flags); | |
ae786624 DW |
1306 | } |
1307 | ||
1308 | struct dma_async_tx_descriptor * | |
1309 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
1310 | unsigned int src_cnt, size_t len, | |
1311 | enum sum_check_flags *result, unsigned long flags) | |
1312 | { | |
7727eaa4 | 1313 | struct dma_device *dma = chan->device; |
ae786624 DW |
1314 | unsigned char scf[src_cnt]; |
1315 | dma_addr_t pq[2]; | |
1316 | ||
1317 | /* the cleanup routine only sets bits on validate failure, it | |
1318 | * does not clear bits on validate success... so clear it here | |
1319 | */ | |
1320 | *result = 0; | |
1321 | ||
1322 | memset(scf, 0, src_cnt); | |
ae786624 | 1323 | pq[0] = src[0]; |
de581b65 DW |
1324 | flags |= DMA_PREP_PQ_DISABLE_Q; |
1325 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 | 1326 | |
7727eaa4 DJ |
1327 | |
1328 | return (src_cnt > 8) && (dma->max_pq > 8) ? | |
1329 | __ioat3_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1, | |
1330 | scf, len, flags) : | |
1331 | __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, | |
1332 | scf, len, flags); | |
ae786624 DW |
1333 | } |
1334 | ||
58c8649e DW |
1335 | static struct dma_async_tx_descriptor * |
1336 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
1337 | { | |
1338 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
1339 | struct ioat_ring_ent *desc; | |
1340 | struct ioat_dma_descriptor *hw; | |
58c8649e | 1341 | |
074cc476 DW |
1342 | if (ioat2_check_space_lock(ioat, 1) == 0) |
1343 | desc = ioat2_get_ring_ent(ioat, ioat->head); | |
58c8649e DW |
1344 | else |
1345 | return NULL; | |
1346 | ||
1347 | hw = desc->hw; | |
1348 | hw->ctl = 0; | |
1349 | hw->ctl_f.null = 1; | |
1350 | hw->ctl_f.int_en = 1; | |
1351 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
1352 | hw->ctl_f.compl_write = 1; | |
1353 | hw->size = NULL_DESC_BUFFER_SIZE; | |
1354 | hw->src_addr = 0; | |
1355 | hw->dst_addr = 0; | |
1356 | ||
1357 | desc->txd.flags = flags; | |
1358 | desc->len = 1; | |
1359 | ||
1360 | dump_desc_dbg(ioat, desc); | |
1361 | ||
1362 | /* we leave the channel locked to ensure in order submission */ | |
1363 | return &desc->txd; | |
1364 | } | |
1365 | ||
4bf27b8b | 1366 | static void ioat3_dma_test_callback(void *dma_async_param) |
9de6fc71 DW |
1367 | { |
1368 | struct completion *cmp = dma_async_param; | |
1369 | ||
1370 | complete(cmp); | |
1371 | } | |
1372 | ||
1373 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
4bf27b8b | 1374 | static int ioat_xor_val_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1375 | { |
1376 | int i, src_idx; | |
1377 | struct page *dest; | |
1378 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
1379 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1380 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
1381 | dma_addr_t dma_addr, dest_dma; | |
1382 | struct dma_async_tx_descriptor *tx; | |
1383 | struct dma_chan *dma_chan; | |
1384 | dma_cookie_t cookie; | |
1385 | u8 cmp_byte = 0; | |
1386 | u32 cmp_word; | |
1387 | u32 xor_val_result; | |
1388 | int err = 0; | |
1389 | struct completion cmp; | |
1390 | unsigned long tmo; | |
1391 | struct device *dev = &device->pdev->dev; | |
1392 | struct dma_device *dma = &device->common; | |
7369f56e | 1393 | u8 op = 0; |
9de6fc71 DW |
1394 | |
1395 | dev_dbg(dev, "%s\n", __func__); | |
1396 | ||
1397 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
1398 | return 0; | |
1399 | ||
1400 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1401 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
1402 | if (!xor_srcs[src_idx]) { | |
1403 | while (src_idx--) | |
1404 | __free_page(xor_srcs[src_idx]); | |
1405 | return -ENOMEM; | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | dest = alloc_page(GFP_KERNEL); | |
1410 | if (!dest) { | |
1411 | while (src_idx--) | |
1412 | __free_page(xor_srcs[src_idx]); | |
1413 | return -ENOMEM; | |
1414 | } | |
1415 | ||
1416 | /* Fill in src buffers */ | |
1417 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
1418 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
1419 | for (i = 0; i < PAGE_SIZE; i++) | |
1420 | ptr[i] = (1 << src_idx); | |
1421 | } | |
1422 | ||
1423 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
1424 | cmp_byte ^= (u8) (1 << src_idx); | |
1425 | ||
1426 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
1427 | (cmp_byte << 8) | cmp_byte; | |
1428 | ||
1429 | memset(page_address(dest), 0, PAGE_SIZE); | |
1430 | ||
1431 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
1432 | device_node); | |
1433 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
1434 | err = -ENODEV; | |
1435 | goto out; | |
1436 | } | |
1437 | ||
1438 | /* test xor */ | |
7369f56e BZ |
1439 | op = IOAT_OP_XOR; |
1440 | ||
9de6fc71 DW |
1441 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
1442 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1443 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
1444 | DMA_TO_DEVICE); | |
1445 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
1446 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
7369f56e BZ |
1447 | DMA_PREP_INTERRUPT | |
1448 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1449 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1450 | |
1451 | if (!tx) { | |
1452 | dev_err(dev, "Self-test xor prep failed\n"); | |
1453 | err = -ENODEV; | |
7369f56e | 1454 | goto dma_unmap; |
9de6fc71 DW |
1455 | } |
1456 | ||
1457 | async_tx_ack(tx); | |
1458 | init_completion(&cmp); | |
1459 | tx->callback = ioat3_dma_test_callback; | |
1460 | tx->callback_param = &cmp; | |
1461 | cookie = tx->tx_submit(tx); | |
1462 | if (cookie < 0) { | |
1463 | dev_err(dev, "Self-test xor setup failed\n"); | |
1464 | err = -ENODEV; | |
7369f56e | 1465 | goto dma_unmap; |
9de6fc71 DW |
1466 | } |
1467 | dma->device_issue_pending(dma_chan); | |
1468 | ||
1469 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1470 | ||
07934481 | 1471 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1472 | dev_err(dev, "Self-test xor timed out\n"); |
1473 | err = -ENODEV; | |
7369f56e | 1474 | goto dma_unmap; |
9de6fc71 DW |
1475 | } |
1476 | ||
7369f56e BZ |
1477 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1478 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1479 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1480 | ||
9de6fc71 DW |
1481 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
1482 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
1483 | u32 *ptr = page_address(dest); | |
1484 | if (ptr[i] != cmp_word) { | |
1485 | dev_err(dev, "Self-test xor failed compare\n"); | |
1486 | err = -ENODEV; | |
1487 | goto free_resources; | |
1488 | } | |
1489 | } | |
ac498987 | 1490 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
9de6fc71 DW |
1491 | |
1492 | /* skip validate if the capability is not present */ | |
1493 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
1494 | goto free_resources; | |
1495 | ||
7369f56e BZ |
1496 | op = IOAT_OP_XOR_VAL; |
1497 | ||
9de6fc71 DW |
1498 | /* validate the sources with the destintation page */ |
1499 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1500 | xor_val_srcs[i] = xor_srcs[i]; | |
1501 | xor_val_srcs[i] = dest; | |
1502 | ||
1503 | xor_val_result = 1; | |
1504 | ||
1505 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1506 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1507 | DMA_TO_DEVICE); | |
1508 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1509 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1510 | &xor_val_result, DMA_PREP_INTERRUPT | |
1511 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1512 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1513 | if (!tx) { |
1514 | dev_err(dev, "Self-test zero prep failed\n"); | |
1515 | err = -ENODEV; | |
7369f56e | 1516 | goto dma_unmap; |
9de6fc71 DW |
1517 | } |
1518 | ||
1519 | async_tx_ack(tx); | |
1520 | init_completion(&cmp); | |
1521 | tx->callback = ioat3_dma_test_callback; | |
1522 | tx->callback_param = &cmp; | |
1523 | cookie = tx->tx_submit(tx); | |
1524 | if (cookie < 0) { | |
1525 | dev_err(dev, "Self-test zero setup failed\n"); | |
1526 | err = -ENODEV; | |
7369f56e | 1527 | goto dma_unmap; |
9de6fc71 DW |
1528 | } |
1529 | dma->device_issue_pending(dma_chan); | |
1530 | ||
1531 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1532 | ||
07934481 | 1533 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1534 | dev_err(dev, "Self-test validate timed out\n"); |
1535 | err = -ENODEV; | |
7369f56e | 1536 | goto dma_unmap; |
9de6fc71 DW |
1537 | } |
1538 | ||
7369f56e BZ |
1539 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1540 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1541 | ||
9de6fc71 DW |
1542 | if (xor_val_result != 0) { |
1543 | dev_err(dev, "Self-test validate failed compare\n"); | |
1544 | err = -ENODEV; | |
1545 | goto free_resources; | |
1546 | } | |
1547 | ||
1548 | /* skip memset if the capability is not present */ | |
1549 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) | |
1550 | goto free_resources; | |
1551 | ||
1552 | /* test memset */ | |
7369f56e BZ |
1553 | op = IOAT_OP_FILL; |
1554 | ||
9de6fc71 DW |
1555 | dma_addr = dma_map_page(dev, dest, 0, |
1556 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1557 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, | |
7369f56e BZ |
1558 | DMA_PREP_INTERRUPT | |
1559 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1560 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1561 | if (!tx) { |
1562 | dev_err(dev, "Self-test memset prep failed\n"); | |
1563 | err = -ENODEV; | |
7369f56e | 1564 | goto dma_unmap; |
9de6fc71 DW |
1565 | } |
1566 | ||
1567 | async_tx_ack(tx); | |
1568 | init_completion(&cmp); | |
1569 | tx->callback = ioat3_dma_test_callback; | |
1570 | tx->callback_param = &cmp; | |
1571 | cookie = tx->tx_submit(tx); | |
1572 | if (cookie < 0) { | |
1573 | dev_err(dev, "Self-test memset setup failed\n"); | |
1574 | err = -ENODEV; | |
7369f56e | 1575 | goto dma_unmap; |
9de6fc71 DW |
1576 | } |
1577 | dma->device_issue_pending(dma_chan); | |
1578 | ||
1579 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1580 | ||
07934481 | 1581 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1582 | dev_err(dev, "Self-test memset timed out\n"); |
1583 | err = -ENODEV; | |
7369f56e | 1584 | goto dma_unmap; |
9de6fc71 DW |
1585 | } |
1586 | ||
7369f56e BZ |
1587 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); |
1588 | ||
9de6fc71 DW |
1589 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { |
1590 | u32 *ptr = page_address(dest); | |
1591 | if (ptr[i]) { | |
1592 | dev_err(dev, "Self-test memset failed compare\n"); | |
1593 | err = -ENODEV; | |
1594 | goto free_resources; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | /* test for non-zero parity sum */ | |
7369f56e BZ |
1599 | op = IOAT_OP_XOR_VAL; |
1600 | ||
9de6fc71 DW |
1601 | xor_val_result = 0; |
1602 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1603 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1604 | DMA_TO_DEVICE); | |
1605 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1606 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
7369f56e BZ |
1607 | &xor_val_result, DMA_PREP_INTERRUPT | |
1608 | DMA_COMPL_SKIP_SRC_UNMAP | | |
1609 | DMA_COMPL_SKIP_DEST_UNMAP); | |
9de6fc71 DW |
1610 | if (!tx) { |
1611 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1612 | err = -ENODEV; | |
7369f56e | 1613 | goto dma_unmap; |
9de6fc71 DW |
1614 | } |
1615 | ||
1616 | async_tx_ack(tx); | |
1617 | init_completion(&cmp); | |
1618 | tx->callback = ioat3_dma_test_callback; | |
1619 | tx->callback_param = &cmp; | |
1620 | cookie = tx->tx_submit(tx); | |
1621 | if (cookie < 0) { | |
1622 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1623 | err = -ENODEV; | |
7369f56e | 1624 | goto dma_unmap; |
9de6fc71 DW |
1625 | } |
1626 | dma->device_issue_pending(dma_chan); | |
1627 | ||
1628 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1629 | ||
07934481 | 1630 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
9de6fc71 DW |
1631 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
1632 | err = -ENODEV; | |
7369f56e | 1633 | goto dma_unmap; |
9de6fc71 DW |
1634 | } |
1635 | ||
1636 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1637 | dev_err(dev, "Self-test validate failed compare\n"); | |
1638 | err = -ENODEV; | |
7369f56e | 1639 | goto dma_unmap; |
9de6fc71 DW |
1640 | } |
1641 | ||
7369f56e BZ |
1642 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
1643 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); | |
1644 | ||
1645 | goto free_resources; | |
1646 | dma_unmap: | |
1647 | if (op == IOAT_OP_XOR) { | |
1648 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
1649 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1650 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1651 | DMA_TO_DEVICE); | |
1652 | } else if (op == IOAT_OP_XOR_VAL) { | |
1653 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1654 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, | |
1655 | DMA_TO_DEVICE); | |
1656 | } else if (op == IOAT_OP_FILL) | |
1657 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); | |
9de6fc71 DW |
1658 | free_resources: |
1659 | dma->device_free_chan_resources(dma_chan); | |
1660 | out: | |
1661 | src_idx = IOAT_NUM_SRC_TEST; | |
1662 | while (src_idx--) | |
1663 | __free_page(xor_srcs[src_idx]); | |
1664 | __free_page(dest); | |
1665 | return err; | |
1666 | } | |
1667 | ||
4bf27b8b | 1668 | static int ioat3_dma_self_test(struct ioatdma_device *device) |
9de6fc71 DW |
1669 | { |
1670 | int rc = ioat_dma_self_test(device); | |
1671 | ||
1672 | if (rc) | |
1673 | return rc; | |
1674 | ||
1675 | rc = ioat_xor_val_self_test(device); | |
1676 | if (rc) | |
1677 | return rc; | |
1678 | ||
1679 | return 0; | |
1680 | } | |
1681 | ||
8a52b9ff DJ |
1682 | static int ioat3_irq_reinit(struct ioatdma_device *device) |
1683 | { | |
1684 | int msixcnt = device->common.chancnt; | |
1685 | struct pci_dev *pdev = device->pdev; | |
1686 | int i; | |
1687 | struct msix_entry *msix; | |
1688 | struct ioat_chan_common *chan; | |
1689 | int err = 0; | |
1690 | ||
1691 | switch (device->irq_mode) { | |
1692 | case IOAT_MSIX: | |
1693 | ||
1694 | for (i = 0; i < msixcnt; i++) { | |
1695 | msix = &device->msix_entries[i]; | |
1696 | chan = ioat_chan_by_index(device, i); | |
1697 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1698 | } | |
1699 | ||
1700 | pci_disable_msix(pdev); | |
1701 | break; | |
1702 | ||
1703 | case IOAT_MSIX_SINGLE: | |
1704 | msix = &device->msix_entries[0]; | |
1705 | chan = ioat_chan_by_index(device, 0); | |
1706 | devm_free_irq(&pdev->dev, msix->vector, chan); | |
1707 | pci_disable_msix(pdev); | |
1708 | break; | |
1709 | ||
1710 | case IOAT_MSI: | |
1711 | chan = ioat_chan_by_index(device, 0); | |
1712 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1713 | pci_disable_msi(pdev); | |
1714 | break; | |
1715 | ||
1716 | case IOAT_INTX: | |
1717 | chan = ioat_chan_by_index(device, 0); | |
1718 | devm_free_irq(&pdev->dev, pdev->irq, chan); | |
1719 | break; | |
1720 | ||
1721 | default: | |
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | device->irq_mode = IOAT_NOIRQ; | |
1726 | ||
1727 | err = ioat_dma_setup_interrupts(device); | |
1728 | ||
1729 | return err; | |
1730 | } | |
1731 | ||
a6d52d70 DW |
1732 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1733 | { | |
1734 | /* throw away whatever the channel was doing and get it | |
1735 | * initialized, with ioat3 specific workarounds | |
1736 | */ | |
1737 | struct ioatdma_device *device = chan->device; | |
1738 | struct pci_dev *pdev = device->pdev; | |
1739 | u32 chanerr; | |
1740 | u16 dev_id; | |
1741 | int err; | |
1742 | ||
1743 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1744 | ||
1745 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1746 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1747 | ||
6ead7e48 DJ |
1748 | if (device->version < IOAT_VER_3_3) { |
1749 | /* clear any pending errors */ | |
1750 | err = pci_read_config_dword(pdev, | |
1751 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1752 | if (err) { | |
1753 | dev_err(&pdev->dev, | |
1754 | "channel error register unreachable\n"); | |
1755 | return err; | |
1756 | } | |
1757 | pci_write_config_dword(pdev, | |
1758 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
a6d52d70 | 1759 | |
6ead7e48 DJ |
1760 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
1761 | * (workaround for spurious config parity error after restart) | |
1762 | */ | |
1763 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1764 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1765 | pci_write_config_dword(pdev, | |
1766 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1767 | 0x10); | |
1768 | } | |
1769 | } | |
a6d52d70 | 1770 | |
8a52b9ff DJ |
1771 | err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
1772 | if (err) { | |
1773 | dev_err(&pdev->dev, "Failed to reset!\n"); | |
1774 | return err; | |
570727b5 DJ |
1775 | } |
1776 | ||
8a52b9ff DJ |
1777 | if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev)) |
1778 | err = ioat3_irq_reinit(device); | |
570727b5 | 1779 | |
8a52b9ff | 1780 | return err; |
570727b5 DJ |
1781 | } |
1782 | ||
4bf27b8b | 1783 | int ioat3_dma_probe(struct ioatdma_device *device, int dca) |
bf40a686 DW |
1784 | { |
1785 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1786 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1787 | struct dma_device *dma; |
1788 | struct dma_chan *c; | |
1789 | struct ioat_chan_common *chan; | |
e3232714 | 1790 | bool is_raid_device = false; |
bf40a686 | 1791 | int err; |
bf40a686 DW |
1792 | u32 cap; |
1793 | ||
1794 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1795 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1796 | device->self_test = ioat3_dma_self_test; |
bf40a686 DW |
1797 | dma = &device->common; |
1798 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1799 | dma->device_issue_pending = ioat2_issue_pending; | |
1800 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1801 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e | 1802 | |
570727b5 | 1803 | if (is_xeon_cb32(pdev)) |
f26df1a1 DJ |
1804 | dma->copy_align = 6; |
1805 | ||
58c8649e DW |
1806 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); |
1807 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1808 | ||
bf40a686 | 1809 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c DW |
1810 | |
1811 | /* dca is incompatible with raid operations */ | |
1812 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) | |
1813 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
1814 | ||
b094ad3b | 1815 | if (cap & IOAT_CAP_XOR) { |
e3232714 | 1816 | is_raid_device = true; |
b094ad3b | 1817 | dma->max_xor = 8; |
2adfc550 | 1818 | dma->xor_align = 6; |
b094ad3b DW |
1819 | |
1820 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1821 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1822 | ||
1823 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1824 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1825 | } | |
eceec44e | 1826 | |
d69d235b | 1827 | if (cap & IOAT_CAP_PQ) { |
e3232714 | 1828 | is_raid_device = true; |
7727eaa4 DJ |
1829 | |
1830 | if (cap & IOAT_CAP_RAID16SS) { | |
1831 | dma_set_maxpq(dma, 16, 0); | |
eceec44e | 1832 | dma->pq_align = 0; |
7727eaa4 DJ |
1833 | } else { |
1834 | dma_set_maxpq(dma, 8, 0); | |
1835 | if (is_xeon_cb32(pdev)) | |
1836 | dma->pq_align = 6; | |
1837 | else | |
1838 | dma->pq_align = 0; | |
1839 | } | |
d69d235b DW |
1840 | |
1841 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1842 | dma->device_prep_dma_pq = ioat3_prep_pq; | |
1843 | ||
1844 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1845 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
ae786624 DW |
1846 | |
1847 | if (!(cap & IOAT_CAP_XOR)) { | |
7727eaa4 DJ |
1848 | if (cap & IOAT_CAP_RAID16SS) { |
1849 | dma->max_xor = 16; | |
eceec44e | 1850 | dma->xor_align = 0; |
7727eaa4 DJ |
1851 | } else { |
1852 | dma->max_xor = 8; | |
1853 | if (is_xeon_cb32(pdev)) | |
1854 | dma->xor_align = 6; | |
1855 | else | |
1856 | dma->xor_align = 0; | |
1857 | } | |
ae786624 DW |
1858 | |
1859 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1860 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1861 | ||
1862 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1863 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1864 | } | |
d69d235b | 1865 | } |
eceec44e | 1866 | |
e3232714 DW |
1867 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
1868 | dma_cap_set(DMA_MEMSET, dma->cap_mask); | |
1869 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; | |
1870 | } | |
1871 | ||
1872 | ||
9a37f644 DJ |
1873 | dma->device_tx_status = ioat3_tx_status; |
1874 | device->cleanup_fn = ioat3_cleanup_event; | |
1875 | device->timer_fn = ioat3_timer_event; | |
bf40a686 | 1876 | |
3f09ede4 DJ |
1877 | if (is_xeon_cb32(pdev)) { |
1878 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); | |
1879 | dma->device_prep_dma_xor_val = NULL; | |
7b3cc2b1 | 1880 | |
3f09ede4 DJ |
1881 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); |
1882 | dma->device_prep_dma_pq_val = NULL; | |
1883 | } | |
7b3cc2b1 | 1884 | |
7727eaa4 DJ |
1885 | /* starting with CB3.3 super extended descriptors are supported */ |
1886 | if (cap & IOAT_CAP_RAID16SS) { | |
1887 | char pool_name[14]; | |
1888 | int i; | |
1889 | ||
1890 | /* allocate sw descriptor pool for SED */ | |
1891 | device->sed_pool = kmem_cache_create("ioat_sed", | |
1892 | sizeof(struct ioat_sed_ent), 0, 0, NULL); | |
1893 | if (!device->sed_pool) | |
1894 | return -ENOMEM; | |
1895 | ||
1896 | for (i = 0; i < MAX_SED_POOLS; i++) { | |
1897 | snprintf(pool_name, 14, "ioat_hw%d_sed", i); | |
1898 | ||
1899 | /* allocate SED DMA pool */ | |
1900 | device->sed_hw_pool[i] = dma_pool_create(pool_name, | |
1901 | &pdev->dev, | |
1902 | SED_SIZE * (i + 1), 64, 0); | |
1903 | if (!device->sed_hw_pool[i]) | |
1904 | goto sed_pool_cleanup; | |
1905 | ||
1906 | } | |
1907 | } | |
1908 | ||
bf40a686 DW |
1909 | err = ioat_probe(device); |
1910 | if (err) | |
1911 | return err; | |
1912 | ioat_set_tcp_copy_break(262144); | |
1913 | ||
1914 | list_for_each_entry(c, &dma->channels, device_node) { | |
1915 | chan = to_chan_common(c); | |
1916 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1917 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1918 | } | |
1919 | ||
1920 | err = ioat_register(device); | |
1921 | if (err) | |
1922 | return err; | |
5669e31c DW |
1923 | |
1924 | ioat_kobject_add(device, &ioat2_ktype); | |
1925 | ||
bf40a686 DW |
1926 | if (dca) |
1927 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1928 | ||
1929 | return 0; | |
7727eaa4 DJ |
1930 | |
1931 | sed_pool_cleanup: | |
1932 | if (device->sed_pool) { | |
1933 | int i; | |
1934 | kmem_cache_destroy(device->sed_pool); | |
1935 | ||
1936 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1937 | if (device->sed_hw_pool[i]) | |
1938 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1939 | } | |
1940 | ||
1941 | return -ENOMEM; | |
1942 | } | |
1943 | ||
1944 | void ioat3_dma_remove(struct ioatdma_device *device) | |
1945 | { | |
1946 | if (device->sed_pool) { | |
1947 | int i; | |
1948 | kmem_cache_destroy(device->sed_pool); | |
1949 | ||
1950 | for (i = 0; i < MAX_SED_POOLS; i++) | |
1951 | if (device->sed_hw_pool[i]) | |
1952 | dma_pool_destroy(device->sed_hw_pool[i]); | |
1953 | } | |
bf40a686 | 1954 | } |